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review.evervolv.com / android_kernel_htc_msm8960 / 97ad00dc3702615c66f58e691cf5ca63707a0db5 / . / arch / arm / boot / dts / msm8974.dtsi
blob: 0b7d2c5159942af0d816134008fdfcc5674e10ef [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Kevin Chan350b6932012-08-01 02:21:00 -0700[diff] [blame]16/include/ "msm8974-camera.dtsi"
Pratik Patelf20bacb2012-07-21 14:46:36 -0700[diff] [blame]17/include/ "msm8974-coresight.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]18/include/ "msm-gdsc.dtsi"
Olav Haugan49173442012-08-01 13:23:18 -0700[diff] [blame]19/include/ "msm8974-ion.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]20/include/ "msm8974-gpu.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]21
22/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]23 model = "Qualcomm MSM 8974";
24 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]25 interrupt-parent = <&intc>;
26
27 intc: interrupt-controller@F9000000 {
28 compatible = "qcom,msm-qgic2";
29 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]30 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]31 reg = <0xF9000000 0x1000>,
32 <0xF9002000 0x1000>;
33 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]34
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]35 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]36 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -0700[diff] [blame]37 gpio-controller;
38 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]39 interrupt-controller;
40 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]41 reg = <0xfd510000 0x4000>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]42 };
43
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]44 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]45 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]46 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]47 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]48 };
49
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]50 qcom,vidc@fdc00000 {
51 compatible = "qcom,msm-vidc";
52 reg = <0xfdc00000 0xff000>;
53 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]54 vidc-cp-map = <0x1000000 0x40000000>;
55 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -0700[diff] [blame]56 load-freq-tbl = <979200 410000000>,
57 <560145 266670000>,
58 <421161 200000000>,
59 <243000 133330000>,
60 <108000 100000000>,
61 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]62 };
63
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]64 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]65 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]66 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]67 interrupts = <0 109 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]68 status = "disabled";
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]69 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]70
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]71 serial@f995e000 {
72 compatible = "qcom,msm-lsuart-v14";
73 reg = <0xf995e000 0x1000>;
74 interrupts = <0 114 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]75 status = "disabled";
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]76 };
77
Stepan Moskovchenko5269b602012-08-08 17:57:09 -0700[diff] [blame]78 serial@f991e000 {
79 compatible = "qcom,msm-lsuart-v14";
80 reg = <0xf991e000 0x1000>;
81 interrupts = <0 108 0>;
82 status = "disabled";
83 };
84
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]85 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]86 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]87 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]88 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]89 HSUSB_VDDCX-supply = <&pm8841_s2>;
90 HSUSB_1p8-supply = <&pm8941_l6>;
91 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]92
93 qcom,hsusb-otg-phy-type = <2>;
94 qcom,hsusb-otg-mode = <1>;
95 qcom,hsusb-otg-otg-control = <1>;
Manu Gautambd53fba2012-07-31 16:13:06 +0530[diff] [blame]96 qcom,hsusb-otg-disable-reset;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]97 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]98
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]99 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]100 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]101 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]102 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]103 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]104 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]105 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]106 vdd-supply = <&pm8941_l20>;
107 vdd-io-supply = <&pm8941_s3>;
108
109 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
110 qcom,sdcc-vdd-current_level = <800 500000>;
111
112 qcom,sdcc-vdd-io-always_on;
113 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
114 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]115
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]116 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
117 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
118 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
119 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
120
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]121 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
122 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]123 qcom,sdcc-bus-width = <8>;
124 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]125 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]126 };
127
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]128 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]129 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]130 compatible = "qcom,msm-sdcc";
131 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]132 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]133 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]134 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]135 vdd-supply = <&pm8941_l21>;
136 vdd-io-supply = <&pm8941_l13>;
137
138 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
139 qcom,sdcc-vdd-current_level = <9000 800000>;
140
141 qcom,sdcc-vdd-io-always_on;
142 qcom,sdcc-vdd-io-lpm_sup;
143 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
144 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]145
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]146 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
147 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
148 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
149 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
150
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]151 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
152 qcom,sdcc-sup-voltages = <2950 2950>;
153 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]154 qcom,sdcc-xpc;
155 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
156 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]157 };
158
159 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]160 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]161 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]162 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]163 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]164 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]165 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]166
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]167 gpios = <&msmgpio 40 0>, /* CLK */
168 <&msmgpio 39 0>, /* CMD */
169 <&msmgpio 38 0>, /* DATA0 */
170 <&msmgpio 37 0>, /* DATA1 */
171 <&msmgpio 36 0>, /* DATA2 */
172 <&msmgpio 35 0>; /* DATA3 */
173 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
174
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]175 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
176 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]177 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]178 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]179 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]180 };
181
182 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]183 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]184 compatible = "qcom,msm-sdcc";
185 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]186 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]187 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]188 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]189
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]190 gpios = <&msmgpio 93 0>, /* CLK */
191 <&msmgpio 91 0>, /* CMD */
192 <&msmgpio 96 0>, /* DATA0 */
193 <&msmgpio 95 0>, /* DATA1 */
194 <&msmgpio 94 0>, /* DATA2 */
195 <&msmgpio 92 0>; /* DATA3 */
196 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
197
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]198 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
199 qcom,sdcc-sup-voltages = <1800 1800>;
200 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]201 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]202 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]203 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]204
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]205 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]206 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]207 reg = <0xf9984000 0x15000>,
208 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]209 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]210
211 qcom,bam-dma-res-pipes = <6>;
212 };
213
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]214
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]215 spi@f9924000 {
216 compatible = "qcom,spi-qup-v2";
217 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]218 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]219 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]220 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]221
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]222 slim@fe12f000 {
223 cell-index = <1>;
224 compatible = "qcom,slim-msm";
225 reg = <0xfe12f000 0x35000>,
226 <0xfe104000 0x20000>;
227 reg-names = "slimbus_physical", "slimbus_bam_physical";
228 interrupts = <0 163 0 0 164 0>;
229 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
230 qcom,min-clk-gear = <10>;
Sagar Dhariac0d6cf52012-07-31 19:17:26 -0600[diff] [blame]231 qcom,rxreg-access;
Kiran Kandie8bf5d52012-08-06 16:03:16 -0700[diff] [blame]232
233 taiko_codec {
234 compatible = "qcom,taiko-slim-pgd";
235 elemental-addr = [00 01 A0 00 17 02];
236
237 qcom,cdc-reset-gpio = <&msmgpio 63 0>;
238
239 cdc-vdd-buck-supply = <&pm8941_s2>;
240 qcom,cdc-vdd-buck-voltage = <2150000 2150000>;
241 qcom,cdc-vdd-buck-current = <650000>;
242
243 cdc-vdd-tx-h-supply = <&pm8941_s3>;
244 qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
245 qcom,cdc-vdd-tx-h-current = <25000>;
246
247 cdc-vdd-rx-h-supply = <&pm8941_s3>;
248 qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
249 qcom,cdc-vdd-rx-h-current = <25000>;
250
251 cdc-vddpx-1-supply = <&pm8941_s3>;
252 qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
253 qcom,cdc-vddpx-1-current = <10000>;
254
255 cdc-vdd-a-1p2v-supply = <&pm8941_l1>;
256 qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>;
257 qcom,cdc-vdd-a-1p2v-current = <10000>;
258
259 cdc-vddcx-1-supply = <&pm8941_l1>;
260 qcom,cdc-vddcx-1-voltage = <1225000 1225000>;
261 qcom,cdc-vddcx-1-current = <10000>;
262
263 cdc-vddcx-2-supply = <&pm8941_l1>;
264 qcom,cdc-vddcx-2-voltage = <1225000 1225000>;
265 qcom,cdc-vddcx-2-current = <10000>;
266
267 qcom,cdc-micbias-ldoh-v = <0x3>;
268 qcom,cdc-micbias-cfilt1-mv = <1800>;
269 qcom,cdc-micbias-cfilt2-mv = <2700>;
270 qcom,cdc-micbias-cfilt3-mv = <1800>;
271 qcom,cdc-micbias1-cfilt-sel = <0x0>;
272 qcom,cdc-micbias2-cfilt-sel = <0x1>;
273 qcom,cdc-micbias3-cfilt-sel = <0x2>;
274 qcom,cdc-micbias4-cfilt-sel = <0x2>;
275
276 qcom,cdc-slim-ifd = "taiko-slim-ifd";
277 qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02];
278 };
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]279 };
280
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]281 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]282 cell-index = <0>;
283 compatible = "qcom,spmi-pmic-arb";
284 reg = <0xfc4cf000 0x1000>,
285 <0Xfc4cb000 0x1000>;
286 /* 190,ee0_krait_hlos_spmi_periph_irq */
287 /* 187,channel_0_krait_hlos_trans_done_irq */
288 interrupts = <0 190 0 0 187 0>;
289 qcom,pmic-arb-ee = <0>;
290 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]291 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
292 <0x13100001>, /* PM8941_LDO2 */
293 <0x13200002>, /* PM8941_LDO3 */
294 <0x13300003>, /* PM8941_LDO4 */
295 <0x13400004>, /* PM8941_LDO5 */
296 <0x13500005>, /* PM8941_LDO6 */
297 <0x13600006>, /* PM8941_LDO7 */
298 <0x13700007>, /* PM8941_LDO8 */
299 <0x13800008>, /* PM8941_LDO9 */
300 <0x13900009>, /* PM8941_LDO10 */
301 <0x13a0000a>, /* PM8941_LDO11 */
302 <0x13b0000b>, /* PM8941_LDO12 */
303 <0x13c0000c>, /* PM8941_LDO13 */
304 <0x13d0000d>, /* PM8941_LDO14 */
305 <0x13e0000e>, /* PM8941_LDO15 */
306 <0x13f0000f>, /* PM8941_LDO16 */
307 <0x14000010>, /* PM8941_LDO17 */
308 <0x14100011>, /* PM8941_LDO18 */
309 <0x14200012>, /* PM8941_LDO19 */
310 <0x14300013>, /* PM8941_LDO20 */
311 <0x14400014>, /* PM8941_LDO21 */
312 <0x14500015>, /* PM8941_LDO22 */
313 <0x14600016>, /* PM8941_LDO23 */
314 <0x14700017>, /* PM8941_LDO24 */
315 <0x14800018>, /* PM8941_LDO25 */
316 <0x14900019>, /* PM8941_LDO26 */
317 <0x0c00001a>, /* PM8941_GPIO1 */
318 <0x0c10001b>, /* PM8941_GPIO2 */
319 <0x0c20001c>, /* PM8941_GPIO3 */
320 <0x0c30001d>, /* PM8941_GPIO4 */
321 <0x0c40001e>, /* PM8941_GPIO5 */
322 <0x0c50001f>, /* PM8941_GPIO6 */
323 <0x0c600020>, /* PM8941_GPIO7 */
324 <0x0c700021>, /* PM8941_GPIO8 */
325 <0x0c800022>, /* PM8941_GPIO9 */
326 <0x0c900023>, /* PM8941_GPIO10 */
327 <0x0ca00024>, /* PM8941_GPIO11 */
328 <0x0cb00025>, /* PM8941_GPIO12 */
329 <0x0cc00026>, /* PM8941_GPIO13 */
330 <0x0cd00027>, /* PM8941_GPIO14 */
331 <0x0ce00028>, /* PM8941_GPIO15 */
332 <0x0cf00029>, /* PM8941_GPIO16 */
333 <0x0d00002a>, /* PM8941_GPIO17 */
334 <0x0d10002b>, /* PM8941_GPIO18 */
335 <0x0d20002c>, /* PM8941_GPIO19 */
336 <0x0d30002d>, /* PM8941_GPIO20 */
337 <0x0d40002e>, /* PM8941_GPIO21 */
338 <0x0d50002f>, /* PM8941_GPIO22 */
339 <0x0d600030>, /* PM8941_GPIO23 */
340 <0x0d700031>, /* PM8941_GPIO24 */
341 <0x0d800032>, /* PM8941_GPIO25 */
342 <0x0d900033>, /* PM8941_GPIO26 */
343 <0x0da00034>, /* PM8941_GPIO27 */
344 <0x0db00035>, /* PM8941_GPIO28 */
345 <0x0dc00036>, /* PM8941_GPIO29 */
346 <0x0dd00037>, /* PM8941_GPIO30 */
347 <0x0de00038>, /* PM8941_GPIO31 */
348 <0x0df00039>, /* PM8941_GPIO32 */
349 <0x0e00003a>, /* PM8941_GPIO33 */
350 <0x0e10003b>, /* PM8941_GPIO34 */
351 <0x0e20003c>, /* PM8941_GPIO35 */
352 <0x0e30003d>, /* PM8941_GPIO36 */
353 <0x0280003e>, /* COINCELL */
354 <0x0100003f>, /* SMBC_OVP */
355 <0x01100040>, /* SMBC_CHG */
356 <0x01200041>, /* SMBC_BIF */
357 <0x00500042>, /* INTERRUPT */
358 <0x00100043>, /* PM8941_0 */
359 <0x20100044>, /* PM8841_0 */
360 <0x10100045>, /* PM8941_1 */
361 <0x30100046>, /* PM8841_1 */
362 <0x00800047>, /* PON0 */
363 <0x20800048>, /* PON1 */
364 <0x11000049>, /* PM8941_SMPS1 */
365 <0x1110004a>, /* PM8941_SMPS2 */
366 <0x1120004b>, /* PM8941_SMPS3 */
367 <0x3100004c>, /* PM8841_SMPS1 */
368 <0x3110004d>, /* PM8841_SMPS2 */
369 <0x3120004e>, /* PM8841_SMPS3 */
370 <0x3130004f>, /* PM8841_SMPS4 */
371 <0x31400050>, /* PM8841_SMPS5 */
372 <0x31500051>, /* PM8841_SMPS6 */
373 <0x31600052>, /* PM8841_SMPS7 */
374 <0x31700053>, /* PM8841_SMPS8 */
375 <0x05000054>, /* SHARED_XO */
376 <0x05100055>, /* BB_CLK1 */
377 <0x05200056>, /* BB_CLK2 */
378 <0x05900057>, /* SLEEP_CLK */
379 <0x07000058>, /* PBS_CORE */
380 <0x07100059>, /* PBS_CLIENT1 */
381 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]382 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]383
384 i2c@f9966000 {
385 cell-index = <0>;
386 compatible = "qcom,i2c-qup";
387 reg = <0Xf9966000 0x1000>;
388 reg-names = "qup_phys_addr";
389 interrupts = <0 104 0>;
390 interrupt-names = "qup_err_intr";
391 qcom,i2c-bus-freq = <100000>;
392 qcom,i2c-src-freq = <24000000>;
393 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]394
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]395 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]396 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]397 krait0-supply = <&krait0_vreg>;
398 krait1-supply = <&krait1_vreg>;
399 krait2-supply = <&krait2_vreg>;
400 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]401 krait0_mem-supply = <&pm8841_s1_ao>;
402 krait1_mem-supply = <&pm8841_s1_ao>;
403 krait2_mem-supply = <&pm8841_s1_ao>;
404 krait3_mem-supply = <&pm8841_s1_ao>;
405 krait0_dig-supply = <&pm8841_s2_corner_ao>;
406 krait1_dig-supply = <&pm8841_s2_corner_ao>;
407 krait2_dig-supply = <&pm8841_s2_corner_ao>;
408 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]409 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
410 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
411 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
412 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
413 l2_hfpll_a-supply = <&pm8941_s2_ao>;
414 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
415 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
416 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
417 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
418 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]419 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]420
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]421 qcom,ssusb@f9200000 {
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]422 compatible = "qcom,dwc-usb3-msm";
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]423 reg = <0xf9200000 0xfc000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]424 interrupts = <0 131 0 0 179 0>;
425 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]426 SSUSB_VDDCX-supply = <&pm8841_s2>;
427 SSUSB_1p8-supply = <&pm8941_l6>;
428 HSUSB_VDDCX-supply = <&pm8841_s2>;
429 HSUSB_1p8-supply = <&pm8941_l6>;
430 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]431 qcom,dwc-usb3-msm-dbm-eps = <4>;
432 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]433
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]434 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
435 parent-supply = <&pm8841_s4>;
436 };
437
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]438 qcom,lpass@fe200000 {
439 compatible = "qcom,pil-q6v5-lpass";
440 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]441 <0xfd485100 0x00010>;
442
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]443 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]444 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]445
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]446 qcom,msm-pcm {
447 compatible = "qcom,msm-pcm-dsp";
448 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]449
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]450 qcom,msm-pcm-routing {
451 compatible = "qcom,msm-pcm-routing";
452 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]453
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]454 qcom,msm-pcm-lpa {
455 compatible = "qcom,msm-pcm-lpa";
456 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]457
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]458 qcom,msm-compr-dsp {
459 compatible = "qcom,msm-compr-dsp";
460 };
461
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]462 qcom,msm-voip-dsp {
463 compatible = "qcom,msm-voip-dsp";
464 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]465
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]466 qcom,msm-stub-codec {
467 compatible = "qcom,msm-stub-codec";
468 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]469
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]470 qcom,msm-dai-fe {
471 compatible = "qcom,msm-dai-fe";
472 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]473
Joonwoo Park6572ac52012-07-10 17:17:00 -0700[diff] [blame]474 qcom,msm-dai-q6 {
475 compatible = "qcom,msm-dai-q6";
476 qcom,msm-dai-q6-sb-0-rx {
477 compatible = "qcom,msm-dai-q6-dev";
478 qcom,msm-dai-q6-dev-id = <16384>;
479 };
480
481 qcom,msm-dai-q6-sb-0-tx {
482 compatible = "qcom,msm-dai-q6-dev";
483 qcom,msm-dai-q6-dev-id = <16385>;
484 };
485 };
486
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]487 qcom,msm-auxpcm {
488 compatible = "qcom,msm-auxpcm-resource";
489 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
490 qcom,msm-cpudai-auxpcm-mode = <0>;
491 qcom,msm-cpudai-auxpcm-sync = <1>;
492 qcom,msm-cpudai-auxpcm-frame = <5>;
493 qcom,msm-cpudai-auxpcm-quant = <2>;
494 qcom,msm-cpudai-auxpcm-slot = <1>;
495 qcom,msm-cpudai-auxpcm-data = <0>;
496 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]497
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]498 qcom,msm-auxpcm-rx {
499 qcom,msm-auxpcm-dev-id = <4106>;
500 compatible = "qcom,msm-auxpcm-dev";
501 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]502
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]503 qcom,msm-auxpcm-tx {
504 qcom,msm-auxpcm-dev-id = <4107>;
505 compatible = "qcom,msm-auxpcm-dev";
506 };
507 };
508
509 qcom,msm-pcm-hostless {
510 compatible = "qcom,msm-pcm-hostless";
511 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]512
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700[diff] [blame]513 qcom,msm-ocmem-audio {
514 compatible = "qcom,msm-ocmem-audio";
515 qcom,msm-ocmem-audio-src-id = <11>;
516 qcom,msm-ocmem-audio-dst-id = <604>;
517 qcom,msm-ocmem-audio-ab = <32505856>;
518 qcom,msm-ocmem-audio-ib = <32505856>;
519 };
520
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]521 qcom,mss@fc880000 {
522 compatible = "qcom,pil-q6v5-mss";
523 reg = <0xfc880000 0x100>,
524 <0xfd485000 0x400>,
525 <0xfc820000 0x020>,
Matt Wagantall16bc5cc2012-08-09 21:33:23 -0700[diff] [blame]526 <0xfc401680 0x004>,
527 <0xfc980008 0x004>;
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]528 vdd_mss-supply = <&pm8841_s3>;
529
530 qcom,firmware-name = "mba";
531 qcom,pil-self-auth = <1>;
532 };
533
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]534 qcom,mba@fc820000 {
535 compatible = "qcom,pil-mba";
536 reg = <0xfc820000 0x0020>,
537 <0x0d1fc000 0x4000>;
538
539 qcom,firmware-name = "modem";
540 qcom,depends-on = "mba";
541 };
542
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]543 qcom,pronto@fb21b000 {
544 compatible = "qcom,pil-pronto";
545 reg = <0xfb21b000 0x3000>,
546 <0xfc401700 0x4>,
547 <0xfd485300 0xc>;
548 vdd_pronto_pll-supply = <&pm8941_l12>;
549
550 qcom,firmware-name = "wcnss";
551 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]552
553 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]554 compatible = "qcom,msm-ocmem";
555 reg = <0xfdd00000 0x2000>,
556 <0xfdd02000 0x2000>,
557 <0xfe039000 0x400>,
558 <0xfec00000 0x180000>;
559 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
560 interrupts = <0 76 0 0 77 0>;
561 interrupt-names = "ocmem_irq", "dm_irq";
562 qcom,ocmem-num-regions = <0x3>;
Naveen Ramarajba3a6262012-08-02 17:14:27 -0700[diff] [blame]563 qcom,resource-type = <0x706d636f>;
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]564 #address-cells = <1>;
565 #size-cells = <1>;
566 ranges = <0x0 0xfec00000 0x180000>;
567
568 partition@0 {
569 reg = <0x0 0x100000>;
570 qcom,ocmem-part-name = "graphics";
571 qcom,ocmem-part-min = <0x80000>;
572 };
573
574 partition@80000 {
575 reg = <0x80000 0xA0000>;
576 qcom,ocmem-part-name = "lp_audio";
577 qcom,ocmem-part-min = <0xA0000>;
578 };
579
580 partition@E0000 {
581 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame]582 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]583 qcom,ocmem-part-min = <0x20000>;
584 };
585
586 partition@100000 {
587 reg = <0x100000 0x80000>;
588 qcom,ocmem-part-name = "video";
589 qcom,ocmem-part-min = <0x55000>;
590 };
591
592 partition@140000 {
593 reg = <0x140000 0x40000>;
594 qcom,ocmem-part-name = "sensors";
595 qcom,ocmem-part-min = <0x40000>;
596 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]597 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]598
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]599 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]600 compatible = "qcom,rpm-smd";
601 rpm-channel-name = "rpm_requests";
602 rpm-channel-type = <15>; /* SMD_APPS_RPM */
603 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]604
605 qcom,msm-rng@f9bff000 {
606 compatible = "qcom,msm-rng";
607 reg = <0xf9bff000 0x200>;
608 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]609
610 qcom,qseecom@fe806000 {
611 compatible = "qcom,qseecom";
612 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]613
614 qcom,mdss_mdp@fd900000 {
615 cell-index = <0>;
616 compatible = "qcom,mdss_mdp";
617 reg = <0xfd900000 0x22100>;
618 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]619 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]620 };
621
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]622 mdss_dsi: qcom,mdss_dsi@fd922800 {
623 cell-index = <1>;
624 compatible = "qcom,msm-mdss-dsi";
625 reg = <0xfd922800 0x5ac>,
626 <0xfd8c0000 0x01000>;
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]627 };
628
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]629 qcom,mdss_wb_panel {
630 cell-index = <1>;
631 compatible = "qcom,mdss_wb";
632 qcom,mdss_pan_res = <640 480>;
633 qcom,mdss_pan_bpp = <24>;
634 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]635
636 qcom,wdt@f9017000 {
637 compatible = "qcom,msm-watchdog";
638 reg = <0xf9017000 0x1000>;
639 interrupts = <0 3 0 0 4 0>;
640 qcom,bark-time = <11000>;
641 qcom,pet-time = <10000>;
642 qcom,ipi-ping = <1>;
643 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]644
645 qcom,tz-log@fe805720 {
646 compatible = "qcom,tz-log";
647 reg = <0xfe805720 0x1000>;
648 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]649
650 qcom,venus@fdce0000 {
651 compatible = "qcom,pil-venus";
652 reg = <0xfdce0000 0x4000>,
653 <0xfdc80208 0x8>;
654 vdd-supply = <&gdsc_venus>;
655
656 qcom,firmware-name = "venus";
657 qcom,firmware-min-paddr = <0xF500000>;
658 qcom,firmware-max-paddr = <0xFA00000>;
659 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]660
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700[diff] [blame]661 qcom,cache_erp {
662 compatible = "qcom,cache_erp";
663 interrupts = <1 9 0>, <0 2 0>;
664 interrupt-names = "l1_irq", "l2_irq";
665 };
666
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]667 tsens@fc4a8000 {
668 compatible = "qcom,msm-tsens";
669 reg = <0xfc4a8000 0x2000>,
670 <0xfc4b80d0 0x5>;
671 reg-names = "tsens_physical", "tsens_eeprom_physical";
672 interrupts = <0 184 0>;
673 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700[diff] [blame]674 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
675 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]676 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700[diff] [blame]677
678 qcom,msm-rtb {
679 compatible = "qcom,msm-rtb";
680 qcom,memory-reservation-type = "EBI1";
681 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
682 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]683
684 qcom,qcedev@fd440000 {
685 compatible = "qcom,qcedev";
686 reg = <0xfd440000 0x20000>,
687 <0xfd444000 0x8000>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700[diff] [blame^]688 reg-names = "crypto-base","crypto-bam-base";
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]689 interrupts = <0 235 0>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700[diff] [blame^]690 qcom,bam-pipe-pair = <0>;
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]691 };
692
693 qcom,qcrypto@fd444000 {
694 compatible = "qcom,qcrypto";
695 reg = <0xfd440000 0x20000>,
696 <0xfd444000 0x8000>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700[diff] [blame^]697 reg-names = "crypto-base","crypto-bam-base";
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]698 interrupts = <0 235 0>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700[diff] [blame^]699 qcom,bam-pipe-pair = <1>;
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]700 };
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]701
702 qcom,usbbam@f9304000 {
703 compatible = "qcom,usb-bam-msm";
704 reg = <0xf9304000 0x9000>;
705 interrupts = <0 132 0>;
706 qcom,usb-active-bam = <0>;
707 qcom,usb-total-bam-num = <1>;
708 qcom,usb-bam-num-pipes = <16>;
709 qcom,usb-base-address = <0xf9200000>;
710
711 qcom,pipe1 {
712 label = "usb-to-peri-qdss-dwc3";
713 qcom,usb-bam-type = <0>;
714 qcom,src-bam-physical-address = <0>;
715 qcom,src-bam-pipe-index = <0>;
716 qcom,dst-bam-physical-address = <0>;
717 qcom,dst-bam-pipe-index = <0>;
718 qcom,data-fifo-offset = <0>;
719 qcom,data-fifo-size = <0>;
720 qcom,descriptor-fifo-offset = <0>;
721 qcom,descriptor-fifo-size = <0>;
722 };
723
724 qcom,pipe2 {
725 label = "peri-to-usb-qdss-dwc3";
726 qcom,usb-bam-type = <0>;
727 qcom,src-bam-physical-address = <0xfc37C000>;
728 qcom,src-bam-pipe-index = <0>;
729 qcom,dst-bam-physical-address = <0xf9304000>;
730 qcom,dst-bam-pipe-index = <2>;
731 qcom,data-fifo-offset = <0xf0000>;
732 qcom,data-fifo-size = <0x4000>;
733 qcom,descriptor-fifo-offset = <0xf4000>;
734 qcom,descriptor-fifo-size = <0x1400>;
735 };
736 };
Eugene Seahce52ef22012-07-12 12:40:38 -0600[diff] [blame]737
738 qcom,msm-thermal {
739 compatible = "qcom,msm-thermal";
740 qcom,sensor-id = <0>;
741 qcom,poll-ms = <250>;
742 qcom,limit-temp = <60>;
743 qcom,temp-hysteresis = <10>;
744 qcom,freq-step = <2>;
745 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]746};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]747
748/include/ "msm-pm8x41-rpm-regulator.dtsi"
749/include/ "msm-pm8841.dtsi"
750/include/ "msm-pm8941.dtsi"
751/include/ "msm8974-regulator.dtsi"
752/include/ "msm8974-gpio.dtsi"