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Mike Frysinger5d1617b2008-04-24 05:03:26 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2004-2009 Analog Devices Inc.
3 * 2007 David Rowe
4 * 2006 Intratrade Ltd.
5 * Ivan Danov <idanov@gmail.com>
6 * 2005 National ICT Australia (NICTA)
7 * Aidan Williams <aidan@nicta.com.au>
Mike Frysinger5d1617b2008-04-24 05:03:26 +08008 *
Robin Getz96f10502009-09-24 14:11:24 +00009 * Licensed under the GPL-2 or later.
Mike Frysinger5d1617b2008-04-24 05:03:26 +080010 */
11
12#include <linux/device.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
19#include <linux/usb/isp1362.h>
20#endif
21#include <asm/irq.h>
22#include <asm/bfin5xx_spi.h>
Mike Frysinger99e452e2009-12-03 23:37:07 +000023#include <asm/portmux.h>
Mike Frysinger5d1617b2008-04-24 05:03:26 +080024
25/*
26 * Name the Board for the /proc/cpuinfo
27 */
28const char bfin_board_name[] = "IP04/IP08";
29
30/*
31 * Driver needs to know address, irq and flag pin.
32 */
33#if defined(CONFIG_BFIN532_IP0X)
34#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
35
36#include <linux/dm9000.h>
37
38static struct resource dm9000_resource1[] = {
39 {
40 .start = 0x20100000,
41 .end = 0x20100000 + 1,
42 .flags = IORESOURCE_MEM
43 },{
44 .start = 0x20100000 + 2,
45 .end = 0x20100000 + 3,
46 .flags = IORESOURCE_MEM
47 },{
48 .start = IRQ_PF15,
49 .end = IRQ_PF15,
50 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
51 }
52};
53
54static struct resource dm9000_resource2[] = {
55 {
56 .start = 0x20200000,
57 .end = 0x20200000 + 1,
58 .flags = IORESOURCE_MEM
59 },{
60 .start = 0x20200000 + 2,
61 .end = 0x20200000 + 3,
62 .flags = IORESOURCE_MEM
63 },{
64 .start = IRQ_PF14,
65 .end = IRQ_PF14,
66 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
67 }
68};
69
70/*
71* for the moment we limit ourselves to 16bit IO until some
72* better IO routines can be written and tested
73*/
74static struct dm9000_plat_data dm9000_platdata1 = {
75 .flags = DM9000_PLATF_16BITONLY,
76};
77
78static struct platform_device dm9000_device1 = {
79 .name = "dm9000",
80 .id = 0,
81 .num_resources = ARRAY_SIZE(dm9000_resource1),
82 .resource = dm9000_resource1,
83 .dev = {
84 .platform_data = &dm9000_platdata1,
85 }
86};
87
88static struct dm9000_plat_data dm9000_platdata2 = {
89 .flags = DM9000_PLATF_16BITONLY,
90};
91
92static struct platform_device dm9000_device2 = {
93 .name = "dm9000",
94 .id = 1,
95 .num_resources = ARRAY_SIZE(dm9000_resource2),
96 .resource = dm9000_resource2,
97 .dev = {
98 .platform_data = &dm9000_platdata2,
99 }
100};
101
102#endif
103#endif
104
105
106#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
107/* all SPI peripherals info goes here */
108
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800109#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
110static struct bfin5xx_spi_chip mmc_spi_chip_info = {
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800111 .enable_dma = 0, /* if 1 - block!!! */
112 .bits_per_word = 8,
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800113};
114#endif
115
116/* Notice: for blackfin, the speed_hz is the value of register
117 * SPI_BAUD, not the real baudrate */
118static struct spi_board_info bfin_spi_board_info[] __initdata = {
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800119#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800120 {
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800121 .modalias = "mmc_spi",
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800122 .max_speed_hz = 2,
123 .bus_num = 1,
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800124 .chip_select = 5,
125 .controller_data = &mmc_spi_chip_info,
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800126 },
127#endif
128};
129
130/* SPI controller data */
131static struct bfin5xx_spi_master spi_bfin_master_info = {
132 .num_chipselect = 8,
133 .enable_dma = 1, /* master has the ability to do dma transfer */
134};
135
136static struct platform_device spi_bfin_master_device = {
137 .name = "bfin-spi-master",
138 .id = 1, /* Bus number */
139 .dev = {
140 .platform_data = &spi_bfin_master_info, /* Passed to driver */
141 },
142};
143#endif /* spi master and devices */
144
145#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
146static struct resource bfin_uart_resources[] = {
147 {
148 .start = 0xFFC00400,
149 .end = 0xFFC004FF,
150 .flags = IORESOURCE_MEM,
151 },
152};
153
154static struct platform_device bfin_uart_device = {
155 .name = "bfin-uart",
156 .id = 1,
157 .num_resources = ARRAY_SIZE(bfin_uart_resources),
158 .resource = bfin_uart_resources,
159};
160#endif
161
Graf Yang5be36d22008-04-25 03:09:15 +0800162#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang5be36d22008-04-25 03:09:15 +0800163#ifdef CONFIG_BFIN_SIR0
Graf Yang42bd8bc2009-01-07 23:14:39 +0800164static struct resource bfin_sir0_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800165 {
166 .start = 0xFFC00400,
167 .end = 0xFFC004FF,
168 .flags = IORESOURCE_MEM,
169 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800170 {
171 .start = IRQ_UART0_RX,
172 .end = IRQ_UART0_RX+1,
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .start = CH_UART0_RX,
177 .end = CH_UART0_RX+1,
178 .flags = IORESOURCE_DMA,
179 },
Graf Yang5be36d22008-04-25 03:09:15 +0800180};
181
Graf Yang42bd8bc2009-01-07 23:14:39 +0800182static struct platform_device bfin_sir0_device = {
Graf Yang5be36d22008-04-25 03:09:15 +0800183 .name = "bfin_sir",
184 .id = 0,
Graf Yang42bd8bc2009-01-07 23:14:39 +0800185 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
186 .resource = bfin_sir0_resources,
Graf Yang5be36d22008-04-25 03:09:15 +0800187};
188#endif
Graf Yang42bd8bc2009-01-07 23:14:39 +0800189#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800190
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800191#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
192static struct resource isp1362_hcd_resources[] = {
193 {
194 .start = 0x20300000,
195 .end = 0x20300000 + 1,
196 .flags = IORESOURCE_MEM,
197 },{
198 .start = 0x20300000 + 2,
199 .end = 0x20300000 + 3,
200 .flags = IORESOURCE_MEM,
201 },{
202 .start = IRQ_PF11,
203 .end = IRQ_PF11,
204 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
205 },
206};
207
208static struct isp1362_platform_data isp1362_priv = {
209 .sel15Kres = 1,
210 .clknotstop = 0,
211 .oc_enable = 0, /* external OC */
212 .int_act_high = 0,
213 .int_edge_triggered = 0,
214 .remote_wakeup_connected = 0,
215 .no_power_switching = 1,
216 .power_switching_mode = 0,
217};
218
219static struct platform_device isp1362_hcd_device = {
220 .name = "isp1362-hcd",
221 .id = 0,
222 .dev = {
223 .platform_data = &isp1362_priv,
224 },
225 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
226 .resource = isp1362_hcd_resources,
227};
228#endif
229
230
231static struct platform_device *ip0x_devices[] __initdata = {
232#if defined(CONFIG_BFIN532_IP0X)
233#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
234 &dm9000_device1,
235 &dm9000_device2,
236#endif
237#endif
238
239#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
240 &spi_bfin_master_device,
241#endif
242
243#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
244 &bfin_uart_device,
245#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800246
247#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang42bd8bc2009-01-07 23:14:39 +0800248#ifdef CONFIG_BFIN_SIR0
249 &bfin_sir0_device,
250#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800251#endif
252
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800253#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
254 &isp1362_hcd_device,
255#endif
256};
257
258static int __init ip0x_init(void)
259{
260 int i;
261
262 printk(KERN_INFO "%s(): registering device resources\n", __func__);
263 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
264
265#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
266 for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
267 int j = 1 << bfin_spi_board_info[i].chip_select;
268 /* set spi cs to 1 */
269 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
270 bfin_write_FIO_FLAG_S(j);
271 }
272 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
273#endif
274
275 return 0;
276}
277
278arch_initcall(ip0x_init);