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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _INTELFB_H
2#define _INTELFB_H
3
4/* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */
5
6#include <linux/agp_backend.h>
7#include <linux/fb.h>
8
9
10/*** Version/name ***/
Dave Airlie9a906032006-03-23 21:53:05 +110011#define INTELFB_VERSION "0.9.4"
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#define INTELFB_MODULE_NAME "intelfb"
Dave Airlie9a906032006-03-23 21:53:05 +110013#define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM"
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15
16/*** Debug/feature defines ***/
17
18#ifndef DEBUG
19#define DEBUG 0
20#endif
21
22#ifndef VERBOSE
23#define VERBOSE 0
24#endif
25
26#ifndef REGDUMP
27#define REGDUMP 0
28#endif
29
30#ifndef DETECT_VGA_CLASS_ONLY
31#define DETECT_VGA_CLASS_ONLY 1
32#endif
33
34#ifndef ALLOCATE_FOR_PANNING
35#define ALLOCATE_FOR_PANNING 1
36#endif
37
38#ifndef PREFERRED_MODE
39#define PREFERRED_MODE "1024x768-32@70"
40#endif
41
42/*** hw-related values ***/
43
Antonino A. Daplas4b3760c2005-12-19 15:11:40 +080044/* Resource Allocation */
45#define INTELFB_FB_ACQUIRED 1
46#define INTELFB_MMIO_ACQUIRED 2
47
Linus Torvalds1da177e2005-04-16 15:20:36 -070048/* PCI ids for supported devices */
49#define PCI_DEVICE_ID_INTEL_830M 0x3577
50#define PCI_DEVICE_ID_INTEL_845G 0x2562
51#define PCI_DEVICE_ID_INTEL_85XGM 0x3582
52#define PCI_DEVICE_ID_INTEL_865G 0x2572
53#define PCI_DEVICE_ID_INTEL_915G 0x2582
Scott MacKenzie3a590262005-11-07 01:00:33 -080054#define PCI_DEVICE_ID_INTEL_915GM 0x2592
Dave Airlie9639d5e2006-03-23 11:23:55 +110055#define PCI_DEVICE_ID_INTEL_945G 0x2772
Dave Airlie9a906032006-03-23 21:53:05 +110056#define PCI_DEVICE_ID_INTEL_945GM 0x27A2
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
58/* Size of MMIO region */
59#define INTEL_REG_SIZE 0x80000
60
61#define STRIDE_ALIGNMENT 16
Dennis Munsiedf7df8a2006-05-27 18:17:52 +100062#define STRIDE_ALIGNMENT_I9XX 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
64#define PALETTE_8_ENTRIES 256
65
66
67/*** Macros ***/
68
69/* basic arithmetic */
70#define KB(x) ((x) * 1024)
71#define MB(x) ((x) * 1024 * 1024)
72#define BtoKB(x) ((x) / 1024)
73#define BtoMB(x) ((x) / 1024 / 1024)
74
75#define GTT_PAGE_SIZE KB(4)
76
77#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
78#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
79#define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE)
80#define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE)
81
82/* messages */
83#define PFX INTELFB_MODULE_NAME ": "
84
85#define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args)
86#define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args)
87#define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args)
88#define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args)
89#if DEBUG
90#define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args)
91#else
92#define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args)
93#endif
94
95/* get commonly used pointers */
96#define GET_DINFO(info) (info)->par
97
98/* misc macros */
99#define ACCEL(d, i) \
100 ((d)->accel && !(d)->ring_lockup && \
101 ((i)->var.accel_flags & FB_ACCELF_TEXT))
102
103/*#define NOACCEL_CHIPSET(d) \
104 ((d)->chipset != INTEL_865G)*/
105#define NOACCEL_CHIPSET(d) \
106 (0)
107
108#define FIXED_MODE(d) ((d)->fixed_mode)
109
110/*** Driver paramters ***/
111
112#define RINGBUFFER_SIZE KB(64)
113#define HW_CURSOR_SIZE KB(4)
114
115/* Intel agpgart driver */
116#define AGP_PHYSICAL_MEMORY 2
117
118/*** Data Types ***/
119
120/* supported chipsets */
121enum intel_chips {
122 INTEL_830M,
123 INTEL_845G,
124 INTEL_85XGM,
125 INTEL_852GM,
126 INTEL_852GME,
127 INTEL_855GM,
128 INTEL_855GME,
129 INTEL_865G,
Scott MacKenzie3a590262005-11-07 01:00:33 -0800130 INTEL_915G,
Dave Airlie9639d5e2006-03-23 11:23:55 +1100131 INTEL_915GM,
Dave Airlie9a906032006-03-23 21:53:05 +1100132 INTEL_945G,
133 INTEL_945GM,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134};
135
136struct intelfb_hwstate {
137 u32 vga0_divisor;
138 u32 vga1_divisor;
139 u32 vga_pd;
140 u32 dpll_a;
141 u32 dpll_b;
142 u32 fpa0;
143 u32 fpa1;
144 u32 fpb0;
145 u32 fpb1;
146 u32 palette_a[PALETTE_8_ENTRIES];
147 u32 palette_b[PALETTE_8_ENTRIES];
148 u32 htotal_a;
149 u32 hblank_a;
150 u32 hsync_a;
151 u32 vtotal_a;
152 u32 vblank_a;
153 u32 vsync_a;
154 u32 src_size_a;
155 u32 bclrpat_a;
156 u32 htotal_b;
157 u32 hblank_b;
158 u32 hsync_b;
159 u32 vtotal_b;
160 u32 vblank_b;
161 u32 vsync_b;
162 u32 src_size_b;
163 u32 bclrpat_b;
164 u32 adpa;
165 u32 dvoa;
166 u32 dvob;
167 u32 dvoc;
168 u32 dvoa_srcdim;
169 u32 dvob_srcdim;
170 u32 dvoc_srcdim;
171 u32 lvds;
172 u32 pipe_a_conf;
173 u32 pipe_b_conf;
174 u32 disp_arb;
175 u32 cursor_a_control;
176 u32 cursor_b_control;
177 u32 cursor_a_base;
178 u32 cursor_b_base;
179 u32 cursor_size;
180 u32 disp_a_ctrl;
181 u32 disp_b_ctrl;
182 u32 disp_a_base;
183 u32 disp_b_base;
184 u32 cursor_a_palette[4];
185 u32 cursor_b_palette[4];
186 u32 disp_a_stride;
187 u32 disp_b_stride;
188 u32 vgacntrl;
189 u32 add_id;
190 u32 swf0x[7];
191 u32 swf1x[7];
192 u32 swf3x[3];
193 u32 fence[8];
194 u32 instpm;
195 u32 mem_mode;
196 u32 fw_blc_0;
197 u32 fw_blc_1;
Eric Hustvedt9a5f0192006-06-20 14:36:41 -0400198 u16 hwstam;
199 u16 ier;
200 u16 iir;
201 u16 imr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202};
203
204struct intelfb_heap_data {
205 u32 physical;
206 u8 __iomem *virtual;
207 u32 offset; // in GATT pages
208 u32 size; // in bytes
209};
210
211struct intelfb_info {
212 struct fb_info *info;
213 struct fb_ops *fbops;
214 struct pci_dev *pdev;
215
216 struct intelfb_hwstate save_state;
217
218 /* agpgart structs */
219 struct agp_memory *gtt_fb_mem; // use all stolen memory or vram
220 struct agp_memory *gtt_ring_mem; // ring buffer
221 struct agp_memory *gtt_cursor_mem; // hw cursor
222
223 /* use a gart reserved fb mem */
224 u8 fbmem_gart;
225
226 /* mtrr support */
227 u32 mtrr_reg;
228 u32 has_mtrr;
229
230 /* heap data */
231 struct intelfb_heap_data aperture;
232 struct intelfb_heap_data fb;
233 struct intelfb_heap_data ring;
234 struct intelfb_heap_data cursor;
235
236 /* mmio regs */
237 u32 mmio_base_phys;
238 u8 __iomem *mmio_base;
239
240 /* fb start offset (in bytes) */
241 u32 fb_start;
242
243 /* ring buffer */
Al Viro0fe6e2d2006-06-23 06:05:39 +0100244 u32 ring_head;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 u32 ring_tail;
246 u32 ring_tail_mask;
247 u32 ring_space;
248 u32 ring_lockup;
249
250 /* palette */
251 u32 pseudo_palette[17];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
253 /* chip info */
254 int pci_chipset;
255 int chipset;
256 const char *name;
257 int mobile;
258
259 /* current mode */
260 int bpp, depth;
261 u32 visual;
262 int xres, yres, pitch;
263 int pixclock;
264
265 /* current pipe */
266 int pipe;
267
268 /* some flags */
269 int accel;
270 int hwcursor;
271 int fixed_mode;
272 int ring_active;
Antonino A. Daplas4b3760c2005-12-19 15:11:40 +0800273 int flag;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
275 /* hw cursor */
276 int cursor_on;
277 int cursor_blanked;
278 u8 cursor_src[64];
279
280 /* initial parameters */
281 int initial_vga;
282 struct fb_var_screeninfo initial_var;
283 u32 initial_fb_base;
284 u32 initial_video_ram;
285 u32 initial_pitch;
286
287 /* driver registered */
288 int registered;
Dave Airlied0249602006-03-20 20:26:45 +1100289
290 /* index into plls */
291 int pll_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292};
293
Dave Airlie3aff13c2006-03-31 17:08:52 +1000294#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))
Dave Airlie8bb91f62006-03-23 13:06:32 +1100295
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296/*** function prototypes ***/
297
298extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
299
300#endif /* _INTELFB_H */