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review.evervolv.com / android_kernel_htc_msm8960 / 9ad5897c2659b3c610e0c717e8b3dbfb496d2c74 / . / include / asm-arm / arch-omap / dma.h
blob: ccbcb580a5c17b90326c8c9c679cfe737d0d908d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * linux/include/asm-arm/arch-omap/dma.h
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#define MAX_DMA_ADDRESS 0xffffffff
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]25#define MAX_DMA_CHANNELS 0
26
27/* Hardware registers for omap1 */
28#define OMAP_DMA_BASE (0xfffed800)
29#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
30#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
31#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
32#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
33#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
34#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
35#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
36#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
37#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
38#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
39#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
40#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
41#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
42#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
43#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
44#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
45#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
46#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
47#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
48#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
49
50/* Hardware registers for omap2 */
51#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
52#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
53#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
54#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
55#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
56#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
57#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
58#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
59#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
60#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
61#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
62#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
63#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
64#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
65#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
66#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
67
68#ifdef CONFIG_ARCH_OMAP1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]69
70#define OMAP_LOGICAL_DMA_CH_COUNT 17
71
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]72/* Common channel specific registers for omap1 */
73#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
74#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
75#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
76#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
77#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
78#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
79#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
80#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
81#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
82#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
83#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
84#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
85#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
86
87#else
88
89#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
90
91/* Common channel specific registers for omap2 */
92#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
93#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
94#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
95#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
96#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
97#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
98#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
99#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
100#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
101#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
102#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
103#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
104#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
105
106#endif
107
108/* Channel specific registers only on omap1 */
109#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
110#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
111#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
112#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
113#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
114#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
115#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
116#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
117
118/* Channel specific registers only on omap2 */
119#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
120#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
121#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
122#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
123#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
124
125/*----------------------------------------------------------------------------*/
126
127/* DMA channels for omap1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]128#define OMAP_DMA_NO_DEVICE 0
129#define OMAP_DMA_MCSI1_TX 1
130#define OMAP_DMA_MCSI1_RX 2
131#define OMAP_DMA_I2C_RX 3
132#define OMAP_DMA_I2C_TX 4
133#define OMAP_DMA_EXT_NDMA_REQ 5
134#define OMAP_DMA_EXT_NDMA_REQ2 6
135#define OMAP_DMA_UWIRE_TX 7
136#define OMAP_DMA_MCBSP1_TX 8
137#define OMAP_DMA_MCBSP1_RX 9
138#define OMAP_DMA_MCBSP3_TX 10
139#define OMAP_DMA_MCBSP3_RX 11
140#define OMAP_DMA_UART1_TX 12
141#define OMAP_DMA_UART1_RX 13
142#define OMAP_DMA_UART2_TX 14
143#define OMAP_DMA_UART2_RX 15
144#define OMAP_DMA_MCBSP2_TX 16
145#define OMAP_DMA_MCBSP2_RX 17
146#define OMAP_DMA_UART3_TX 18
147#define OMAP_DMA_UART3_RX 19
148#define OMAP_DMA_CAMERA_IF_RX 20
149#define OMAP_DMA_MMC_TX 21
150#define OMAP_DMA_MMC_RX 22
151#define OMAP_DMA_NAND 23
152#define OMAP_DMA_IRQ_LCD_LINE 24
153#define OMAP_DMA_MEMORY_STICK 25
154#define OMAP_DMA_USB_W2FC_RX0 26
155#define OMAP_DMA_USB_W2FC_RX1 27
156#define OMAP_DMA_USB_W2FC_RX2 28
157#define OMAP_DMA_USB_W2FC_TX0 29
158#define OMAP_DMA_USB_W2FC_TX1 30
159#define OMAP_DMA_USB_W2FC_TX2 31
160
161/* These are only for 1610 */
162#define OMAP_DMA_CRYPTO_DES_IN 32
163#define OMAP_DMA_SPI_TX 33
164#define OMAP_DMA_SPI_RX 34
165#define OMAP_DMA_CRYPTO_HASH 35
166#define OMAP_DMA_CCP_ATTN 36
167#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
168#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
169#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
170#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
171#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
172#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
173#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
174#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
175#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
176#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
177#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
178#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
179#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
180#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
181#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
182#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
183#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
184#define OMAP_DMA_MMC2_TX 54
185#define OMAP_DMA_MMC2_RX 55
186#define OMAP_DMA_CRYPTO_DES_OUT 56
187
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]188/* DMA channels for 24xx */
189#define OMAP24XX_DMA_NO_DEVICE 0
190#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
191#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */
192#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */
193#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
194#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
195#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
196#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */
197#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
198#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
199#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
200#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
201#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
202#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]203
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]204#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
205#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
206#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
207#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
208#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
209#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
210#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
211#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
212#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
213#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
214#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
215#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
216#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
217#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
218#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */
219#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */
220#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */
221#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */
222#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */
223#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */
224#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */
225#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */
226#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */
227#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */
228#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */
229#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */
230#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */
231#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */
232#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */
233#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]234
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]235#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */
236#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */
237#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */
238#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */
239#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */
240#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */
241#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */
242#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */
243#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */
244#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */
245#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */
246#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */
247#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
248#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
249#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
250
251/*----------------------------------------------------------------------------*/
252
253/* Hardware registers for LCD DMA */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]254#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
255#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
256#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
257#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
258#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
259#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
260
261#define OMAP1610_DMA_LCD_BASE (0xfffee300)
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]262#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]263#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
264#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
265#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
266#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
267#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
268#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
269#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
270#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
271#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
272#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
273#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
274#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
275#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
276#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
277#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
278#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
279
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]280#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]281#define OMAP_DMA_DROP_IRQ (1 << 1)
282#define OMAP_DMA_HALF_IRQ (1 << 2)
283#define OMAP_DMA_FRAME_IRQ (1 << 3)
284#define OMAP_DMA_LAST_IRQ (1 << 4)
285#define OMAP_DMA_BLOCK_IRQ (1 << 5)
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]286#define OMAP1_DMA_SYNC_IRQ (1 << 6)
287#define OMAP2_DMA_PKT_IRQ (1 << 7)
288#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
289#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
290#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
291#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]292
293#define OMAP_DMA_DATA_TYPE_S8 0x00
294#define OMAP_DMA_DATA_TYPE_S16 0x01
295#define OMAP_DMA_DATA_TYPE_S32 0x02
296
297#define OMAP_DMA_SYNC_ELEMENT 0x00
298#define OMAP_DMA_SYNC_FRAME 0x01
299#define OMAP_DMA_SYNC_BLOCK 0x02
300
301#define OMAP_DMA_PORT_EMIFF 0x00
302#define OMAP_DMA_PORT_EMIFS 0x01
303#define OMAP_DMA_PORT_OCP_T1 0x02
304#define OMAP_DMA_PORT_TIPB 0x03
305#define OMAP_DMA_PORT_OCP_T2 0x04
306#define OMAP_DMA_PORT_MPUI 0x05
307
308#define OMAP_DMA_AMODE_CONSTANT 0x00
309#define OMAP_DMA_AMODE_POST_INC 0x01
310#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
311#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
312
313/* LCD DMA block numbers */
314enum {
315 OMAP_LCD_DMA_B1_TOP,
316 OMAP_LCD_DMA_B1_BOTTOM,
317 OMAP_LCD_DMA_B2_TOP,
318 OMAP_LCD_DMA_B2_BOTTOM
319};
320
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]321/* REVISIT: Check if BURST_4 is really 1 (or 2) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]322enum omap_dma_burst_mode {
323 OMAP_DMA_DATA_BURST_DIS = 0,
324 OMAP_DMA_DATA_BURST_4,
325 OMAP_DMA_DATA_BURST_8
326};
327
328enum omap_dma_color_mode {
329 OMAP_DMA_COLOR_DIS = 0,
330 OMAP_DMA_CONSTANT_FILL,
331 OMAP_DMA_TRANSPARENT_COPY
332};
333
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]334struct omap_dma_channel_params {
335 int data_type; /* data type 8,16,32 */
336 int elem_count; /* number of elements in a frame */
337 int frame_count; /* number of frames in a element */
338
339 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
340 int src_amode; /* constant , post increment, indexed , double indexed */
341 int src_start; /* source address : physical */
342 int src_ei; /* source element index */
343 int src_fi; /* source frame index */
344
345 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
346 int dst_amode; /* constant , post increment, indexed , double indexed */
347 int dst_start; /* source address : physical */
348 int dst_ei; /* source element index */
349 int dst_fi; /* source frame index */
350
351 int trigger; /* trigger attached if the channel is synchronized */
352 int sync_mode; /* sycn on element, frame , block or packet */
353 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
354
355 int ie; /* interrupt enabled */
356};
357
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]359extern void omap_set_dma_priority(int dst_port, int priority);
360extern int omap_request_dma(int dev_id, const char *dev_name,
361 void (* callback)(int lch, u16 ch_status, void *data),
362 void *data, int *dma_ch);
363extern void omap_enable_dma_irq(int ch, u16 irq_bits);
364extern void omap_disable_dma_irq(int ch, u16 irq_bits);
365extern void omap_free_dma(int ch);
366extern void omap_start_dma(int lch);
367extern void omap_stop_dma(int lch);
368extern void omap_set_dma_transfer_params(int lch, int data_type,
369 int elem_count, int frame_count,
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]370 int sync_mode,
371 int dma_trigger, int src_or_dst_synch);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]372extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
373 u32 color);
374
375extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]376 unsigned long src_start,
377 int src_ei, int src_fi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]378extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
379extern void omap_set_dma_src_data_pack(int lch, int enable);
380extern void omap_set_dma_src_burst_mode(int lch,
381 enum omap_dma_burst_mode burst_mode);
382
383extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]384 unsigned long dest_start,
385 int dst_ei, int dst_fi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]386extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
387extern void omap_set_dma_dest_data_pack(int lch, int enable);
388extern void omap_set_dma_dest_burst_mode(int lch,
389 enum omap_dma_burst_mode burst_mode);
390
Tony Lindgren9ad58972005-11-10 14:26:53 +0000[diff] [blame^]391extern void omap_set_dma_params(int lch,
392 struct omap_dma_channel_params * params);
393
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]394extern void omap_dma_link_lch (int lch_head, int lch_queue);
395extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
396
397extern dma_addr_t omap_get_dma_src_pos(int lch);
398extern dma_addr_t omap_get_dma_dst_pos(int lch);
Tony Lindgren9839c6b2005-09-07 17:20:27 +0100[diff] [blame]399extern int omap_get_dma_src_addr_counter(int lch);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]400extern void omap_clear_dma(int lch);
Tony Lindgrenbb13b5f2005-07-10 19:58:18 +0100[diff] [blame]401extern int omap_dma_running(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]402
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]403/* LCD DMA functions */
404extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
405 void *data);
406extern void omap_free_lcd_dma(void);
407extern void omap_setup_lcd_dma(void);
408extern void omap_enable_lcd_dma(void);
409extern void omap_stop_lcd_dma(void);
410extern void omap_set_lcd_dma_ext_controller(int external);
411extern void omap_set_lcd_dma_single_transfer(int single);
412extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
413 int data_type);
414extern void omap_set_lcd_dma_b1_rotation(int rotate);
415extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
416extern void omap_set_lcd_dma_b1_mirror(int mirror);
417extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
418
419#endif /* __ASM_ARCH_DMA_H */