| Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. |
| 3 | * |
| 4 | * Authors: Shlomi Gridish <gridish@freescale.com> |
| 5 | * Li Yang <leoli@freescale.com> |
| 6 | * |
| 7 | * Description: |
| 8 | * Internal header file for UCC unit routines. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | */ |
| 15 | #ifndef __UCC_H__ |
| 16 | #define __UCC_H__ |
| 17 | |
| 18 | #include <asm/immap_qe.h> |
| 19 | #include <asm/qe.h> |
| 20 | |
| 21 | #define STATISTICS |
| 22 | |
| 23 | #define UCC_MAX_NUM 8 |
| 24 | |
| 25 | /* Slow or fast type for UCCs. |
| 26 | */ |
| 27 | enum ucc_speed_type { |
| 28 | UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW |
| 29 | }; |
| 30 | |
| 31 | /* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR). |
| 32 | */ |
| 33 | enum ucc_pram_initial_offset { |
| 34 | UCC_PRAM_OFFSET_UCC1 = 0x8400, |
| 35 | UCC_PRAM_OFFSET_UCC2 = 0x8500, |
| 36 | UCC_PRAM_OFFSET_UCC3 = 0x8600, |
| 37 | UCC_PRAM_OFFSET_UCC4 = 0x9000, |
| 38 | UCC_PRAM_OFFSET_UCC5 = 0x8000, |
| 39 | UCC_PRAM_OFFSET_UCC6 = 0x8100, |
| 40 | UCC_PRAM_OFFSET_UCC7 = 0x8200, |
| 41 | UCC_PRAM_OFFSET_UCC8 = 0x8300 |
| 42 | }; |
| 43 | |
| 44 | /* ucc_set_type |
| 45 | * Sets UCC to slow or fast mode. |
| 46 | * |
| 47 | * ucc_num - (In) number of UCC (0-7). |
| 48 | * regs - (In) pointer to registers base for the UCC. |
| 49 | * speed - (In) slow or fast mode for UCC. |
| 50 | */ |
| 51 | int ucc_set_type(int ucc_num, struct ucc_common *regs, |
| 52 | enum ucc_speed_type speed); |
| 53 | |
| 54 | /* ucc_init_guemr |
| 55 | * Init the Guemr register. |
| 56 | * |
| 57 | * regs - (In) pointer to registers base for the UCC. |
| 58 | */ |
| 59 | int ucc_init_guemr(struct ucc_common *regs); |
| 60 | |
| 61 | int ucc_set_qe_mux_mii_mng(int ucc_num); |
| 62 | |
| 63 | int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode); |
| 64 | |
| 65 | int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask); |
| 66 | |
| 67 | /* QE MUX clock routing for UCC |
| 68 | */ |
| 69 | static inline int ucc_set_qe_mux_grant(int ucc_num, int set) |
| 70 | { |
| 71 | return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT); |
| 72 | } |
| 73 | |
| 74 | static inline int ucc_set_qe_mux_tsa(int ucc_num, int set) |
| 75 | { |
| 76 | return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA); |
| 77 | } |
| 78 | |
| 79 | static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set) |
| 80 | { |
| 81 | return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT); |
| 82 | } |
| 83 | |
| 84 | #endif /* __UCC_H__ */ |