Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 9c07082b8d70190813bc27dd430dbb2b41a1a44b / . / drivers / gpu / msm / kgsl_iommu.h
blob: 6e049964e489189982ccba07da0010cac804b1e5 [file] [log] [blame]
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#ifndef __KGSL_IOMMU_H
14#define __KGSL_IOMMU_H
15
16#include <mach/iommu.h>
17
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]18#define KGSL_IOMMU_CTX_OFFSET_V1 0
Shubhraprakash Das15a8b462012-08-16 23:24:28 -0700[diff] [blame]19#define KGSL_IOMMU_CTX_OFFSET_V2 0x8000
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]20#define KGSL_IOMMU_CTX_SHIFT 12
Jordan Crouse95b68472012-05-25 10:25:01 -0600[diff] [blame]21
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]22enum kgsl_iommu_reg_map {
23 KGSL_IOMMU_GLOBAL_BASE = 0,
24 KGSL_IOMMU_CTX_TTBR0,
25 KGSL_IOMMU_CTX_TTBR1,
26 KGSL_IOMMU_CTX_FSR,
27 KGSL_IOMMU_CTX_TLBIALL,
Shubhraprakash Das2747cf62012-09-27 23:05:43 -0700[diff] [blame]28 KGSL_IOMMU_CTX_RESUME,
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]29 KGSL_IOMMU_REG_MAX
30};
31
32struct kgsl_iommu_register_list {
33 unsigned int reg_offset;
34 unsigned int reg_mask;
35 unsigned int reg_shift;
36};
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]37
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]38/*
39 * Max number of iommu units that the gpu core can have
40 * On APQ8064, KGSL can control a maximum of 2 IOMMU units.
41 */
42#define KGSL_IOMMU_MAX_UNITS 2
43
44/* Max number of iommu contexts per IOMMU unit */
45#define KGSL_IOMMU_MAX_DEVS_PER_UNIT 2
46
Shubhraprakash Dasd8cbcd12012-05-07 16:11:32 -0600[diff] [blame]47/* Macros to read/write IOMMU registers */
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]48#define KGSL_IOMMU_SET_CTX_REG(iommu, iommu_unit, ctx, REG, val) \
49 writel_relaxed(val, \
50 iommu_unit->reg_map.hostptr + \
51 iommu->iommu_reg_list[KGSL_IOMMU_CTX_##REG].reg_offset +\
52 (ctx << KGSL_IOMMU_CTX_SHIFT) + \
53 iommu->ctx_offset)
Shubhraprakash Dasd8cbcd12012-05-07 16:11:32 -0600[diff] [blame]54
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]55#define KGSL_IOMMU_GET_CTX_REG(iommu, iommu_unit, ctx, REG) \
56 readl_relaxed( \
57 iommu_unit->reg_map.hostptr + \
58 iommu->iommu_reg_list[KGSL_IOMMU_CTX_##REG].reg_offset +\
59 (ctx << KGSL_IOMMU_CTX_SHIFT) + \
60 iommu->ctx_offset)
Shubhraprakash Dasd8cbcd12012-05-07 16:11:32 -0600[diff] [blame]61
62/* Gets the lsb value of pagetable */
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]63#define KGSL_IOMMMU_PT_LSB(iommu, pt_val) \
64 (pt_val & \
65 ~(iommu->iommu_reg_list[KGSL_IOMMU_CTX_TTBR0].reg_mask << \
66 iommu->iommu_reg_list[KGSL_IOMMU_CTX_TTBR0].reg_shift))
Shubhraprakash Dasd8cbcd12012-05-07 16:11:32 -0600[diff] [blame]67
Shubhraprakash Dase9541a32012-05-09 22:25:55 -0600[diff] [blame]68/* offset at which a nop command is placed in setstate_memory */
69#define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024
70
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]71/*
72 * struct kgsl_iommu_device - Structure holding data about iommu contexts
73 * @dev: Device pointer to iommu context
74 * @attached: Indicates whether this iommu context is presently attached to
75 * a pagetable/domain or not
76 * @pt_lsb: The LSB of IOMMU_TTBR0 register which is the pagetable
77 * register
78 * @ctx_id: This iommu units context id. It can be either 0 or 1
79 * @clk_enabled: If set indicates that iommu clocks of this iommu context
80 * are on, else the clocks are off
Shubhraprakash Das2747cf62012-09-27 23:05:43 -0700[diff] [blame]81 * fault: Flag when set indicates that this iommu device has caused a page
82 * fault
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]83 */
84struct kgsl_iommu_device {
85 struct device *dev;
86 bool attached;
87 unsigned int pt_lsb;
88 enum kgsl_iommu_context_id ctx_id;
89 bool clk_enabled;
Jordan Crouse95b68472012-05-25 10:25:01 -0600[diff] [blame]90 struct kgsl_device *kgsldev;
Shubhraprakash Das2747cf62012-09-27 23:05:43 -0700[diff] [blame]91 int fault;
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]92};
93
94/*
95 * struct kgsl_iommu_unit - Structure holding data about iommu units. An IOMMU
96 * units is basically a separte IOMMU h/w block with it's own IOMMU contexts
97 * @dev: Pointer to array of struct kgsl_iommu_device which has information
98 * about the IOMMU contexts under this IOMMU unit
99 * @dev_count: Number of IOMMU contexts that are valid in the previous feild
100 * @reg_map: Memory descriptor which holds the mapped address of this IOMMU
101 * units register range
102 */
103struct kgsl_iommu_unit {
104 struct kgsl_iommu_device dev[KGSL_IOMMU_MAX_DEVS_PER_UNIT];
105 unsigned int dev_count;
106 struct kgsl_memdesc reg_map;
107};
108
109/*
110 * struct kgsl_iommu - Structure holding iommu data for kgsl driver
111 * @dev: Array of kgsl_iommu_device which contain information about
112 * iommu contexts owned by graphics cores
113 * @unit_count: Number of IOMMU units that are available for this
114 * instance of the IOMMU driver
115 * @iommu_last_cmd_ts: The timestamp of last command submitted that
116 * aceeses iommu registers
Shubhraprakash Dascb068072012-06-07 17:52:41 -0600[diff] [blame]117 * @clk_event_queued: Indicates whether an event to disable clocks
118 * is already queued or not
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]119 * @device: Pointer to kgsl device
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]120 * @ctx_offset: The context offset to be added to base address when
121 * accessing IOMMU registers
122 * @iommu_reg_list: List of IOMMU registers { offset, map, shift } array
Tarun Karra9c070822012-11-27 16:43:51 -0700[diff] [blame^]123 * @sync_lock_vars: Pointer to the IOMMU spinlock for serializing access to the
124 * IOMMU registers
125 * @sync_lock_desc: GPU Memory descriptor for the memory containing the
126 * spinlocks
127 * @sync_lock_initialized: True if the sync_lock feature is enabled
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]128 */
129struct kgsl_iommu {
130 struct kgsl_iommu_unit iommu_units[KGSL_IOMMU_MAX_UNITS];
131 unsigned int unit_count;
132 unsigned int iommu_last_cmd_ts;
Shubhraprakash Dascb068072012-06-07 17:52:41 -0600[diff] [blame]133 bool clk_event_queued;
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]134 struct kgsl_device *device;
Shubhraprakash Das3cf33be2012-08-16 22:42:55 -0700[diff] [blame]135 unsigned int ctx_offset;
136 struct kgsl_iommu_register_list *iommu_reg_list;
Tarun Karra9c070822012-11-27 16:43:51 -0700[diff] [blame^]137 struct remote_iommu_petersons_spinlock *sync_lock_vars;
138 struct kgsl_memdesc sync_lock_desc;
139 bool sync_lock_initialized;
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]140};
141
142/*
143 * struct kgsl_iommu_pt - Iommu pagetable structure private to kgsl driver
144 * @domain: Pointer to the iommu domain that contains the iommu pagetable
145 * @iommu: Pointer to iommu structure
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]146 */
147struct kgsl_iommu_pt {
148 struct iommu_domain *domain;
149 struct kgsl_iommu *iommu;
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]150};
151
152#endif