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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053019#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080021
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <linux/input/pmic8058-keypad.h>
23#include <linux/pmic8058-batt-alarm.h>
24#include <linux/pmic8058-pwrkey.h>
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +053025#include <linux/rtc/rtc-pm8058.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070026#include <linux/pmic8058-vibrator.h>
27#include <linux/leds.h>
28#include <linux/pmic8058-othc.h>
29#include <linux/mfd/pmic8901.h>
30#include <linux/regulator/pmic8058-regulator.h>
31#include <linux/regulator/pmic8901-regulator.h>
32#include <linux/bootmem.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/leds-pmic8058.h>
36#include <linux/pmic8058-xoadc.h>
37#include <linux/msm_adc.h>
38#include <linux/m_adcproc.h>
39#include <linux/mfd/marimba.h>
40#include <linux/msm-charger.h>
41#include <linux/i2c.h>
42#include <linux/i2c/sx150x.h>
43#include <linux/smsc911x.h>
44#include <linux/spi/spi.h>
45#include <linux/input/tdisc_shinetsu.h>
46#include <linux/input/cy8c_ts.h>
47#include <linux/cyttsp.h>
48#include <linux/i2c/isa1200.h>
49#include <linux/dma-mapping.h>
50#include <linux/i2c/bq27520.h>
51
52#ifdef CONFIG_ANDROID_PMEM
53#include <linux/android_pmem.h>
54#endif
55
56#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
57#include <linux/i2c/smb137b.h>
58#endif
Lei Zhou338cab82011-08-19 13:38:17 -040059#ifdef CONFIG_SND_SOC_WM8903
60#include <sound/wm8903.h>
61#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080062#include <asm/mach-types.h>
63#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080065
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#include <mach/dma.h>
67#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080068#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#include <mach/irqs.h>
70#include <mach/msm_spi.h>
71#include <mach/msm_serial_hs.h>
72#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080073#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#include <mach/msm_memtypes.h>
75#include <asm/mach/mmc.h>
76#include <mach/msm_battery.h>
77#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070078#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070079#ifdef CONFIG_MSM_DSPS
80#include <mach/msm_dsps.h>
81#endif
82#include <mach/msm_xo.h>
83#include <mach/msm_bus_board.h>
84#include <mach/socinfo.h>
85#include <linux/i2c/isl9519.h>
86#ifdef CONFIG_USB_G_ANDROID
87#include <linux/usb/android.h>
88#include <mach/usbdiag.h>
89#endif
90#include <linux/regulator/consumer.h>
91#include <linux/regulator/machine.h>
92#include <mach/sdio_al.h>
93#include <mach/rpm.h>
94#include <mach/rpm-regulator.h>
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070095#include <mach/restart.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080096
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070097#include "devices.h"
98#include "devices-msm8x60.h"
99#include "cpuidle.h"
100#include "pm.h"
101#include "mpm.h"
102#include "spm.h"
103#include "rpm_log.h"
104#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700105#include "gpiomux-8x60.h"
106#include "rpm_stats.h"
107#include "peripheral-loader.h"
108#include <linux/platform_data/qcom_crypto_device.h>
109#include "rpm_resources.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -0700110#include "acpuclock.h"
Steve Mucklea55df6e2010-01-07 12:43:24 -0800111
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700112#define MSM_SHARED_RAM_PHYS 0x40000000
113
114/* Macros assume PMIC GPIOs start at 0 */
115#define PM8058_GPIO_BASE NR_MSM_GPIOS
116#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
117#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
118#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
119#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
120#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
121#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
122
123#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
124 PM8058_GPIOS + PM8058_MPPS)
125#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
126#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
127#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
128 NR_PMIC8058_IRQS)
129
130#define MDM2AP_SYNC 129
131
Terence Hampson1c73fef2011-07-19 17:10:49 -0400132#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700133#define LCDC_SPI_GPIO_CLK 73
134#define LCDC_SPI_GPIO_CS 72
135#define LCDC_SPI_GPIO_MOSI 70
136#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
137#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
138#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
139#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
140#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400141#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -0700143#define PANEL_NAME_MAX_LEN 30
144#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
145#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
146#define MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME "mipi_video_toshiba_wvga"
147#define HDMI_PANEL_NAME "hdmi_msm"
148#define TVOUT_PANEL_NAME "tvout_msm"
149
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150#define DSPS_PIL_GENERIC_NAME "dsps"
151#define DSPS_PIL_FLUID_NAME "dsps_fluid"
152
153enum {
154 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
155 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
156 /* CORE expander */
157 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
158 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
159 GPIO_WLAN_DEEP_SLEEP_N,
160 GPIO_LVDS_SHUTDOWN_N,
161 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
162 GPIO_MS_SYS_RESET_N,
163 GPIO_CAP_TS_RESOUT_N,
164 GPIO_CAP_GAUGE_BI_TOUT,
165 GPIO_ETHERNET_PME,
166 GPIO_EXT_GPS_LNA_EN,
167 GPIO_MSM_WAKES_BT,
168 GPIO_ETHERNET_RESET_N,
169 GPIO_HEADSET_DET_N,
170 GPIO_USB_UICC_EN,
171 GPIO_BACKLIGHT_EN,
172 GPIO_EXT_CAMIF_PWR_EN,
173 GPIO_BATT_GAUGE_INT_N,
174 GPIO_BATT_GAUGE_EN,
175 /* DOCKING expander */
176 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
177 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
178 GPIO_AUX_JTAG_DET_N,
179 GPIO_DONGLE_DET_N,
180 GPIO_SVIDEO_LOAD_DET,
181 GPIO_SVID_AMP_SHUTDOWN1_N,
182 GPIO_SVID_AMP_SHUTDOWN0_N,
183 GPIO_SDC_WP,
184 GPIO_IRDA_PWDN,
185 GPIO_IRDA_RESET_N,
186 GPIO_DONGLE_GPIO0,
187 GPIO_DONGLE_GPIO1,
188 GPIO_DONGLE_GPIO2,
189 GPIO_DONGLE_GPIO3,
190 GPIO_DONGLE_PWR_EN,
191 GPIO_EMMC_RESET_N,
192 GPIO_TP_EXP2_IO15,
193 /* SURF expander */
194 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
195 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
196 GPIO_SD_CARD_DET_2,
197 GPIO_SD_CARD_DET_4,
198 GPIO_SD_CARD_DET_5,
199 GPIO_UIM3_RST,
200 GPIO_SURF_EXPANDER_IO5,
201 GPIO_SURF_EXPANDER_IO6,
202 GPIO_ADC_I2C_EN,
203 GPIO_SURF_EXPANDER_IO8,
204 GPIO_SURF_EXPANDER_IO9,
205 GPIO_SURF_EXPANDER_IO10,
206 GPIO_SURF_EXPANDER_IO11,
207 GPIO_SURF_EXPANDER_IO12,
208 GPIO_SURF_EXPANDER_IO13,
209 GPIO_SURF_EXPANDER_IO14,
210 GPIO_SURF_EXPANDER_IO15,
211 /* LEFT KB IO expander */
212 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
213 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
214 GPIO_LEFT_LED_2,
215 GPIO_LEFT_LED_3,
216 GPIO_LEFT_LED_WLAN,
217 GPIO_JOYSTICK_EN,
218 GPIO_CAP_TS_SLEEP,
219 GPIO_LEFT_KB_IO6,
220 GPIO_LEFT_LED_5,
221 /* RIGHT KB IO expander */
222 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
223 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
224 GPIO_RIGHT_LED_2,
225 GPIO_RIGHT_LED_3,
226 GPIO_RIGHT_LED_BT,
227 GPIO_WEB_CAMIF_STANDBY,
228 GPIO_COMPASS_RST_N,
229 GPIO_WEB_CAMIF_RESET_N,
230 GPIO_RIGHT_LED_5,
231 GPIO_R_ALTIMETER_RESET_N,
232 /* FLUID S IO expander */
233 GPIO_SOUTH_EXPANDER_BASE,
234 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
235 GPIO_MIC1_ANCL_SEL,
236 GPIO_HS_MIC4_SEL,
237 GPIO_FML_MIC3_SEL,
238 GPIO_FMR_MIC5_SEL,
239 GPIO_TS_SLEEP,
240 GPIO_HAP_SHIFT_LVL_OE,
241 GPIO_HS_SW_DIR,
242 /* FLUID N IO expander */
243 GPIO_NORTH_EXPANDER_BASE,
244 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
245 GPIO_EPM_5V_BOOST_EN,
246 GPIO_AUX_CAM_2P7_EN,
247 GPIO_LED_FLASH_EN,
248 GPIO_LED1_GREEN_N,
249 GPIO_LED2_RED_N,
250 GPIO_FRONT_CAM_RESET_N,
251 GPIO_EPM_LVLSFT_EN,
252 GPIO_N_ALTIMETER_RESET_N,
253 /* EPM expander */
254 GPIO_EPM_EXPANDER_BASE,
255 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
256 GPIO_PWR_MON_RESET_N,
257 GPIO_ADC1_PWDN_N,
258 GPIO_ADC2_PWDN_N,
259 GPIO_EPM_EXPANDER_IO4,
260 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
261 GPIO_ADC2_MUX_SPI_INT_N,
262 GPIO_EPM_EXPANDER_IO7,
263 GPIO_PWR_MON_ENABLE,
264 GPIO_EPM_SPI_ADC1_CS_N,
265 GPIO_EPM_SPI_ADC2_CS_N,
266 GPIO_EPM_EXPANDER_IO11,
267 GPIO_EPM_EXPANDER_IO12,
268 GPIO_EPM_EXPANDER_IO13,
269 GPIO_EPM_EXPANDER_IO14,
270 GPIO_EPM_EXPANDER_IO15,
271};
272
273/*
274 * The UI_INTx_N lines are pmic gpio lines which connect i2c
275 * gpio expanders to the pm8058.
276 */
277#define UI_INT1_N 25
278#define UI_INT2_N 34
279#define UI_INT3_N 14
280/*
281FM GPIO is GPIO 18 on PMIC 8058.
282As the index starts from 0 in the PMIC driver, and hence 17
283corresponds to GPIO 18 on PMIC 8058.
284*/
285#define FM_GPIO 17
286
287#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
288static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
289static void *sdc2_status_notify_cb_devid;
290#endif
291
292#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
293static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
294static void *sdc5_status_notify_cb_devid;
295#endif
296
297static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
298 [0] = {
299 .reg_base_addr = MSM_SAW0_BASE,
300
301#ifdef CONFIG_MSM_AVS_HW
302 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
303#endif
304 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
305 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
306 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
307 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
308
309 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
310 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
311 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
312
313 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
314 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
315 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
316
317 .awake_vlevel = 0x94,
318 .retention_vlevel = 0x81,
319 .collapse_vlevel = 0x20,
320 .retention_mid_vlevel = 0x94,
321 .collapse_mid_vlevel = 0x8C,
322
323 .vctl_timeout_us = 50,
324 },
325
326 [1] = {
327 .reg_base_addr = MSM_SAW1_BASE,
328
329#ifdef CONFIG_MSM_AVS_HW
330 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
331#endif
332 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
333 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
334 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
335 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
336
337 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
338 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
339 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
340
341 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
342 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
343 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
344
345 .awake_vlevel = 0x94,
346 .retention_vlevel = 0x81,
347 .collapse_vlevel = 0x20,
348 .retention_mid_vlevel = 0x94,
349 .collapse_mid_vlevel = 0x8C,
350
351 .vctl_timeout_us = 50,
352 },
353};
354
355static struct msm_spm_platform_data msm_spm_data[] __initdata = {
356 [0] = {
357 .reg_base_addr = MSM_SAW0_BASE,
358
359#ifdef CONFIG_MSM_AVS_HW
360 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
361#endif
362 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
363 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
364 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
365 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
366
367 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
368 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
369 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
370
371 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
372 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
373 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
374
375 .awake_vlevel = 0xA0,
376 .retention_vlevel = 0x89,
377 .collapse_vlevel = 0x20,
378 .retention_mid_vlevel = 0x89,
379 .collapse_mid_vlevel = 0x89,
380
381 .vctl_timeout_us = 50,
382 },
383
384 [1] = {
385 .reg_base_addr = MSM_SAW1_BASE,
386
387#ifdef CONFIG_MSM_AVS_HW
388 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
389#endif
390 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
391 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
392 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
393 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
394
395 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
396 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
397 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
398
399 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
400 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
401 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
402
403 .awake_vlevel = 0xA0,
404 .retention_vlevel = 0x89,
405 .collapse_vlevel = 0x20,
406 .retention_mid_vlevel = 0x89,
407 .collapse_mid_vlevel = 0x89,
408
409 .vctl_timeout_us = 50,
410 },
411};
412
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700413/*
414 * Consumer specific regulator names:
415 * regulator name consumer dev_name
416 */
417static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
418 REGULATOR_SUPPLY("8901_s0", NULL),
419};
420static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
421 REGULATOR_SUPPLY("8901_s1", NULL),
422};
423
424static struct regulator_init_data saw_s0_init_data = {
425 .constraints = {
426 .name = "8901_s0",
427 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700428 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700429 .max_uV = 1250000,
430 },
431 .consumer_supplies = vreg_consumers_8901_S0,
432 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
433};
434
435static struct regulator_init_data saw_s1_init_data = {
436 .constraints = {
437 .name = "8901_s1",
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700439 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700440 .max_uV = 1250000,
441 },
442 .consumer_supplies = vreg_consumers_8901_S1,
443 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
444};
445
446static struct platform_device msm_device_saw_s0 = {
447 .name = "saw-regulator",
448 .id = 0,
449 .dev = {
450 .platform_data = &saw_s0_init_data,
451 },
452};
453
454static struct platform_device msm_device_saw_s1 = {
455 .name = "saw-regulator",
456 .id = 1,
457 .dev = {
458 .platform_data = &saw_s1_init_data,
459 },
460};
461
462/*
463 * The smc91x configuration varies depending on platform.
464 * The resources data structure is filled in at runtime.
465 */
466static struct resource smc91x_resources[] = {
467 [0] = {
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device smc91x_device = {
476 .name = "smc91x",
477 .id = 0,
478 .num_resources = ARRAY_SIZE(smc91x_resources),
479 .resource = smc91x_resources,
480};
481
482static struct resource smsc911x_resources[] = {
483 [0] = {
484 .flags = IORESOURCE_MEM,
485 .start = 0x1b800000,
486 .end = 0x1b8000ff
487 },
488 [1] = {
489 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
490 },
491};
492
493static struct smsc911x_platform_config smsc911x_config = {
494 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
495 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
496 .flags = SMSC911X_USE_16BIT,
497 .has_reset_gpio = 1,
498 .reset_gpio = GPIO_ETHERNET_RESET_N
499};
500
501static struct platform_device smsc911x_device = {
502 .name = "smsc911x",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(smsc911x_resources),
505 .resource = smsc911x_resources,
506 .dev = {
507 .platform_data = &smsc911x_config
508 }
509};
510
511#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
512 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
513 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
514 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
515
516#define QCE_SIZE 0x10000
517#define QCE_0_BASE 0x18500000
518
519#define QCE_HW_KEY_SUPPORT 0
520#define QCE_SHA_HMAC_SUPPORT 0
521#define QCE_SHARE_CE_RESOURCE 2
522#define QCE_CE_SHARED 1
523
524static struct resource qcrypto_resources[] = {
525 [0] = {
526 .start = QCE_0_BASE,
527 .end = QCE_0_BASE + QCE_SIZE - 1,
528 .flags = IORESOURCE_MEM,
529 },
530 [1] = {
531 .name = "crypto_channels",
532 .start = DMOV_CE_IN_CHAN,
533 .end = DMOV_CE_OUT_CHAN,
534 .flags = IORESOURCE_DMA,
535 },
536 [2] = {
537 .name = "crypto_crci_in",
538 .start = DMOV_CE_IN_CRCI,
539 .end = DMOV_CE_IN_CRCI,
540 .flags = IORESOURCE_DMA,
541 },
542 [3] = {
543 .name = "crypto_crci_out",
544 .start = DMOV_CE_OUT_CRCI,
545 .end = DMOV_CE_OUT_CRCI,
546 .flags = IORESOURCE_DMA,
547 },
548 [4] = {
549 .name = "crypto_crci_hash",
550 .start = DMOV_CE_HASH_CRCI,
551 .end = DMOV_CE_HASH_CRCI,
552 .flags = IORESOURCE_DMA,
553 },
554};
555
556static struct resource qcedev_resources[] = {
557 [0] = {
558 .start = QCE_0_BASE,
559 .end = QCE_0_BASE + QCE_SIZE - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .name = "crypto_channels",
564 .start = DMOV_CE_IN_CHAN,
565 .end = DMOV_CE_OUT_CHAN,
566 .flags = IORESOURCE_DMA,
567 },
568 [2] = {
569 .name = "crypto_crci_in",
570 .start = DMOV_CE_IN_CRCI,
571 .end = DMOV_CE_IN_CRCI,
572 .flags = IORESOURCE_DMA,
573 },
574 [3] = {
575 .name = "crypto_crci_out",
576 .start = DMOV_CE_OUT_CRCI,
577 .end = DMOV_CE_OUT_CRCI,
578 .flags = IORESOURCE_DMA,
579 },
580 [4] = {
581 .name = "crypto_crci_hash",
582 .start = DMOV_CE_HASH_CRCI,
583 .end = DMOV_CE_HASH_CRCI,
584 .flags = IORESOURCE_DMA,
585 },
586};
587
588#endif
589
590#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
591 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
592
593static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
594 .ce_shared = QCE_CE_SHARED,
595 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
596 .hw_key_support = QCE_HW_KEY_SUPPORT,
597 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
598};
599
600static struct platform_device qcrypto_device = {
601 .name = "qcrypto",
602 .id = 0,
603 .num_resources = ARRAY_SIZE(qcrypto_resources),
604 .resource = qcrypto_resources,
605 .dev = {
606 .coherent_dma_mask = DMA_BIT_MASK(32),
607 .platform_data = &qcrypto_ce_hw_suppport,
608 },
609};
610#endif
611
612#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
613 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
614
615static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
616 .ce_shared = QCE_CE_SHARED,
617 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
618 .hw_key_support = QCE_HW_KEY_SUPPORT,
619 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
620};
621
622static struct platform_device qcedev_device = {
623 .name = "qce",
624 .id = 0,
625 .num_resources = ARRAY_SIZE(qcedev_resources),
626 .resource = qcedev_resources,
627 .dev = {
628 .coherent_dma_mask = DMA_BIT_MASK(32),
629 .platform_data = &qcedev_ce_hw_suppport,
630 },
631};
632#endif
633
634#if defined(CONFIG_HAPTIC_ISA1200) || \
635 defined(CONFIG_HAPTIC_ISA1200_MODULE)
636
637static const char *vregs_isa1200_name[] = {
638 "8058_s3",
639 "8901_l4",
640};
641
642static const int vregs_isa1200_val[] = {
643 1800000,/* uV */
644 2600000,
645};
646static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
647static struct msm_xo_voter *xo_handle_a1;
648
649static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800650{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700651 int i, rc = 0;
652
653 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
654 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
655 regulator_disable(vregs_isa1200[i]);
656 if (rc < 0) {
657 pr_err("%s: vreg %s %s failed (%d)\n",
658 __func__, vregs_isa1200_name[i],
659 vreg_on ? "enable" : "disable", rc);
660 goto vreg_fail;
661 }
662 }
663
664 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
665 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
666 if (rc < 0) {
667 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
668 __func__, vreg_on ? "" : "de-", rc);
669 goto vreg_fail;
670 }
671 return 0;
672
673vreg_fail:
674 while (i--)
675 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
676 regulator_disable(vregs_isa1200[i]);
677 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800678}
679
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700680static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800681{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700682 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800683
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700684 if (enable == true) {
685 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
686 vregs_isa1200[i] = regulator_get(NULL,
687 vregs_isa1200_name[i]);
688 if (IS_ERR(vregs_isa1200[i])) {
689 pr_err("%s: regulator get of %s failed (%ld)\n",
690 __func__, vregs_isa1200_name[i],
691 PTR_ERR(vregs_isa1200[i]));
692 rc = PTR_ERR(vregs_isa1200[i]);
693 goto vreg_get_fail;
694 }
695 rc = regulator_set_voltage(vregs_isa1200[i],
696 vregs_isa1200_val[i], vregs_isa1200_val[i]);
697 if (rc) {
698 pr_err("%s: regulator_set_voltage(%s) failed\n",
699 __func__, vregs_isa1200_name[i]);
700 goto vreg_get_fail;
701 }
702 }
Steve Muckle9161d302010-02-11 11:50:40 -0800703
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700704 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
705 if (rc) {
706 pr_err("%s: unable to request gpio %d (%d)\n",
707 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
708 goto vreg_get_fail;
709 }
Steve Muckle9161d302010-02-11 11:50:40 -0800710
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700711 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
712 if (rc) {
713 pr_err("%s: Unable to set direction\n", __func__);;
714 goto free_gpio;
715 }
716
717 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
718 if (IS_ERR(xo_handle_a1)) {
719 rc = PTR_ERR(xo_handle_a1);
720 pr_err("%s: failed to get the handle for A1(%d)\n",
721 __func__, rc);
722 goto gpio_set_dir;
723 }
724 } else {
725 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
726 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
727
728 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
729 regulator_put(vregs_isa1200[i]);
730
731 msm_xo_put(xo_handle_a1);
732 }
733
734 return 0;
735gpio_set_dir:
736 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
737free_gpio:
738 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
739vreg_get_fail:
740 while (i)
741 regulator_put(vregs_isa1200[--i]);
742 return rc;
743}
744
745#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
746static struct isa1200_platform_data isa1200_1_pdata = {
747 .name = "vibrator",
748 .power_on = isa1200_power,
749 .dev_setup = isa1200_dev_setup,
750 /*gpio to enable haptic*/
751 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
752 .max_timeout = 15000,
753 .mode_ctrl = PWM_GEN_MODE,
754 .pwm_fd = {
755 .pwm_div = 256,
756 },
757 .is_erm = false,
758 .smart_en = true,
759 .ext_clk_en = true,
760 .chip_en = 1,
761};
762
763static struct i2c_board_info msm_isa1200_board_info[] = {
764 {
765 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
766 .platform_data = &isa1200_1_pdata,
767 },
768};
769#endif
770
771#if defined(CONFIG_BATTERY_BQ27520) || \
772 defined(CONFIG_BATTERY_BQ27520_MODULE)
773static struct bq27520_platform_data bq27520_pdata = {
774 .name = "fuel-gauge",
775 .vreg_name = "8058_s3",
776 .vreg_value = 1800000,
777 .soc_int = GPIO_BATT_GAUGE_INT_N,
778 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
779 .chip_en = GPIO_BATT_GAUGE_EN,
780 .enable_dlog = 0, /* if enable coulomb counter logger */
781};
782
783static struct i2c_board_info msm_bq27520_board_info[] = {
784 {
785 I2C_BOARD_INFO("bq27520", 0xaa>>1),
786 .platform_data = &bq27520_pdata,
787 },
788};
789#endif
790
791static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
792 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
793 .idle_supported = 1,
794 .suspend_supported = 1,
795 .idle_enabled = 0,
796 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700797 },
798
799 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
800 .idle_supported = 1,
801 .suspend_supported = 1,
802 .idle_enabled = 0,
803 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700804 },
805
806 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
807 .idle_supported = 1,
808 .suspend_supported = 1,
809 .idle_enabled = 1,
810 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700811 },
812
813 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
814 .idle_supported = 1,
815 .suspend_supported = 1,
816 .idle_enabled = 0,
817 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700818 },
819
820 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
821 .idle_supported = 1,
822 .suspend_supported = 1,
823 .idle_enabled = 0,
824 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700825 },
826
827 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
828 .idle_supported = 1,
829 .suspend_supported = 1,
830 .idle_enabled = 1,
831 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700832 },
833};
834
835static struct msm_cpuidle_state msm_cstates[] __initdata = {
836 {0, 0, "C0", "WFI",
837 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
838
839 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
840 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
841
842 {0, 2, "C2", "POWER_COLLAPSE",
843 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
844
845 {1, 0, "C0", "WFI",
846 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
847
848 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
849 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
850};
851
852static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
853 {
854 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
855 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
856 true,
857 1, 8000, 100000, 1,
858 },
859
860 {
861 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
862 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
863 true,
864 1500, 5000, 60100000, 3000,
865 },
866
867 {
868 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
869 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
870 false,
871 1800, 5000, 60350000, 3500,
872 },
873 {
874 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
875 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
876 false,
877 3800, 4500, 65350000, 5500,
878 },
879
880 {
881 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
882 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
883 false,
884 2800, 2500, 66850000, 4800,
885 },
886
887 {
888 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
889 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
890 false,
891 4800, 2000, 71850000, 6800,
892 },
893
894 {
895 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
896 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
897 false,
898 6800, 500, 75850000, 8800,
899 },
900
901 {
902 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
903 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
904 false,
905 7800, 0, 76350000, 9800,
906 },
907};
908
909#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
910
911#define ISP1763_INT_GPIO 117
912#define ISP1763_RST_GPIO 152
913static struct resource isp1763_resources[] = {
914 [0] = {
915 .flags = IORESOURCE_MEM,
916 .start = 0x1D000000,
917 .end = 0x1D005FFF, /* 24KB */
918 },
919 [1] = {
920 .flags = IORESOURCE_IRQ,
921 },
922};
923static void __init msm8x60_cfg_isp1763(void)
924{
925 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
926 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
927}
928
929static int isp1763_setup_gpio(int enable)
930{
931 int status = 0;
932
933 if (enable) {
934 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
935 if (status) {
936 pr_err("%s:Failed to request GPIO %d\n",
937 __func__, ISP1763_INT_GPIO);
938 return status;
939 }
940 status = gpio_direction_input(ISP1763_INT_GPIO);
941 if (status) {
942 pr_err("%s:Failed to configure GPIO %d\n",
943 __func__, ISP1763_INT_GPIO);
944 goto gpio_free_int;
945 }
946 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
947 if (status) {
948 pr_err("%s:Failed to request GPIO %d\n",
949 __func__, ISP1763_RST_GPIO);
950 goto gpio_free_int;
951 }
952 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
953 if (status) {
954 pr_err("%s:Failed to configure GPIO %d\n",
955 __func__, ISP1763_RST_GPIO);
956 goto gpio_free_rst;
957 }
958 pr_debug("\nISP GPIO configuration done\n");
959 return status;
960 }
961
962gpio_free_rst:
963 gpio_free(ISP1763_RST_GPIO);
964gpio_free_int:
965 gpio_free(ISP1763_INT_GPIO);
966
967 return status;
968}
969static struct isp1763_platform_data isp1763_pdata = {
970 .reset_gpio = ISP1763_RST_GPIO,
971 .setup_gpio = isp1763_setup_gpio
972};
973
974static struct platform_device isp1763_device = {
975 .name = "isp1763_usb",
976 .num_resources = ARRAY_SIZE(isp1763_resources),
977 .resource = isp1763_resources,
978 .dev = {
979 .platform_data = &isp1763_pdata
980 }
981};
982#endif
983
984#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
Anji jonnalaeb9e60d2011-10-05 12:19:46 +0530985static struct msm_otg_platform_data msm_otg_pdata;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700986static struct regulator *ldo6_3p3;
987static struct regulator *ldo7_1p8;
988static struct regulator *vdd_cx;
989#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
990notify_vbus_state notify_vbus_state_func_ptr;
991static int usb_phy_susp_dig_vol = 750000;
992static int pmic_id_notif_supported;
993
994#ifdef CONFIG_USB_EHCI_MSM_72K
995#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
996struct delayed_work pmic_id_det;
997
998static int __init usb_id_pin_rework_setup(char *support)
999{
1000 if (strncmp(support, "true", 4) == 0)
1001 pmic_id_notif_supported = 1;
1002
1003 return 1;
1004}
1005__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1006
1007static void pmic_id_detect(struct work_struct *w)
1008{
1009 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1010 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1011
1012 if (notify_vbus_state_func_ptr)
1013 (*notify_vbus_state_func_ptr) (val);
1014}
1015
1016static irqreturn_t pmic_id_on_irq(int irq, void *data)
1017{
1018 /*
1019 * Spurious interrupts are observed on pmic gpio line
1020 * even though there is no state change on USB ID. Schedule the
1021 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001022 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001023 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001024
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001025 return IRQ_HANDLED;
1026}
1027
1028static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1029{
1030 unsigned ret = -ENODEV;
1031
1032 if (!callback)
1033 return -EINVAL;
1034
1035 if (machine_is_msm8x60_fluid())
1036 return -ENOTSUPP;
1037
1038 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1039 pr_debug("%s: USB_ID pin is not routed to PMIC"
1040 "on V1 surf/ffa\n", __func__);
1041 return -ENOTSUPP;
1042 }
1043
1044 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1045 !pmic_id_notif_supported) {
1046 pr_debug("%s: USB_ID is not routed to PMIC"
1047 "on V2 ffa\n", __func__);
1048 return -ENOTSUPP;
1049 }
1050
1051 usb_phy_susp_dig_vol = 500000;
1052
1053 if (init) {
1054 notify_vbus_state_func_ptr = callback;
1055 ret = pm8901_mpp_config_digital_out(1,
1056 PM8901_MPP_DIG_LEVEL_L5, 1);
1057 if (ret) {
1058 pr_err("%s: MPP2 configuration failed\n", __func__);
1059 return -ENODEV;
1060 }
1061 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
1062 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1063 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1064 "msm_otg_id", NULL);
1065 if (ret) {
1066 pm8901_mpp_config_digital_out(1,
1067 PM8901_MPP_DIG_LEVEL_L5, 0);
1068 pr_err("%s:pmic_usb_id interrupt registration failed",
1069 __func__);
1070 return ret;
1071 }
1072 /* Notify the initial Id status */
1073 pmic_id_detect(&pmic_id_det.work);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301074 msm_otg_pdata.pmic_id_irq = PMICID_INT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001075 } else {
1076 free_irq(PMICID_INT, 0);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301077 msm_otg_pdata.pmic_id_irq = 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001078 cancel_delayed_work_sync(&pmic_id_det);
1079 notify_vbus_state_func_ptr = NULL;
1080 ret = pm8901_mpp_config_digital_out(1,
1081 PM8901_MPP_DIG_LEVEL_L5, 0);
1082 if (ret) {
1083 pr_err("%s:MPP2 configuration failed\n", __func__);
1084 return -ENODEV;
1085 }
1086 }
1087 return 0;
1088}
1089#endif
1090
1091#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1092#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1093static int msm_hsusb_init_vddcx(int init)
1094{
1095 int ret = 0;
1096
1097 if (init) {
1098 vdd_cx = regulator_get(NULL, "8058_s1");
1099 if (IS_ERR(vdd_cx)) {
1100 return PTR_ERR(vdd_cx);
1101 }
1102
1103 ret = regulator_set_voltage(vdd_cx,
1104 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1105 USB_PHY_MAX_VDD_DIG_VOL);
1106 if (ret) {
1107 pr_err("%s: unable to set the voltage for regulator"
1108 "vdd_cx\n", __func__);
1109 regulator_put(vdd_cx);
1110 return ret;
1111 }
1112
1113 ret = regulator_enable(vdd_cx);
1114 if (ret) {
1115 pr_err("%s: unable to enable regulator"
1116 "vdd_cx\n", __func__);
1117 regulator_put(vdd_cx);
1118 }
1119 } else {
1120 ret = regulator_disable(vdd_cx);
1121 if (ret) {
1122 pr_err("%s: Unable to disable the regulator:"
1123 "vdd_cx\n", __func__);
1124 return ret;
1125 }
1126
1127 regulator_put(vdd_cx);
1128 }
1129
1130 return ret;
1131}
1132
1133static int msm_hsusb_config_vddcx(int high)
1134{
1135 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1136 int min_vol;
1137 int ret;
1138
1139 if (high)
1140 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1141 else
1142 min_vol = usb_phy_susp_dig_vol;
1143
1144 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1145 if (ret) {
1146 pr_err("%s: unable to set the voltage for regulator"
1147 "vdd_cx\n", __func__);
1148 return ret;
1149 }
1150
1151 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1152
1153 return ret;
1154}
1155
1156#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1157#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1158#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1159#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1160
1161#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1162#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1163#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1164#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1165static int msm_hsusb_ldo_init(int init)
1166{
1167 int rc = 0;
1168
1169 if (init) {
1170 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1171 if (IS_ERR(ldo6_3p3))
1172 return PTR_ERR(ldo6_3p3);
1173
1174 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1175 if (IS_ERR(ldo7_1p8)) {
1176 rc = PTR_ERR(ldo7_1p8);
1177 goto put_3p3;
1178 }
1179
1180 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1181 USB_PHY_3P3_VOL_MAX);
1182 if (rc) {
1183 pr_err("%s: Unable to set voltage level for"
1184 "ldo6_3p3 regulator\n", __func__);
1185 goto put_1p8;
1186 }
1187 rc = regulator_enable(ldo6_3p3);
1188 if (rc) {
1189 pr_err("%s: Unable to enable the regulator:"
1190 "ldo6_3p3\n", __func__);
1191 goto put_1p8;
1192 }
1193 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1194 USB_PHY_1P8_VOL_MAX);
1195 if (rc) {
1196 pr_err("%s: Unable to set voltage level for"
1197 "ldo7_1p8 regulator\n", __func__);
1198 goto disable_3p3;
1199 }
1200 rc = regulator_enable(ldo7_1p8);
1201 if (rc) {
1202 pr_err("%s: Unable to enable the regulator:"
1203 "ldo7_1p8\n", __func__);
1204 goto disable_3p3;
1205 }
1206
1207 return 0;
1208 }
1209
1210 regulator_disable(ldo7_1p8);
1211disable_3p3:
1212 regulator_disable(ldo6_3p3);
1213put_1p8:
1214 regulator_put(ldo7_1p8);
1215put_3p3:
1216 regulator_put(ldo6_3p3);
1217 return rc;
1218}
1219
1220static int msm_hsusb_ldo_enable(int on)
1221{
1222 int ret = 0;
1223
1224 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1225 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1226 return -ENODEV;
1227 }
1228
1229 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1230 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1231 return -ENODEV;
1232 }
1233
1234 if (on) {
1235 ret = regulator_set_optimum_mode(ldo7_1p8,
1236 USB_PHY_1P8_HPM_LOAD);
1237 if (ret < 0) {
1238 pr_err("%s: Unable to set HPM of the regulator:"
1239 "ldo7_1p8\n", __func__);
1240 return ret;
1241 }
1242 ret = regulator_set_optimum_mode(ldo6_3p3,
1243 USB_PHY_3P3_HPM_LOAD);
1244 if (ret < 0) {
1245 pr_err("%s: Unable to set HPM of the regulator:"
1246 "ldo6_3p3\n", __func__);
1247 regulator_set_optimum_mode(ldo7_1p8,
1248 USB_PHY_1P8_LPM_LOAD);
1249 return ret;
1250 }
1251 } else {
1252 ret = regulator_set_optimum_mode(ldo7_1p8,
1253 USB_PHY_1P8_LPM_LOAD);
1254 if (ret < 0)
1255 pr_err("%s: Unable to set LPM of the regulator:"
1256 "ldo7_1p8\n", __func__);
1257 ret = regulator_set_optimum_mode(ldo6_3p3,
1258 USB_PHY_3P3_LPM_LOAD);
1259 if (ret < 0)
1260 pr_err("%s: Unable to set LPM of the regulator:"
1261 "ldo6_3p3\n", __func__);
1262 }
1263
1264 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1265 return ret < 0 ? ret : 0;
1266 }
1267#endif
1268#ifdef CONFIG_USB_EHCI_MSM_72K
1269#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1270static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1271{
1272 static int vbus_is_on;
1273
1274 /* If VBUS is already on (or off), do nothing. */
1275 if (on == vbus_is_on)
1276 return;
1277 smb137b_otg_power(on);
1278 vbus_is_on = on;
1279}
1280#endif
1281static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1282{
1283 static struct regulator *votg_5v_switch;
1284 static struct regulator *ext_5v_reg;
1285 static int vbus_is_on;
1286
1287 /* If VBUS is already on (or off), do nothing. */
1288 if (on == vbus_is_on)
1289 return;
1290
1291 if (!votg_5v_switch) {
1292 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1293 if (IS_ERR(votg_5v_switch)) {
1294 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1295 return;
1296 }
1297 }
1298 if (!ext_5v_reg) {
1299 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1300 if (IS_ERR(ext_5v_reg)) {
1301 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1302 return;
1303 }
1304 }
1305 if (on) {
1306 if (regulator_enable(ext_5v_reg)) {
1307 pr_err("%s: Unable to enable the regulator:"
1308 " ext_5v_reg\n", __func__);
1309 return;
1310 }
1311 if (regulator_enable(votg_5v_switch)) {
1312 pr_err("%s: Unable to enable the regulator:"
1313 " votg_5v_switch\n", __func__);
1314 return;
1315 }
1316 } else {
1317 if (regulator_disable(votg_5v_switch))
1318 pr_err("%s: Unable to enable the regulator:"
1319 " votg_5v_switch\n", __func__);
1320 if (regulator_disable(ext_5v_reg))
1321 pr_err("%s: Unable to enable the regulator:"
1322 " ext_5v_reg\n", __func__);
1323 }
1324
1325 vbus_is_on = on;
1326}
1327
1328static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1329 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1330 .power_budget = 390,
1331};
1332#endif
1333
1334#ifdef CONFIG_BATTERY_MSM8X60
1335static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1336 int init)
1337{
1338 int ret = -ENOTSUPP;
1339
1340#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1341 if (machine_is_msm8x60_fluid()) {
1342 if (init)
1343 msm_charger_register_vbus_sn(callback);
1344 else
1345 msm_charger_unregister_vbus_sn(callback);
1346 return 0;
1347 }
1348#endif
1349 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1350 * hence, irrespective of either peripheral only mode or
1351 * OTG (host and peripheral) modes, can depend on pmic for
1352 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001353 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001354 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1355 && (machine_is_msm8x60_surf() ||
1356 pmic_id_notif_supported)) {
1357 if (init)
1358 ret = msm_charger_register_vbus_sn(callback);
1359 else {
1360 msm_charger_unregister_vbus_sn(callback);
1361 ret = 0;
1362 }
1363 } else {
1364#if !defined(CONFIG_USB_EHCI_MSM_72K)
1365 if (init)
1366 ret = msm_charger_register_vbus_sn(callback);
1367 else {
1368 msm_charger_unregister_vbus_sn(callback);
1369 ret = 0;
1370 }
1371#endif
1372 }
1373 return ret;
1374}
1375#endif
1376
1377#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1378static struct msm_otg_platform_data msm_otg_pdata = {
1379 /* if usb link is in sps there is no need for
1380 * usb pclk as dayatona fabric clock will be
1381 * used instead
1382 */
1383 .pclk_src_name = "dfab_usb_hs_clk",
1384 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1385 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1386 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301387 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001388#ifdef CONFIG_USB_EHCI_MSM_72K
1389 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
1390#endif
1391#ifdef CONFIG_USB_EHCI_MSM_72K
1392 .vbus_power = msm_hsusb_vbus_power,
1393#endif
1394#ifdef CONFIG_BATTERY_MSM8X60
1395 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1396#endif
1397 .ldo_init = msm_hsusb_ldo_init,
1398 .ldo_enable = msm_hsusb_ldo_enable,
1399 .config_vddcx = msm_hsusb_config_vddcx,
1400 .init_vddcx = msm_hsusb_init_vddcx,
1401#ifdef CONFIG_BATTERY_MSM8X60
1402 .chg_vbus_draw = msm_charger_vbus_draw,
1403#endif
1404};
1405#endif
1406
1407#ifdef CONFIG_USB_GADGET_MSM_72K
1408static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1409 .is_phy_status_timer_on = 1,
1410};
1411#endif
1412
1413#ifdef CONFIG_USB_G_ANDROID
1414
1415#define PID_MAGIC_ID 0x71432909
1416#define SERIAL_NUM_MAGIC_ID 0x61945374
1417#define SERIAL_NUMBER_LENGTH 127
1418#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1419
1420struct magic_num_struct {
1421 uint32_t pid;
1422 uint32_t serial_num;
1423};
1424
1425struct dload_struct {
1426 uint32_t reserved1;
1427 uint32_t reserved2;
1428 uint32_t reserved3;
1429 uint16_t reserved4;
1430 uint16_t pid;
1431 char serial_number[SERIAL_NUMBER_LENGTH];
1432 uint16_t reserved5;
1433 struct magic_num_struct
1434 magic_struct;
1435};
1436
1437static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1438{
1439 struct dload_struct __iomem *dload = 0;
1440
1441 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1442 if (!dload) {
1443 pr_err("%s: cannot remap I/O memory region: %08x\n",
1444 __func__, DLOAD_USB_BASE_ADD);
1445 return -ENXIO;
1446 }
1447
1448 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1449 __func__, dload, pid, snum);
1450 /* update pid */
1451 dload->magic_struct.pid = PID_MAGIC_ID;
1452 dload->pid = pid;
1453
1454 /* update serial number */
1455 dload->magic_struct.serial_num = 0;
1456 if (!snum)
1457 return 0;
1458
1459 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1460 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1461 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1462
1463 iounmap(dload);
1464
1465 return 0;
1466}
1467
1468static struct android_usb_platform_data android_usb_pdata = {
1469 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1470};
1471
1472static struct platform_device android_usb_device = {
1473 .name = "android_usb",
1474 .id = -1,
1475 .dev = {
1476 .platform_data = &android_usb_pdata,
1477 },
1478};
1479
1480
1481#endif
1482
1483#ifdef CONFIG_MSM_VPE
1484static struct resource msm_vpe_resources[] = {
1485 {
1486 .start = 0x05300000,
1487 .end = 0x05300000 + SZ_1M - 1,
1488 .flags = IORESOURCE_MEM,
1489 },
1490 {
1491 .start = INT_VPE,
1492 .end = INT_VPE,
1493 .flags = IORESOURCE_IRQ,
1494 },
1495};
1496
1497static struct platform_device msm_vpe_device = {
1498 .name = "msm_vpe",
1499 .id = 0,
1500 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1501 .resource = msm_vpe_resources,
1502};
1503#endif
1504
1505#ifdef CONFIG_MSM_CAMERA
1506#ifdef CONFIG_MSM_CAMERA_FLASH
1507#define VFE_CAMIF_TIMER1_GPIO 29
1508#define VFE_CAMIF_TIMER2_GPIO 30
1509#define VFE_CAMIF_TIMER3_GPIO_INT 31
1510#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1511static struct msm_camera_sensor_flash_src msm_flash_src = {
1512 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1513 ._fsrc.pmic_src.num_of_src = 2,
1514 ._fsrc.pmic_src.low_current = 100,
1515 ._fsrc.pmic_src.high_current = 300,
1516 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1517 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1518 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1519};
1520#ifdef CONFIG_IMX074
1521static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1522 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1523 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1524 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1525 .flash_recharge_duration = 50000,
1526 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1527};
1528#endif
1529#endif
1530
1531int msm_cam_gpio_tbl[] = {
1532 32,/*CAMIF_MCLK*/
1533 47,/*CAMIF_I2C_DATA*/
1534 48,/*CAMIF_I2C_CLK*/
1535 105,/*STANDBY*/
1536};
1537
1538enum msm_cam_stat{
1539 MSM_CAM_OFF,
1540 MSM_CAM_ON,
1541};
1542
1543static int config_gpio_table(enum msm_cam_stat stat)
1544{
1545 int rc = 0, i = 0;
1546 if (stat == MSM_CAM_ON) {
1547 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1548 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1549 if (unlikely(rc < 0)) {
1550 pr_err("%s not able to get gpio\n", __func__);
1551 for (i--; i >= 0; i--)
1552 gpio_free(msm_cam_gpio_tbl[i]);
1553 break;
1554 }
1555 }
1556 } else {
1557 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1558 gpio_free(msm_cam_gpio_tbl[i]);
1559 }
1560 return rc;
1561}
1562
1563static struct msm_camera_sensor_platform_info sensor_board_info = {
1564 .mount_angle = 0
1565};
1566
1567/*external regulator VREG_5V*/
1568static struct regulator *reg_flash_5V;
1569
1570static int config_camera_on_gpios_fluid(void)
1571{
1572 int rc = 0;
1573
1574 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1575 if (IS_ERR(reg_flash_5V)) {
1576 pr_err("'%s' regulator not found, rc=%ld\n",
1577 "8901_mpp0", IS_ERR(reg_flash_5V));
1578 return -ENODEV;
1579 }
1580
1581 rc = regulator_enable(reg_flash_5V);
1582 if (rc) {
1583 pr_err("'%s' regulator enable failed, rc=%d\n",
1584 "8901_mpp0", rc);
1585 regulator_put(reg_flash_5V);
1586 return rc;
1587 }
1588
1589#ifdef CONFIG_IMX074
1590 sensor_board_info.mount_angle = 90;
1591#endif
1592 rc = config_gpio_table(MSM_CAM_ON);
1593 if (rc < 0) {
1594 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1595 "failed\n", __func__);
1596 return rc;
1597 }
1598
1599 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1600 if (rc < 0) {
1601 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1602 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1603 regulator_disable(reg_flash_5V);
1604 regulator_put(reg_flash_5V);
1605 return rc;
1606 }
1607 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1608 msleep(20);
1609 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1610
1611
1612 /*Enable LED_FLASH_EN*/
1613 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1614 if (rc < 0) {
1615 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1616 "failed\n", __func__, GPIO_LED_FLASH_EN);
1617
1618 regulator_disable(reg_flash_5V);
1619 regulator_put(reg_flash_5V);
1620 config_gpio_table(MSM_CAM_OFF);
1621 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1622 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1623 return rc;
1624 }
1625 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1626 msleep(20);
1627 return rc;
1628}
1629
1630
1631static void config_camera_off_gpios_fluid(void)
1632{
1633 regulator_disable(reg_flash_5V);
1634 regulator_put(reg_flash_5V);
1635
1636 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1637 gpio_free(GPIO_LED_FLASH_EN);
1638
1639 config_gpio_table(MSM_CAM_OFF);
1640
1641 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1642 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1643}
1644static int config_camera_on_gpios(void)
1645{
1646 int rc = 0;
1647
1648 if (machine_is_msm8x60_fluid())
1649 return config_camera_on_gpios_fluid();
1650
1651 rc = config_gpio_table(MSM_CAM_ON);
1652 if (rc < 0) {
1653 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1654 "failed\n", __func__);
1655 return rc;
1656 }
1657
Jilai Wang971f97f2011-07-13 14:25:25 -04001658 if (!machine_is_msm8x60_dragon()) {
1659 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1660 if (rc < 0) {
1661 config_gpio_table(MSM_CAM_OFF);
1662 pr_err("%s: CAMSENSOR gpio %d request"
1663 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1664 return rc;
1665 }
1666 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1667 msleep(20);
1668 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001669 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001670
1671#ifdef CONFIG_MSM_CAMERA_FLASH
1672#ifdef CONFIG_IMX074
1673 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1674 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1675#endif
1676#endif
1677 return rc;
1678}
1679
1680static void config_camera_off_gpios(void)
1681{
1682 if (machine_is_msm8x60_fluid())
1683 return config_camera_off_gpios_fluid();
1684
1685
1686 config_gpio_table(MSM_CAM_OFF);
1687
Jilai Wang971f97f2011-07-13 14:25:25 -04001688 if (!machine_is_msm8x60_dragon()) {
1689 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1690 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1691 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001692}
1693
1694#ifdef CONFIG_QS_S5K4E1
1695
1696#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1697
1698static int config_camera_on_gpios_qs_cam_fluid(void)
1699{
1700 int rc = 0;
1701
1702 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1703 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1704 if (rc < 0) {
1705 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1706 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1707 return rc;
1708 }
1709 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1710 msleep(20);
1711 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1712 msleep(20);
1713
1714 /*
1715 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1716 * to enable 2.7V power to Camera
1717 */
1718 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1719 if (rc < 0) {
1720 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1721 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1722 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1723 gpio_free(QS_CAM_HC37_CAM_PD);
1724 return rc;
1725 }
1726 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1727 msleep(20);
1728 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1729 msleep(20);
1730
1731 rc = config_camera_on_gpios_fluid();
1732 if (rc < 0) {
1733 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1734 " failed\n", __func__);
1735 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1736 gpio_free(QS_CAM_HC37_CAM_PD);
1737 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1738 gpio_free(GPIO_AUX_CAM_2P7_EN);
1739 return rc;
1740 }
1741 return rc;
1742}
1743
1744static void config_camera_off_gpios_qs_cam_fluid(void)
1745{
1746 /*
1747 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1748 * to disable 2.7V power to Camera
1749 */
1750 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1751 gpio_free(GPIO_AUX_CAM_2P7_EN);
1752
1753 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1754 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1755 gpio_free(QS_CAM_HC37_CAM_PD);
1756
1757 config_camera_off_gpios_fluid();
1758 return;
1759}
1760
1761static int config_camera_on_gpios_qs_cam(void)
1762{
1763 int rc = 0;
1764
1765 if (machine_is_msm8x60_fluid())
1766 return config_camera_on_gpios_qs_cam_fluid();
1767
1768 rc = config_camera_on_gpios();
1769 return rc;
1770}
1771
1772static void config_camera_off_gpios_qs_cam(void)
1773{
1774 if (machine_is_msm8x60_fluid())
1775 return config_camera_off_gpios_qs_cam_fluid();
1776
1777 config_camera_off_gpios();
1778 return;
1779}
1780#endif
1781
1782static int config_camera_on_gpios_web_cam(void)
1783{
1784 int rc = 0;
1785 rc = config_gpio_table(MSM_CAM_ON);
1786 if (rc < 0) {
1787 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1788 "failed\n", __func__);
1789 return rc;
1790 }
1791
Jilai Wang53d27a82011-07-13 14:32:58 -04001792 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001793 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1794 if (rc < 0) {
1795 config_gpio_table(MSM_CAM_OFF);
1796 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1797 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1798 return rc;
1799 }
1800 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1801 }
1802 return rc;
1803}
1804
1805static void config_camera_off_gpios_web_cam(void)
1806{
1807 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001808 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001809 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1810 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1811 }
1812 return;
1813}
1814
1815#ifdef CONFIG_MSM_BUS_SCALING
1816static struct msm_bus_vectors cam_init_vectors[] = {
1817 {
1818 .src = MSM_BUS_MASTER_VFE,
1819 .dst = MSM_BUS_SLAVE_SMI,
1820 .ab = 0,
1821 .ib = 0,
1822 },
1823 {
1824 .src = MSM_BUS_MASTER_VFE,
1825 .dst = MSM_BUS_SLAVE_EBI_CH0,
1826 .ab = 0,
1827 .ib = 0,
1828 },
1829 {
1830 .src = MSM_BUS_MASTER_VPE,
1831 .dst = MSM_BUS_SLAVE_SMI,
1832 .ab = 0,
1833 .ib = 0,
1834 },
1835 {
1836 .src = MSM_BUS_MASTER_VPE,
1837 .dst = MSM_BUS_SLAVE_EBI_CH0,
1838 .ab = 0,
1839 .ib = 0,
1840 },
1841 {
1842 .src = MSM_BUS_MASTER_JPEG_ENC,
1843 .dst = MSM_BUS_SLAVE_SMI,
1844 .ab = 0,
1845 .ib = 0,
1846 },
1847 {
1848 .src = MSM_BUS_MASTER_JPEG_ENC,
1849 .dst = MSM_BUS_SLAVE_EBI_CH0,
1850 .ab = 0,
1851 .ib = 0,
1852 },
1853};
1854
1855static struct msm_bus_vectors cam_preview_vectors[] = {
1856 {
1857 .src = MSM_BUS_MASTER_VFE,
1858 .dst = MSM_BUS_SLAVE_SMI,
1859 .ab = 0,
1860 .ib = 0,
1861 },
1862 {
1863 .src = MSM_BUS_MASTER_VFE,
1864 .dst = MSM_BUS_SLAVE_EBI_CH0,
1865 .ab = 283115520,
1866 .ib = 452984832,
1867 },
1868 {
1869 .src = MSM_BUS_MASTER_VPE,
1870 .dst = MSM_BUS_SLAVE_SMI,
1871 .ab = 0,
1872 .ib = 0,
1873 },
1874 {
1875 .src = MSM_BUS_MASTER_VPE,
1876 .dst = MSM_BUS_SLAVE_EBI_CH0,
1877 .ab = 0,
1878 .ib = 0,
1879 },
1880 {
1881 .src = MSM_BUS_MASTER_JPEG_ENC,
1882 .dst = MSM_BUS_SLAVE_SMI,
1883 .ab = 0,
1884 .ib = 0,
1885 },
1886 {
1887 .src = MSM_BUS_MASTER_JPEG_ENC,
1888 .dst = MSM_BUS_SLAVE_EBI_CH0,
1889 .ab = 0,
1890 .ib = 0,
1891 },
1892};
1893
1894static struct msm_bus_vectors cam_video_vectors[] = {
1895 {
1896 .src = MSM_BUS_MASTER_VFE,
1897 .dst = MSM_BUS_SLAVE_SMI,
1898 .ab = 283115520,
1899 .ib = 452984832,
1900 },
1901 {
1902 .src = MSM_BUS_MASTER_VFE,
1903 .dst = MSM_BUS_SLAVE_EBI_CH0,
1904 .ab = 283115520,
1905 .ib = 452984832,
1906 },
1907 {
1908 .src = MSM_BUS_MASTER_VPE,
1909 .dst = MSM_BUS_SLAVE_SMI,
1910 .ab = 319610880,
1911 .ib = 511377408,
1912 },
1913 {
1914 .src = MSM_BUS_MASTER_VPE,
1915 .dst = MSM_BUS_SLAVE_EBI_CH0,
1916 .ab = 0,
1917 .ib = 0,
1918 },
1919 {
1920 .src = MSM_BUS_MASTER_JPEG_ENC,
1921 .dst = MSM_BUS_SLAVE_SMI,
1922 .ab = 0,
1923 .ib = 0,
1924 },
1925 {
1926 .src = MSM_BUS_MASTER_JPEG_ENC,
1927 .dst = MSM_BUS_SLAVE_EBI_CH0,
1928 .ab = 0,
1929 .ib = 0,
1930 },
1931};
1932
1933static struct msm_bus_vectors cam_snapshot_vectors[] = {
1934 {
1935 .src = MSM_BUS_MASTER_VFE,
1936 .dst = MSM_BUS_SLAVE_SMI,
1937 .ab = 566231040,
1938 .ib = 905969664,
1939 },
1940 {
1941 .src = MSM_BUS_MASTER_VFE,
1942 .dst = MSM_BUS_SLAVE_EBI_CH0,
1943 .ab = 69984000,
1944 .ib = 111974400,
1945 },
1946 {
1947 .src = MSM_BUS_MASTER_VPE,
1948 .dst = MSM_BUS_SLAVE_SMI,
1949 .ab = 0,
1950 .ib = 0,
1951 },
1952 {
1953 .src = MSM_BUS_MASTER_VPE,
1954 .dst = MSM_BUS_SLAVE_EBI_CH0,
1955 .ab = 0,
1956 .ib = 0,
1957 },
1958 {
1959 .src = MSM_BUS_MASTER_JPEG_ENC,
1960 .dst = MSM_BUS_SLAVE_SMI,
1961 .ab = 320864256,
1962 .ib = 513382810,
1963 },
1964 {
1965 .src = MSM_BUS_MASTER_JPEG_ENC,
1966 .dst = MSM_BUS_SLAVE_EBI_CH0,
1967 .ab = 320864256,
1968 .ib = 513382810,
1969 },
1970};
1971
1972static struct msm_bus_vectors cam_zsl_vectors[] = {
1973 {
1974 .src = MSM_BUS_MASTER_VFE,
1975 .dst = MSM_BUS_SLAVE_SMI,
1976 .ab = 566231040,
1977 .ib = 905969664,
1978 },
1979 {
1980 .src = MSM_BUS_MASTER_VFE,
1981 .dst = MSM_BUS_SLAVE_EBI_CH0,
1982 .ab = 706199040,
1983 .ib = 1129918464,
1984 },
1985 {
1986 .src = MSM_BUS_MASTER_VPE,
1987 .dst = MSM_BUS_SLAVE_SMI,
1988 .ab = 0,
1989 .ib = 0,
1990 },
1991 {
1992 .src = MSM_BUS_MASTER_VPE,
1993 .dst = MSM_BUS_SLAVE_EBI_CH0,
1994 .ab = 0,
1995 .ib = 0,
1996 },
1997 {
1998 .src = MSM_BUS_MASTER_JPEG_ENC,
1999 .dst = MSM_BUS_SLAVE_SMI,
2000 .ab = 320864256,
2001 .ib = 513382810,
2002 },
2003 {
2004 .src = MSM_BUS_MASTER_JPEG_ENC,
2005 .dst = MSM_BUS_SLAVE_EBI_CH0,
2006 .ab = 320864256,
2007 .ib = 513382810,
2008 },
2009};
2010
2011static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2012 {
2013 .src = MSM_BUS_MASTER_VFE,
2014 .dst = MSM_BUS_SLAVE_SMI,
2015 .ab = 212336640,
2016 .ib = 339738624,
2017 },
2018 {
2019 .src = MSM_BUS_MASTER_VFE,
2020 .dst = MSM_BUS_SLAVE_EBI_CH0,
2021 .ab = 25090560,
2022 .ib = 40144896,
2023 },
2024 {
2025 .src = MSM_BUS_MASTER_VPE,
2026 .dst = MSM_BUS_SLAVE_SMI,
2027 .ab = 239708160,
2028 .ib = 383533056,
2029 },
2030 {
2031 .src = MSM_BUS_MASTER_VPE,
2032 .dst = MSM_BUS_SLAVE_EBI_CH0,
2033 .ab = 79902720,
2034 .ib = 127844352,
2035 },
2036 {
2037 .src = MSM_BUS_MASTER_JPEG_ENC,
2038 .dst = MSM_BUS_SLAVE_SMI,
2039 .ab = 0,
2040 .ib = 0,
2041 },
2042 {
2043 .src = MSM_BUS_MASTER_JPEG_ENC,
2044 .dst = MSM_BUS_SLAVE_EBI_CH0,
2045 .ab = 0,
2046 .ib = 0,
2047 },
2048};
2049
2050static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2051 {
2052 .src = MSM_BUS_MASTER_VFE,
2053 .dst = MSM_BUS_SLAVE_SMI,
2054 .ab = 0,
2055 .ib = 0,
2056 },
2057 {
2058 .src = MSM_BUS_MASTER_VFE,
2059 .dst = MSM_BUS_SLAVE_EBI_CH0,
2060 .ab = 300902400,
2061 .ib = 481443840,
2062 },
2063 {
2064 .src = MSM_BUS_MASTER_VPE,
2065 .dst = MSM_BUS_SLAVE_SMI,
2066 .ab = 230307840,
2067 .ib = 368492544,
2068 },
2069 {
2070 .src = MSM_BUS_MASTER_VPE,
2071 .dst = MSM_BUS_SLAVE_EBI_CH0,
2072 .ab = 245113344,
2073 .ib = 392181351,
2074 },
2075 {
2076 .src = MSM_BUS_MASTER_JPEG_ENC,
2077 .dst = MSM_BUS_SLAVE_SMI,
2078 .ab = 106536960,
2079 .ib = 170459136,
2080 },
2081 {
2082 .src = MSM_BUS_MASTER_JPEG_ENC,
2083 .dst = MSM_BUS_SLAVE_EBI_CH0,
2084 .ab = 106536960,
2085 .ib = 170459136,
2086 },
2087};
2088
2089static struct msm_bus_paths cam_bus_client_config[] = {
2090 {
2091 ARRAY_SIZE(cam_init_vectors),
2092 cam_init_vectors,
2093 },
2094 {
2095 ARRAY_SIZE(cam_preview_vectors),
2096 cam_preview_vectors,
2097 },
2098 {
2099 ARRAY_SIZE(cam_video_vectors),
2100 cam_video_vectors,
2101 },
2102 {
2103 ARRAY_SIZE(cam_snapshot_vectors),
2104 cam_snapshot_vectors,
2105 },
2106 {
2107 ARRAY_SIZE(cam_zsl_vectors),
2108 cam_zsl_vectors,
2109 },
2110 {
2111 ARRAY_SIZE(cam_stereo_video_vectors),
2112 cam_stereo_video_vectors,
2113 },
2114 {
2115 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2116 cam_stereo_snapshot_vectors,
2117 },
2118};
2119
2120static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2121 cam_bus_client_config,
2122 ARRAY_SIZE(cam_bus_client_config),
2123 .name = "msm_camera",
2124};
2125#endif
2126
2127struct msm_camera_device_platform_data msm_camera_device_data = {
2128 .camera_gpio_on = config_camera_on_gpios,
2129 .camera_gpio_off = config_camera_off_gpios,
2130 .ioext.csiphy = 0x04800000,
2131 .ioext.csisz = 0x00000400,
2132 .ioext.csiirq = CSI_0_IRQ,
2133 .ioclk.mclk_clk_rate = 24000000,
2134 .ioclk.vfe_clk_rate = 228570000,
2135#ifdef CONFIG_MSM_BUS_SCALING
2136 .cam_bus_scale_table = &cam_bus_client_pdata,
2137#endif
2138};
2139
2140#ifdef CONFIG_QS_S5K4E1
2141struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2142 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2143 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2144 .ioext.csiphy = 0x04800000,
2145 .ioext.csisz = 0x00000400,
2146 .ioext.csiirq = CSI_0_IRQ,
2147 .ioclk.mclk_clk_rate = 24000000,
2148 .ioclk.vfe_clk_rate = 228570000,
2149#ifdef CONFIG_MSM_BUS_SCALING
2150 .cam_bus_scale_table = &cam_bus_client_pdata,
2151#endif
2152};
2153#endif
2154
2155struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2156 .camera_gpio_on = config_camera_on_gpios_web_cam,
2157 .camera_gpio_off = config_camera_off_gpios_web_cam,
2158 .ioext.csiphy = 0x04900000,
2159 .ioext.csisz = 0x00000400,
2160 .ioext.csiirq = CSI_1_IRQ,
2161 .ioclk.mclk_clk_rate = 24000000,
2162 .ioclk.vfe_clk_rate = 228570000,
2163#ifdef CONFIG_MSM_BUS_SCALING
2164 .cam_bus_scale_table = &cam_bus_client_pdata,
2165#endif
2166};
2167
2168struct resource msm_camera_resources[] = {
2169 {
2170 .start = 0x04500000,
2171 .end = 0x04500000 + SZ_1M - 1,
2172 .flags = IORESOURCE_MEM,
2173 },
2174 {
2175 .start = VFE_IRQ,
2176 .end = VFE_IRQ,
2177 .flags = IORESOURCE_IRQ,
2178 },
2179};
2180#ifdef CONFIG_MT9E013
2181static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2182 .mount_angle = 0
2183};
2184
2185static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2186 .flash_type = MSM_CAMERA_FLASH_LED,
2187 .flash_src = &msm_flash_src
2188};
2189
2190static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2191 .sensor_name = "mt9e013",
2192 .sensor_reset = 106,
2193 .sensor_pwd = 85,
2194 .vcm_pwd = 1,
2195 .vcm_enable = 0,
2196 .pdata = &msm_camera_device_data,
2197 .resource = msm_camera_resources,
2198 .num_resources = ARRAY_SIZE(msm_camera_resources),
2199 .flash_data = &flash_mt9e013,
2200 .strobe_flash_data = &strobe_flash_xenon,
2201 .sensor_platform_info = &mt9e013_sensor_8660_info,
2202 .csi_if = 1
2203};
2204struct platform_device msm_camera_sensor_mt9e013 = {
2205 .name = "msm_camera_mt9e013",
2206 .dev = {
2207 .platform_data = &msm_camera_sensor_mt9e013_data,
2208 },
2209};
2210#endif
2211
2212#ifdef CONFIG_IMX074
2213static struct msm_camera_sensor_flash_data flash_imx074 = {
2214 .flash_type = MSM_CAMERA_FLASH_LED,
2215 .flash_src = &msm_flash_src
2216};
2217
2218static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2219 .sensor_name = "imx074",
2220 .sensor_reset = 106,
2221 .sensor_pwd = 85,
2222 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2223 .vcm_enable = 1,
2224 .pdata = &msm_camera_device_data,
2225 .resource = msm_camera_resources,
2226 .num_resources = ARRAY_SIZE(msm_camera_resources),
2227 .flash_data = &flash_imx074,
2228 .strobe_flash_data = &strobe_flash_xenon,
2229 .sensor_platform_info = &sensor_board_info,
2230 .csi_if = 1
2231};
2232struct platform_device msm_camera_sensor_imx074 = {
2233 .name = "msm_camera_imx074",
2234 .dev = {
2235 .platform_data = &msm_camera_sensor_imx074_data,
2236 },
2237};
2238#endif
2239#ifdef CONFIG_WEBCAM_OV9726
2240
2241static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2242 .mount_angle = 0
2243};
2244
2245static struct msm_camera_sensor_flash_data flash_ov9726 = {
2246 .flash_type = MSM_CAMERA_FLASH_LED,
2247 .flash_src = &msm_flash_src
2248};
2249static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2250 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002251 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002252 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2253 .sensor_pwd = 85,
2254 .vcm_pwd = 1,
2255 .vcm_enable = 0,
2256 .pdata = &msm_camera_device_data_web_cam,
2257 .resource = msm_camera_resources,
2258 .num_resources = ARRAY_SIZE(msm_camera_resources),
2259 .flash_data = &flash_ov9726,
2260 .sensor_platform_info = &ov9726_sensor_8660_info,
2261 .csi_if = 1
2262};
2263struct platform_device msm_camera_sensor_webcam_ov9726 = {
2264 .name = "msm_camera_ov9726",
2265 .dev = {
2266 .platform_data = &msm_camera_sensor_ov9726_data,
2267 },
2268};
2269#endif
2270#ifdef CONFIG_WEBCAM_OV7692
2271static struct msm_camera_sensor_flash_data flash_ov7692 = {
2272 .flash_type = MSM_CAMERA_FLASH_LED,
2273 .flash_src = &msm_flash_src
2274};
2275static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2276 .sensor_name = "ov7692",
2277 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2278 .sensor_pwd = 85,
2279 .vcm_pwd = 1,
2280 .vcm_enable = 0,
2281 .pdata = &msm_camera_device_data_web_cam,
2282 .resource = msm_camera_resources,
2283 .num_resources = ARRAY_SIZE(msm_camera_resources),
2284 .flash_data = &flash_ov7692,
2285 .csi_if = 1
2286};
2287
2288static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2289 .name = "msm_camera_ov7692",
2290 .dev = {
2291 .platform_data = &msm_camera_sensor_ov7692_data,
2292 },
2293};
2294#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002295#ifdef CONFIG_VX6953
2296static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2297 .mount_angle = 270
2298};
2299
2300static struct msm_camera_sensor_flash_data flash_vx6953 = {
2301 .flash_type = MSM_CAMERA_FLASH_NONE,
2302 .flash_src = &msm_flash_src
2303};
2304
2305static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2306 .sensor_name = "vx6953",
2307 .sensor_reset = 63,
2308 .sensor_pwd = 63,
2309 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2310 .vcm_enable = 1,
2311 .pdata = &msm_camera_device_data,
2312 .resource = msm_camera_resources,
2313 .num_resources = ARRAY_SIZE(msm_camera_resources),
2314 .flash_data = &flash_vx6953,
2315 .sensor_platform_info = &vx6953_sensor_8660_info,
2316 .csi_if = 1
2317};
2318struct platform_device msm_camera_sensor_vx6953 = {
2319 .name = "msm_camera_vx6953",
2320 .dev = {
2321 .platform_data = &msm_camera_sensor_vx6953_data,
2322 },
2323};
2324#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002325#ifdef CONFIG_QS_S5K4E1
2326
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302327static struct msm_camera_sensor_platform_info qs_s5k4e1_sensor_8660_info = {
2328#ifdef CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
2329 .mount_angle = 90
2330#else
2331 .mount_angle = 0
2332#endif
2333};
2334
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002335static char eeprom_data[864];
2336static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2337 .flash_type = MSM_CAMERA_FLASH_LED,
2338 .flash_src = &msm_flash_src
2339};
2340
2341static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2342 .sensor_name = "qs_s5k4e1",
2343 .sensor_reset = 106,
2344 .sensor_pwd = 85,
2345 .vcm_pwd = 1,
2346 .vcm_enable = 0,
2347 .pdata = &msm_camera_device_data_qs_cam,
2348 .resource = msm_camera_resources,
2349 .num_resources = ARRAY_SIZE(msm_camera_resources),
2350 .flash_data = &flash_qs_s5k4e1,
2351 .strobe_flash_data = &strobe_flash_xenon,
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302352 .sensor_platform_info = &qs_s5k4e1_sensor_8660_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002353 .csi_if = 1,
2354 .eeprom_data = eeprom_data,
2355};
2356struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2357 .name = "msm_camera_qs_s5k4e1",
2358 .dev = {
2359 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2360 },
2361};
2362#endif
2363static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2364 #ifdef CONFIG_MT9E013
2365 {
2366 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2367 },
2368 #endif
2369 #ifdef CONFIG_IMX074
2370 {
2371 I2C_BOARD_INFO("imx074", 0x1A),
2372 },
2373 #endif
2374 #ifdef CONFIG_WEBCAM_OV7692
2375 {
2376 I2C_BOARD_INFO("ov7692", 0x78),
2377 },
2378 #endif
2379 #ifdef CONFIG_WEBCAM_OV9726
2380 {
2381 I2C_BOARD_INFO("ov9726", 0x10),
2382 },
2383 #endif
2384 #ifdef CONFIG_QS_S5K4E1
2385 {
2386 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2387 },
2388 #endif
2389};
Jilai Wang971f97f2011-07-13 14:25:25 -04002390
2391static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002392 #ifdef CONFIG_WEBCAM_OV9726
2393 {
2394 I2C_BOARD_INFO("ov9726", 0x10),
2395 },
2396 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002397 #ifdef CONFIG_VX6953
2398 {
2399 I2C_BOARD_INFO("vx6953", 0x20),
2400 },
2401 #endif
2402};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002403#endif
2404
2405#ifdef CONFIG_MSM_GEMINI
2406static struct resource msm_gemini_resources[] = {
2407 {
2408 .start = 0x04600000,
2409 .end = 0x04600000 + SZ_1M - 1,
2410 .flags = IORESOURCE_MEM,
2411 },
2412 {
2413 .start = INT_JPEG,
2414 .end = INT_JPEG,
2415 .flags = IORESOURCE_IRQ,
2416 },
2417};
2418
2419static struct platform_device msm_gemini_device = {
2420 .name = "msm_gemini",
2421 .resource = msm_gemini_resources,
2422 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2423};
2424#endif
2425
2426#ifdef CONFIG_I2C_QUP
2427static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2428{
2429}
2430
2431static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2432 .clk_freq = 384000,
2433 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002434 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2435};
2436
2437static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2438 .clk_freq = 100000,
2439 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002440 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2441};
2442
2443static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2444 .clk_freq = 100000,
2445 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002446 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2447};
2448
2449static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2450 .clk_freq = 100000,
2451 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002452 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2453};
2454
2455static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2456 .clk_freq = 100000,
2457 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002458 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2459};
2460
2461static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2462 .clk_freq = 100000,
2463 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002464 .use_gsbi_shared_mode = 1,
2465 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2466};
2467#endif
2468
2469#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2470static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2471 .max_clock_speed = 24000000,
2472};
2473
2474static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2475 .max_clock_speed = 24000000,
2476};
2477#endif
2478
2479#ifdef CONFIG_I2C_SSBI
2480/* PMIC SSBI */
2481static struct msm_i2c_ssbi_platform_data msm_ssbi1_pdata = {
2482 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2483};
2484
2485/* PMIC SSBI */
2486static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2487 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2488};
2489
2490/* CODEC/TSSC SSBI */
2491static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2492 .controller_type = MSM_SBI_CTRL_SSBI,
2493};
2494#endif
2495
2496#ifdef CONFIG_BATTERY_MSM
2497/* Use basic value for fake MSM battery */
2498static struct msm_psy_batt_pdata msm_psy_batt_data = {
2499 .avail_chg_sources = AC_CHG,
2500};
2501
2502static struct platform_device msm_batt_device = {
2503 .name = "msm-battery",
2504 .id = -1,
2505 .dev.platform_data = &msm_psy_batt_data,
2506};
2507#endif
2508
2509#ifdef CONFIG_FB_MSM_LCDC_DSUB
2510/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2511 prim = 1024 x 600 x 4(bpp) x 2(pages)
2512 This is the difference. */
2513#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2514#else
2515#define MSM_FB_DSUB_PMEM_ADDER (0)
2516#endif
2517
2518/* Sensors DSPS platform data */
2519#ifdef CONFIG_MSM_DSPS
2520
2521static struct dsps_gpio_info dsps_surf_gpios[] = {
2522 {
2523 .name = "compass_rst_n",
2524 .num = GPIO_COMPASS_RST_N,
2525 .on_val = 1, /* device not in reset */
2526 .off_val = 0, /* device in reset */
2527 },
2528 {
2529 .name = "gpio_r_altimeter_reset_n",
2530 .num = GPIO_R_ALTIMETER_RESET_N,
2531 .on_val = 1, /* device not in reset */
2532 .off_val = 0, /* device in reset */
2533 }
2534};
2535
2536static struct dsps_gpio_info dsps_fluid_gpios[] = {
2537 {
2538 .name = "gpio_n_altimeter_reset_n",
2539 .num = GPIO_N_ALTIMETER_RESET_N,
2540 .on_val = 1, /* device not in reset */
2541 .off_val = 0, /* device in reset */
2542 }
2543};
2544
2545static void __init msm8x60_init_dsps(void)
2546{
2547 struct msm_dsps_platform_data *pdata =
2548 msm_dsps_device.dev.platform_data;
2549 /*
2550 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2551 * to the power supply and not controled via GPIOs. Fluid uses a
2552 * different IO-Expender (north) than used on surf/ffa.
2553 */
2554 if (machine_is_msm8x60_fluid()) {
2555 /* fluid has different firmware, gpios */
2556 peripheral_dsps.name = DSPS_PIL_FLUID_NAME;
2557 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2558 pdata->gpios = dsps_fluid_gpios;
2559 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2560 } else {
2561 peripheral_dsps.name = DSPS_PIL_GENERIC_NAME;
2562 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2563 pdata->gpios = dsps_surf_gpios;
2564 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2565 }
2566
2567 msm_pil_add_device(&peripheral_dsps);
2568
2569 platform_device_register(&msm_dsps_device);
2570}
2571#endif /* CONFIG_MSM_DSPS */
2572
2573#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002574#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002575#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002576#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002577#endif
2578
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002579#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2580#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
2581#elif defined(CONFIG_FB_MSM_TVOUT)
2582#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
2583#else
2584#define MSM_FB_EXT_BUFT_SIZE 0
2585#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002586
2587#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002588/* width x height x 3 bpp x 2 frame buffer */
2589#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002590#define MSM_FB_WRITEBACK_OFFSET \
2591 (MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002592#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002593#define MSM_FB_WRITEBACK_SIZE 0
2594#define MSM_FB_WRITEBACK_OFFSET 0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002595#endif
2596
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002597#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2598/* 4 bpp x 2 page HDMI case */
2599#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
2600#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002601/* Note: must be multiple of 4096 */
2602#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
2603 MSM_FB_WRITEBACK_SIZE + \
2604 MSM_FB_DSUB_PMEM_ADDER, 4096)
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002605#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002606
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002607#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2608#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
2609#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002610#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002611#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002612
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002613static int writeback_offset(void)
2614{
2615 return MSM_FB_WRITEBACK_OFFSET;
2616}
2617
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002618#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2619#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002620#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002621
2622#define MSM_SMI_BASE 0x38000000
2623#define MSM_SMI_SIZE 0x4000000
2624
2625#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2626#define KERNEL_SMI_SIZE 0x300000
2627
2628#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2629#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2630#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2631
2632static unsigned fb_size;
2633static int __init fb_size_setup(char *p)
2634{
2635 fb_size = memparse(p, NULL);
2636 return 0;
2637}
2638early_param("fb_size", fb_size_setup);
2639
2640static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2641static int __init pmem_kernel_ebi1_size_setup(char *p)
2642{
2643 pmem_kernel_ebi1_size = memparse(p, NULL);
2644 return 0;
2645}
2646early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2647
2648#ifdef CONFIG_ANDROID_PMEM
2649static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2650static int __init pmem_sf_size_setup(char *p)
2651{
2652 pmem_sf_size = memparse(p, NULL);
2653 return 0;
2654}
2655early_param("pmem_sf_size", pmem_sf_size_setup);
2656
2657static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2658
2659static int __init pmem_adsp_size_setup(char *p)
2660{
2661 pmem_adsp_size = memparse(p, NULL);
2662 return 0;
2663}
2664early_param("pmem_adsp_size", pmem_adsp_size_setup);
2665
2666static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2667
2668static int __init pmem_audio_size_setup(char *p)
2669{
2670 pmem_audio_size = memparse(p, NULL);
2671 return 0;
2672}
2673early_param("pmem_audio_size", pmem_audio_size_setup);
2674#endif
2675
2676static struct resource msm_fb_resources[] = {
2677 {
2678 .flags = IORESOURCE_DMA,
2679 }
2680};
2681
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002682static int msm_fb_detect_panel(const char *name)
2683{
2684 if (machine_is_msm8x60_fluid()) {
2685 uint32_t soc_platform_version = socinfo_get_platform_version();
2686 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2687#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2688 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002689 strnlen(LCDC_SAMSUNG_OLED_PANEL_NAME,
2690 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002691 return 0;
2692#endif
2693 } else { /*P3 and up use AUO panel */
2694#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2695 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002696 strnlen(LCDC_AUO_PANEL_NAME,
2697 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002698 return 0;
2699#endif
2700 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002701#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2702 } else if machine_is_msm8x60_dragon() {
2703 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002704 strnlen(LCDC_NT35582_PANEL_NAME,
2705 PANEL_NAME_MAX_LEN)))
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002706 return 0;
2707#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002708 } else {
2709 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002710 strnlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2711 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002712 return 0;
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002713
2714#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
2715 !defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
2716 !defined(CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT)
2717 if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2718 strnlen(MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2719 PANEL_NAME_MAX_LEN)))
2720 return 0;
2721
2722 if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2723 strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2724 PANEL_NAME_MAX_LEN)))
2725 return 0;
2726
2727 if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2728 strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2729 PANEL_NAME_MAX_LEN)))
2730 return 0;
2731#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002732 }
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002733
2734 if (!strncmp(name, HDMI_PANEL_NAME,
2735 strnlen(HDMI_PANEL_NAME,
2736 PANEL_NAME_MAX_LEN)))
2737 return 0;
2738
2739 if (!strncmp(name, TVOUT_PANEL_NAME,
2740 strnlen(TVOUT_PANEL_NAME,
2741 PANEL_NAME_MAX_LEN)))
2742 return 0;
2743
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002744 pr_warning("%s: not supported '%s'", __func__, name);
2745 return -ENODEV;
2746}
2747
2748static struct msm_fb_platform_data msm_fb_pdata = {
2749 .detect_client = msm_fb_detect_panel,
2750};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002751
2752static struct platform_device msm_fb_device = {
2753 .name = "msm_fb",
2754 .id = 0,
2755 .num_resources = ARRAY_SIZE(msm_fb_resources),
2756 .resource = msm_fb_resources,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002757 .dev.platform_data = &msm_fb_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002758};
2759
2760#ifdef CONFIG_ANDROID_PMEM
2761static struct android_pmem_platform_data android_pmem_pdata = {
2762 .name = "pmem",
2763 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2764 .cached = 1,
2765 .memory_type = MEMTYPE_EBI1,
2766};
2767
2768static struct platform_device android_pmem_device = {
2769 .name = "android_pmem",
2770 .id = 0,
2771 .dev = {.platform_data = &android_pmem_pdata},
2772};
2773
2774static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2775 .name = "pmem_adsp",
2776 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2777 .cached = 0,
2778 .memory_type = MEMTYPE_EBI1,
2779};
2780
2781static struct platform_device android_pmem_adsp_device = {
2782 .name = "android_pmem",
2783 .id = 2,
2784 .dev = { .platform_data = &android_pmem_adsp_pdata },
2785};
2786
2787static struct android_pmem_platform_data android_pmem_audio_pdata = {
2788 .name = "pmem_audio",
2789 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2790 .cached = 0,
2791 .memory_type = MEMTYPE_EBI1,
2792};
2793
2794static struct platform_device android_pmem_audio_device = {
2795 .name = "android_pmem",
2796 .id = 4,
2797 .dev = { .platform_data = &android_pmem_audio_pdata },
2798};
2799
Laura Abbott1e36a022011-06-22 17:08:13 -07002800#define PMEM_BUS_WIDTH(_bw) \
2801 { \
2802 .vectors = &(struct msm_bus_vectors){ \
2803 .src = MSM_BUS_MASTER_AMPSS_M0, \
2804 .dst = MSM_BUS_SLAVE_SMI, \
2805 .ib = (_bw), \
2806 .ab = 0, \
2807 }, \
2808 .num_paths = 1, \
2809 }
2810static struct msm_bus_paths pmem_smi_table[] = {
2811 [0] = PMEM_BUS_WIDTH(0), /* Off */
2812 [1] = PMEM_BUS_WIDTH(1), /* On */
2813};
2814
2815static struct msm_bus_scale_pdata smi_client_pdata = {
2816 .usecase = pmem_smi_table,
2817 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2818 .name = "pmem_smi",
2819};
2820
2821void pmem_request_smi_region(void *data)
2822{
2823 int bus_id = (int) data;
2824
2825 msm_bus_scale_client_update_request(bus_id, 1);
2826}
2827
2828void pmem_release_smi_region(void *data)
2829{
2830 int bus_id = (int) data;
2831
2832 msm_bus_scale_client_update_request(bus_id, 0);
2833}
2834
2835void *pmem_setup_smi_region(void)
2836{
2837 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2838}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002839static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2840 .name = "pmem_smipool",
2841 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2842 .cached = 0,
2843 .memory_type = MEMTYPE_SMI,
Laura Abbott1e36a022011-06-22 17:08:13 -07002844 .request_region = pmem_request_smi_region,
2845 .release_region = pmem_release_smi_region,
2846 .setup_region = pmem_setup_smi_region,
2847 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002848};
2849static struct platform_device android_pmem_smipool_device = {
2850 .name = "android_pmem",
2851 .id = 7,
2852 .dev = { .platform_data = &android_pmem_smipool_pdata },
2853};
2854
2855#endif
2856
2857#define GPIO_DONGLE_PWR_EN 258
2858static void setup_display_power(void);
2859static int lcdc_vga_enabled;
2860static int vga_enable_request(int enable)
2861{
2862 if (enable)
2863 lcdc_vga_enabled = 1;
2864 else
2865 lcdc_vga_enabled = 0;
2866 setup_display_power();
2867
2868 return 0;
2869}
2870
2871#define GPIO_BACKLIGHT_PWM0 0
2872#define GPIO_BACKLIGHT_PWM1 1
2873
2874static int pmic_backlight_gpio[2]
2875 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2876static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2877 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2878 .vga_switch = vga_enable_request,
2879};
2880
2881static struct platform_device lcdc_samsung_panel_device = {
2882 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2883 .id = 0,
2884 .dev = {
2885 .platform_data = &lcdc_samsung_panel_data,
2886 }
2887};
2888#if (!defined(CONFIG_SPI_QUP)) && \
2889 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2890 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2891
2892static int lcdc_spi_gpio_array_num[] = {
2893 LCDC_SPI_GPIO_CLK,
2894 LCDC_SPI_GPIO_CS,
2895 LCDC_SPI_GPIO_MOSI,
2896};
2897
2898static uint32_t lcdc_spi_gpio_config_data[] = {
2899 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2900 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2901 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2902 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2903 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2904 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2905};
2906
2907static void lcdc_config_spi_gpios(int enable)
2908{
2909 int n;
2910 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2911 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2912}
2913#endif
2914
2915#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2916#ifdef CONFIG_SPI_QUP
2917static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2918 {
2919 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2920 .mode = SPI_MODE_3,
2921 .bus_num = 1,
2922 .chip_select = 0,
2923 .max_speed_hz = 10800000,
2924 }
2925};
2926#endif /* CONFIG_SPI_QUP */
2927
2928static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2929#ifndef CONFIG_SPI_QUP
2930 .panel_config_gpio = lcdc_config_spi_gpios,
2931 .gpio_num = lcdc_spi_gpio_array_num,
2932#endif
2933};
2934
2935static struct platform_device lcdc_samsung_oled_panel_device = {
2936 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2937 .id = 0,
2938 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2939};
2940#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2941
2942#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2943#ifdef CONFIG_SPI_QUP
2944static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2945 {
2946 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2947 .mode = SPI_MODE_3,
2948 .bus_num = 1,
2949 .chip_select = 0,
2950 .max_speed_hz = 10800000,
2951 }
2952};
2953#endif
2954
2955static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
2956#ifndef CONFIG_SPI_QUP
2957 .panel_config_gpio = lcdc_config_spi_gpios,
2958 .gpio_num = lcdc_spi_gpio_array_num,
2959#endif
2960};
2961
2962static struct platform_device lcdc_auo_wvga_panel_device = {
2963 .name = LCDC_AUO_PANEL_NAME,
2964 .id = 0,
2965 .dev.platform_data = &lcdc_auo_wvga_panel_data,
2966};
2967#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
2968
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002969#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2970
2971#define GPIO_NT35582_RESET 94
2972#define GPIO_NT35582_BL_EN_HW_PIN 24
2973#define GPIO_NT35582_BL_EN \
2974 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
2975
2976static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
2977
2978static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
2979 .gpio_num = lcdc_nt35582_pmic_gpio,
2980};
2981
2982static struct platform_device lcdc_nt35582_panel_device = {
2983 .name = LCDC_NT35582_PANEL_NAME,
2984 .id = 0,
2985 .dev = {
2986 .platform_data = &lcdc_nt35582_panel_data,
2987 }
2988};
2989
2990static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
2991 {
2992 .modalias = "lcdc_nt35582_spi",
2993 .mode = SPI_MODE_0,
2994 .bus_num = 0,
2995 .chip_select = 0,
2996 .max_speed_hz = 1100000,
2997 }
2998};
2999#endif
3000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003001#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
3002static struct resource hdmi_msm_resources[] = {
3003 {
3004 .name = "hdmi_msm_qfprom_addr",
3005 .start = 0x00700000,
3006 .end = 0x007060FF,
3007 .flags = IORESOURCE_MEM,
3008 },
3009 {
3010 .name = "hdmi_msm_hdmi_addr",
3011 .start = 0x04A00000,
3012 .end = 0x04A00FFF,
3013 .flags = IORESOURCE_MEM,
3014 },
3015 {
3016 .name = "hdmi_msm_irq",
3017 .start = HDMI_IRQ,
3018 .end = HDMI_IRQ,
3019 .flags = IORESOURCE_IRQ,
3020 },
3021};
3022
3023static int hdmi_enable_5v(int on);
3024static int hdmi_core_power(int on, int show);
3025static int hdmi_cec_power(int on);
3026
3027static struct msm_hdmi_platform_data hdmi_msm_data = {
3028 .irq = HDMI_IRQ,
3029 .enable_5v = hdmi_enable_5v,
3030 .core_power = hdmi_core_power,
3031 .cec_power = hdmi_cec_power,
3032};
3033
3034static struct platform_device hdmi_msm_device = {
3035 .name = "hdmi_msm",
3036 .id = 0,
3037 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
3038 .resource = hdmi_msm_resources,
3039 .dev.platform_data = &hdmi_msm_data,
3040};
3041#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
3042
3043#ifdef CONFIG_FB_MSM_MIPI_DSI
3044static struct platform_device mipi_dsi_toshiba_panel_device = {
3045 .name = "mipi_toshiba",
3046 .id = 0,
3047};
3048
3049#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3050
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003051static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003052 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
Chandan Uddaraju83eac3c2011-09-11 18:32:23 -07003053 .fpga_ctrl_mode = FPGA_EBI2_INTF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003054};
3055
3056static struct platform_device mipi_dsi_novatek_panel_device = {
3057 .name = "mipi_novatek",
3058 .id = 0,
3059 .dev = {
3060 .platform_data = &novatek_pdata,
3061 }
3062};
3063#endif
3064
3065static void __init msm8x60_allocate_memory_regions(void)
3066{
3067 void *addr;
3068 unsigned long size;
3069
3070 size = MSM_FB_SIZE;
3071 addr = alloc_bootmem_align(size, 0x1000);
3072 msm_fb_resources[0].start = __pa(addr);
3073 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3074 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3075 size, addr, __pa(addr));
3076
3077}
3078
3079#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3080 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3081/*virtual key support */
3082static ssize_t tma300_vkeys_show(struct kobject *kobj,
3083 struct kobj_attribute *attr, char *buf)
3084{
3085 return sprintf(buf,
3086 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3087 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3088 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3089 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3090 "\n");
3091}
3092
3093static struct kobj_attribute tma300_vkeys_attr = {
3094 .attr = {
3095 .mode = S_IRUGO,
3096 },
3097 .show = &tma300_vkeys_show,
3098};
3099
3100static struct attribute *tma300_properties_attrs[] = {
3101 &tma300_vkeys_attr.attr,
3102 NULL
3103};
3104
3105static struct attribute_group tma300_properties_attr_group = {
3106 .attrs = tma300_properties_attrs,
3107};
3108
3109static struct kobject *properties_kobj;
3110
3111
3112
3113#define CYTTSP_TS_GPIO_IRQ 61
3114static int cyttsp_platform_init(struct i2c_client *client)
3115{
3116 int rc = -EINVAL;
3117 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3118
3119 if (machine_is_msm8x60_fluid()) {
3120 pm8058_l5 = regulator_get(NULL, "8058_l5");
3121 if (IS_ERR(pm8058_l5)) {
3122 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3123 __func__, PTR_ERR(pm8058_l5));
3124 rc = PTR_ERR(pm8058_l5);
3125 return rc;
3126 }
3127 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3128 if (rc) {
3129 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3130 __func__, rc);
3131 goto reg_l5_put;
3132 }
3133
3134 rc = regulator_enable(pm8058_l5);
3135 if (rc) {
3136 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3137 __func__, rc);
3138 goto reg_l5_put;
3139 }
3140 }
3141 /* vote for s3 to enable i2c communication lines */
3142 pm8058_s3 = regulator_get(NULL, "8058_s3");
3143 if (IS_ERR(pm8058_s3)) {
3144 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3145 __func__, PTR_ERR(pm8058_s3));
3146 rc = PTR_ERR(pm8058_s3);
3147 goto reg_l5_disable;
3148 }
3149
3150 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3151 if (rc) {
3152 pr_err("%s: regulator_set_voltage() = %d\n",
3153 __func__, rc);
3154 goto reg_s3_put;
3155 }
3156
3157 rc = regulator_enable(pm8058_s3);
3158 if (rc) {
3159 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3160 __func__, rc);
3161 goto reg_s3_put;
3162 }
3163
3164 /* wait for vregs to stabilize */
3165 usleep_range(10000, 10000);
3166
3167 /* check this device active by reading first byte/register */
3168 rc = i2c_smbus_read_byte_data(client, 0x01);
3169 if (rc < 0) {
3170 pr_err("%s: i2c sanity check failed\n", __func__);
3171 goto reg_s3_disable;
3172 }
3173
3174 /* virtual keys */
3175 if (machine_is_msm8x60_fluid()) {
3176 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3177 properties_kobj = kobject_create_and_add("board_properties",
3178 NULL);
3179 if (properties_kobj)
3180 rc = sysfs_create_group(properties_kobj,
3181 &tma300_properties_attr_group);
3182 if (!properties_kobj || rc)
3183 pr_err("%s: failed to create board_properties\n",
3184 __func__);
3185 }
3186 return CY_OK;
3187
3188reg_s3_disable:
3189 regulator_disable(pm8058_s3);
3190reg_s3_put:
3191 regulator_put(pm8058_s3);
3192reg_l5_disable:
3193 if (machine_is_msm8x60_fluid())
3194 regulator_disable(pm8058_l5);
3195reg_l5_put:
3196 if (machine_is_msm8x60_fluid())
3197 regulator_put(pm8058_l5);
3198 return rc;
3199}
3200
3201static int cyttsp_platform_resume(struct i2c_client *client)
3202{
3203 /* add any special code to strobe a wakeup pin or chip reset */
3204 msleep(10);
3205
3206 return CY_OK;
3207}
3208
3209static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3210 .flags = 0x04,
3211 .gen = CY_GEN3, /* or */
3212 .use_st = CY_USE_ST,
3213 .use_mt = CY_USE_MT,
3214 .use_hndshk = CY_SEND_HNDSHK,
3215 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303216 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003217 .use_gestures = CY_USE_GESTURES,
3218 /* activate up to 4 groups
3219 * and set active distance
3220 */
3221 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3222 CY_GEST_GRP3 | CY_GEST_GRP4 |
3223 CY_ACT_DIST,
3224 /* change act_intrvl to customize the Active power state
3225 * scanning/processing refresh interval for Operating mode
3226 */
3227 .act_intrvl = CY_ACT_INTRVL_DFLT,
3228 /* change tch_tmout to customize the touch timeout for the
3229 * Active power state for Operating mode
3230 */
3231 .tch_tmout = CY_TCH_TMOUT_DFLT,
3232 /* change lp_intrvl to customize the Low Power power state
3233 * scanning/processing refresh interval for Operating mode
3234 */
3235 .lp_intrvl = CY_LP_INTRVL_DFLT,
3236 .sleep_gpio = -1,
3237 .resout_gpio = -1,
3238 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3239 .resume = cyttsp_platform_resume,
3240 .init = cyttsp_platform_init,
3241};
3242
3243static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3244 .panel_maxx = 1083,
3245 .panel_maxy = 659,
3246 .disp_minx = 30,
3247 .disp_maxx = 1053,
3248 .disp_miny = 30,
3249 .disp_maxy = 629,
3250 .correct_fw_ver = 8,
3251 .fw_fname = "cyttsp_8660_ffa.hex",
3252 .flags = 0x00,
3253 .gen = CY_GEN2, /* or */
3254 .use_st = CY_USE_ST,
3255 .use_mt = CY_USE_MT,
3256 .use_hndshk = CY_SEND_HNDSHK,
3257 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303258 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003259 .use_gestures = CY_USE_GESTURES,
3260 /* activate up to 4 groups
3261 * and set active distance
3262 */
3263 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3264 CY_GEST_GRP3 | CY_GEST_GRP4 |
3265 CY_ACT_DIST,
3266 /* change act_intrvl to customize the Active power state
3267 * scanning/processing refresh interval for Operating mode
3268 */
3269 .act_intrvl = CY_ACT_INTRVL_DFLT,
3270 /* change tch_tmout to customize the touch timeout for the
3271 * Active power state for Operating mode
3272 */
3273 .tch_tmout = CY_TCH_TMOUT_DFLT,
3274 /* change lp_intrvl to customize the Low Power power state
3275 * scanning/processing refresh interval for Operating mode
3276 */
3277 .lp_intrvl = CY_LP_INTRVL_DFLT,
3278 .sleep_gpio = -1,
3279 .resout_gpio = -1,
3280 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3281 .resume = cyttsp_platform_resume,
3282 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303283 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003284};
3285static void cyttsp_set_params(void)
3286{
3287 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3288 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3289 cyttsp_fluid_pdata.panel_maxx = 539;
3290 cyttsp_fluid_pdata.panel_maxy = 994;
3291 cyttsp_fluid_pdata.disp_minx = 30;
3292 cyttsp_fluid_pdata.disp_maxx = 509;
3293 cyttsp_fluid_pdata.disp_miny = 60;
3294 cyttsp_fluid_pdata.disp_maxy = 859;
3295 cyttsp_fluid_pdata.correct_fw_ver = 4;
3296 } else {
3297 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3298 cyttsp_fluid_pdata.panel_maxx = 550;
3299 cyttsp_fluid_pdata.panel_maxy = 1013;
3300 cyttsp_fluid_pdata.disp_minx = 35;
3301 cyttsp_fluid_pdata.disp_maxx = 515;
3302 cyttsp_fluid_pdata.disp_miny = 69;
3303 cyttsp_fluid_pdata.disp_maxy = 869;
3304 cyttsp_fluid_pdata.correct_fw_ver = 5;
3305 }
3306
3307}
3308
3309static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3310 {
3311 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3312 .platform_data = &cyttsp_fluid_pdata,
3313#ifndef CY_USE_TIMER
3314 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3315#endif /* CY_USE_TIMER */
3316 },
3317};
3318
3319static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3320 {
3321 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3322 .platform_data = &cyttsp_tmg240_pdata,
3323#ifndef CY_USE_TIMER
3324 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3325#endif /* CY_USE_TIMER */
3326 },
3327};
3328#endif
3329
3330static struct regulator *vreg_tmg200;
3331
3332#define TS_PEN_IRQ_GPIO 61
3333static int tmg200_power(int vreg_on)
3334{
3335 int rc = -EINVAL;
3336
3337 if (!vreg_tmg200) {
3338 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3339 __func__, rc);
3340 return rc;
3341 }
3342
3343 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3344 regulator_disable(vreg_tmg200);
3345 if (rc < 0)
3346 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3347 __func__, vreg_on ? "enable" : "disable", rc);
3348
3349 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003350 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003351
3352 return rc;
3353}
3354
3355static int tmg200_dev_setup(bool enable)
3356{
3357 int rc;
3358
3359 if (enable) {
3360 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3361 if (IS_ERR(vreg_tmg200)) {
3362 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3363 __func__, PTR_ERR(vreg_tmg200));
3364 rc = PTR_ERR(vreg_tmg200);
3365 return rc;
3366 }
3367
3368 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3369 if (rc) {
3370 pr_err("%s: regulator_set_voltage() = %d\n",
3371 __func__, rc);
3372 goto reg_put;
3373 }
3374 } else {
3375 /* put voltage sources */
3376 regulator_put(vreg_tmg200);
3377 }
3378 return 0;
3379reg_put:
3380 regulator_put(vreg_tmg200);
3381 return rc;
3382}
3383
3384static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3385 .ts_name = "msm_tmg200_ts",
3386 .dis_min_x = 0,
3387 .dis_max_x = 1023,
3388 .dis_min_y = 0,
3389 .dis_max_y = 599,
3390 .min_tid = 0,
3391 .max_tid = 255,
3392 .min_touch = 0,
3393 .max_touch = 255,
3394 .min_width = 0,
3395 .max_width = 255,
3396 .power_on = tmg200_power,
3397 .dev_setup = tmg200_dev_setup,
3398 .nfingers = 2,
3399 .irq_gpio = TS_PEN_IRQ_GPIO,
3400 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3401};
3402
3403static struct i2c_board_info cy8ctmg200_board_info[] = {
3404 {
3405 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3406 .platform_data = &cy8ctmg200_pdata,
3407 }
3408};
3409
Zhang Chang Ken211df572011-07-05 19:16:39 -04003410static struct regulator *vreg_tma340;
3411
3412static int tma340_power(int vreg_on)
3413{
3414 int rc = -EINVAL;
3415
3416 if (!vreg_tma340) {
3417 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3418 __func__, rc);
3419 return rc;
3420 }
3421
3422 rc = vreg_on ? regulator_enable(vreg_tma340) :
3423 regulator_disable(vreg_tma340);
3424 if (rc < 0)
3425 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3426 __func__, vreg_on ? "enable" : "disable", rc);
3427
3428 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003429 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003430
3431 return rc;
3432}
3433
3434static struct kobject *tma340_prop_kobj;
3435
3436static int tma340_dragon_dev_setup(bool enable)
3437{
3438 int rc;
3439
3440 if (enable) {
3441 vreg_tma340 = regulator_get(NULL, "8901_l2");
3442 if (IS_ERR(vreg_tma340)) {
3443 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3444 __func__, PTR_ERR(vreg_tma340));
3445 rc = PTR_ERR(vreg_tma340);
3446 return rc;
3447 }
3448
3449 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3450 if (rc) {
3451 pr_err("%s: regulator_set_voltage() = %d\n",
3452 __func__, rc);
3453 goto reg_put;
3454 }
3455 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3456 tma340_prop_kobj = kobject_create_and_add("board_properties",
3457 NULL);
3458 if (tma340_prop_kobj) {
3459 rc = sysfs_create_group(tma340_prop_kobj,
3460 &tma300_properties_attr_group);
3461 if (rc) {
3462 kobject_put(tma340_prop_kobj);
3463 pr_err("%s: failed to create board_properties\n",
3464 __func__);
3465 goto reg_put;
3466 }
3467 }
3468
3469 } else {
3470 /* put voltage sources */
3471 regulator_put(vreg_tma340);
3472 /* destroy virtual keys */
3473 if (tma340_prop_kobj) {
3474 sysfs_remove_group(tma340_prop_kobj,
3475 &tma300_properties_attr_group);
3476 kobject_put(tma340_prop_kobj);
3477 }
3478 }
3479 return 0;
3480reg_put:
3481 regulator_put(vreg_tma340);
3482 return rc;
3483}
3484
3485
3486static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3487 .ts_name = "cy8ctma340",
3488 .dis_min_x = 0,
3489 .dis_max_x = 479,
3490 .dis_min_y = 0,
3491 .dis_max_y = 799,
3492 .min_tid = 0,
3493 .max_tid = 255,
3494 .min_touch = 0,
3495 .max_touch = 255,
3496 .min_width = 0,
3497 .max_width = 255,
3498 .power_on = tma340_power,
3499 .dev_setup = tma340_dragon_dev_setup,
3500 .nfingers = 2,
3501 .irq_gpio = TS_PEN_IRQ_GPIO,
3502 .resout_gpio = -1,
3503};
3504
3505static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3506 {
3507 I2C_BOARD_INFO("cy8ctma340", 0x24),
3508 .platform_data = &cy8ctma340_dragon_pdata,
3509 }
3510};
3511
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003512#ifdef CONFIG_SERIAL_MSM_HS
3513static int configure_uart_gpios(int on)
3514{
3515 int ret = 0, i;
3516 int uart_gpios[] = {53, 54, 55, 56};
3517 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3518 if (on) {
3519 ret = msm_gpiomux_get(uart_gpios[i]);
3520 if (unlikely(ret))
3521 break;
3522 } else {
3523 ret = msm_gpiomux_put(uart_gpios[i]);
3524 if (unlikely(ret))
3525 return ret;
3526 }
3527 }
3528 if (ret)
3529 for (; i >= 0; i--)
3530 msm_gpiomux_put(uart_gpios[i]);
3531 return ret;
3532}
3533static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3534 .inject_rx_on_wakeup = 1,
3535 .rx_to_inject = 0xFD,
3536 .gpio_config = configure_uart_gpios,
3537};
3538#endif
3539
3540
3541#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3542
3543static struct gpio_led gpio_exp_leds_config[] = {
3544 {
3545 .name = "left_led1:green",
3546 .gpio = GPIO_LEFT_LED_1,
3547 .active_low = 1,
3548 .retain_state_suspended = 0,
3549 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3550 },
3551 {
3552 .name = "left_led2:red",
3553 .gpio = GPIO_LEFT_LED_2,
3554 .active_low = 1,
3555 .retain_state_suspended = 0,
3556 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3557 },
3558 {
3559 .name = "left_led3:green",
3560 .gpio = GPIO_LEFT_LED_3,
3561 .active_low = 1,
3562 .retain_state_suspended = 0,
3563 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3564 },
3565 {
3566 .name = "wlan_led:orange",
3567 .gpio = GPIO_LEFT_LED_WLAN,
3568 .active_low = 1,
3569 .retain_state_suspended = 0,
3570 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3571 },
3572 {
3573 .name = "left_led5:green",
3574 .gpio = GPIO_LEFT_LED_5,
3575 .active_low = 1,
3576 .retain_state_suspended = 0,
3577 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3578 },
3579 {
3580 .name = "right_led1:green",
3581 .gpio = GPIO_RIGHT_LED_1,
3582 .active_low = 1,
3583 .retain_state_suspended = 0,
3584 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3585 },
3586 {
3587 .name = "right_led2:red",
3588 .gpio = GPIO_RIGHT_LED_2,
3589 .active_low = 1,
3590 .retain_state_suspended = 0,
3591 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3592 },
3593 {
3594 .name = "right_led3:green",
3595 .gpio = GPIO_RIGHT_LED_3,
3596 .active_low = 1,
3597 .retain_state_suspended = 0,
3598 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3599 },
3600 {
3601 .name = "bt_led:blue",
3602 .gpio = GPIO_RIGHT_LED_BT,
3603 .active_low = 1,
3604 .retain_state_suspended = 0,
3605 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3606 },
3607 {
3608 .name = "right_led5:green",
3609 .gpio = GPIO_RIGHT_LED_5,
3610 .active_low = 1,
3611 .retain_state_suspended = 0,
3612 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3613 },
3614};
3615
3616static struct gpio_led_platform_data gpio_leds_pdata = {
3617 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3618 .leds = gpio_exp_leds_config,
3619};
3620
3621static struct platform_device gpio_leds = {
3622 .name = "leds-gpio",
3623 .id = -1,
3624 .dev = {
3625 .platform_data = &gpio_leds_pdata,
3626 },
3627};
3628
3629static struct gpio_led fluid_gpio_leds[] = {
3630 {
3631 .name = "dual_led:green",
3632 .gpio = GPIO_LED1_GREEN_N,
3633 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3634 .active_low = 1,
3635 .retain_state_suspended = 0,
3636 },
3637 {
3638 .name = "dual_led:red",
3639 .gpio = GPIO_LED2_RED_N,
3640 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3641 .active_low = 1,
3642 .retain_state_suspended = 0,
3643 },
3644};
3645
3646static struct gpio_led_platform_data gpio_led_pdata = {
3647 .leds = fluid_gpio_leds,
3648 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3649};
3650
3651static struct platform_device fluid_leds_gpio = {
3652 .name = "leds-gpio",
3653 .id = -1,
3654 .dev = {
3655 .platform_data = &gpio_led_pdata,
3656 },
3657};
3658
3659#endif
3660
3661#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3662
3663static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3664 .phys_addr_base = 0x00106000,
3665 .reg_offsets = {
3666 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3667 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3668 },
3669 .phys_size = SZ_8K,
3670 .log_len = 4096, /* log's buffer length in bytes */
3671 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3672};
3673
3674static struct platform_device msm_rpm_log_device = {
3675 .name = "msm_rpm_log",
3676 .id = -1,
3677 .dev = {
3678 .platform_data = &msm_rpm_log_pdata,
3679 },
3680};
3681#endif
3682
3683#ifdef CONFIG_BATTERY_MSM8X60
3684static struct msm_charger_platform_data msm_charger_data = {
3685 .safety_time = 180,
3686 .update_time = 1,
3687 .max_voltage = 4200,
3688 .min_voltage = 3200,
3689};
3690
3691static struct platform_device msm_charger_device = {
3692 .name = "msm-charger",
3693 .id = -1,
3694 .dev = {
3695 .platform_data = &msm_charger_data,
3696 }
3697};
3698#endif
3699
3700/*
3701 * Consumer specific regulator names:
3702 * regulator name consumer dev_name
3703 */
3704static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3705 REGULATOR_SUPPLY("8058_l0", NULL),
3706};
3707static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3708 REGULATOR_SUPPLY("8058_l1", NULL),
3709};
3710static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3711 REGULATOR_SUPPLY("8058_l2", NULL),
3712};
3713static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3714 REGULATOR_SUPPLY("8058_l3", NULL),
3715};
3716static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3717 REGULATOR_SUPPLY("8058_l4", NULL),
3718};
3719static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3720 REGULATOR_SUPPLY("8058_l5", NULL),
3721};
3722static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3723 REGULATOR_SUPPLY("8058_l6", NULL),
3724};
3725static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3726 REGULATOR_SUPPLY("8058_l7", NULL),
3727};
3728static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3729 REGULATOR_SUPPLY("8058_l8", NULL),
3730};
3731static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3732 REGULATOR_SUPPLY("8058_l9", NULL),
3733};
3734static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3735 REGULATOR_SUPPLY("8058_l10", NULL),
3736};
3737static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3738 REGULATOR_SUPPLY("8058_l11", NULL),
3739};
3740static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3741 REGULATOR_SUPPLY("8058_l12", NULL),
3742};
3743static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3744 REGULATOR_SUPPLY("8058_l13", NULL),
3745};
3746static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3747 REGULATOR_SUPPLY("8058_l14", NULL),
3748};
3749static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3750 REGULATOR_SUPPLY("8058_l15", NULL),
3751};
3752static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3753 REGULATOR_SUPPLY("8058_l16", NULL),
3754};
3755static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3756 REGULATOR_SUPPLY("8058_l17", NULL),
3757};
3758static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3759 REGULATOR_SUPPLY("8058_l18", NULL),
3760};
3761static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3762 REGULATOR_SUPPLY("8058_l19", NULL),
3763};
3764static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3765 REGULATOR_SUPPLY("8058_l20", NULL),
3766};
3767static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3768 REGULATOR_SUPPLY("8058_l21", NULL),
3769};
3770static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3771 REGULATOR_SUPPLY("8058_l22", NULL),
3772};
3773static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3774 REGULATOR_SUPPLY("8058_l23", NULL),
3775};
3776static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3777 REGULATOR_SUPPLY("8058_l24", NULL),
3778};
3779static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3780 REGULATOR_SUPPLY("8058_l25", NULL),
3781};
3782static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3783 REGULATOR_SUPPLY("8058_s0", NULL),
3784};
3785static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3786 REGULATOR_SUPPLY("8058_s1", NULL),
3787};
3788static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3789 REGULATOR_SUPPLY("8058_s2", NULL),
3790};
3791static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3792 REGULATOR_SUPPLY("8058_s3", NULL),
3793};
3794static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3795 REGULATOR_SUPPLY("8058_s4", NULL),
3796};
3797static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3798 REGULATOR_SUPPLY("8058_lvs0", NULL),
3799};
3800static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3801 REGULATOR_SUPPLY("8058_lvs1", NULL),
3802};
3803static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3804 REGULATOR_SUPPLY("8058_ncp", NULL),
3805};
3806
3807static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3808 REGULATOR_SUPPLY("8901_l0", NULL),
3809};
3810static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3811 REGULATOR_SUPPLY("8901_l1", NULL),
3812};
3813static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3814 REGULATOR_SUPPLY("8901_l2", NULL),
3815};
3816static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3817 REGULATOR_SUPPLY("8901_l3", NULL),
3818};
3819static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3820 REGULATOR_SUPPLY("8901_l4", NULL),
3821};
3822static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3823 REGULATOR_SUPPLY("8901_l5", NULL),
3824};
3825static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3826 REGULATOR_SUPPLY("8901_l6", NULL),
3827};
3828static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3829 REGULATOR_SUPPLY("8901_s2", NULL),
3830};
3831static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3832 REGULATOR_SUPPLY("8901_s3", NULL),
3833};
3834static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3835 REGULATOR_SUPPLY("8901_s4", NULL),
3836};
3837static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3838 REGULATOR_SUPPLY("8901_lvs0", NULL),
3839};
3840static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3841 REGULATOR_SUPPLY("8901_lvs1", NULL),
3842};
3843static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3844 REGULATOR_SUPPLY("8901_lvs2", NULL),
3845};
3846static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3847 REGULATOR_SUPPLY("8901_lvs3", NULL),
3848};
3849static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3850 REGULATOR_SUPPLY("8901_mvs0", NULL),
3851};
3852
David Collins6f032ba2011-08-31 14:08:15 -07003853/* Pin control regulators */
3854static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
3855 REGULATOR_SUPPLY("8058_l8_pc", NULL),
3856};
3857static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
3858 REGULATOR_SUPPLY("8058_l20_pc", NULL),
3859};
3860static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
3861 REGULATOR_SUPPLY("8058_l21_pc", NULL),
3862};
3863static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
3864 REGULATOR_SUPPLY("8058_s2_pc", NULL),
3865};
3866static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
3867 REGULATOR_SUPPLY("8901_l0_pc", NULL),
3868};
3869static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
3870 REGULATOR_SUPPLY("8901_s4_pc", NULL),
3871};
3872
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003873#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3874 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
David Collins6f032ba2011-08-31 14:08:15 -07003875 _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003876 _always_on) \
David Collins6f032ba2011-08-31 14:08:15 -07003877 { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003878 .init_data = { \
3879 .constraints = { \
David Collins6f032ba2011-08-31 14:08:15 -07003880 .valid_modes_mask = _modes, \
3881 .valid_ops_mask = _ops, \
3882 .min_uV = _min_uV, \
3883 .max_uV = _max_uV, \
3884 .input_uV = _min_uV, \
3885 .apply_uV = _apply_uV, \
3886 .always_on = _always_on, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003887 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003888 .consumer_supplies = vreg_consumers_##_id, \
3889 .num_consumer_supplies = \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003890 ARRAY_SIZE(vreg_consumers_##_id), \
3891 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003892 .id = RPM_VREG_ID_##_id, \
3893 .default_uV = _default_uV, \
3894 .peak_uA = _peak_uA, \
3895 .avg_uA = _avg_uA, \
3896 .pull_down_enable = _pull_down, \
3897 .pin_ctrl = _pin_ctrl, \
3898 .freq = RPM_VREG_FREQ_##_freq, \
3899 .pin_fn = _pin_fn, \
3900 .force_mode = _force_mode, \
3901 .state = _state, \
3902 .sleep_selectable = _sleep_selectable, \
3903 }
3904
3905/* Pin control initialization */
3906#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
3907 { \
3908 .init_data = { \
3909 .constraints = { \
3910 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
3911 .always_on = _always_on, \
3912 }, \
3913 .num_consumer_supplies = \
3914 ARRAY_SIZE(vreg_consumers_##_id##_PC), \
3915 .consumer_supplies = vreg_consumers_##_id##_PC, \
3916 }, \
3917 .id = RPM_VREG_ID_##_id##_PC, \
3918 .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003919 .pin_ctrl = _pin_ctrl, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003920 }
3921
3922/*
3923 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3924 * via the peak_uA value specified in the table below. If the value is less
3925 * than the high power min threshold for the regulator, then the regulator will
3926 * be set to LPM. Otherwise, it will be set to HPM.
3927 *
3928 * This value can be further overridden by specifying an initial mode via
3929 * .init_data.constraints.initial_mode.
3930 */
3931
David Collins6f032ba2011-08-31 14:08:15 -07003932#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3933 _init_peak_uA) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003934 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3935 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3936 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3937 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3938 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003939 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3940 RPM_VREG_PIN_FN_8660_ENABLE, \
3941 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003942 _sleep_selectable, _always_on)
3943
David Collins6f032ba2011-08-31 14:08:15 -07003944#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3945 _init_peak_uA, _freq) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003946 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3947 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3948 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3949 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3950 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003951 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
3952 RPM_VREG_PIN_FN_8660_ENABLE, \
3953 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3954 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003955
David Collins6f032ba2011-08-31 14:08:15 -07003956#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003957 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
3958 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003959 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3960 RPM_VREG_PIN_FN_8660_ENABLE, \
3961 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3962 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003963
David Collins6f032ba2011-08-31 14:08:15 -07003964#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003965 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
3966 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003967 _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3968 RPM_VREG_PIN_FN_8660_ENABLE, \
3969 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3970 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003971
David Collins6f032ba2011-08-31 14:08:15 -07003972#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
3973#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
3974#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
3975#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
3976#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003977
David Collins6f032ba2011-08-31 14:08:15 -07003978/* RPM early regulator constraints */
3979static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
3980 /* ID a_on pd ss min_uV max_uV init_ip freq */
3981 RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
3982 RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003983};
3984
David Collins6f032ba2011-08-31 14:08:15 -07003985/* RPM regulator constraints */
3986static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
3987 /* ID a_on pd ss min_uV max_uV init_ip */
3988 RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
3989 RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
3990 RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
3991 RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
3992 RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
3993 RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3994 RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
3995 RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
3996 RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
3997 RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
3998 RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
3999 RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
4000 RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
4001 RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
4002 RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
4003 RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4004 RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
4005 RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
4006 RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
4007 RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
4008 RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4009 RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
4010 RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
4011 RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4012 RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4013 RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004014
David Collins6f032ba2011-08-31 14:08:15 -07004015 /* ID a_on pd ss min_uV max_uV init_ip freq */
4016 RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
4017 RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
4018 RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
4019
4020 /* ID a_on pd ss */
4021 RPM_VS(PM8058_LVS0, 0, 1, 0),
4022 RPM_VS(PM8058_LVS1, 0, 1, 0),
4023
4024 /* ID a_on pd ss min_uV max_uV */
4025 RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
4026
4027 /* ID a_on pd ss min_uV max_uV init_ip */
4028 RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4029 RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4030 RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
4031 RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4032 RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4033 RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4034 RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
4035
4036 /* ID a_on pd ss min_uV max_uV init_ip freq */
4037 RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
4038 RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
4039 RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
4040
4041 /* ID a_on pd ss */
4042 RPM_VS(PM8901_LVS0, 1, 1, 0),
4043 RPM_VS(PM8901_LVS1, 0, 1, 0),
4044 RPM_VS(PM8901_LVS2, 0, 1, 0),
4045 RPM_VS(PM8901_LVS3, 0, 1, 0),
4046 RPM_VS(PM8901_MVS0, 0, 1, 0),
4047
4048 /* ID a_on pin_func pin_ctrl */
4049 RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4050 RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4051 RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4052 RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
4053 RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4054 RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4055};
4056
4057static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
4058 .init_data = rpm_regulator_early_init_data,
4059 .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
4060 .version = RPM_VREG_VERSION_8660,
4061 .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
4062 .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
4063};
4064
4065static struct rpm_regulator_platform_data rpm_regulator_pdata = {
4066 .init_data = rpm_regulator_init_data,
4067 .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
4068 .version = RPM_VREG_VERSION_8660,
4069};
4070
4071static struct platform_device rpm_regulator_early_device = {
4072 .name = "rpm-regulator",
4073 .id = 0,
4074 .dev = {
4075 .platform_data = &rpm_regulator_early_pdata,
4076 },
4077};
4078
4079static struct platform_device rpm_regulator_device = {
4080 .name = "rpm-regulator",
4081 .id = 1,
4082 .dev = {
4083 .platform_data = &rpm_regulator_pdata,
4084 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004085};
4086
4087static struct platform_device *early_regulators[] __initdata = {
4088 &msm_device_saw_s0,
4089 &msm_device_saw_s1,
David Collins6f032ba2011-08-31 14:08:15 -07004090 &rpm_regulator_early_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004091};
4092
4093static struct platform_device *early_devices[] __initdata = {
4094#ifdef CONFIG_MSM_BUS_SCALING
4095 &msm_bus_apps_fabric,
4096 &msm_bus_sys_fabric,
4097 &msm_bus_mm_fabric,
4098 &msm_bus_sys_fpb,
4099 &msm_bus_cpss_fpb,
4100#endif
4101 &msm_device_dmov_adm0,
4102 &msm_device_dmov_adm1,
4103};
4104
4105#if (defined(CONFIG_MARIMBA_CORE)) && \
4106 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4107
4108static int bluetooth_power(int);
4109static struct platform_device msm_bt_power_device = {
4110 .name = "bt_power",
4111 .id = -1,
4112 .dev = {
4113 .platform_data = &bluetooth_power,
4114 },
4115};
4116#endif
4117
4118static struct platform_device msm_tsens_device = {
4119 .name = "tsens-tm",
4120 .id = -1,
4121};
4122
4123static struct platform_device *rumi_sim_devices[] __initdata = {
4124 &smc91x_device,
4125 &msm_device_uart_dm12,
4126#ifdef CONFIG_I2C_QUP
4127 &msm_gsbi3_qup_i2c_device,
4128 &msm_gsbi4_qup_i2c_device,
4129 &msm_gsbi7_qup_i2c_device,
4130 &msm_gsbi8_qup_i2c_device,
4131 &msm_gsbi9_qup_i2c_device,
4132 &msm_gsbi12_qup_i2c_device,
4133#endif
4134#ifdef CONFIG_I2C_SSBI
4135 &msm_device_ssbi1,
4136 &msm_device_ssbi2,
4137 &msm_device_ssbi3,
4138#endif
4139#ifdef CONFIG_ANDROID_PMEM
4140 &android_pmem_device,
4141 &android_pmem_adsp_device,
4142 &android_pmem_audio_device,
4143 &android_pmem_smipool_device,
4144#endif
4145#ifdef CONFIG_MSM_ROTATOR
4146 &msm_rotator_device,
4147#endif
4148 &msm_fb_device,
4149 &msm_kgsl_3d0,
4150 &msm_kgsl_2d0,
4151 &msm_kgsl_2d1,
4152 &lcdc_samsung_panel_device,
4153#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4154 &hdmi_msm_device,
4155#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4156#ifdef CONFIG_MSM_CAMERA
4157#ifdef CONFIG_MT9E013
4158 &msm_camera_sensor_mt9e013,
4159#endif
4160#ifdef CONFIG_IMX074
4161 &msm_camera_sensor_imx074,
4162#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004163#ifdef CONFIG_VX6953
4164 &msm_camera_sensor_vx6953,
4165#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004166#ifdef CONFIG_WEBCAM_OV7692
4167 &msm_camera_sensor_webcam_ov7692,
4168#endif
4169#ifdef CONFIG_WEBCAM_OV9726
4170 &msm_camera_sensor_webcam_ov9726,
4171#endif
4172#ifdef CONFIG_QS_S5K4E1
4173 &msm_camera_sensor_qs_s5k4e1,
4174#endif
4175#endif
4176#ifdef CONFIG_MSM_GEMINI
4177 &msm_gemini_device,
4178#endif
4179#ifdef CONFIG_MSM_VPE
4180 &msm_vpe_device,
4181#endif
4182 &msm_device_vidc,
4183};
4184
4185#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4186enum {
4187 SX150X_CORE,
4188 SX150X_DOCKING,
4189 SX150X_SURF,
4190 SX150X_LEFT_FHA,
4191 SX150X_RIGHT_FHA,
4192 SX150X_SOUTH,
4193 SX150X_NORTH,
4194 SX150X_CORE_FLUID,
4195};
4196
4197static struct sx150x_platform_data sx150x_data[] __initdata = {
4198 [SX150X_CORE] = {
4199 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4200 .oscio_is_gpo = false,
4201 .io_pullup_ena = 0x0c08,
4202 .io_pulldn_ena = 0x4060,
4203 .io_open_drain_ena = 0x000c,
4204 .io_polarity = 0,
4205 .irq_summary = -1, /* see fixup_i2c_configs() */
4206 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4207 },
4208 [SX150X_DOCKING] = {
4209 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4210 .oscio_is_gpo = false,
4211 .io_pullup_ena = 0x5e06,
4212 .io_pulldn_ena = 0x81b8,
4213 .io_open_drain_ena = 0,
4214 .io_polarity = 0,
4215 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4216 UI_INT2_N),
4217 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4218 GPIO_DOCKING_EXPANDER_BASE -
4219 GPIO_EXPANDER_GPIO_BASE,
4220 },
4221 [SX150X_SURF] = {
4222 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4223 .oscio_is_gpo = false,
4224 .io_pullup_ena = 0,
4225 .io_pulldn_ena = 0,
4226 .io_open_drain_ena = 0,
4227 .io_polarity = 0,
4228 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4229 UI_INT1_N),
4230 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4231 GPIO_SURF_EXPANDER_BASE -
4232 GPIO_EXPANDER_GPIO_BASE,
4233 },
4234 [SX150X_LEFT_FHA] = {
4235 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4236 .oscio_is_gpo = false,
4237 .io_pullup_ena = 0,
4238 .io_pulldn_ena = 0x40,
4239 .io_open_drain_ena = 0,
4240 .io_polarity = 0,
4241 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4242 UI_INT3_N),
4243 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4244 GPIO_LEFT_KB_EXPANDER_BASE -
4245 GPIO_EXPANDER_GPIO_BASE,
4246 },
4247 [SX150X_RIGHT_FHA] = {
4248 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4249 .oscio_is_gpo = true,
4250 .io_pullup_ena = 0,
4251 .io_pulldn_ena = 0,
4252 .io_open_drain_ena = 0,
4253 .io_polarity = 0,
4254 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4255 UI_INT3_N),
4256 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4257 GPIO_RIGHT_KB_EXPANDER_BASE -
4258 GPIO_EXPANDER_GPIO_BASE,
4259 },
4260 [SX150X_SOUTH] = {
4261 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4262 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4263 GPIO_SOUTH_EXPANDER_BASE -
4264 GPIO_EXPANDER_GPIO_BASE,
4265 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4266 },
4267 [SX150X_NORTH] = {
4268 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4269 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4270 GPIO_NORTH_EXPANDER_BASE -
4271 GPIO_EXPANDER_GPIO_BASE,
4272 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4273 .oscio_is_gpo = true,
4274 .io_open_drain_ena = 0x30,
4275 },
4276 [SX150X_CORE_FLUID] = {
4277 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4278 .oscio_is_gpo = false,
4279 .io_pullup_ena = 0x0408,
4280 .io_pulldn_ena = 0x4060,
4281 .io_open_drain_ena = 0x0008,
4282 .io_polarity = 0,
4283 .irq_summary = -1, /* see fixup_i2c_configs() */
4284 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4285 },
4286};
4287
4288#ifdef CONFIG_SENSORS_MSM_ADC
4289/* Configuration of EPM expander is done when client
4290 * request an adc read
4291 */
4292static struct sx150x_platform_data sx150x_epmdata = {
4293 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4294 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4295 GPIO_EPM_EXPANDER_BASE -
4296 GPIO_EXPANDER_GPIO_BASE,
4297 .irq_summary = -1,
4298};
4299#endif
4300
4301/* sx150x_low_power_cfg
4302 *
4303 * This data and init function are used to put unused gpio-expander output
4304 * lines into their low-power states at boot. The init
4305 * function must be deferred until a later init stage because the i2c
4306 * gpio expander drivers do not probe until after they are registered
4307 * (see register_i2c_devices) and the work-queues for those registrations
4308 * are processed. Because these lines are unused, there is no risk of
4309 * competing with a device driver for the gpio.
4310 *
4311 * gpio lines whose low-power states are input are naturally in their low-
4312 * power configurations once probed, see the platform data structures above.
4313 */
4314struct sx150x_low_power_cfg {
4315 unsigned gpio;
4316 unsigned val;
4317};
4318
4319static struct sx150x_low_power_cfg
4320common_sx150x_lp_cfgs[] __initdata = {
4321 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4322 {GPIO_EXT_GPS_LNA_EN, 0},
4323 {GPIO_MSM_WAKES_BT, 0},
4324 {GPIO_USB_UICC_EN, 0},
4325 {GPIO_BATT_GAUGE_EN, 0},
4326};
4327
4328static struct sx150x_low_power_cfg
4329surf_ffa_sx150x_lp_cfgs[] __initdata = {
4330 {GPIO_MIPI_DSI_RST_N, 0},
4331 {GPIO_DONGLE_PWR_EN, 0},
4332 {GPIO_CAP_TS_SLEEP, 1},
4333 {GPIO_WEB_CAMIF_RESET_N, 0},
4334};
4335
4336static void __init
4337cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4338{
4339 unsigned n;
4340 int rc;
4341
4342 for (n = 0; n < nelems; ++n) {
4343 rc = gpio_request(cfgs[n].gpio, NULL);
4344 if (!rc) {
4345 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4346 gpio_free(cfgs[n].gpio);
4347 }
4348
4349 if (rc) {
4350 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4351 __func__, cfgs[n].gpio, rc);
4352 }
Steve Muckle9161d302010-02-11 11:50:40 -08004353 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004354}
4355
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004356static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004357{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004358 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4359 ARRAY_SIZE(common_sx150x_lp_cfgs));
4360 if (!machine_is_msm8x60_fluid())
4361 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4362 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4363 return 0;
4364}
4365module_init(cfg_sx150xs_low_power);
4366
4367#ifdef CONFIG_I2C
4368static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4369 {
4370 I2C_BOARD_INFO("sx1509q", 0x3e),
4371 .platform_data = &sx150x_data[SX150X_CORE]
4372 },
4373};
4374
4375static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4376 {
4377 I2C_BOARD_INFO("sx1509q", 0x3f),
4378 .platform_data = &sx150x_data[SX150X_DOCKING]
4379 },
4380};
4381
4382static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4383 {
4384 I2C_BOARD_INFO("sx1509q", 0x70),
4385 .platform_data = &sx150x_data[SX150X_SURF]
4386 }
4387};
4388
4389static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4390 {
4391 I2C_BOARD_INFO("sx1508q", 0x21),
4392 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4393 },
4394 {
4395 I2C_BOARD_INFO("sx1508q", 0x22),
4396 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4397 }
4398};
4399
4400static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4401 {
4402 I2C_BOARD_INFO("sx1508q", 0x23),
4403 .platform_data = &sx150x_data[SX150X_SOUTH]
4404 },
4405 {
4406 I2C_BOARD_INFO("sx1508q", 0x20),
4407 .platform_data = &sx150x_data[SX150X_NORTH]
4408 }
4409};
4410
4411static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4412 {
4413 I2C_BOARD_INFO("sx1509q", 0x3e),
4414 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4415 },
4416};
4417
4418#ifdef CONFIG_SENSORS_MSM_ADC
4419static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4420 {
4421 I2C_BOARD_INFO("sx1509q", 0x3e),
4422 .platform_data = &sx150x_epmdata
4423 },
4424};
4425#endif
4426#endif
4427#endif
4428
4429#ifdef CONFIG_SENSORS_MSM_ADC
4430static struct resource resources_adc[] = {
4431 {
4432 .start = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4433 .end = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4434 .flags = IORESOURCE_IRQ,
4435 },
4436};
4437
4438static struct adc_access_fn xoadc_fn = {
4439 pm8058_xoadc_select_chan_and_start_conv,
4440 pm8058_xoadc_read_adc_code,
4441 pm8058_xoadc_get_properties,
4442 pm8058_xoadc_slot_request,
4443 pm8058_xoadc_restore_slot,
4444 pm8058_xoadc_calibrate,
4445};
4446
4447#if defined(CONFIG_I2C) && \
4448 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4449static struct regulator *vreg_adc_epm1;
4450
4451static struct i2c_client *epm_expander_i2c_register_board(void)
4452
4453{
4454 struct i2c_adapter *i2c_adap;
4455 struct i2c_client *client = NULL;
4456 i2c_adap = i2c_get_adapter(0x0);
4457
4458 if (i2c_adap == NULL)
4459 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4460
4461 if (i2c_adap != NULL)
4462 client = i2c_new_device(i2c_adap,
4463 &fluid_expanders_i2c_epm_info[0]);
4464 return client;
4465
4466}
4467
4468static unsigned int msm_adc_gpio_configure_expander_enable(void)
4469{
4470 int rc = 0;
4471 static struct i2c_client *epm_i2c_client;
4472
4473 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4474
4475 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4476
4477 if (IS_ERR(vreg_adc_epm1)) {
4478 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4479 return 0;
4480 }
4481
4482 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4483 if (rc)
4484 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4485 "regulator set voltage failed\n");
4486
4487 rc = regulator_enable(vreg_adc_epm1);
4488 if (rc) {
4489 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4490 "Error while enabling regulator for epm s3 %d\n", rc);
4491 return rc;
4492 }
4493
4494 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4495 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4496
4497 msleep(1000);
4498
4499 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4500 if (!rc) {
4501 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4502 "Configure 5v boost\n");
4503 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4504 } else {
4505 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4506 "Error for epm 5v boost en\n");
4507 goto exit_vreg_epm;
4508 }
4509
4510 msleep(500);
4511
4512 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4513 if (!rc) {
4514 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4515 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4516 "Configure epm 3.3v\n");
4517 } else {
4518 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4519 "Error for gpio 3.3ven\n");
4520 goto exit_vreg_epm;
4521 }
4522 msleep(500);
4523
4524 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4525 "Trying to request EPM LVLSFT_EN\n");
4526 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4527 if (!rc) {
4528 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4529 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4530 "Configure the lvlsft\n");
4531 } else {
4532 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4533 "Error for epm lvlsft_en\n");
4534 goto exit_vreg_epm;
4535 }
4536
4537 msleep(500);
4538
4539 if (!epm_i2c_client)
4540 epm_i2c_client = epm_expander_i2c_register_board();
4541
4542 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4543 if (!rc)
4544 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4545 if (rc) {
4546 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4547 ": GPIO PWR MON Enable issue\n");
4548 goto exit_vreg_epm;
4549 }
4550
4551 msleep(1000);
4552
4553 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4554 if (!rc) {
4555 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4556 if (rc) {
4557 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4558 ": ADC1_PWDN error direction out\n");
4559 goto exit_vreg_epm;
4560 }
4561 }
4562
4563 msleep(100);
4564
4565 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4566 if (!rc) {
4567 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4568 if (rc) {
4569 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4570 ": ADC2_PWD error direction out\n");
4571 goto exit_vreg_epm;
4572 }
4573 }
4574
4575 msleep(1000);
4576
4577 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4578 if (!rc) {
4579 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4580 if (rc) {
4581 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4582 "Gpio request problem %d\n", rc);
4583 goto exit_vreg_epm;
4584 }
4585 }
4586
4587 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4588 if (!rc) {
4589 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4590 if (rc) {
4591 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4592 ": EPM_SPI_ADC1_CS_N error\n");
4593 goto exit_vreg_epm;
4594 }
4595 }
4596
4597 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4598 if (!rc) {
4599 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4600 if (rc) {
4601 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4602 ": EPM_SPI_ADC2_Cs_N error\n");
4603 goto exit_vreg_epm;
4604 }
4605 }
4606
4607 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4608 "the power monitor reset for epm\n");
4609
4610 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4611 if (!rc) {
4612 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4613 if (rc) {
4614 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4615 ": Error in the power mon reset\n");
4616 goto exit_vreg_epm;
4617 }
4618 }
4619
4620 msleep(1000);
4621
4622 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4623
4624 msleep(500);
4625
4626 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4627
4628 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4629
4630 return rc;
4631
4632exit_vreg_epm:
4633 regulator_disable(vreg_adc_epm1);
4634
4635 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4636 " rc = %d.\n", rc);
4637 return rc;
4638};
4639
4640static unsigned int msm_adc_gpio_configure_expander_disable(void)
4641{
4642 int rc = 0;
4643
4644 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4645 gpio_free(GPIO_PWR_MON_RESET_N);
4646
4647 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4648 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4649
4650 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4651 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4652
4653 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4654 gpio_free(GPIO_PWR_MON_START);
4655
4656 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4657 gpio_free(GPIO_ADC1_PWDN_N);
4658
4659 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4660 gpio_free(GPIO_ADC2_PWDN_N);
4661
4662 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4663 gpio_free(GPIO_PWR_MON_ENABLE);
4664
4665 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4666 gpio_free(GPIO_EPM_LVLSFT_EN);
4667
4668 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4669 gpio_free(GPIO_EPM_5V_BOOST_EN);
4670
4671 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4672 gpio_free(GPIO_EPM_3_3V_EN);
4673
4674 rc = regulator_disable(vreg_adc_epm1);
4675 if (rc)
4676 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4677 "Error while enabling regulator for epm s3 %d\n", rc);
4678 regulator_put(vreg_adc_epm1);
4679
4680 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4681 return rc;
4682};
4683
4684unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4685{
4686 int rc = 0;
4687
4688 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4689 cs_enable);
4690
4691 if (cs_enable < 16) {
4692 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4693 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4694 } else {
4695 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4696 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4697 }
4698 return rc;
4699};
4700
4701unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4702{
4703 int rc = 0;
4704
4705 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4706
4707 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4708
4709 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4710
4711 return rc;
4712};
4713#endif
4714
4715static struct msm_adc_channels msm_adc_channels_data[] = {
4716 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4717 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4718 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4719 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4720 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4721 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4722 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4723 CHAN_PATH_TYPE4,
4724 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4725 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4726 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4727 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4728 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4729 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4730 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4731 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4732 CHAN_PATH_TYPE12,
4733 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4734 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4735 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4736 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4737 CHAN_PATH_TYPE_NONE,
4738 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4739 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4740 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4741 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4742 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4743 scale_xtern_chgr_cur},
4744 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4745 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4746 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4747 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4748 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4749 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4750 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4751 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4752 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4753 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4754 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4755 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4756};
4757
4758static char *msm_adc_fluid_device_names[] = {
4759 "ADS_ADC1",
4760 "ADS_ADC2",
4761};
4762
4763static struct msm_adc_platform_data msm_adc_pdata = {
4764 .channel = msm_adc_channels_data,
4765 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4766#if defined(CONFIG_I2C) && \
4767 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4768 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4769 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4770 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4771 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4772#endif
4773};
4774
4775static struct platform_device msm_adc_device = {
4776 .name = "msm_adc",
4777 .id = -1,
4778 .dev = {
4779 .platform_data = &msm_adc_pdata,
4780 },
4781};
4782
4783static void pmic8058_xoadc_mpp_config(void)
4784{
4785 int rc;
4786
4787 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4788 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4789 if (rc)
4790 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4791
4792 rc = pm8058_mpp_config_analog_input(XOADC_MPP_3,
4793 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
4794 if (rc)
4795 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
4796
4797 rc = pm8058_mpp_config_analog_input(XOADC_MPP_5,
4798 PM_MPP_AIN_AMUX_CH9, PM_MPP_AOUT_CTL_DISABLE);
4799 if (rc)
4800 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
4801
4802 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
4803 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
4804 if (rc)
4805 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
4806
4807 rc = pm8058_mpp_config_analog_input(XOADC_MPP_8,
4808 PM_MPP_AIN_AMUX_CH8, PM_MPP_AOUT_CTL_DISABLE);
4809 if (rc)
4810 pr_err("%s: Config mpp8 on pmic 8058 failed\n", __func__);
4811
4812 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
4813 PM_MPP_AIN_AMUX_CH7, PM_MPP_AOUT_CTL_DISABLE);
4814 if (rc)
4815 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
4816}
4817
4818static struct regulator *vreg_ldo18_adc;
4819
4820static int pmic8058_xoadc_vreg_config(int on)
4821{
4822 int rc;
4823
4824 if (on) {
4825 rc = regulator_enable(vreg_ldo18_adc);
4826 if (rc)
4827 pr_err("%s: Enable of regulator ldo18_adc "
4828 "failed\n", __func__);
4829 } else {
4830 rc = regulator_disable(vreg_ldo18_adc);
4831 if (rc)
4832 pr_err("%s: Disable of regulator ldo18_adc "
4833 "failed\n", __func__);
4834 }
4835
4836 return rc;
4837}
4838
4839static int pmic8058_xoadc_vreg_setup(void)
4840{
4841 int rc;
4842
4843 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4844 if (IS_ERR(vreg_ldo18_adc)) {
4845 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4846 __func__, PTR_ERR(vreg_ldo18_adc));
4847 rc = PTR_ERR(vreg_ldo18_adc);
4848 goto fail;
4849 }
4850
4851 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4852 if (rc) {
4853 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4854 goto fail;
4855 }
4856
4857 return rc;
4858fail:
4859 regulator_put(vreg_ldo18_adc);
4860 return rc;
4861}
4862
4863static void pmic8058_xoadc_vreg_shutdown(void)
4864{
4865 regulator_put(vreg_ldo18_adc);
4866}
4867
4868/* usec. For this ADC,
4869 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4870 * Each channel has different configuration, thus at the time of starting
4871 * the conversion, xoadc will return actual conversion time
4872 * */
4873static struct adc_properties pm8058_xoadc_data = {
4874 .adc_reference = 2200, /* milli-voltage for this adc */
4875 .bitresolution = 15,
4876 .bipolar = 0,
4877 .conversiontime = 54,
4878};
4879
4880static struct xoadc_platform_data xoadc_pdata = {
4881 .xoadc_prop = &pm8058_xoadc_data,
4882 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4883 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4884 .xoadc_num = XOADC_PMIC_0,
4885 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4886 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4887};
4888#endif
4889
4890#ifdef CONFIG_MSM_SDIO_AL
4891
4892static unsigned mdm2ap_status = 140;
4893
4894static int configure_mdm2ap_status(int on)
4895{
4896 int ret = 0;
4897 if (on)
4898 ret = msm_gpiomux_get(mdm2ap_status);
4899 else
4900 ret = msm_gpiomux_put(mdm2ap_status);
4901
4902 if (ret)
4903 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4904 on);
4905
4906 return ret;
4907}
4908
4909
4910static int get_mdm2ap_status(void)
4911{
4912 return gpio_get_value(mdm2ap_status);
4913}
4914
4915static struct sdio_al_platform_data sdio_al_pdata = {
4916 .config_mdm2ap_status = configure_mdm2ap_status,
4917 .get_mdm2ap_status = get_mdm2ap_status,
4918 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004919 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004920 .peer_sdioc_version_major = 0x0004,
4921 .peer_sdioc_boot_version_minor = 0x0001,
4922 .peer_sdioc_boot_version_major = 0x0003
4923};
4924
4925struct platform_device msm_device_sdio_al = {
4926 .name = "msm_sdio_al",
4927 .id = -1,
4928 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004929 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004930 .platform_data = &sdio_al_pdata,
4931 },
4932};
4933
4934#endif /* CONFIG_MSM_SDIO_AL */
4935
4936static struct platform_device *charm_devices[] __initdata = {
4937 &msm_charm_modem,
4938#ifdef CONFIG_MSM_SDIO_AL
4939 &msm_device_sdio_al,
4940#endif
4941};
4942
Lei Zhou338cab82011-08-19 13:38:17 -04004943#ifdef CONFIG_SND_SOC_MSM8660_APQ
4944static struct platform_device *dragon_alsa_devices[] __initdata = {
4945 &msm_pcm,
4946 &msm_pcm_routing,
4947 &msm_cpudai0,
4948 &msm_cpudai1,
4949 &msm_cpudai_hdmi_rx,
4950 &msm_cpudai_bt_rx,
4951 &msm_cpudai_bt_tx,
4952 &msm_cpudai_fm_rx,
4953 &msm_cpudai_fm_tx,
4954 &msm_cpu_fe,
4955 &msm_stub_codec,
4956 &msm_lpa_pcm,
4957};
4958#endif
4959
4960static struct platform_device *asoc_devices[] __initdata = {
4961 &asoc_msm_pcm,
4962 &asoc_msm_dai0,
4963 &asoc_msm_dai1,
4964};
4965
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004966static struct platform_device *surf_devices[] __initdata = {
4967 &msm_device_smd,
4968 &msm_device_uart_dm12,
4969#ifdef CONFIG_I2C_QUP
4970 &msm_gsbi3_qup_i2c_device,
4971 &msm_gsbi4_qup_i2c_device,
4972 &msm_gsbi7_qup_i2c_device,
4973 &msm_gsbi8_qup_i2c_device,
4974 &msm_gsbi9_qup_i2c_device,
4975 &msm_gsbi12_qup_i2c_device,
4976#endif
4977#ifdef CONFIG_SERIAL_MSM_HS
4978 &msm_device_uart_dm1,
4979#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05304980#ifdef CONFIG_MSM_SSBI
4981 &msm_device_ssbi_pmic1,
4982#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004983#ifdef CONFIG_I2C_SSBI
4984 &msm_device_ssbi1,
4985 &msm_device_ssbi2,
4986 &msm_device_ssbi3,
4987#endif
4988#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
4989 &isp1763_device,
4990#endif
4991
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004992#if defined (CONFIG_MSM_8x60_VOIP)
4993 &asoc_msm_mvs,
4994 &asoc_mvs_dai0,
4995 &asoc_mvs_dai1,
4996#endif
Lei Zhou338cab82011-08-19 13:38:17 -04004997
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004998#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
4999 &msm_device_otg,
5000#endif
5001#ifdef CONFIG_USB_GADGET_MSM_72K
5002 &msm_device_gadget_peripheral,
5003#endif
5004#ifdef CONFIG_USB_G_ANDROID
5005 &android_usb_device,
5006#endif
5007#ifdef CONFIG_BATTERY_MSM
5008 &msm_batt_device,
5009#endif
5010#ifdef CONFIG_ANDROID_PMEM
5011 &android_pmem_device,
5012 &android_pmem_adsp_device,
5013 &android_pmem_audio_device,
5014 &android_pmem_smipool_device,
5015#endif
5016#ifdef CONFIG_MSM_ROTATOR
5017 &msm_rotator_device,
5018#endif
5019 &msm_fb_device,
5020 &msm_kgsl_3d0,
5021 &msm_kgsl_2d0,
5022 &msm_kgsl_2d1,
5023 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005024#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5025 &lcdc_nt35582_panel_device,
5026#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005027#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
5028 &lcdc_samsung_oled_panel_device,
5029#endif
5030#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
5031 &lcdc_auo_wvga_panel_device,
5032#endif
5033#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
5034 &hdmi_msm_device,
5035#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
5036#ifdef CONFIG_FB_MSM_MIPI_DSI
5037 &mipi_dsi_toshiba_panel_device,
5038 &mipi_dsi_novatek_panel_device,
5039#endif
5040#ifdef CONFIG_MSM_CAMERA
5041#ifdef CONFIG_MT9E013
5042 &msm_camera_sensor_mt9e013,
5043#endif
5044#ifdef CONFIG_IMX074
5045 &msm_camera_sensor_imx074,
5046#endif
5047#ifdef CONFIG_WEBCAM_OV7692
5048 &msm_camera_sensor_webcam_ov7692,
5049#endif
5050#ifdef CONFIG_WEBCAM_OV9726
5051 &msm_camera_sensor_webcam_ov9726,
5052#endif
5053#ifdef CONFIG_QS_S5K4E1
5054 &msm_camera_sensor_qs_s5k4e1,
5055#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04005056#ifdef CONFIG_VX6953
5057 &msm_camera_sensor_vx6953,
5058#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005059#endif
5060#ifdef CONFIG_MSM_GEMINI
5061 &msm_gemini_device,
5062#endif
5063#ifdef CONFIG_MSM_VPE
5064 &msm_vpe_device,
5065#endif
5066
5067#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5068 &msm_rpm_log_device,
5069#endif
5070#if defined(CONFIG_MSM_RPM_STATS_LOG)
5071 &msm_rpm_stat_device,
5072#endif
5073 &msm_device_vidc,
5074#if (defined(CONFIG_MARIMBA_CORE)) && \
5075 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5076 &msm_bt_power_device,
5077#endif
5078#ifdef CONFIG_SENSORS_MSM_ADC
5079 &msm_adc_device,
5080#endif
David Collins6f032ba2011-08-31 14:08:15 -07005081 &rpm_regulator_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005082
5083#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5084 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5085 &qcrypto_device,
5086#endif
5087
5088#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5089 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5090 &qcedev_device,
5091#endif
5092
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005093
5094#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5095#ifdef CONFIG_MSM_USE_TSIF1
5096 &msm_device_tsif[1],
5097#else
5098 &msm_device_tsif[0],
5099#endif /* CONFIG_MSM_USE_TSIF1 */
5100#endif /* CONFIG_TSIF */
5101
5102#ifdef CONFIG_HW_RANDOM_MSM
5103 &msm_device_rng,
5104#endif
5105
5106 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005107 &msm_rpm_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005108
5109};
5110
5111static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5112 /* Kernel SMI memory pool for video core, used for firmware */
5113 /* and encoder, decoder scratch buffers */
5114 /* Kernel SMI memory pool should always precede the user space */
5115 /* SMI memory pool, as the video core will use offset address */
5116 /* from the Firmware base */
5117 [MEMTYPE_SMI_KERNEL] = {
5118 .start = KERNEL_SMI_BASE,
5119 .limit = KERNEL_SMI_SIZE,
5120 .size = KERNEL_SMI_SIZE,
5121 .flags = MEMTYPE_FLAGS_FIXED,
5122 },
5123 /* User space SMI memory pool for video core */
5124 /* used for encoder, decoder input & output buffers */
5125 [MEMTYPE_SMI] = {
5126 .start = USER_SMI_BASE,
5127 .limit = USER_SMI_SIZE,
5128 .flags = MEMTYPE_FLAGS_FIXED,
5129 },
5130 [MEMTYPE_EBI0] = {
5131 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5132 },
5133 [MEMTYPE_EBI1] = {
5134 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5135 },
5136};
5137
5138static void __init size_pmem_devices(void)
5139{
5140#ifdef CONFIG_ANDROID_PMEM
5141 android_pmem_adsp_pdata.size = pmem_adsp_size;
5142 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
5143 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5144 android_pmem_pdata.size = pmem_sf_size;
5145#endif
5146}
5147
5148static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5149{
5150 msm8x60_reserve_table[p->memory_type].size += p->size;
5151}
5152
5153static void __init reserve_pmem_memory(void)
5154{
5155#ifdef CONFIG_ANDROID_PMEM
5156 reserve_memory_for(&android_pmem_adsp_pdata);
5157 reserve_memory_for(&android_pmem_smipool_pdata);
5158 reserve_memory_for(&android_pmem_audio_pdata);
5159 reserve_memory_for(&android_pmem_pdata);
5160 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5161#endif
5162}
5163
5164static void __init msm8x60_calculate_reserve_sizes(void)
5165{
5166 size_pmem_devices();
5167 reserve_pmem_memory();
5168}
5169
5170static int msm8x60_paddr_to_memtype(unsigned int paddr)
5171{
5172 if (paddr >= 0x40000000 && paddr < 0x60000000)
5173 return MEMTYPE_EBI1;
5174 if (paddr >= 0x38000000 && paddr < 0x40000000)
5175 return MEMTYPE_SMI;
5176 return MEMTYPE_NONE;
5177}
5178
5179static struct reserve_info msm8x60_reserve_info __initdata = {
5180 .memtype_reserve_table = msm8x60_reserve_table,
5181 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5182 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5183};
5184
5185static void __init msm8x60_reserve(void)
5186{
5187 reserve_info = &msm8x60_reserve_info;
5188 msm_reserve();
5189}
5190
5191#define EXT_CHG_VALID_MPP 10
5192#define EXT_CHG_VALID_MPP_2 11
5193
5194#ifdef CONFIG_ISL9519_CHARGER
5195static int isl_detection_setup(void)
5196{
5197 int ret = 0;
5198
5199 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5200 PM8058_MPP_DIG_LEVEL_S3,
5201 PM_MPP_DIN_TO_INT);
5202 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5203 PM8058_MPP_DIG_LEVEL_S3,
5204 PM_MPP_BI_PULLUP_10KOHM
5205 );
5206 return ret;
5207}
5208
5209static struct isl_platform_data isl_data __initdata = {
5210 .chgcurrent = 700,
5211 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5212 .chg_detection_config = isl_detection_setup,
5213 .max_system_voltage = 4200,
5214 .min_system_voltage = 3200,
5215 .term_current = 120,
5216 .input_current = 2048,
5217};
5218
5219static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5220 {
5221 I2C_BOARD_INFO("isl9519q", 0x9),
5222 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5223 .platform_data = &isl_data,
5224 },
5225};
5226#endif
5227
5228#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5229static int smb137b_detection_setup(void)
5230{
5231 int ret = 0;
5232
5233 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5234 PM8058_MPP_DIG_LEVEL_S3,
5235 PM_MPP_DIN_TO_INT);
5236 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5237 PM8058_MPP_DIG_LEVEL_S3,
5238 PM_MPP_BI_PULLUP_10KOHM);
5239 return ret;
5240}
5241
5242static struct smb137b_platform_data smb137b_data __initdata = {
5243 .chg_detection_config = smb137b_detection_setup,
5244 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5245 .batt_mah_rating = 950,
5246};
5247
5248static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5249 {
5250 I2C_BOARD_INFO("smb137b", 0x08),
5251 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5252 .platform_data = &smb137b_data,
5253 },
5254};
5255#endif
5256
5257#ifdef CONFIG_PMIC8058
5258#define PMIC_GPIO_SDC3_DET 22
5259
5260static int pm8058_gpios_init(void)
5261{
5262 int i;
5263 int rc;
5264 struct pm8058_gpio_cfg {
5265 int gpio;
5266 struct pm8058_gpio cfg;
5267 };
5268
5269 struct pm8058_gpio_cfg gpio_cfgs[] = {
5270 { /* FFA ethernet */
5271 6,
5272 {
5273 .direction = PM_GPIO_DIR_IN,
5274 .pull = PM_GPIO_PULL_DN,
5275 .vin_sel = 2,
5276 .function = PM_GPIO_FUNC_NORMAL,
5277 .inv_int_pol = 0,
5278 },
5279 },
5280#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5281 {
5282 PMIC_GPIO_SDC3_DET - 1,
5283 {
5284 .direction = PM_GPIO_DIR_IN,
5285 .pull = PM_GPIO_PULL_UP_30,
5286 .vin_sel = 2,
5287 .function = PM_GPIO_FUNC_NORMAL,
5288 .inv_int_pol = 0,
5289 },
5290 },
5291#endif
5292 { /* core&surf gpio expander */
5293 UI_INT1_N,
5294 {
5295 .direction = PM_GPIO_DIR_IN,
5296 .pull = PM_GPIO_PULL_NO,
5297 .vin_sel = PM_GPIO_VIN_S3,
5298 .function = PM_GPIO_FUNC_NORMAL,
5299 .inv_int_pol = 0,
5300 },
5301 },
5302 { /* docking gpio expander */
5303 UI_INT2_N,
5304 {
5305 .direction = PM_GPIO_DIR_IN,
5306 .pull = PM_GPIO_PULL_NO,
5307 .vin_sel = PM_GPIO_VIN_S3,
5308 .function = PM_GPIO_FUNC_NORMAL,
5309 .inv_int_pol = 0,
5310 },
5311 },
5312 { /* FHA/keypad gpio expanders */
5313 UI_INT3_N,
5314 {
5315 .direction = PM_GPIO_DIR_IN,
5316 .pull = PM_GPIO_PULL_NO,
5317 .vin_sel = PM_GPIO_VIN_S3,
5318 .function = PM_GPIO_FUNC_NORMAL,
5319 .inv_int_pol = 0,
5320 },
5321 },
5322 { /* TouchDisc Interrupt */
5323 5,
5324 {
5325 .direction = PM_GPIO_DIR_IN,
5326 .pull = PM_GPIO_PULL_UP_1P5,
5327 .vin_sel = 2,
5328 .function = PM_GPIO_FUNC_NORMAL,
5329 .inv_int_pol = 0,
5330 }
5331 },
5332 { /* Timpani Reset */
5333 20,
5334 {
5335 .direction = PM_GPIO_DIR_OUT,
5336 .output_value = 1,
5337 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5338 .pull = PM_GPIO_PULL_DN,
5339 .out_strength = PM_GPIO_STRENGTH_HIGH,
5340 .function = PM_GPIO_FUNC_NORMAL,
5341 .vin_sel = 2,
5342 .inv_int_pol = 0,
5343 }
5344 },
5345 { /* PMIC ID interrupt */
5346 36,
5347 {
5348 .direction = PM_GPIO_DIR_IN,
5349 .pull = PM_GPIO_PULL_UP_1P5,
5350 .function = PM_GPIO_FUNC_NORMAL,
5351 .vin_sel = 2,
5352 .inv_int_pol = 0,
5353 }
5354 },
5355 };
5356
5357#if defined(CONFIG_HAPTIC_ISA1200) || \
5358 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5359
5360 struct pm8058_gpio_cfg en_hap_gpio_cfg = {
5361 PMIC_GPIO_HAP_ENABLE,
5362 {
5363 .direction = PM_GPIO_DIR_OUT,
5364 .pull = PM_GPIO_PULL_NO,
5365 .out_strength = PM_GPIO_STRENGTH_HIGH,
5366 .function = PM_GPIO_FUNC_NORMAL,
5367 .inv_int_pol = 0,
5368 .vin_sel = 2,
5369 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5370 .output_value = 0,
5371 }
5372
5373 };
5374#endif
5375
5376#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5377 struct pm8058_gpio_cfg line_in_gpio_cfg = {
5378 18,
5379 {
5380 .direction = PM_GPIO_DIR_IN,
5381 .pull = PM_GPIO_PULL_UP_1P5,
5382 .vin_sel = 2,
5383 .function = PM_GPIO_FUNC_NORMAL,
5384 .inv_int_pol = 0,
5385 }
5386 };
5387#endif
5388
5389#if defined(CONFIG_QS_S5K4E1)
5390 {
5391 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
5392 26,
5393 {
5394 .direction = PM_GPIO_DIR_OUT,
5395 .output_value = 0,
5396 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5397 .pull = PM_GPIO_PULL_DN,
5398 .out_strength = PM_GPIO_STRENGTH_HIGH,
5399 .function = PM_GPIO_FUNC_NORMAL,
5400 .vin_sel = 2,
5401 .inv_int_pol = 0,
5402 }
5403 };
5404#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005405#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5406 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
5407 GPIO_NT35582_BL_EN_HW_PIN - 1,
5408 {
5409 .direction = PM_GPIO_DIR_OUT,
5410 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5411 .output_value = 1,
5412 .pull = PM_GPIO_PULL_UP_30,
5413 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
5414 .vin_sel = PM_GPIO_VIN_L5,
5415 .out_strength = PM_GPIO_STRENGTH_HIGH,
5416 .function = PM_GPIO_FUNC_NORMAL,
5417 .inv_int_pol = 0,
5418 }
5419 };
5420#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005421#if defined(CONFIG_HAPTIC_ISA1200) || \
5422 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5423 if (machine_is_msm8x60_fluid()) {
5424 rc = pm8058_gpio_config(en_hap_gpio_cfg.gpio,
5425 &en_hap_gpio_cfg.cfg);
5426 if (rc < 0) {
5427 pr_err("%s pmic haptics gpio config failed\n",
5428 __func__);
5429 return rc;
5430 }
5431 }
5432#endif
5433
5434#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5435 /* Line_in only for 8660 ffa & surf */
5436 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005437 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005438 machine_is_msm8x60_fusn_ffa()) {
5439 rc = pm8058_gpio_config(line_in_gpio_cfg.gpio,
5440 &line_in_gpio_cfg.cfg);
5441 if (rc < 0) {
5442 pr_err("%s pmic line_in gpio config failed\n",
5443 __func__);
5444 return rc;
5445 }
5446 }
5447#endif
5448
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005449#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5450 if (machine_is_msm8x60_dragon()) {
5451 rc = pm8058_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
5452 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5453 if (rc < 0) {
5454 pr_err("%s pmic gpio config failed\n", __func__);
5455 return rc;
5456 }
5457 }
5458#endif
5459
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005460#if defined(CONFIG_QS_S5K4E1)
5461 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5462 if (machine_is_msm8x60_fluid()) {
5463 rc = pm8058_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
5464 &qs_hc37_cam_pd_gpio_cfg.cfg);
5465 if (rc < 0) {
5466 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5467 __func__);
5468 return rc;
5469 }
5470 }
5471 }
5472#endif
5473
5474 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
5475 rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
5476 &gpio_cfgs[i].cfg);
5477 if (rc < 0) {
5478 pr_err("%s pmic gpio config failed\n",
5479 __func__);
5480 return rc;
5481 }
5482 }
5483
5484 return 0;
5485}
5486
5487static const unsigned int ffa_keymap[] = {
5488 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5489 KEY(0, 1, KEY_UP), /* NAV - UP */
5490 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5491 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5492
5493 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5494 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5495 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5496 KEY(1, 3, KEY_VOLUMEDOWN),
5497
5498 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5499
5500 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5501 KEY(4, 1, KEY_UP), /* USER_UP */
5502 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5503 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5504 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5505
5506 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5507 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5508 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5509 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5510 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5511};
5512
Zhang Chang Ken683be172011-08-10 17:45:34 -04005513static const unsigned int dragon_keymap[] = {
5514 KEY(0, 0, KEY_MENU),
5515 KEY(0, 2, KEY_1),
5516 KEY(0, 3, KEY_4),
5517 KEY(0, 4, KEY_7),
5518
5519 KEY(1, 0, KEY_UP),
5520 KEY(1, 1, KEY_LEFT),
5521 KEY(1, 2, KEY_DOWN),
5522 KEY(1, 3, KEY_5),
5523 KEY(1, 4, KEY_8),
5524
5525 KEY(2, 0, KEY_HOME),
5526 KEY(2, 1, KEY_REPLY),
5527 KEY(2, 2, KEY_2),
5528 KEY(2, 3, KEY_6),
5529 KEY(2, 4, KEY_0),
5530
5531 KEY(3, 0, KEY_VOLUMEUP),
5532 KEY(3, 1, KEY_RIGHT),
5533 KEY(3, 2, KEY_3),
5534 KEY(3, 3, KEY_9),
5535 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5536
5537 KEY(4, 0, KEY_VOLUMEDOWN),
5538 KEY(4, 1, KEY_BACK),
5539 KEY(4, 2, KEY_CAMERA),
5540 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5541};
5542
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005543static struct resource resources_keypad[] = {
5544 {
5545 .start = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5546 .end = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5547 .flags = IORESOURCE_IRQ,
5548 },
5549 {
5550 .start = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5551 .end = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5552 .flags = IORESOURCE_IRQ,
5553 },
5554};
5555
5556static struct matrix_keymap_data ffa_keymap_data = {
5557 .keymap_size = ARRAY_SIZE(ffa_keymap),
5558 .keymap = ffa_keymap,
5559};
5560
5561static struct pmic8058_keypad_data ffa_keypad_data = {
5562 .input_name = "ffa-keypad",
5563 .input_phys_device = "ffa-keypad/input0",
5564 .num_rows = 6,
5565 .num_cols = 5,
5566 .rows_gpio_start = 8,
5567 .cols_gpio_start = 0,
5568 .debounce_ms = {8, 10},
5569 .scan_delay_ms = 32,
5570 .row_hold_ns = 91500,
5571 .wakeup = 1,
5572 .keymap_data = &ffa_keymap_data,
5573};
5574
Zhang Chang Ken683be172011-08-10 17:45:34 -04005575static struct matrix_keymap_data dragon_keymap_data = {
5576 .keymap_size = ARRAY_SIZE(dragon_keymap),
5577 .keymap = dragon_keymap,
5578};
5579
5580static struct pmic8058_keypad_data dragon_keypad_data = {
5581 .input_name = "dragon-keypad",
5582 .input_phys_device = "dragon-keypad/input0",
5583 .num_rows = 6,
5584 .num_cols = 5,
5585 .rows_gpio_start = 8,
5586 .cols_gpio_start = 0,
5587 .debounce_ms = {8, 10},
5588 .scan_delay_ms = 32,
5589 .row_hold_ns = 91500,
5590 .wakeup = 1,
5591 .keymap_data = &dragon_keymap_data,
5592};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005593static const unsigned int fluid_keymap[] = {
5594 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5595 KEY(0, 1, KEY_UP), /* NAV - UP */
5596 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5597 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5598
5599 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5600 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5601 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5602 KEY(1, 3, KEY_VOLUMEUP),
5603
5604 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5605
5606 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5607 KEY(4, 1, KEY_UP), /* USER_UP */
5608 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5609 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5610 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5611
Jilai Wang9a895102011-07-12 14:00:35 -04005612 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005613 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5614 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5615 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5616 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5617};
5618
5619static struct matrix_keymap_data fluid_keymap_data = {
5620 .keymap_size = ARRAY_SIZE(fluid_keymap),
5621 .keymap = fluid_keymap,
5622};
5623
5624static struct pmic8058_keypad_data fluid_keypad_data = {
5625 .input_name = "fluid-keypad",
5626 .input_phys_device = "fluid-keypad/input0",
5627 .num_rows = 6,
5628 .num_cols = 5,
5629 .rows_gpio_start = 8,
5630 .cols_gpio_start = 0,
5631 .debounce_ms = {8, 10},
5632 .scan_delay_ms = 32,
5633 .row_hold_ns = 91500,
5634 .wakeup = 1,
5635 .keymap_data = &fluid_keymap_data,
5636};
5637
5638static struct resource resources_pwrkey[] = {
5639 {
5640 .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5641 .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5642 .flags = IORESOURCE_IRQ,
5643 },
5644 {
5645 .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5646 .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5647 .flags = IORESOURCE_IRQ,
5648 },
5649};
5650
5651static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
5652 .pull_up = 1,
5653 .kpd_trigger_delay_us = 970,
5654 .wakeup = 1,
5655 .pwrkey_time_ms = 500,
5656};
5657
5658static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
5659 .initial_vibrate_ms = 500,
5660 .level_mV = 3000,
5661 .max_timeout_ms = 15000,
5662};
5663
5664#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5665#define PM8058_OTHC_CNTR_BASE0 0xA0
5666#define PM8058_OTHC_CNTR_BASE1 0x134
5667#define PM8058_OTHC_CNTR_BASE2 0x137
5668#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5669
5670static struct othc_accessory_info othc_accessories[] = {
5671 {
5672 .accessory = OTHC_SVIDEO_OUT,
5673 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5674 | OTHC_ADC_DETECT,
5675 .key_code = SW_VIDEOOUT_INSERT,
5676 .enabled = false,
5677 .adc_thres = {
5678 .min_threshold = 20,
5679 .max_threshold = 40,
5680 },
5681 },
5682 {
5683 .accessory = OTHC_ANC_HEADPHONE,
5684 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5685 OTHC_SWITCH_DETECT,
5686 .gpio = PM8058_LINE_IN_DET_GPIO,
5687 .active_low = 1,
5688 .key_code = SW_HEADPHONE_INSERT,
5689 .enabled = true,
5690 },
5691 {
5692 .accessory = OTHC_ANC_HEADSET,
5693 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5694 .gpio = PM8058_LINE_IN_DET_GPIO,
5695 .active_low = 1,
5696 .key_code = SW_HEADPHONE_INSERT,
5697 .enabled = true,
5698 },
5699 {
5700 .accessory = OTHC_HEADPHONE,
5701 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5702 .key_code = SW_HEADPHONE_INSERT,
5703 .enabled = true,
5704 },
5705 {
5706 .accessory = OTHC_MICROPHONE,
5707 .detect_flags = OTHC_GPIO_DETECT,
5708 .gpio = PM8058_LINE_IN_DET_GPIO,
5709 .active_low = 1,
5710 .key_code = SW_MICROPHONE_INSERT,
5711 .enabled = true,
5712 },
5713 {
5714 .accessory = OTHC_HEADSET,
5715 .detect_flags = OTHC_MICBIAS_DETECT,
5716 .key_code = SW_HEADPHONE_INSERT,
5717 .enabled = true,
5718 },
5719};
5720
5721static struct othc_switch_info switch_info[] = {
5722 {
5723 .min_adc_threshold = 0,
5724 .max_adc_threshold = 100,
5725 .key_code = KEY_PLAYPAUSE,
5726 },
5727 {
5728 .min_adc_threshold = 100,
5729 .max_adc_threshold = 200,
5730 .key_code = KEY_REWIND,
5731 },
5732 {
5733 .min_adc_threshold = 200,
5734 .max_adc_threshold = 500,
5735 .key_code = KEY_FASTFORWARD,
5736 },
5737};
5738
5739static struct othc_n_switch_config switch_config = {
5740 .voltage_settling_time_ms = 0,
5741 .num_adc_samples = 3,
5742 .adc_channel = CHANNEL_ADC_HDSET,
5743 .switch_info = switch_info,
5744 .num_keys = ARRAY_SIZE(switch_info),
5745 .default_sw_en = true,
5746 .default_sw_idx = 0,
5747};
5748
5749static struct hsed_bias_config hsed_bias_config = {
5750 /* HSED mic bias config info */
5751 .othc_headset = OTHC_HEADSET_NO,
5752 .othc_lowcurr_thresh_uA = 100,
5753 .othc_highcurr_thresh_uA = 600,
5754 .othc_hyst_prediv_us = 7800,
5755 .othc_period_clkdiv_us = 62500,
5756 .othc_hyst_clk_us = 121000,
5757 .othc_period_clk_us = 312500,
5758 .othc_wakeup = 1,
5759};
5760
5761static struct othc_hsed_config hsed_config_1 = {
5762 .hsed_bias_config = &hsed_bias_config,
5763 /*
5764 * The detection delay and switch reporting delay are
5765 * required to encounter a hardware bug (spurious switch
5766 * interrupts on slow insertion/removal of the headset).
5767 * This will introduce a delay in reporting the accessory
5768 * insertion and removal to the userspace.
5769 */
5770 .detection_delay_ms = 1500,
5771 /* Switch info */
5772 .switch_debounce_ms = 1500,
5773 .othc_support_n_switch = false,
5774 .switch_config = &switch_config,
5775 .ir_gpio = -1,
5776 /* Accessory info */
5777 .accessories_support = true,
5778 .accessories = othc_accessories,
5779 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5780};
5781
5782static struct othc_regulator_config othc_reg = {
5783 .regulator = "8058_l5",
5784 .max_uV = 2850000,
5785 .min_uV = 2850000,
5786};
5787
5788/* MIC_BIAS0 is configured as normal MIC BIAS */
5789static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5790 .micbias_select = OTHC_MICBIAS_0,
5791 .micbias_capability = OTHC_MICBIAS,
5792 .micbias_enable = OTHC_SIGNAL_OFF,
5793 .micbias_regulator = &othc_reg,
5794};
5795
5796/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5797static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5798 .micbias_select = OTHC_MICBIAS_1,
5799 .micbias_capability = OTHC_MICBIAS_HSED,
5800 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5801 .micbias_regulator = &othc_reg,
5802 .hsed_config = &hsed_config_1,
5803 .hsed_name = "8660_handset",
5804};
5805
5806/* MIC_BIAS2 is configured as normal MIC BIAS */
5807static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5808 .micbias_select = OTHC_MICBIAS_2,
5809 .micbias_capability = OTHC_MICBIAS,
5810 .micbias_enable = OTHC_SIGNAL_OFF,
5811 .micbias_regulator = &othc_reg,
5812};
5813
5814static struct resource resources_othc_0[] = {
5815 {
5816 .name = "othc_base",
5817 .start = PM8058_OTHC_CNTR_BASE0,
5818 .end = PM8058_OTHC_CNTR_BASE0,
5819 .flags = IORESOURCE_IO,
5820 },
5821};
5822
5823static struct resource resources_othc_1[] = {
5824 {
5825 .start = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5826 .end = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5827 .flags = IORESOURCE_IRQ,
5828 },
5829 {
5830 .start = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5831 .end = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5832 .flags = IORESOURCE_IRQ,
5833 },
5834 {
5835 .name = "othc_base",
5836 .start = PM8058_OTHC_CNTR_BASE1,
5837 .end = PM8058_OTHC_CNTR_BASE1,
5838 .flags = IORESOURCE_IO,
5839 },
5840};
5841
5842static struct resource resources_othc_2[] = {
5843 {
5844 .name = "othc_base",
5845 .start = PM8058_OTHC_CNTR_BASE2,
5846 .end = PM8058_OTHC_CNTR_BASE2,
5847 .flags = IORESOURCE_IO,
5848 },
5849};
5850
5851static void __init msm8x60_init_pm8058_othc(void)
5852{
5853 int i;
5854
5855 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5856 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5857 machine_is_msm8x60_fusn_ffa()) {
5858 /* 3-switch headset supported only by V2 FFA and FLUID */
5859 hsed_config_1.accessories_adc_support = true,
5860 /* ADC based accessory detection works only on V2 and FLUID */
5861 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5862 hsed_config_1.othc_support_n_switch = true;
5863 }
5864
5865 /* IR GPIO is absent on FLUID */
5866 if (machine_is_msm8x60_fluid())
5867 hsed_config_1.ir_gpio = -1;
5868
5869 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5870 if (machine_is_msm8x60_fluid()) {
5871 switch (othc_accessories[i].accessory) {
5872 case OTHC_ANC_HEADPHONE:
5873 case OTHC_ANC_HEADSET:
5874 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5875 break;
5876 case OTHC_MICROPHONE:
5877 othc_accessories[i].enabled = false;
5878 break;
5879 case OTHC_SVIDEO_OUT:
5880 othc_accessories[i].enabled = true;
5881 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5882 break;
5883 }
5884 }
5885 }
5886}
5887#endif
5888
5889static struct resource resources_pm8058_charger[] = {
5890 { .name = "CHGVAL",
5891 .start = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5892 .end = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5893 .flags = IORESOURCE_IRQ,
5894 },
5895 { .name = "CHGINVAL",
5896 .start = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5897 .end = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5898 .flags = IORESOURCE_IRQ,
5899 },
5900 {
5901 .name = "CHGILIM",
5902 .start = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5903 .end = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5904 .flags = IORESOURCE_IRQ,
5905 },
5906 {
5907 .name = "VCP",
5908 .start = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5909 .end = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5910 .flags = IORESOURCE_IRQ,
5911 },
5912 {
5913 .name = "ATC_DONE",
5914 .start = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5915 .end = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5916 .flags = IORESOURCE_IRQ,
5917 },
5918 {
5919 .name = "ATCFAIL",
5920 .start = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5921 .end = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5922 .flags = IORESOURCE_IRQ,
5923 },
5924 {
5925 .name = "AUTO_CHGDONE",
5926 .start = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5927 .end = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5928 .flags = IORESOURCE_IRQ,
5929 },
5930 {
5931 .name = "AUTO_CHGFAIL",
5932 .start = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5933 .end = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5934 .flags = IORESOURCE_IRQ,
5935 },
5936 {
5937 .name = "CHGSTATE",
5938 .start = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5939 .end = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5940 .flags = IORESOURCE_IRQ,
5941 },
5942 {
5943 .name = "FASTCHG",
5944 .start = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5945 .end = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5946 .flags = IORESOURCE_IRQ,
5947 },
5948 {
5949 .name = "CHG_END",
5950 .start = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5951 .end = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5952 .flags = IORESOURCE_IRQ,
5953 },
5954 {
5955 .name = "BATTTEMP",
5956 .start = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5957 .end = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5958 .flags = IORESOURCE_IRQ,
5959 },
5960 {
5961 .name = "CHGHOT",
5962 .start = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5963 .end = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5964 .flags = IORESOURCE_IRQ,
5965 },
5966 {
5967 .name = "CHGTLIMIT",
5968 .start = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5969 .end = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5970 .flags = IORESOURCE_IRQ,
5971 },
5972 {
5973 .name = "CHG_GONE",
5974 .start = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5975 .end = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5976 .flags = IORESOURCE_IRQ,
5977 },
5978 {
5979 .name = "VCPMAJOR",
5980 .start = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5981 .end = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5982 .flags = IORESOURCE_IRQ,
5983 },
5984 {
5985 .name = "VBATDET",
5986 .start = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5987 .end = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5988 .flags = IORESOURCE_IRQ,
5989 },
5990 {
5991 .name = "BATFET",
5992 .start = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5993 .end = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5994 .flags = IORESOURCE_IRQ,
5995 },
5996 {
5997 .name = "BATT_REPLACE",
5998 .start = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5999 .end = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
6000 .flags = IORESOURCE_IRQ,
6001 },
6002 {
6003 .name = "BATTCONNECT",
6004 .start = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
6005 .end = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
6006 .flags = IORESOURCE_IRQ,
6007 },
6008 {
6009 .name = "VBATDET_LOW",
6010 .start = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6011 .end = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6012 .flags = IORESOURCE_IRQ,
6013 },
6014};
6015
6016static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
6017{
6018 struct pm8058_gpio pwm_gpio_config = {
6019 .direction = PM_GPIO_DIR_OUT,
6020 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
6021 .output_value = 0,
6022 .pull = PM_GPIO_PULL_NO,
6023 .vin_sel = PM_GPIO_VIN_VPH,
6024 .out_strength = PM_GPIO_STRENGTH_HIGH,
6025 .function = PM_GPIO_FUNC_2,
6026 };
6027
6028 int rc = -EINVAL;
6029 int id, mode, max_mA;
6030
6031 id = mode = max_mA = 0;
6032 switch (ch) {
6033 case 0:
6034 case 1:
6035 case 2:
6036 if (on) {
6037 id = 24 + ch;
6038 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
6039 if (rc)
6040 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
6041 __func__, id, rc);
6042 }
6043 break;
6044
6045 case 6:
6046 id = PM_PWM_LED_FLASH;
6047 mode = PM_PWM_CONF_PWM1;
6048 max_mA = 300;
6049 break;
6050
6051 case 7:
6052 id = PM_PWM_LED_FLASH1;
6053 mode = PM_PWM_CONF_PWM1;
6054 max_mA = 300;
6055 break;
6056
6057 default:
6058 break;
6059 }
6060
6061 if (ch >= 6 && ch <= 7) {
6062 if (!on) {
6063 mode = PM_PWM_CONF_NONE;
6064 max_mA = 0;
6065 }
6066 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6067 if (rc)
6068 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6069 __func__, ch, rc);
6070 }
6071 return rc;
6072
6073}
6074
6075static struct pm8058_pwm_pdata pm8058_pwm_data = {
6076 .config = pm8058_pwm_config,
6077};
6078
6079#define PM8058_GPIO_INT 88
6080
6081static struct pm8058_gpio_platform_data pm8058_gpio_data = {
6082 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6083 .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
6084 .init = pm8058_gpios_init,
6085};
6086
6087static struct pm8058_gpio_platform_data pm8058_mpp_data = {
6088 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
6089 .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
6090};
6091
6092static struct resource resources_rtc[] = {
6093 {
6094 .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6095 .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6096 .flags = IORESOURCE_IRQ,
6097 },
6098 {
6099 .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6100 .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6101 .flags = IORESOURCE_IRQ,
6102 },
6103};
6104
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306105static struct pm8058_rtc_platform_data pm8058_rtc_pdata = {
6106 .rtc_alarm_powerup = false,
6107};
6108
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006109static struct pmic8058_led pmic8058_flash_leds[] = {
6110 [0] = {
6111 .name = "camera:flash0",
6112 .max_brightness = 15,
6113 .id = PMIC8058_ID_FLASH_LED_0,
6114 },
6115 [1] = {
6116 .name = "camera:flash1",
6117 .max_brightness = 15,
6118 .id = PMIC8058_ID_FLASH_LED_1,
6119 },
6120};
6121
6122static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6123 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6124 .leds = pmic8058_flash_leds,
6125};
6126
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006127static struct pmic8058_led pmic8058_dragon_leds[] = {
6128 [0] = {
6129 /* RED */
6130 .name = "led_drv0",
6131 .max_brightness = 15,
6132 .id = PMIC8058_ID_LED_0,
6133 },/* 300 mA flash led0 drv sink */
6134 [1] = {
6135 /* Yellow */
6136 .name = "led_drv1",
6137 .max_brightness = 15,
6138 .id = PMIC8058_ID_LED_1,
6139 },/* 300 mA flash led0 drv sink */
6140 [2] = {
6141 /* Green */
6142 .name = "led_drv2",
6143 .max_brightness = 15,
6144 .id = PMIC8058_ID_LED_2,
6145 },/* 300 mA flash led0 drv sink */
6146 [3] = {
6147 .name = "led_psensor",
6148 .max_brightness = 15,
6149 .id = PMIC8058_ID_LED_KB_LIGHT,
6150 },/* 300 mA flash led0 drv sink */
6151};
6152
6153static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6154 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6155 .leds = pmic8058_dragon_leds,
6156};
6157
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006158static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6159 [0] = {
6160 .name = "led:drv0",
6161 .max_brightness = 15,
6162 .id = PMIC8058_ID_FLASH_LED_0,
6163 },/* 300 mA flash led0 drv sink */
6164 [1] = {
6165 .name = "led:drv1",
6166 .max_brightness = 15,
6167 .id = PMIC8058_ID_FLASH_LED_1,
6168 },/* 300 mA flash led1 sink */
6169 [2] = {
6170 .name = "led:drv2",
6171 .max_brightness = 20,
6172 .id = PMIC8058_ID_LED_0,
6173 },/* 40 mA led0 sink */
6174 [3] = {
6175 .name = "keypad:drv",
6176 .max_brightness = 15,
6177 .id = PMIC8058_ID_LED_KB_LIGHT,
6178 },/* 300 mA keypad drv sink */
6179};
6180
6181static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6182 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6183 .leds = pmic8058_fluid_flash_leds,
6184};
6185
6186static struct resource resources_temp_alarm[] = {
6187 {
6188 .start = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6189 .end = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6190 .flags = IORESOURCE_IRQ,
6191 },
6192};
6193
6194static struct resource resources_pm8058_misc[] = {
6195 {
6196 .start = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6197 .end = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6198 .flags = IORESOURCE_IRQ,
6199 },
6200};
6201
6202static struct resource resources_pm8058_batt_alarm[] = {
6203 {
6204 .start = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6205 .end = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6206 .flags = IORESOURCE_IRQ,
6207 },
6208};
6209
6210#define PM8058_SUBDEV_KPD 0
6211#define PM8058_SUBDEV_LED 1
6212#define PM8058_SUBDEV_VIB 2
6213
6214static struct mfd_cell pm8058_subdevs[] = {
6215 {
6216 .name = "pm8058-keypad",
6217 .id = -1,
6218 .num_resources = ARRAY_SIZE(resources_keypad),
6219 .resources = resources_keypad,
6220 },
6221 { .name = "pm8058-led",
6222 .id = -1,
6223 },
6224 {
6225 .name = "pm8058-vib",
6226 .id = -1,
6227 },
6228 { .name = "pm8058-gpio",
6229 .id = -1,
6230 .platform_data = &pm8058_gpio_data,
6231 .pdata_size = sizeof(pm8058_gpio_data),
6232 },
6233 { .name = "pm8058-mpp",
6234 .id = -1,
6235 .platform_data = &pm8058_mpp_data,
6236 .pdata_size = sizeof(pm8058_mpp_data),
6237 },
6238 { .name = "pm8058-pwrkey",
6239 .id = -1,
6240 .resources = resources_pwrkey,
6241 .num_resources = ARRAY_SIZE(resources_pwrkey),
6242 .platform_data = &pwrkey_pdata,
6243 .pdata_size = sizeof(pwrkey_pdata),
6244 },
6245 {
6246 .name = "pm8058-pwm",
6247 .id = -1,
6248 .platform_data = &pm8058_pwm_data,
6249 .pdata_size = sizeof(pm8058_pwm_data),
6250 },
6251#ifdef CONFIG_SENSORS_MSM_ADC
6252 {
6253 .name = "pm8058-xoadc",
6254 .id = -1,
6255 .num_resources = ARRAY_SIZE(resources_adc),
6256 .resources = resources_adc,
6257 .platform_data = &xoadc_pdata,
6258 .pdata_size = sizeof(xoadc_pdata),
6259 },
6260#endif
6261#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
6262 {
6263 .name = "pm8058-othc",
6264 .id = 0,
6265 .platform_data = &othc_config_pdata_0,
6266 .pdata_size = sizeof(othc_config_pdata_0),
6267 .num_resources = ARRAY_SIZE(resources_othc_0),
6268 .resources = resources_othc_0,
6269 },
6270 {
6271 /* OTHC1 module has headset/switch dection */
6272 .name = "pm8058-othc",
6273 .id = 1,
6274 .num_resources = ARRAY_SIZE(resources_othc_1),
6275 .resources = resources_othc_1,
6276 .platform_data = &othc_config_pdata_1,
6277 .pdata_size = sizeof(othc_config_pdata_1),
6278 },
6279 {
6280 .name = "pm8058-othc",
6281 .id = 2,
6282 .platform_data = &othc_config_pdata_2,
6283 .pdata_size = sizeof(othc_config_pdata_2),
6284 .num_resources = ARRAY_SIZE(resources_othc_2),
6285 .resources = resources_othc_2,
6286 },
6287#endif
6288 {
6289 .name = "pm8058-rtc",
6290 .id = -1,
6291 .num_resources = ARRAY_SIZE(resources_rtc),
6292 .resources = resources_rtc,
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306293 .platform_data = &pm8058_rtc_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006294 },
6295 {
6296 .name = "pm8058-tm",
6297 .id = -1,
6298 .num_resources = ARRAY_SIZE(resources_temp_alarm),
6299 .resources = resources_temp_alarm,
6300 },
6301 { .name = "pm8058-upl",
6302 .id = -1,
6303 },
6304 {
6305 .name = "pm8058-misc",
6306 .id = -1,
6307 .num_resources = ARRAY_SIZE(resources_pm8058_misc),
6308 .resources = resources_pm8058_misc,
6309 },
6310 { .name = "pm8058-batt-alarm",
6311 .id = -1,
6312 .num_resources = ARRAY_SIZE(resources_pm8058_batt_alarm),
6313 .resources = resources_pm8058_batt_alarm,
6314 },
6315};
6316
Terence Hampson90508a92011-08-09 10:40:08 -04006317static struct pmic8058_charger_data pmic8058_charger_dragon = {
6318 .max_source_current = 1800,
6319 .charger_type = CHG_TYPE_AC,
6320};
6321
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006322static struct mfd_cell pm8058_charger_sub_dev = {
6323 .name = "pm8058-charger",
6324 .id = -1,
6325 .num_resources = ARRAY_SIZE(resources_pm8058_charger),
6326 .resources = resources_pm8058_charger,
6327};
6328
6329static struct pm8058_platform_data pm8058_platform_data = {
6330 .irq_base = PM8058_IRQ_BASE,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306331 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006332
6333 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
6334 .sub_devices = pm8058_subdevs,
6335 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6336};
6337
6338static struct i2c_board_info pm8058_boardinfo[] __initdata = {
6339 {
6340 I2C_BOARD_INFO("pm8058-core", 0x55),
6341 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
6342 .platform_data = &pm8058_platform_data,
6343 },
6344};
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306345
6346#ifdef CONFIG_MSM_SSBI
6347static struct msm_ssbi_platform_data msm8x60_ssbi_pm8058_pdata __devinitdata = {
6348 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
6349 .slave = {
6350 .name = "pm8058-core",
6351 .platform_data = &pm8058_platform_data,
6352 },
6353};
6354#endif
6355#endif /* CONFIG_PMIC8058 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006356
6357#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6358 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6359#define TDISC_I2C_SLAVE_ADDR 0x67
6360#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6361#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6362
6363static const char *vregs_tdisc_name[] = {
6364 "8058_l5",
6365 "8058_s3",
6366};
6367
6368static const int vregs_tdisc_val[] = {
6369 2850000,/* uV */
6370 1800000,
6371};
6372static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6373
6374static int tdisc_shinetsu_setup(void)
6375{
6376 int rc, i;
6377
6378 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6379 if (rc) {
6380 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6381 __func__);
6382 return rc;
6383 }
6384
6385 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6386 if (rc) {
6387 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6388 __func__);
6389 goto fail_gpio_oe;
6390 }
6391
6392 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6393 if (rc) {
6394 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6395 __func__);
6396 gpio_free(GPIO_JOYSTICK_EN);
6397 goto fail_gpio_oe;
6398 }
6399
6400 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6401 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6402 if (IS_ERR(vregs_tdisc[i])) {
6403 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6404 __func__, vregs_tdisc_name[i],
6405 PTR_ERR(vregs_tdisc[i]));
6406 rc = PTR_ERR(vregs_tdisc[i]);
6407 goto vreg_get_fail;
6408 }
6409
6410 rc = regulator_set_voltage(vregs_tdisc[i],
6411 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6412 if (rc) {
6413 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6414 __func__, rc);
6415 goto vreg_set_voltage_fail;
6416 }
6417 }
6418
6419 return rc;
6420vreg_set_voltage_fail:
6421 i++;
6422vreg_get_fail:
6423 while (i)
6424 regulator_put(vregs_tdisc[--i]);
6425fail_gpio_oe:
6426 gpio_free(PMIC_GPIO_TDISC);
6427 return rc;
6428}
6429
6430static void tdisc_shinetsu_release(void)
6431{
6432 int i;
6433
6434 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6435 regulator_put(vregs_tdisc[i]);
6436
6437 gpio_free(PMIC_GPIO_TDISC);
6438 gpio_free(GPIO_JOYSTICK_EN);
6439}
6440
6441static int tdisc_shinetsu_enable(void)
6442{
6443 int i, rc = -EINVAL;
6444
6445 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6446 rc = regulator_enable(vregs_tdisc[i]);
6447 if (rc < 0) {
6448 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6449 __func__, vregs_tdisc_name[i], rc);
6450 goto vreg_fail;
6451 }
6452 }
6453
6454 /* Enable the OE (output enable) gpio */
6455 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6456 /* voltage and gpio stabilization delay */
6457 msleep(50);
6458
6459 return 0;
6460vreg_fail:
6461 while (i)
6462 regulator_disable(vregs_tdisc[--i]);
6463 return rc;
6464}
6465
6466static int tdisc_shinetsu_disable(void)
6467{
6468 int i, rc;
6469
6470 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6471 rc = regulator_disable(vregs_tdisc[i]);
6472 if (rc < 0) {
6473 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6474 __func__, vregs_tdisc_name[i], rc);
6475 goto tdisc_reg_fail;
6476 }
6477 }
6478
6479 /* Disable the OE (output enable) gpio */
6480 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6481
6482 return 0;
6483
6484tdisc_reg_fail:
6485 while (i)
6486 regulator_enable(vregs_tdisc[--i]);
6487 return rc;
6488}
6489
6490static struct tdisc_abs_values tdisc_abs = {
6491 .x_max = 32,
6492 .y_max = 32,
6493 .x_min = -32,
6494 .y_min = -32,
6495 .pressure_max = 32,
6496 .pressure_min = 0,
6497};
6498
6499static struct tdisc_platform_data tdisc_data = {
6500 .tdisc_setup = tdisc_shinetsu_setup,
6501 .tdisc_release = tdisc_shinetsu_release,
6502 .tdisc_enable = tdisc_shinetsu_enable,
6503 .tdisc_disable = tdisc_shinetsu_disable,
6504 .tdisc_wakeup = 0,
6505 .tdisc_gpio = PMIC_GPIO_TDISC,
6506 .tdisc_report_keys = true,
6507 .tdisc_report_relative = true,
6508 .tdisc_report_absolute = false,
6509 .tdisc_report_wheel = false,
6510 .tdisc_reverse_x = false,
6511 .tdisc_reverse_y = true,
6512 .tdisc_abs = &tdisc_abs,
6513};
6514
6515static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6516 {
6517 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6518 .irq = TDISC_INT,
6519 .platform_data = &tdisc_data,
6520 },
6521};
6522#endif
6523
6524#define PM_GPIO_CDC_RST_N 20
6525#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6526
6527static struct regulator *vreg_timpani_1;
6528static struct regulator *vreg_timpani_2;
6529
6530static unsigned int msm_timpani_setup_power(void)
6531{
6532 int rc;
6533
6534 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6535 if (IS_ERR(vreg_timpani_1)) {
6536 pr_err("%s: Unable to get 8058_l0\n", __func__);
6537 return -ENODEV;
6538 }
6539
6540 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6541 if (IS_ERR(vreg_timpani_2)) {
6542 pr_err("%s: Unable to get 8058_s3\n", __func__);
6543 regulator_put(vreg_timpani_1);
6544 return -ENODEV;
6545 }
6546
6547 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6548 if (rc) {
6549 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6550 goto fail;
6551 }
6552
6553 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6554 if (rc) {
6555 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6556 goto fail;
6557 }
6558
6559 rc = regulator_enable(vreg_timpani_1);
6560 if (rc) {
6561 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6562 goto fail;
6563 }
6564
6565 /* The settings for LDO0 should be set such that
6566 * it doesn't require to reset the timpani. */
6567 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6568 if (rc < 0) {
6569 pr_err("Timpani regulator optimum mode setting failed\n");
6570 goto fail;
6571 }
6572
6573 rc = regulator_enable(vreg_timpani_2);
6574 if (rc) {
6575 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6576 regulator_disable(vreg_timpani_1);
6577 goto fail;
6578 }
6579
6580 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6581 if (rc) {
6582 pr_err("%s: GPIO Request %d failed\n", __func__,
6583 GPIO_CDC_RST_N);
6584 regulator_disable(vreg_timpani_1);
6585 regulator_disable(vreg_timpani_2);
6586 goto fail;
6587 } else {
6588 gpio_direction_output(GPIO_CDC_RST_N, 1);
6589 usleep_range(1000, 1050);
6590 gpio_direction_output(GPIO_CDC_RST_N, 0);
6591 usleep_range(1000, 1050);
6592 gpio_direction_output(GPIO_CDC_RST_N, 1);
6593 gpio_free(GPIO_CDC_RST_N);
6594 }
6595 return rc;
6596
6597fail:
6598 regulator_put(vreg_timpani_1);
6599 regulator_put(vreg_timpani_2);
6600 return rc;
6601}
6602
6603static void msm_timpani_shutdown_power(void)
6604{
6605 int rc;
6606
6607 rc = regulator_disable(vreg_timpani_1);
6608 if (rc)
6609 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6610
6611 regulator_put(vreg_timpani_1);
6612
6613 rc = regulator_disable(vreg_timpani_2);
6614 if (rc)
6615 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6616
6617 regulator_put(vreg_timpani_2);
6618}
6619
6620/* Power analog function of codec */
6621static struct regulator *vreg_timpani_cdc_apwr;
6622static int msm_timpani_codec_power(int vreg_on)
6623{
6624 int rc = 0;
6625
6626 if (!vreg_timpani_cdc_apwr) {
6627
6628 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6629
6630 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6631 pr_err("%s: vreg_get failed (%ld)\n",
6632 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6633 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6634 return rc;
6635 }
6636 }
6637
6638 if (vreg_on) {
6639
6640 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6641 2200000, 2200000);
6642 if (rc) {
6643 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6644 __func__);
6645 goto vreg_fail;
6646 }
6647
6648 rc = regulator_enable(vreg_timpani_cdc_apwr);
6649 if (rc) {
6650 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6651 goto vreg_fail;
6652 }
6653 } else {
6654 rc = regulator_disable(vreg_timpani_cdc_apwr);
6655 if (rc) {
6656 pr_err("%s: vreg_disable failed %d\n",
6657 __func__, rc);
6658 goto vreg_fail;
6659 }
6660 }
6661
6662 return 0;
6663
6664vreg_fail:
6665 regulator_put(vreg_timpani_cdc_apwr);
6666 vreg_timpani_cdc_apwr = NULL;
6667 return rc;
6668}
6669
6670static struct marimba_codec_platform_data timpani_codec_pdata = {
6671 .marimba_codec_power = msm_timpani_codec_power,
6672};
6673
6674#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6675#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6676
6677static struct marimba_platform_data timpani_pdata = {
6678 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6679 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6680 .marimba_setup = msm_timpani_setup_power,
6681 .marimba_shutdown = msm_timpani_shutdown_power,
6682 .codec = &timpani_codec_pdata,
6683 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6684};
6685
6686#define TIMPANI_I2C_SLAVE_ADDR 0xD
6687
6688static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6689 {
6690 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6691 .platform_data = &timpani_pdata,
6692 },
6693};
6694
Lei Zhou338cab82011-08-19 13:38:17 -04006695#ifdef CONFIG_SND_SOC_WM8903
6696static struct wm8903_platform_data wm8903_pdata = {
6697 .gpio_cfg[2] = 0x3A8,
6698};
6699
6700#define WM8903_I2C_SLAVE_ADDR 0x34
6701static struct i2c_board_info wm8903_codec_i2c_info[] = {
6702 {
6703 I2C_BOARD_INFO("wm8903", WM8903_I2C_SLAVE_ADDR >> 1),
6704 .platform_data = &wm8903_pdata,
6705 },
6706};
6707#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006708#ifdef CONFIG_PMIC8901
6709
6710#define PM8901_GPIO_INT 91
6711
6712static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6713 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6714 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6715};
6716
6717static struct resource pm8901_temp_alarm[] = {
6718 {
6719 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6720 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6721 .flags = IORESOURCE_IRQ,
6722 },
6723 {
6724 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6725 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6726 .flags = IORESOURCE_IRQ,
6727 },
6728};
6729
6730/*
6731 * Consumer specific regulator names:
6732 * regulator name consumer dev_name
6733 */
6734static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6735 REGULATOR_SUPPLY("8901_mpp0", NULL),
6736};
6737static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6738 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6739};
6740static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6741 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6742};
6743
6744#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6745 _always_on, _active_high) \
6746 [PM8901_VREG_ID_##_id] = { \
6747 .init_data = { \
6748 .constraints = { \
6749 .valid_modes_mask = _modes, \
6750 .valid_ops_mask = _ops, \
6751 .min_uV = _min_uV, \
6752 .max_uV = _max_uV, \
6753 .input_uV = _min_uV, \
6754 .apply_uV = _apply_uV, \
6755 .always_on = _always_on, \
6756 }, \
6757 .consumer_supplies = vreg_consumers_8901_##_id, \
6758 .num_consumer_supplies = \
6759 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6760 }, \
6761 .active_high = _active_high, \
6762 }
6763
6764#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6765 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6766 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6767
6768#define PM8901_VREG_INIT_VS(_id) \
6769 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6770 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6771
6772static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6773 PM8901_VREG_INIT_MPP(MPP0, 1),
6774
6775 PM8901_VREG_INIT_VS(USB_OTG),
6776 PM8901_VREG_INIT_VS(HDMI_MVS),
6777};
6778
6779#define PM8901_VREG(_id) { \
6780 .name = "pm8901-regulator", \
6781 .id = _id, \
6782 .platform_data = &pm8901_vreg_init_pdata[_id], \
6783 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6784}
6785
6786static struct mfd_cell pm8901_subdevs[] = {
6787 { .name = "pm8901-mpp",
6788 .id = -1,
6789 .platform_data = &pm8901_mpp_data,
6790 .pdata_size = sizeof(pm8901_mpp_data),
6791 },
6792 { .name = "pm8901-tm",
6793 .id = -1,
6794 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6795 .resources = pm8901_temp_alarm,
6796 },
6797 PM8901_VREG(PM8901_VREG_ID_MPP0),
6798 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6799 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6800};
6801
6802static struct pm8901_platform_data pm8901_platform_data = {
6803 .irq_base = PM8901_IRQ_BASE,
6804 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6805 .sub_devices = pm8901_subdevs,
6806 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6807};
6808
6809static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6810 {
6811 I2C_BOARD_INFO("pm8901-core", 0x55),
6812 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6813 .platform_data = &pm8901_platform_data,
6814 },
6815};
6816
6817#endif /* CONFIG_PMIC8901 */
6818
6819#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6820 || defined(CONFIG_GPIO_SX150X_MODULE))
6821
6822static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006823static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006824
6825struct bahama_config_register{
6826 u8 reg;
6827 u8 value;
6828 u8 mask;
6829};
6830
6831enum version{
6832 VER_1_0,
6833 VER_2_0,
6834 VER_UNSUPPORTED = 0xFF
6835};
6836
6837static u8 read_bahama_ver(void)
6838{
6839 int rc;
6840 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6841 u8 bahama_version;
6842
6843 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6844 if (rc < 0) {
6845 printk(KERN_ERR
6846 "%s: version read failed: %d\n",
6847 __func__, rc);
6848 return VER_UNSUPPORTED;
6849 } else {
6850 printk(KERN_INFO
6851 "%s: version read got: 0x%x\n",
6852 __func__, bahama_version);
6853 }
6854
6855 switch (bahama_version) {
6856 case 0x08: /* varient of bahama v1 */
6857 case 0x10:
6858 case 0x00:
6859 return VER_1_0;
6860 case 0x09: /* variant of bahama v2 */
6861 return VER_2_0;
6862 default:
6863 return VER_UNSUPPORTED;
6864 }
6865}
6866
6867static unsigned int msm_bahama_setup_power(void)
6868{
6869 int rc = 0;
6870 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006871
6872 if (machine_is_msm8x60_dragon())
6873 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6874
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006875 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6876
6877 if (IS_ERR(vreg_bahama)) {
6878 rc = PTR_ERR(vreg_bahama);
6879 pr_err("%s: regulator_get %s = %d\n", __func__,
6880 msm_bahama_regulator, rc);
6881 }
6882
6883 if (!rc)
6884 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6885 else {
6886 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6887 msm_bahama_regulator, rc);
6888 goto unget;
6889 }
6890
6891 if (!rc)
6892 rc = regulator_enable(vreg_bahama);
6893 else {
6894 pr_err("%s: regulator_enable %s = %d\n", __func__,
6895 msm_bahama_regulator, rc);
6896 goto unget;
6897 }
6898
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006899 if (!rc) {
6900 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6901 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006902 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006903 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006904 goto unenable;
6905 }
6906
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006907 if (!rc) {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006908 gpio_direction_output(msm_bahama_sys_rst, 0);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006909 usleep_range(1000, 1050);
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006910 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006911 usleep_range(1000, 1050);
6912 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006913 pr_err("%s: gpio_direction_output %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006914 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006915 goto unrequest;
6916 }
6917
6918 return rc;
6919
6920unrequest:
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006921 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006922unenable:
6923 regulator_disable(vreg_bahama);
6924unget:
6925 regulator_put(vreg_bahama);
6926 return rc;
6927};
6928static unsigned int msm_bahama_shutdown_power(int value)
6929
6930
6931{
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006932 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006933
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006934 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006935
6936 regulator_disable(vreg_bahama);
6937
6938 regulator_put(vreg_bahama);
6939
6940 return 0;
6941};
6942
6943static unsigned int msm_bahama_core_config(int type)
6944{
6945 int rc = 0;
6946
6947 if (type == BAHAMA_ID) {
6948
6949 int i;
6950 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6951
6952 const struct bahama_config_register v20_init[] = {
6953 /* reg, value, mask */
6954 { 0xF4, 0x84, 0xFF }, /* AREG */
6955 { 0xF0, 0x04, 0xFF } /* DREG */
6956 };
6957
6958 if (read_bahama_ver() == VER_2_0) {
6959 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6960 u8 value = v20_init[i].value;
6961 rc = marimba_write_bit_mask(&config,
6962 v20_init[i].reg,
6963 &value,
6964 sizeof(v20_init[i].value),
6965 v20_init[i].mask);
6966 if (rc < 0) {
6967 printk(KERN_ERR
6968 "%s: reg %d write failed: %d\n",
6969 __func__, v20_init[i].reg, rc);
6970 return rc;
6971 }
6972 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6973 " mask 0x%02x\n",
6974 __func__, v20_init[i].reg,
6975 v20_init[i].value, v20_init[i].mask);
6976 }
6977 }
6978 }
6979 printk(KERN_INFO "core type: %d\n", type);
6980
6981 return rc;
6982}
6983
6984static struct regulator *fm_regulator_s3;
6985static struct msm_xo_voter *fm_clock;
6986
6987static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6988{
6989 int rc = 0;
6990 struct pm8058_gpio cfg = {
6991 .direction = PM_GPIO_DIR_IN,
6992 .pull = PM_GPIO_PULL_NO,
6993 .vin_sel = PM_GPIO_VIN_S3,
6994 .function = PM_GPIO_FUNC_NORMAL,
6995 .inv_int_pol = 0,
6996 };
6997
6998 if (!fm_regulator_s3) {
6999 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
7000 if (IS_ERR(fm_regulator_s3)) {
7001 rc = PTR_ERR(fm_regulator_s3);
7002 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
7003 __func__, rc);
7004 goto out;
7005 }
7006 }
7007
7008
7009 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
7010 if (rc < 0) {
7011 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
7012 __func__, rc);
7013 goto fm_fail_put;
7014 }
7015
7016 rc = regulator_enable(fm_regulator_s3);
7017 if (rc < 0) {
7018 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
7019 __func__, rc);
7020 goto fm_fail_put;
7021 }
7022
7023 /*Vote for XO clock*/
7024 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
7025
7026 if (IS_ERR(fm_clock)) {
7027 rc = PTR_ERR(fm_clock);
7028 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
7029 __func__, rc);
7030 goto fm_fail_switch;
7031 }
7032
7033 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
7034 if (rc < 0) {
7035 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
7036 __func__, rc);
7037 goto fm_fail_vote;
7038 }
7039
7040 /*GPIO 18 on PMIC is FM_IRQ*/
7041 rc = pm8058_gpio_config(FM_GPIO, &cfg);
7042 if (rc) {
7043 printk(KERN_ERR "%s: return val of pm8058_gpio_config: %d\n",
7044 __func__, rc);
7045 goto fm_fail_clock;
7046 }
7047 goto out;
7048
7049fm_fail_clock:
7050 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7051fm_fail_vote:
7052 msm_xo_put(fm_clock);
7053fm_fail_switch:
7054 regulator_disable(fm_regulator_s3);
7055fm_fail_put:
7056 regulator_put(fm_regulator_s3);
7057out:
7058 return rc;
7059};
7060
7061static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
7062{
7063 int rc = 0;
7064 if (fm_regulator_s3 != NULL) {
7065 rc = regulator_disable(fm_regulator_s3);
7066 if (rc < 0) {
7067 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
7068 __func__, rc);
7069 }
7070 regulator_put(fm_regulator_s3);
7071 fm_regulator_s3 = NULL;
7072 }
7073 printk(KERN_ERR "%s: Voting off for XO", __func__);
7074
7075 if (fm_clock != NULL) {
7076 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7077 if (rc < 0) {
7078 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
7079 __func__, rc);
7080 }
7081 msm_xo_put(fm_clock);
7082 }
7083 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
7084}
7085
7086/* Slave id address for FM/CDC/QMEMBIST
7087 * Values can be programmed using Marimba slave id 0
7088 * should there be a conflict with other I2C devices
7089 * */
7090#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
7091#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
7092
7093static struct marimba_fm_platform_data marimba_fm_pdata = {
7094 .fm_setup = fm_radio_setup,
7095 .fm_shutdown = fm_radio_shutdown,
7096 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
7097 .is_fm_soc_i2s_master = false,
7098 .config_i2s_gpio = NULL,
7099};
7100
7101/*
7102Just initializing the BAHAMA related slave
7103*/
7104static struct marimba_platform_data marimba_pdata = {
7105 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
7106 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
7107 .bahama_setup = msm_bahama_setup_power,
7108 .bahama_shutdown = msm_bahama_shutdown_power,
7109 .bahama_core_config = msm_bahama_core_config,
7110 .fm = &marimba_fm_pdata,
7111 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
7112};
7113
7114
7115static struct i2c_board_info msm_marimba_board_info[] = {
7116 {
7117 I2C_BOARD_INFO("marimba", 0xc),
7118 .platform_data = &marimba_pdata,
7119 }
7120};
7121#endif /* CONFIG_MAIMBA_CORE */
7122
7123#ifdef CONFIG_I2C
7124#define I2C_SURF 1
7125#define I2C_FFA (1 << 1)
7126#define I2C_RUMI (1 << 2)
7127#define I2C_SIM (1 << 3)
7128#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007129#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007130
7131struct i2c_registry {
7132 u8 machs;
7133 int bus;
7134 struct i2c_board_info *info;
7135 int len;
7136};
7137
7138static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
7139#ifdef CONFIG_PMIC8058
7140 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007141 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007142 MSM_SSBI1_I2C_BUS_ID,
7143 pm8058_boardinfo,
7144 ARRAY_SIZE(pm8058_boardinfo),
7145 },
7146#endif
7147#ifdef CONFIG_PMIC8901
7148 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007149 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007150 MSM_SSBI2_I2C_BUS_ID,
7151 pm8901_boardinfo,
7152 ARRAY_SIZE(pm8901_boardinfo),
7153 },
7154#endif
7155#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7156 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007157 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007158 MSM_GSBI8_QUP_I2C_BUS_ID,
7159 core_expander_i2c_info,
7160 ARRAY_SIZE(core_expander_i2c_info),
7161 },
7162 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007163 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007164 MSM_GSBI8_QUP_I2C_BUS_ID,
7165 docking_expander_i2c_info,
7166 ARRAY_SIZE(docking_expander_i2c_info),
7167 },
7168 {
7169 I2C_SURF,
7170 MSM_GSBI8_QUP_I2C_BUS_ID,
7171 surf_expanders_i2c_info,
7172 ARRAY_SIZE(surf_expanders_i2c_info),
7173 },
7174 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007175 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007176 MSM_GSBI3_QUP_I2C_BUS_ID,
7177 fha_expanders_i2c_info,
7178 ARRAY_SIZE(fha_expanders_i2c_info),
7179 },
7180 {
7181 I2C_FLUID,
7182 MSM_GSBI3_QUP_I2C_BUS_ID,
7183 fluid_expanders_i2c_info,
7184 ARRAY_SIZE(fluid_expanders_i2c_info),
7185 },
7186 {
7187 I2C_FLUID,
7188 MSM_GSBI8_QUP_I2C_BUS_ID,
7189 fluid_core_expander_i2c_info,
7190 ARRAY_SIZE(fluid_core_expander_i2c_info),
7191 },
7192#endif
7193#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
7194 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
7195 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007196 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007197 MSM_GSBI3_QUP_I2C_BUS_ID,
7198 msm_i2c_gsbi3_tdisc_info,
7199 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7200 },
7201#endif
7202 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007203 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007204 MSM_GSBI3_QUP_I2C_BUS_ID,
7205 cy8ctmg200_board_info,
7206 ARRAY_SIZE(cy8ctmg200_board_info),
7207 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007208 {
7209 I2C_DRAGON,
7210 MSM_GSBI3_QUP_I2C_BUS_ID,
7211 cy8ctma340_dragon_board_info,
7212 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7213 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007214#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7215 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7216 {
7217 I2C_FLUID,
7218 MSM_GSBI3_QUP_I2C_BUS_ID,
7219 cyttsp_fluid_info,
7220 ARRAY_SIZE(cyttsp_fluid_info),
7221 },
7222 {
7223 I2C_FFA | I2C_SURF,
7224 MSM_GSBI3_QUP_I2C_BUS_ID,
7225 cyttsp_ffa_info,
7226 ARRAY_SIZE(cyttsp_ffa_info),
7227 },
7228#endif
7229#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007230 {
7231 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007232 MSM_GSBI4_QUP_I2C_BUS_ID,
7233 msm_camera_boardinfo,
7234 ARRAY_SIZE(msm_camera_boardinfo),
7235 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007236 {
7237 I2C_DRAGON,
7238 MSM_GSBI4_QUP_I2C_BUS_ID,
7239 msm_camera_dragon_boardinfo,
7240 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7241 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007242#endif
7243 {
7244 I2C_SURF | I2C_FFA | I2C_FLUID,
7245 MSM_GSBI7_QUP_I2C_BUS_ID,
7246 msm_i2c_gsbi7_timpani_info,
7247 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7248 },
7249#if defined(CONFIG_MARIMBA_CORE)
7250 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007251 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007252 MSM_GSBI7_QUP_I2C_BUS_ID,
7253 msm_marimba_board_info,
7254 ARRAY_SIZE(msm_marimba_board_info),
7255 },
7256#endif /* CONFIG_MARIMBA_CORE */
7257#ifdef CONFIG_ISL9519_CHARGER
7258 {
7259 I2C_SURF | I2C_FFA,
7260 MSM_GSBI8_QUP_I2C_BUS_ID,
7261 isl_charger_i2c_info,
7262 ARRAY_SIZE(isl_charger_i2c_info),
7263 },
7264#endif
7265#if defined(CONFIG_HAPTIC_ISA1200) || \
7266 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7267 {
7268 I2C_FLUID,
7269 MSM_GSBI8_QUP_I2C_BUS_ID,
7270 msm_isa1200_board_info,
7271 ARRAY_SIZE(msm_isa1200_board_info),
7272 },
7273#endif
7274#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7275 {
7276 I2C_FLUID,
7277 MSM_GSBI8_QUP_I2C_BUS_ID,
7278 smb137b_charger_i2c_info,
7279 ARRAY_SIZE(smb137b_charger_i2c_info),
7280 },
7281#endif
7282#if defined(CONFIG_BATTERY_BQ27520) || \
7283 defined(CONFIG_BATTERY_BQ27520_MODULE)
7284 {
7285 I2C_FLUID,
7286 MSM_GSBI8_QUP_I2C_BUS_ID,
7287 msm_bq27520_board_info,
7288 ARRAY_SIZE(msm_bq27520_board_info),
7289 },
7290#endif
Lei Zhou338cab82011-08-19 13:38:17 -04007291#if defined(CONFIG_SND_SOC_WM8903) || defined(CONFIG_SND_SOC_WM8903_MODULE)
7292 {
7293 I2C_DRAGON,
7294 MSM_GSBI8_QUP_I2C_BUS_ID,
7295 wm8903_codec_i2c_info,
7296 ARRAY_SIZE(wm8903_codec_i2c_info),
7297 },
7298#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007299};
7300#endif /* CONFIG_I2C */
7301
7302static void fixup_i2c_configs(void)
7303{
7304#ifdef CONFIG_I2C
7305#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7306 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7307 sx150x_data[SX150X_CORE].irq_summary =
7308 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007309 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7310 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007311 sx150x_data[SX150X_CORE].irq_summary =
7312 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7313 else if (machine_is_msm8x60_fluid())
7314 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7315 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7316#endif
7317 /*
7318 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7319 * implies that the regulator connected to MPP0 is enabled when
7320 * MPP0 is low.
7321 */
7322 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7323 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7324 else
7325 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7326#endif
7327}
7328
7329static void register_i2c_devices(void)
7330{
7331#ifdef CONFIG_I2C
7332 u8 mach_mask = 0;
7333 int i;
7334
7335 /* Build the matching 'supported_machs' bitmask */
7336 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7337 mach_mask = I2C_SURF;
7338 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7339 mach_mask = I2C_FFA;
7340 else if (machine_is_msm8x60_rumi3())
7341 mach_mask = I2C_RUMI;
7342 else if (machine_is_msm8x60_sim())
7343 mach_mask = I2C_SIM;
7344 else if (machine_is_msm8x60_fluid())
7345 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007346 else if (machine_is_msm8x60_dragon())
7347 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007348 else
7349 pr_err("unmatched machine ID in register_i2c_devices\n");
7350
7351 /* Run the array and install devices as appropriate */
7352 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7353 if (msm8x60_i2c_devices[i].machs & mach_mask)
7354 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7355 msm8x60_i2c_devices[i].info,
7356 msm8x60_i2c_devices[i].len);
7357 }
7358#endif
7359}
7360
7361static void __init msm8x60_init_uart12dm(void)
7362{
7363#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7364 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7365 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7366
7367 if (!fpga_mem)
7368 pr_err("%s(): Error getting memory\n", __func__);
7369
7370 /* Advanced mode */
7371 writew(0xFFFF, fpga_mem + 0x15C);
7372 /* FPGA_UART_SEL */
7373 writew(0, fpga_mem + 0x172);
7374 /* FPGA_GPIO_CONFIG_117 */
7375 writew(1, fpga_mem + 0xEA);
7376 /* FPGA_GPIO_CONFIG_118 */
7377 writew(1, fpga_mem + 0xEC);
7378 mb();
7379 iounmap(fpga_mem);
7380#endif
7381}
7382
7383#define MSM_GSBI9_PHYS 0x19900000
7384#define GSBI_DUAL_MODE_CODE 0x60
7385
7386static void __init msm8x60_init_buses(void)
7387{
7388#ifdef CONFIG_I2C_QUP
7389 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7390 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7391 writel_relaxed(0x6 << 4, gsbi_mem);
7392 /* Ensure protocol code is written before proceeding further */
7393 mb();
7394 iounmap(gsbi_mem);
7395
7396 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7397 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7398 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7399 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7400
7401#ifdef CONFIG_MSM_GSBI9_UART
7402 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7403 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7404 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7405 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7406 iounmap(gsbi_mem);
7407 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7408 }
7409#endif
7410 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7411 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7412#endif
7413#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7414 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7415#endif
7416#ifdef CONFIG_I2C_SSBI
7417 msm_device_ssbi1.dev.platform_data = &msm_ssbi1_pdata;
7418 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7419 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7420#endif
7421
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05307422#ifdef CONFIG_MSM_SSBI
7423 msm_device_ssbi_pmic1.dev.platform_data =
7424 &msm8x60_ssbi_pm8058_pdata;
7425#endif
7426
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007427 if (machine_is_msm8x60_fluid()) {
7428#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7429 (defined(CONFIG_SMB137B_CHARGER) || \
7430 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7431 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7432#endif
7433#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7434 msm_gsbi10_qup_spi_device.dev.platform_data =
7435 &msm_gsbi10_qup_spi_pdata;
7436#endif
7437 }
7438
7439#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7440 /*
7441 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7442 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7443 * and ID notifications are available only on V2 surf and FFA
7444 * with a hardware workaround.
7445 */
7446 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7447 (machine_is_msm8x60_surf() ||
7448 (machine_is_msm8x60_ffa() &&
7449 pmic_id_notif_supported)))
7450 msm_otg_pdata.phy_can_powercollapse = 1;
7451 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7452#endif
7453
7454#ifdef CONFIG_USB_GADGET_MSM_72K
7455 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7456#endif
7457
7458#ifdef CONFIG_SERIAL_MSM_HS
7459 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7460 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7461#endif
7462#ifdef CONFIG_MSM_GSBI9_UART
7463 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7464 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7465 if (IS_ERR(msm_device_uart_gsbi9))
7466 pr_err("%s(): Failed to create uart gsbi9 device\n",
7467 __func__);
7468 }
7469#endif
7470
7471#ifdef CONFIG_MSM_BUS_SCALING
7472
7473 /* RPM calls are only enabled on V2 */
7474 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7475 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7476 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7477 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7478 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7479 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7480 }
7481
7482 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7483 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7484 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7485 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7486 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7487#endif
7488}
7489
7490static void __init msm8x60_map_io(void)
7491{
7492 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7493 msm_map_msm8x60_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007494
7495 if (socinfo_init() < 0)
7496 pr_err("socinfo_init() failed!\n");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007497}
7498
7499/*
7500 * Most segments of the EBI2 bus are disabled by default.
7501 */
7502static void __init msm8x60_init_ebi2(void)
7503{
7504 uint32_t ebi2_cfg;
7505 void *ebi2_cfg_ptr;
Terence Hampsonb36a38c2011-09-19 19:10:40 -04007506 struct clk *mem_clk = clk_get_sys("msm_ebi2", "mem_clk");
7507
7508 if (IS_ERR(mem_clk)) {
7509 pr_err("%s: clk_get_sys(%s,%s), failed", __func__,
7510 "msm_ebi2", "mem_clk");
7511 return;
7512 }
7513 clk_enable(mem_clk);
7514 clk_put(mem_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007515
7516 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7517 if (ebi2_cfg_ptr != 0) {
7518 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7519
7520 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007521 machine_is_msm8x60_fluid() ||
7522 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007523 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7524 else if (machine_is_msm8x60_sim())
7525 ebi2_cfg |= (1 << 4); /* CS2 */
7526 else if (machine_is_msm8x60_rumi3())
7527 ebi2_cfg |= (1 << 5); /* CS3 */
7528
7529 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7530 iounmap(ebi2_cfg_ptr);
7531 }
7532
7533 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007534 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007535 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7536 if (ebi2_cfg_ptr != 0) {
7537 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7538 writel_relaxed(0UL, ebi2_cfg_ptr);
7539
7540 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7541 * LAN9221 Ethernet controller reads and writes.
7542 * The lowest 4 bits are the read delay, the next
7543 * 4 are the write delay. */
7544 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7545#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7546 /*
7547 * RECOVERY=5, HOLD_WR=1
7548 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7549 * WAIT_WR=1, WAIT_RD=2
7550 */
7551 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7552 /*
7553 * HOLD_RD=1
7554 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7555 */
7556 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7557#else
7558 /* EBI2 CS3 muxed address/data,
7559 * two cyc addr enable */
7560 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7561
7562#endif
7563 iounmap(ebi2_cfg_ptr);
7564 }
7565 }
7566}
7567
7568static void __init msm8x60_configure_smc91x(void)
7569{
7570 if (machine_is_msm8x60_sim()) {
7571
7572 smc91x_resources[0].start = 0x1b800300;
7573 smc91x_resources[0].end = 0x1b8003ff;
7574
7575 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7576 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7577
7578 } else if (machine_is_msm8x60_rumi3()) {
7579
7580 smc91x_resources[0].start = 0x1d000300;
7581 smc91x_resources[0].end = 0x1d0003ff;
7582
7583 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7584 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7585 }
7586}
7587
7588static void __init msm8x60_init_tlmm(void)
7589{
7590 if (machine_is_msm8x60_rumi3())
7591 msm_gpio_install_direct_irq(0, 0, 1);
7592}
7593
7594#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7595 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7596 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7597 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7598 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7599
7600/* 8x60 is having 5 SDCC controllers */
7601#define MAX_SDCC_CONTROLLER 5
7602
7603struct msm_sdcc_gpio {
7604 /* maximum 10 GPIOs per SDCC controller */
7605 s16 no;
7606 /* name of this GPIO */
7607 const char *name;
7608 bool always_on;
7609 bool is_enabled;
7610};
7611
7612#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7613static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7614 {159, "sdc1_dat_0"},
7615 {160, "sdc1_dat_1"},
7616 {161, "sdc1_dat_2"},
7617 {162, "sdc1_dat_3"},
7618#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7619 {163, "sdc1_dat_4"},
7620 {164, "sdc1_dat_5"},
7621 {165, "sdc1_dat_6"},
7622 {166, "sdc1_dat_7"},
7623#endif
7624 {167, "sdc1_clk"},
7625 {168, "sdc1_cmd"}
7626};
7627#endif
7628
7629#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7630static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7631 {143, "sdc2_dat_0"},
7632 {144, "sdc2_dat_1", 1},
7633 {145, "sdc2_dat_2"},
7634 {146, "sdc2_dat_3"},
7635#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7636 {147, "sdc2_dat_4"},
7637 {148, "sdc2_dat_5"},
7638 {149, "sdc2_dat_6"},
7639 {150, "sdc2_dat_7"},
7640#endif
7641 {151, "sdc2_cmd"},
7642 {152, "sdc2_clk", 1}
7643};
7644#endif
7645
7646#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7647static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7648 {95, "sdc5_cmd"},
7649 {96, "sdc5_dat_3"},
7650 {97, "sdc5_clk", 1},
7651 {98, "sdc5_dat_2"},
7652 {99, "sdc5_dat_1", 1},
7653 {100, "sdc5_dat_0"}
7654};
7655#endif
7656
7657struct msm_sdcc_pad_pull_cfg {
7658 enum msm_tlmm_pull_tgt pull;
7659 u32 pull_val;
7660};
7661
7662struct msm_sdcc_pad_drv_cfg {
7663 enum msm_tlmm_hdrive_tgt drv;
7664 u32 drv_val;
7665};
7666
7667#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7668static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7669 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7670 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7671 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7672};
7673
7674static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7675 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7676 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7677};
7678
7679static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7680 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7681 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7682 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7683};
7684
7685static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7686 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7687 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7688};
7689#endif
7690
7691#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7692static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7693 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7694 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7695 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7696};
7697
7698static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7699 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7700 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7701};
7702
7703static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7704 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7705 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7706 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7707};
7708
7709static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7710 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7711 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7712};
7713#endif
7714
7715struct msm_sdcc_pin_cfg {
7716 /*
7717 * = 1 if controller pins are using gpios
7718 * = 0 if controller has dedicated MSM pins
7719 */
7720 u8 is_gpio;
7721 u8 cfg_sts;
7722 u8 gpio_data_size;
7723 struct msm_sdcc_gpio *gpio_data;
7724 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7725 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7726 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7727 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7728 u8 pad_drv_data_size;
7729 u8 pad_pull_data_size;
7730 u8 sdio_lpm_gpio_cfg;
7731};
7732
7733
7734static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7735#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7736 [0] = {
7737 .is_gpio = 1,
7738 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7739 .gpio_data = sdc1_gpio_cfg
7740 },
7741#endif
7742#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7743 [1] = {
7744 .is_gpio = 1,
7745 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7746 .gpio_data = sdc2_gpio_cfg
7747 },
7748#endif
7749#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7750 [2] = {
7751 .is_gpio = 0,
7752 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7753 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7754 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7755 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7756 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7757 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7758 },
7759#endif
7760#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7761 [3] = {
7762 .is_gpio = 0,
7763 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7764 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7765 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7766 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7767 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7768 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7769 },
7770#endif
7771#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7772 [4] = {
7773 .is_gpio = 1,
7774 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7775 .gpio_data = sdc5_gpio_cfg
7776 }
7777#endif
7778};
7779
7780static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7781{
7782 int rc = 0;
7783 struct msm_sdcc_pin_cfg *curr;
7784 int n;
7785
7786 curr = &sdcc_pin_cfg_data[dev_id - 1];
7787 if (!curr->gpio_data)
7788 goto out;
7789
7790 for (n = 0; n < curr->gpio_data_size; n++) {
7791 if (enable) {
7792
7793 if (curr->gpio_data[n].always_on &&
7794 curr->gpio_data[n].is_enabled)
7795 continue;
7796 pr_debug("%s: enable: %s\n", __func__,
7797 curr->gpio_data[n].name);
7798 rc = gpio_request(curr->gpio_data[n].no,
7799 curr->gpio_data[n].name);
7800 if (rc) {
7801 pr_err("%s: gpio_request(%d, %s)"
7802 "failed", __func__,
7803 curr->gpio_data[n].no,
7804 curr->gpio_data[n].name);
7805 goto free_gpios;
7806 }
7807 /* set direction as output for all GPIOs */
7808 rc = gpio_direction_output(
7809 curr->gpio_data[n].no, 1);
7810 if (rc) {
7811 pr_err("%s: gpio_direction_output"
7812 "(%d, 1) failed\n", __func__,
7813 curr->gpio_data[n].no);
7814 goto free_gpios;
7815 }
7816 curr->gpio_data[n].is_enabled = 1;
7817 } else {
7818 /*
7819 * now free this GPIO which will put GPIO
7820 * in low power mode and will also put GPIO
7821 * in input mode
7822 */
7823 if (curr->gpio_data[n].always_on)
7824 continue;
7825 pr_debug("%s: disable: %s\n", __func__,
7826 curr->gpio_data[n].name);
7827 gpio_free(curr->gpio_data[n].no);
7828 curr->gpio_data[n].is_enabled = 0;
7829 }
7830 }
7831 curr->cfg_sts = enable;
7832 goto out;
7833
7834free_gpios:
7835 for (; n >= 0; n--)
7836 gpio_free(curr->gpio_data[n].no);
7837out:
7838 return rc;
7839}
7840
7841static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7842{
7843 int rc = 0;
7844 struct msm_sdcc_pin_cfg *curr;
7845 int n;
7846
7847 curr = &sdcc_pin_cfg_data[dev_id - 1];
7848 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7849 goto out;
7850
7851 if (enable) {
7852 /*
7853 * set up the normal driver strength and
7854 * pull config for pads
7855 */
7856 for (n = 0; n < curr->pad_drv_data_size; n++) {
7857 if (curr->sdio_lpm_gpio_cfg) {
7858 if (curr->pad_drv_on_data[n].drv ==
7859 TLMM_HDRV_SDC4_DATA)
7860 continue;
7861 }
7862 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7863 curr->pad_drv_on_data[n].drv_val);
7864 }
7865 for (n = 0; n < curr->pad_pull_data_size; n++) {
7866 if (curr->sdio_lpm_gpio_cfg) {
7867 if (curr->pad_pull_on_data[n].pull ==
7868 TLMM_PULL_SDC4_DATA)
7869 continue;
7870 }
7871 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7872 curr->pad_pull_on_data[n].pull_val);
7873 }
7874 } else {
7875 /* set the low power config for pads */
7876 for (n = 0; n < curr->pad_drv_data_size; n++) {
7877 if (curr->sdio_lpm_gpio_cfg) {
7878 if (curr->pad_drv_off_data[n].drv ==
7879 TLMM_HDRV_SDC4_DATA)
7880 continue;
7881 }
7882 msm_tlmm_set_hdrive(
7883 curr->pad_drv_off_data[n].drv,
7884 curr->pad_drv_off_data[n].drv_val);
7885 }
7886 for (n = 0; n < curr->pad_pull_data_size; n++) {
7887 if (curr->sdio_lpm_gpio_cfg) {
7888 if (curr->pad_pull_off_data[n].pull ==
7889 TLMM_PULL_SDC4_DATA)
7890 continue;
7891 }
7892 msm_tlmm_set_pull(
7893 curr->pad_pull_off_data[n].pull,
7894 curr->pad_pull_off_data[n].pull_val);
7895 }
7896 }
7897 curr->cfg_sts = enable;
7898out:
7899 return rc;
7900}
7901
7902struct sdcc_reg {
7903 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7904 const char *reg_name;
7905 /*
7906 * is set voltage supported for this regulator?
7907 * 0 = not supported, 1 = supported
7908 */
7909 unsigned char set_voltage_sup;
7910 /* voltage level to be set */
7911 unsigned int level;
7912 /* VDD/VCC/VCCQ voltage regulator handle */
7913 struct regulator *reg;
7914 /* is this regulator enabled? */
7915 bool enabled;
7916 /* is this regulator needs to be always on? */
7917 bool always_on;
7918 /* is operating power mode setting required for this regulator? */
7919 bool op_pwr_mode_sup;
7920 /* Load values for low power and high power mode */
7921 unsigned int lpm_uA;
7922 unsigned int hpm_uA;
7923};
7924/* all SDCC controllers requires VDD/VCC voltage */
7925static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7926/* only SDCC1 requires VCCQ voltage */
7927static struct sdcc_reg sdcc_vccq_reg_data[1];
7928/* all SDCC controllers may require voting for VDD PAD voltage */
7929static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7930
7931struct sdcc_reg_data {
7932 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7933 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7934 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7935 unsigned char sts; /* regulator enable/disable status */
7936};
7937/* msm8x60 have 5 SDCC controllers */
7938static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7939
7940static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7941{
7942 int rc = 0;
7943
7944 /* Get the regulator handle */
7945 vreg->reg = regulator_get(NULL, vreg->reg_name);
7946 if (IS_ERR(vreg->reg)) {
7947 rc = PTR_ERR(vreg->reg);
7948 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7949 __func__, vreg->reg_name, rc);
7950 goto out;
7951 }
7952
7953 /* Set the voltage level if required */
7954 if (vreg->set_voltage_sup) {
7955 rc = regulator_set_voltage(vreg->reg, vreg->level,
7956 vreg->level);
7957 if (rc) {
7958 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7959 __func__, vreg->reg_name, rc);
7960 goto vreg_put;
7961 }
7962 }
7963 goto out;
7964
7965vreg_put:
7966 regulator_put(vreg->reg);
7967out:
7968 return rc;
7969}
7970
7971static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7972{
7973 regulator_put(vreg->reg);
7974}
7975
7976/* this init function should be called only once for each SDCC */
7977static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7978{
7979 int rc = 0;
7980 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7981 struct sdcc_reg_data *curr;
7982
7983 curr = &sdcc_vreg_data[dev_id - 1];
7984 curr_vdd_reg = curr->vdd_data;
7985 curr_vccq_reg = curr->vccq_data;
7986 curr_vddp_reg = curr->vddp_data;
7987
7988 if (init) {
7989 /*
7990 * get the regulator handle from voltage regulator framework
7991 * and then try to set the voltage level for the regulator
7992 */
7993 if (curr_vdd_reg) {
7994 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7995 if (rc)
7996 goto out;
7997 }
7998 if (curr_vccq_reg) {
7999 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
8000 if (rc)
8001 goto vdd_reg_deinit;
8002 }
8003 if (curr_vddp_reg) {
8004 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
8005 if (rc)
8006 goto vccq_reg_deinit;
8007 }
8008 goto out;
8009 } else
8010 /* deregister with all regulators from regulator framework */
8011 goto vddp_reg_deinit;
8012
8013vddp_reg_deinit:
8014 if (curr_vddp_reg)
8015 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
8016vccq_reg_deinit:
8017 if (curr_vccq_reg)
8018 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
8019vdd_reg_deinit:
8020 if (curr_vdd_reg)
8021 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
8022out:
8023 return rc;
8024}
8025
8026static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
8027{
8028 int rc;
8029
8030 if (!vreg->enabled) {
8031 rc = regulator_enable(vreg->reg);
8032 if (rc) {
8033 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
8034 __func__, vreg->reg_name, rc);
8035 goto out;
8036 }
8037 vreg->enabled = 1;
8038 }
8039
8040 /* Put always_on regulator in HPM (high power mode) */
8041 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8042 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
8043 if (rc < 0) {
8044 pr_err("%s: reg=%s: HPM setting failed"
8045 " hpm_uA=%d, rc=%d\n",
8046 __func__, vreg->reg_name,
8047 vreg->hpm_uA, rc);
8048 goto vreg_disable;
8049 }
8050 rc = 0;
8051 }
8052 goto out;
8053
8054vreg_disable:
8055 regulator_disable(vreg->reg);
8056 vreg->enabled = 0;
8057out:
8058 return rc;
8059}
8060
8061static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
8062{
8063 int rc;
8064
8065 /* Never disable always_on regulator */
8066 if (!vreg->always_on) {
8067 rc = regulator_disable(vreg->reg);
8068 if (rc) {
8069 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
8070 __func__, vreg->reg_name, rc);
8071 goto out;
8072 }
8073 vreg->enabled = 0;
8074 }
8075
8076 /* Put always_on regulator in LPM (low power mode) */
8077 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8078 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
8079 if (rc < 0) {
8080 pr_err("%s: reg=%s: LPM setting failed"
8081 " lpm_uA=%d, rc=%d\n",
8082 __func__,
8083 vreg->reg_name,
8084 vreg->lpm_uA, rc);
8085 goto out;
8086 }
8087 rc = 0;
8088 }
8089
8090out:
8091 return rc;
8092}
8093
8094static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
8095{
8096 int rc = 0;
8097 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
8098 struct sdcc_reg_data *curr;
8099
8100 curr = &sdcc_vreg_data[dev_id - 1];
8101 curr_vdd_reg = curr->vdd_data;
8102 curr_vccq_reg = curr->vccq_data;
8103 curr_vddp_reg = curr->vddp_data;
8104
8105 /* check if regulators are initialized or not? */
8106 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
8107 (curr_vccq_reg && !curr_vccq_reg->reg) ||
8108 (curr_vddp_reg && !curr_vddp_reg->reg)) {
8109 /* initialize voltage regulators required for this SDCC */
8110 rc = msm_sdcc_vreg_init(dev_id, 1);
8111 if (rc) {
8112 pr_err("%s: regulator init failed = %d\n",
8113 __func__, rc);
8114 goto out;
8115 }
8116 }
8117
8118 if (curr->sts == enable)
8119 goto out;
8120
8121 if (curr_vdd_reg) {
8122 if (enable)
8123 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
8124 else
8125 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
8126 if (rc)
8127 goto out;
8128 }
8129
8130 if (curr_vccq_reg) {
8131 if (enable)
8132 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
8133 else
8134 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
8135 if (rc)
8136 goto out;
8137 }
8138
8139 if (curr_vddp_reg) {
8140 if (enable)
8141 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
8142 else
8143 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
8144 if (rc)
8145 goto out;
8146 }
8147 curr->sts = enable;
8148
8149out:
8150 return rc;
8151}
8152
8153static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
8154{
8155 u32 rc_pin_cfg = 0;
8156 u32 rc_vreg_cfg = 0;
8157 u32 rc = 0;
8158 struct platform_device *pdev;
8159 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8160
8161 pdev = container_of(dv, struct platform_device, dev);
8162
8163 /* setup gpio/pad */
8164 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8165 if (curr_pin_cfg->cfg_sts == !!vdd)
8166 goto setup_vreg;
8167
8168 if (curr_pin_cfg->is_gpio)
8169 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
8170 else
8171 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
8172
8173setup_vreg:
8174 /* setup voltage regulators */
8175 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
8176
8177 if (rc_pin_cfg || rc_vreg_cfg)
8178 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
8179
8180 return rc;
8181}
8182
8183static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
8184{
8185 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8186 struct platform_device *pdev;
8187
8188 pdev = container_of(dv, struct platform_device, dev);
8189 /* setup gpio/pad */
8190 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8191
8192 if (curr_pin_cfg->cfg_sts == active)
8193 return;
8194
8195 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
8196 if (curr_pin_cfg->is_gpio)
8197 msm_sdcc_setup_gpio(pdev->id, active);
8198 else
8199 msm_sdcc_setup_pad(pdev->id, active);
8200 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8201}
8202
8203static int msm_sdc3_get_wpswitch(struct device *dev)
8204{
8205 struct platform_device *pdev;
8206 int status;
8207 pdev = container_of(dev, struct platform_device, dev);
8208
8209 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8210 if (status) {
8211 pr_err("%s:Failed to request GPIO %d\n",
8212 __func__, GPIO_SDC_WP);
8213 } else {
8214 status = gpio_direction_input(GPIO_SDC_WP);
8215 if (!status) {
8216 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8217 pr_info("%s: WP Status for Slot %d = %d\n",
8218 __func__, pdev->id, status);
8219 }
8220 gpio_free(GPIO_SDC_WP);
8221 }
8222 return status;
8223}
8224
8225#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8226int sdc5_register_status_notify(void (*callback)(int, void *),
8227 void *dev_id)
8228{
8229 sdc5_status_notify_cb = callback;
8230 sdc5_status_notify_cb_devid = dev_id;
8231 return 0;
8232}
8233#endif
8234
8235#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8236int sdc2_register_status_notify(void (*callback)(int, void *),
8237 void *dev_id)
8238{
8239 sdc2_status_notify_cb = callback;
8240 sdc2_status_notify_cb_devid = dev_id;
8241 return 0;
8242}
8243#endif
8244
8245/* Interrupt handler for SDC2 and SDC5 detection
8246 * This function uses dual-edge interrputs settings in order
8247 * to get SDIO detection when the GPIO is rising and SDIO removal
8248 * when the GPIO is falling */
8249static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8250{
8251 int status;
8252
8253 if (!machine_is_msm8x60_fusion() &&
8254 !machine_is_msm8x60_fusn_ffa())
8255 return IRQ_NONE;
8256
8257 status = gpio_get_value(MDM2AP_SYNC);
8258 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8259 __func__, status);
8260
8261#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8262 if (sdc2_status_notify_cb) {
8263 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8264 sdc2_status_notify_cb(status,
8265 sdc2_status_notify_cb_devid);
8266 }
8267#endif
8268
8269#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8270 if (sdc5_status_notify_cb) {
8271 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8272 sdc5_status_notify_cb(status,
8273 sdc5_status_notify_cb_devid);
8274 }
8275#endif
8276 return IRQ_HANDLED;
8277}
8278
8279static int msm8x60_multi_sdio_init(void)
8280{
8281 int ret, irq_num;
8282
8283 if (!machine_is_msm8x60_fusion() &&
8284 !machine_is_msm8x60_fusn_ffa())
8285 return 0;
8286
8287 ret = msm_gpiomux_get(MDM2AP_SYNC);
8288 if (ret) {
8289 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8290 __func__, MDM2AP_SYNC, ret);
8291 return ret;
8292 }
8293
8294 irq_num = gpio_to_irq(MDM2AP_SYNC);
8295
8296 ret = request_irq(irq_num,
8297 msm8x60_multi_sdio_slot_status_irq,
8298 IRQ_TYPE_EDGE_BOTH,
8299 "sdio_multidetection", NULL);
8300
8301 if (ret) {
8302 pr_err("%s:Failed to request irq, ret=%d\n",
8303 __func__, ret);
8304 return ret;
8305 }
8306
8307 return ret;
8308}
8309
8310#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8311#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8312static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8313{
8314 int status;
8315
8316 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8317 , "SD_HW_Detect");
8318 if (status) {
8319 pr_err("%s:Failed to request GPIO %d\n", __func__,
8320 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8321 } else {
8322 status = gpio_direction_input(
8323 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8324 if (!status)
8325 status = !(gpio_get_value_cansleep(
8326 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8327 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8328 }
8329 return (unsigned int) status;
8330}
8331#endif
8332#endif
8333
8334#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8335static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8336{
8337 struct platform_device *pdev;
8338 enum msm_mpm_pin pin;
8339 int ret = 0;
8340
8341 pdev = container_of(dev, struct platform_device, dev);
8342
8343 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8344 if (pdev->id == 4)
8345 pin = MSM_MPM_PIN_SDC4_DAT1;
8346 else
8347 return -EINVAL;
8348
8349 switch (mode) {
8350 case SDC_DAT1_DISABLE:
8351 ret = msm_mpm_enable_pin(pin, 0);
8352 break;
8353 case SDC_DAT1_ENABLE:
8354 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8355 ret = msm_mpm_enable_pin(pin, 1);
8356 break;
8357 case SDC_DAT1_ENWAKE:
8358 ret = msm_mpm_set_pin_wake(pin, 1);
8359 break;
8360 case SDC_DAT1_DISWAKE:
8361 ret = msm_mpm_set_pin_wake(pin, 0);
8362 break;
8363 default:
8364 ret = -EINVAL;
8365 break;
8366 }
8367 return ret;
8368}
8369#endif
8370#endif
8371
8372#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8373static struct mmc_platform_data msm8x60_sdc1_data = {
8374 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8375 .translate_vdd = msm_sdcc_setup_power,
8376#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8377 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8378#else
8379 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8380#endif
8381 .msmsdcc_fmin = 400000,
8382 .msmsdcc_fmid = 24000000,
8383 .msmsdcc_fmax = 48000000,
8384 .nonremovable = 1,
8385 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008386};
8387#endif
8388
8389#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8390static struct mmc_platform_data msm8x60_sdc2_data = {
8391 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8392 .translate_vdd = msm_sdcc_setup_power,
8393 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8394 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8395 .msmsdcc_fmin = 400000,
8396 .msmsdcc_fmid = 24000000,
8397 .msmsdcc_fmax = 48000000,
8398 .nonremovable = 0,
8399 .pclk_src_dfab = 1,
8400 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008401#ifdef CONFIG_MSM_SDIO_AL
8402 .is_sdio_al_client = 1,
8403#endif
8404};
8405#endif
8406
8407#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8408static struct mmc_platform_data msm8x60_sdc3_data = {
8409 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8410 .translate_vdd = msm_sdcc_setup_power,
8411 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8412 .wpswitch = msm_sdc3_get_wpswitch,
8413#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8414 .status = msm8x60_sdcc_slot_status,
8415 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8416 PMIC_GPIO_SDC3_DET - 1),
8417 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8418#endif
8419 .msmsdcc_fmin = 400000,
8420 .msmsdcc_fmid = 24000000,
8421 .msmsdcc_fmax = 48000000,
8422 .nonremovable = 0,
8423 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008424};
8425#endif
8426
8427#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8428static struct mmc_platform_data msm8x60_sdc4_data = {
8429 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8430 .translate_vdd = msm_sdcc_setup_power,
8431 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8432 .msmsdcc_fmin = 400000,
8433 .msmsdcc_fmid = 24000000,
8434 .msmsdcc_fmax = 48000000,
8435 .nonremovable = 0,
8436 .pclk_src_dfab = 1,
8437 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008438};
8439#endif
8440
8441#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8442static struct mmc_platform_data msm8x60_sdc5_data = {
8443 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8444 .translate_vdd = msm_sdcc_setup_power,
8445 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8446 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8447 .msmsdcc_fmin = 400000,
8448 .msmsdcc_fmid = 24000000,
8449 .msmsdcc_fmax = 48000000,
8450 .nonremovable = 0,
8451 .pclk_src_dfab = 1,
8452 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008453#ifdef CONFIG_MSM_SDIO_AL
8454 .is_sdio_al_client = 1,
8455#endif
8456};
8457#endif
8458
8459static void __init msm8x60_init_mmc(void)
8460{
8461#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8462 /* SDCC1 : eMMC card connected */
8463 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8464 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8465 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8466 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308467 sdcc_vreg_data[0].vdd_data->always_on = 1;
8468 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8469 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8470 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008471
8472 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8473 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8474 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8475 sdcc_vreg_data[0].vccq_data->always_on = 1;
8476
8477 msm_add_sdcc(1, &msm8x60_sdc1_data);
8478#endif
8479#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8480 /*
8481 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8482 * and no card is connected on 8660 SURF/FFA/FLUID.
8483 */
8484 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8485 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8486 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8487 sdcc_vreg_data[1].vdd_data->level = 1800000;
8488
8489 sdcc_vreg_data[1].vccq_data = NULL;
8490
8491 if (machine_is_msm8x60_fusion())
8492 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8493 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8494#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8495 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8496 msm_sdcc_setup_gpio(2, 1);
8497#endif
8498 msm_add_sdcc(2, &msm8x60_sdc2_data);
8499 }
8500#endif
8501#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8502 /* SDCC3 : External card slot connected */
8503 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8504 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8505 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8506 sdcc_vreg_data[2].vdd_data->level = 2850000;
8507 sdcc_vreg_data[2].vdd_data->always_on = 1;
8508 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8509 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8510 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8511
8512 sdcc_vreg_data[2].vccq_data = NULL;
8513
8514 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8515 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8516 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8517 sdcc_vreg_data[2].vddp_data->level = 2850000;
8518 sdcc_vreg_data[2].vddp_data->always_on = 1;
8519 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8520 /* Sleep current required is ~300 uA. But min. RPM
8521 * vote can be in terms of mA (min. 1 mA).
8522 * So let's vote for 2 mA during sleep.
8523 */
8524 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8525 /* Max. Active current required is 16 mA */
8526 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8527
8528 if (machine_is_msm8x60_fluid())
8529 msm8x60_sdc3_data.wpswitch = NULL;
8530 msm_add_sdcc(3, &msm8x60_sdc3_data);
8531#endif
8532#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8533 /* SDCC4 : WLAN WCN1314 chip is connected */
8534 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8535 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8536 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8537 sdcc_vreg_data[3].vdd_data->level = 1800000;
8538
8539 sdcc_vreg_data[3].vccq_data = NULL;
8540
8541 msm_add_sdcc(4, &msm8x60_sdc4_data);
8542#endif
8543#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8544 /*
8545 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8546 * and no card is connected on 8660 SURF/FFA/FLUID.
8547 */
8548 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8549 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8550 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8551 sdcc_vreg_data[4].vdd_data->level = 1800000;
8552
8553 sdcc_vreg_data[4].vccq_data = NULL;
8554
8555 if (machine_is_msm8x60_fusion())
8556 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8557 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8558#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8559 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8560 msm_sdcc_setup_gpio(5, 1);
8561#endif
8562 msm_add_sdcc(5, &msm8x60_sdc5_data);
8563 }
8564#endif
8565}
8566
8567#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8568static inline void display_common_power(int on) {}
8569#else
8570
8571#define _GET_REGULATOR(var, name) do { \
8572 if (var == NULL) { \
8573 var = regulator_get(NULL, name); \
8574 if (IS_ERR(var)) { \
8575 pr_err("'%s' regulator not found, rc=%ld\n", \
8576 name, PTR_ERR(var)); \
8577 var = NULL; \
8578 } \
8579 } \
8580} while (0)
8581
8582static int dsub_regulator(int on)
8583{
8584 static struct regulator *dsub_reg;
8585 static struct regulator *mpp0_reg;
8586 static int dsub_reg_enabled;
8587 int rc = 0;
8588
8589 _GET_REGULATOR(dsub_reg, "8901_l3");
8590 if (IS_ERR(dsub_reg)) {
8591 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8592 __func__, PTR_ERR(dsub_reg));
8593 return PTR_ERR(dsub_reg);
8594 }
8595
8596 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8597 if (IS_ERR(mpp0_reg)) {
8598 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8599 __func__, PTR_ERR(mpp0_reg));
8600 return PTR_ERR(mpp0_reg);
8601 }
8602
8603 if (on && !dsub_reg_enabled) {
8604 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8605 if (rc) {
8606 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8607 " err=%d", __func__, rc);
8608 goto dsub_regulator_err;
8609 }
8610 rc = regulator_enable(dsub_reg);
8611 if (rc) {
8612 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8613 " err=%d", __func__, rc);
8614 goto dsub_regulator_err;
8615 }
8616 rc = regulator_enable(mpp0_reg);
8617 if (rc) {
8618 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8619 " err=%d", __func__, rc);
8620 goto dsub_regulator_err;
8621 }
8622 dsub_reg_enabled = 1;
8623 } else if (!on && dsub_reg_enabled) {
8624 rc = regulator_disable(dsub_reg);
8625 if (rc)
8626 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8627 " err=%d", __func__, rc);
8628 rc = regulator_disable(mpp0_reg);
8629 if (rc)
8630 printk(KERN_WARNING "%s: failed to disable reg "
8631 "8901_mpp0 err=%d", __func__, rc);
8632 dsub_reg_enabled = 0;
8633 }
8634
8635 return rc;
8636
8637dsub_regulator_err:
8638 regulator_put(mpp0_reg);
8639 regulator_put(dsub_reg);
8640 return rc;
8641}
8642
8643static int display_power_on;
8644static void setup_display_power(void)
8645{
8646 if (display_power_on)
8647 if (lcdc_vga_enabled) {
8648 dsub_regulator(1);
8649 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8650 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8651 if (machine_is_msm8x60_ffa() ||
8652 machine_is_msm8x60_fusn_ffa())
8653 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8654 } else {
8655 dsub_regulator(0);
8656 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8657 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8658 if (machine_is_msm8x60_ffa() ||
8659 machine_is_msm8x60_fusn_ffa())
8660 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8661 }
8662 else {
8663 dsub_regulator(0);
8664 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8665 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8666 /* BACKLIGHT */
8667 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8668 /* LVDS */
8669 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8670 }
8671}
8672
8673#define _GET_REGULATOR(var, name) do { \
8674 if (var == NULL) { \
8675 var = regulator_get(NULL, name); \
8676 if (IS_ERR(var)) { \
8677 pr_err("'%s' regulator not found, rc=%ld\n", \
8678 name, PTR_ERR(var)); \
8679 var = NULL; \
8680 } \
8681 } \
8682} while (0)
8683
8684#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8685
8686static void display_common_power(int on)
8687{
8688 int rc;
8689 static struct regulator *display_reg;
8690
8691 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8692 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8693 if (on) {
8694 /* LVDS */
8695 _GET_REGULATOR(display_reg, "8901_l2");
8696 if (!display_reg)
8697 return;
8698 rc = regulator_set_voltage(display_reg,
8699 3300000, 3300000);
8700 if (rc)
8701 goto out;
8702 rc = regulator_enable(display_reg);
8703 if (rc)
8704 goto out;
8705 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8706 "LVDS_STDN_OUT_N");
8707 if (rc) {
8708 printk(KERN_ERR "%s: LVDS gpio %d request"
8709 "failed\n", __func__,
8710 GPIO_LVDS_SHUTDOWN_N);
8711 goto out2;
8712 }
8713
8714 /* BACKLIGHT */
8715 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8716 if (rc) {
8717 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8718 "failed\n", __func__,
8719 GPIO_BACKLIGHT_EN);
8720 goto out3;
8721 }
8722
8723 if (machine_is_msm8x60_ffa() ||
8724 machine_is_msm8x60_fusn_ffa()) {
8725 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8726 "DONGLE_PWR_EN");
8727 if (rc) {
8728 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8729 " %d request failed\n", __func__,
8730 GPIO_DONGLE_PWR_EN);
8731 goto out4;
8732 }
8733 }
8734
8735 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8736 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8737 if (machine_is_msm8x60_ffa() ||
8738 machine_is_msm8x60_fusn_ffa())
8739 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8740 mdelay(20);
8741 display_power_on = 1;
8742 setup_display_power();
8743 } else {
8744 if (display_power_on) {
8745 display_power_on = 0;
8746 setup_display_power();
8747 mdelay(20);
8748 if (machine_is_msm8x60_ffa() ||
8749 machine_is_msm8x60_fusn_ffa())
8750 gpio_free(GPIO_DONGLE_PWR_EN);
8751 goto out4;
8752 }
8753 }
8754 }
8755#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8756 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8757 else if (machine_is_msm8x60_fluid()) {
8758 static struct regulator *fluid_reg;
8759 static struct regulator *fluid_reg2;
8760
8761 if (on) {
8762 _GET_REGULATOR(fluid_reg, "8901_l2");
8763 if (!fluid_reg)
8764 return;
8765 _GET_REGULATOR(fluid_reg2, "8058_s3");
8766 if (!fluid_reg2) {
8767 regulator_put(fluid_reg);
8768 return;
8769 }
8770 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8771 if (rc) {
8772 regulator_put(fluid_reg2);
8773 regulator_put(fluid_reg);
8774 return;
8775 }
8776 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8777 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8778 regulator_enable(fluid_reg);
8779 regulator_enable(fluid_reg2);
8780 msleep(20);
8781 gpio_direction_output(GPIO_RESX_N, 0);
8782 udelay(10);
8783 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8784 display_power_on = 1;
8785 setup_display_power();
8786 } else {
8787 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8788 gpio_free(GPIO_RESX_N);
8789 msleep(20);
8790 regulator_disable(fluid_reg2);
8791 regulator_disable(fluid_reg);
8792 regulator_put(fluid_reg2);
8793 regulator_put(fluid_reg);
8794 display_power_on = 0;
8795 setup_display_power();
8796 fluid_reg = NULL;
8797 fluid_reg2 = NULL;
8798 }
8799 }
8800#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008801#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8802 else if (machine_is_msm8x60_dragon()) {
8803 static struct regulator *dragon_reg;
8804 static struct regulator *dragon_reg2;
8805
8806 if (on) {
8807 _GET_REGULATOR(dragon_reg, "8901_l2");
8808 if (!dragon_reg)
8809 return;
8810 _GET_REGULATOR(dragon_reg2, "8058_l16");
8811 if (!dragon_reg2) {
8812 regulator_put(dragon_reg);
8813 dragon_reg = NULL;
8814 return;
8815 }
8816
8817 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8818 if (rc) {
8819 pr_err("%s: gpio %d request failed with rc=%d\n",
8820 __func__, GPIO_NT35582_BL_EN, rc);
8821 regulator_put(dragon_reg);
8822 regulator_put(dragon_reg2);
8823 dragon_reg = NULL;
8824 dragon_reg2 = NULL;
8825 return;
8826 }
8827
8828 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8829 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8830 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8831 pr_err("%s: config gpio '%d' failed!\n",
8832 __func__, GPIO_NT35582_RESET);
8833 gpio_free(GPIO_NT35582_BL_EN);
8834 regulator_put(dragon_reg);
8835 regulator_put(dragon_reg2);
8836 dragon_reg = NULL;
8837 dragon_reg2 = NULL;
8838 return;
8839 }
8840
8841 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8842 if (rc) {
8843 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8844 __func__, GPIO_NT35582_RESET, rc);
8845 gpio_free(GPIO_NT35582_BL_EN);
8846 regulator_put(dragon_reg);
8847 regulator_put(dragon_reg2);
8848 dragon_reg = NULL;
8849 dragon_reg2 = NULL;
8850 return;
8851 }
8852
8853 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8854 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8855 regulator_enable(dragon_reg);
8856 regulator_enable(dragon_reg2);
8857 msleep(20);
8858
8859 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8860 msleep(20);
8861 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8862 msleep(20);
8863 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8864 msleep(50);
8865
8866 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8867
8868 display_power_on = 1;
8869 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8870 gpio_free(GPIO_NT35582_RESET);
8871 gpio_free(GPIO_NT35582_BL_EN);
8872 regulator_disable(dragon_reg2);
8873 regulator_disable(dragon_reg);
8874 regulator_put(dragon_reg2);
8875 regulator_put(dragon_reg);
8876 display_power_on = 0;
8877 dragon_reg = NULL;
8878 dragon_reg2 = NULL;
8879 }
8880 }
8881#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008882 return;
8883
8884out4:
8885 gpio_free(GPIO_BACKLIGHT_EN);
8886out3:
8887 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8888out2:
8889 regulator_disable(display_reg);
8890out:
8891 regulator_put(display_reg);
8892 display_reg = NULL;
8893}
8894#undef _GET_REGULATOR
8895#endif
8896
8897static int mipi_dsi_panel_power(int on);
8898
8899#define LCDC_NUM_GPIO 28
8900#define LCDC_GPIO_START 0
8901
8902static void lcdc_samsung_panel_power(int on)
8903{
8904 int n, ret = 0;
8905
8906 display_common_power(on);
8907
8908 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8909 if (on) {
8910 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8911 if (unlikely(ret)) {
8912 pr_err("%s not able to get gpio\n", __func__);
8913 break;
8914 }
8915 } else
8916 gpio_free(LCDC_GPIO_START + n);
8917 }
8918
8919 if (ret) {
8920 for (n--; n >= 0; n--)
8921 gpio_free(LCDC_GPIO_START + n);
8922 }
8923
8924 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8925}
8926
8927#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8928#define _GET_REGULATOR(var, name) do { \
8929 var = regulator_get(NULL, name); \
8930 if (IS_ERR(var)) { \
8931 pr_err("'%s' regulator not found, rc=%ld\n", \
8932 name, IS_ERR(var)); \
8933 var = NULL; \
8934 return -ENODEV; \
8935 } \
8936} while (0)
8937
8938static int hdmi_enable_5v(int on)
8939{
8940 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8941 static struct regulator *reg_8901_mpp0; /* External 5V */
8942 static int prev_on;
8943 int rc;
8944
8945 if (on == prev_on)
8946 return 0;
8947
8948 if (!reg_8901_hdmi_mvs)
8949 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8950 if (!reg_8901_mpp0)
8951 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8952
8953 if (on) {
8954 rc = regulator_enable(reg_8901_mpp0);
8955 if (rc) {
8956 pr_err("'%s' regulator enable failed, rc=%d\n",
8957 "reg_8901_mpp0", rc);
8958 return rc;
8959 }
8960 rc = regulator_enable(reg_8901_hdmi_mvs);
8961 if (rc) {
8962 pr_err("'%s' regulator enable failed, rc=%d\n",
8963 "8901_hdmi_mvs", rc);
8964 return rc;
8965 }
8966 pr_info("%s(on): success\n", __func__);
8967 } else {
8968 rc = regulator_disable(reg_8901_hdmi_mvs);
8969 if (rc)
8970 pr_warning("'%s' regulator disable failed, rc=%d\n",
8971 "8901_hdmi_mvs", rc);
8972 rc = regulator_disable(reg_8901_mpp0);
8973 if (rc)
8974 pr_warning("'%s' regulator disable failed, rc=%d\n",
8975 "reg_8901_mpp0", rc);
8976 pr_info("%s(off): success\n", __func__);
8977 }
8978
8979 prev_on = on;
8980
8981 return 0;
8982}
8983
8984static int hdmi_core_power(int on, int show)
8985{
8986 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8987 static int prev_on;
8988 int rc;
8989
8990 if (on == prev_on)
8991 return 0;
8992
8993 if (!reg_8058_l16)
8994 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8995
8996 if (on) {
8997 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8998 if (!rc)
8999 rc = regulator_enable(reg_8058_l16);
9000 if (rc) {
9001 pr_err("'%s' regulator enable failed, rc=%d\n",
9002 "8058_l16", rc);
9003 return rc;
9004 }
9005 rc = gpio_request(170, "HDMI_DDC_CLK");
9006 if (rc) {
9007 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9008 "HDMI_DDC_CLK", 170, rc);
9009 goto error1;
9010 }
9011 rc = gpio_request(171, "HDMI_DDC_DATA");
9012 if (rc) {
9013 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9014 "HDMI_DDC_DATA", 171, rc);
9015 goto error2;
9016 }
9017 rc = gpio_request(172, "HDMI_HPD");
9018 if (rc) {
9019 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9020 "HDMI_HPD", 172, rc);
9021 goto error3;
9022 }
9023 pr_info("%s(on): success\n", __func__);
9024 } else {
9025 gpio_free(170);
9026 gpio_free(171);
9027 gpio_free(172);
9028 rc = regulator_disable(reg_8058_l16);
9029 if (rc)
9030 pr_warning("'%s' regulator disable failed, rc=%d\n",
9031 "8058_l16", rc);
9032 pr_info("%s(off): success\n", __func__);
9033 }
9034
9035 prev_on = on;
9036
9037 return 0;
9038
9039error3:
9040 gpio_free(171);
9041error2:
9042 gpio_free(170);
9043error1:
9044 regulator_disable(reg_8058_l16);
9045 return rc;
9046}
9047
9048static int hdmi_cec_power(int on)
9049{
9050 static struct regulator *reg_8901_l3; /* HDMI_CEC */
9051 static int prev_on;
9052 int rc;
9053
9054 if (on == prev_on)
9055 return 0;
9056
9057 if (!reg_8901_l3)
9058 _GET_REGULATOR(reg_8901_l3, "8901_l3");
9059
9060 if (on) {
9061 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
9062 if (!rc)
9063 rc = regulator_enable(reg_8901_l3);
9064 if (rc) {
9065 pr_err("'%s' regulator enable failed, rc=%d\n",
9066 "8901_l3", rc);
9067 return rc;
9068 }
9069 rc = gpio_request(169, "HDMI_CEC_VAR");
9070 if (rc) {
9071 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9072 "HDMI_CEC_VAR", 169, rc);
9073 goto error;
9074 }
9075 pr_info("%s(on): success\n", __func__);
9076 } else {
9077 gpio_free(169);
9078 rc = regulator_disable(reg_8901_l3);
9079 if (rc)
9080 pr_warning("'%s' regulator disable failed, rc=%d\n",
9081 "8901_l3", rc);
9082 pr_info("%s(off): success\n", __func__);
9083 }
9084
9085 prev_on = on;
9086
9087 return 0;
9088error:
9089 regulator_disable(reg_8901_l3);
9090 return rc;
9091}
9092
9093#undef _GET_REGULATOR
9094
9095#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
9096
9097static int lcdc_panel_power(int on)
9098{
9099 int flag_on = !!on;
9100 static int lcdc_power_save_on;
9101
9102 if (lcdc_power_save_on == flag_on)
9103 return 0;
9104
9105 lcdc_power_save_on = flag_on;
9106
9107 lcdc_samsung_panel_power(on);
9108
9109 return 0;
9110}
9111
9112#ifdef CONFIG_MSM_BUS_SCALING
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009113static struct msm_bus_vectors mdp_init_vectors[] = {
9114 /* For now, 0th array entry is reserved.
9115 * Please leave 0 as is and don't use it
9116 */
9117 {
9118 .src = MSM_BUS_MASTER_MDP_PORT0,
9119 .dst = MSM_BUS_SLAVE_SMI,
9120 .ab = 0,
9121 .ib = 0,
9122 },
9123 /* Master and slaves can be from different fabrics */
9124 {
9125 .src = MSM_BUS_MASTER_MDP_PORT0,
9126 .dst = MSM_BUS_SLAVE_EBI_CH0,
9127 .ab = 0,
9128 .ib = 0,
9129 },
9130};
9131
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009132#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9133static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
9134 /* If HDMI is used as primary */
9135 {
9136 .src = MSM_BUS_MASTER_MDP_PORT0,
9137 .dst = MSM_BUS_SLAVE_SMI,
9138 .ab = 2000000000,
9139 .ib = 2000000000,
9140 },
9141 /* Master and slaves can be from different fabrics */
9142 {
9143 .src = MSM_BUS_MASTER_MDP_PORT0,
9144 .dst = MSM_BUS_SLAVE_EBI_CH0,
9145 .ab = 2000000000,
9146 .ib = 2000000000,
9147 },
9148};
9149
9150static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9151 {
9152 ARRAY_SIZE(mdp_init_vectors),
9153 mdp_init_vectors,
9154 },
9155 {
9156 ARRAY_SIZE(hdmi_as_primary_vectors),
9157 hdmi_as_primary_vectors,
9158 },
9159 {
9160 ARRAY_SIZE(hdmi_as_primary_vectors),
9161 hdmi_as_primary_vectors,
9162 },
9163 {
9164 ARRAY_SIZE(hdmi_as_primary_vectors),
9165 hdmi_as_primary_vectors,
9166 },
9167 {
9168 ARRAY_SIZE(hdmi_as_primary_vectors),
9169 hdmi_as_primary_vectors,
9170 },
9171 {
9172 ARRAY_SIZE(hdmi_as_primary_vectors),
9173 hdmi_as_primary_vectors,
9174 },
9175};
9176#else
9177#ifdef CONFIG_FB_MSM_LCDC_DSUB
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009178static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9179 /* Default case static display/UI/2d/3d if FB SMI */
9180 {
9181 .src = MSM_BUS_MASTER_MDP_PORT0,
9182 .dst = MSM_BUS_SLAVE_SMI,
9183 .ab = 388800000,
9184 .ib = 486000000,
9185 },
9186 /* Master and slaves can be from different fabrics */
9187 {
9188 .src = MSM_BUS_MASTER_MDP_PORT0,
9189 .dst = MSM_BUS_SLAVE_EBI_CH0,
9190 .ab = 0,
9191 .ib = 0,
9192 },
9193};
9194
9195static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9196 /* Default case static display/UI/2d/3d if FB SMI */
9197 {
9198 .src = MSM_BUS_MASTER_MDP_PORT0,
9199 .dst = MSM_BUS_SLAVE_SMI,
9200 .ab = 0,
9201 .ib = 0,
9202 },
9203 /* Master and slaves can be from different fabrics */
9204 {
9205 .src = MSM_BUS_MASTER_MDP_PORT0,
9206 .dst = MSM_BUS_SLAVE_EBI_CH0,
9207 .ab = 388800000,
9208 .ib = 486000000 * 2,
9209 },
9210};
9211static struct msm_bus_vectors mdp_vga_vectors[] = {
9212 /* VGA and less video */
9213 {
9214 .src = MSM_BUS_MASTER_MDP_PORT0,
9215 .dst = MSM_BUS_SLAVE_SMI,
9216 .ab = 458092800,
9217 .ib = 572616000,
9218 },
9219 {
9220 .src = MSM_BUS_MASTER_MDP_PORT0,
9221 .dst = MSM_BUS_SLAVE_EBI_CH0,
9222 .ab = 458092800,
9223 .ib = 572616000 * 2,
9224 },
9225};
9226static struct msm_bus_vectors mdp_720p_vectors[] = {
9227 /* 720p and less video */
9228 {
9229 .src = MSM_BUS_MASTER_MDP_PORT0,
9230 .dst = MSM_BUS_SLAVE_SMI,
9231 .ab = 471744000,
9232 .ib = 589680000,
9233 },
9234 /* Master and slaves can be from different fabrics */
9235 {
9236 .src = MSM_BUS_MASTER_MDP_PORT0,
9237 .dst = MSM_BUS_SLAVE_EBI_CH0,
9238 .ab = 471744000,
9239 .ib = 589680000 * 2,
9240 },
9241};
9242
9243static struct msm_bus_vectors mdp_1080p_vectors[] = {
9244 /* 1080p and less video */
9245 {
9246 .src = MSM_BUS_MASTER_MDP_PORT0,
9247 .dst = MSM_BUS_SLAVE_SMI,
9248 .ab = 575424000,
9249 .ib = 719280000,
9250 },
9251 /* Master and slaves can be from different fabrics */
9252 {
9253 .src = MSM_BUS_MASTER_MDP_PORT0,
9254 .dst = MSM_BUS_SLAVE_EBI_CH0,
9255 .ab = 575424000,
9256 .ib = 719280000 * 2,
9257 },
9258};
9259
9260#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009261static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9262 /* Default case static display/UI/2d/3d if FB SMI */
9263 {
9264 .src = MSM_BUS_MASTER_MDP_PORT0,
9265 .dst = MSM_BUS_SLAVE_SMI,
9266 .ab = 175110000,
9267 .ib = 218887500,
9268 },
9269 /* Master and slaves can be from different fabrics */
9270 {
9271 .src = MSM_BUS_MASTER_MDP_PORT0,
9272 .dst = MSM_BUS_SLAVE_EBI_CH0,
9273 .ab = 0,
9274 .ib = 0,
9275 },
9276};
9277
9278static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9279 /* Default case static display/UI/2d/3d if FB SMI */
9280 {
9281 .src = MSM_BUS_MASTER_MDP_PORT0,
9282 .dst = MSM_BUS_SLAVE_SMI,
9283 .ab = 0,
9284 .ib = 0,
9285 },
9286 /* Master and slaves can be from different fabrics */
9287 {
9288 .src = MSM_BUS_MASTER_MDP_PORT0,
9289 .dst = MSM_BUS_SLAVE_EBI_CH0,
9290 .ab = 216000000,
9291 .ib = 270000000 * 2,
9292 },
9293};
9294static struct msm_bus_vectors mdp_vga_vectors[] = {
9295 /* VGA and less video */
9296 {
9297 .src = MSM_BUS_MASTER_MDP_PORT0,
9298 .dst = MSM_BUS_SLAVE_SMI,
9299 .ab = 216000000,
9300 .ib = 270000000,
9301 },
9302 {
9303 .src = MSM_BUS_MASTER_MDP_PORT0,
9304 .dst = MSM_BUS_SLAVE_EBI_CH0,
9305 .ab = 216000000,
9306 .ib = 270000000 * 2,
9307 },
9308};
9309
9310static struct msm_bus_vectors mdp_720p_vectors[] = {
9311 /* 720p and less video */
9312 {
9313 .src = MSM_BUS_MASTER_MDP_PORT0,
9314 .dst = MSM_BUS_SLAVE_SMI,
9315 .ab = 230400000,
9316 .ib = 288000000,
9317 },
9318 /* Master and slaves can be from different fabrics */
9319 {
9320 .src = MSM_BUS_MASTER_MDP_PORT0,
9321 .dst = MSM_BUS_SLAVE_EBI_CH0,
9322 .ab = 230400000,
9323 .ib = 288000000 * 2,
9324 },
9325};
9326
9327static struct msm_bus_vectors mdp_1080p_vectors[] = {
9328 /* 1080p and less video */
9329 {
9330 .src = MSM_BUS_MASTER_MDP_PORT0,
9331 .dst = MSM_BUS_SLAVE_SMI,
9332 .ab = 334080000,
9333 .ib = 417600000,
9334 },
9335 /* Master and slaves can be from different fabrics */
9336 {
9337 .src = MSM_BUS_MASTER_MDP_PORT0,
9338 .dst = MSM_BUS_SLAVE_EBI_CH0,
9339 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009340 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009341 },
9342};
9343
9344#endif
9345static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9346 {
9347 ARRAY_SIZE(mdp_init_vectors),
9348 mdp_init_vectors,
9349 },
9350 {
9351 ARRAY_SIZE(mdp_sd_smi_vectors),
9352 mdp_sd_smi_vectors,
9353 },
9354 {
9355 ARRAY_SIZE(mdp_sd_ebi_vectors),
9356 mdp_sd_ebi_vectors,
9357 },
9358 {
9359 ARRAY_SIZE(mdp_vga_vectors),
9360 mdp_vga_vectors,
9361 },
9362 {
9363 ARRAY_SIZE(mdp_720p_vectors),
9364 mdp_720p_vectors,
9365 },
9366 {
9367 ARRAY_SIZE(mdp_1080p_vectors),
9368 mdp_1080p_vectors,
9369 },
9370};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009371#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009372static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9373 mdp_bus_scale_usecases,
9374 ARRAY_SIZE(mdp_bus_scale_usecases),
9375 .name = "mdp",
9376};
9377
9378#endif
9379#ifdef CONFIG_MSM_BUS_SCALING
9380static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9381 /* For now, 0th array entry is reserved.
9382 * Please leave 0 as is and don't use it
9383 */
9384 {
9385 .src = MSM_BUS_MASTER_MDP_PORT0,
9386 .dst = MSM_BUS_SLAVE_SMI,
9387 .ab = 0,
9388 .ib = 0,
9389 },
9390 /* Master and slaves can be from different fabrics */
9391 {
9392 .src = MSM_BUS_MASTER_MDP_PORT0,
9393 .dst = MSM_BUS_SLAVE_EBI_CH0,
9394 .ab = 0,
9395 .ib = 0,
9396 },
9397};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009398#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9399static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9400 /* For now, 0th array entry is reserved.
9401 * Please leave 0 as is and don't use it
9402 */
9403 {
9404 .src = MSM_BUS_MASTER_MDP_PORT0,
9405 .dst = MSM_BUS_SLAVE_SMI,
9406 .ab = 2000000000,
9407 .ib = 2000000000,
9408 },
9409 /* Master and slaves can be from different fabrics */
9410 {
9411 .src = MSM_BUS_MASTER_MDP_PORT0,
9412 .dst = MSM_BUS_SLAVE_EBI_CH0,
9413 .ab = 2000000000,
9414 .ib = 2000000000,
9415 },
9416};
9417#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009418static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9419 /* For now, 0th array entry is reserved.
9420 * Please leave 0 as is and don't use it
9421 */
9422 {
9423 .src = MSM_BUS_MASTER_MDP_PORT0,
9424 .dst = MSM_BUS_SLAVE_SMI,
9425 .ab = 566092800,
9426 .ib = 707616000,
9427 },
9428 /* Master and slaves can be from different fabrics */
9429 {
9430 .src = MSM_BUS_MASTER_MDP_PORT0,
9431 .dst = MSM_BUS_SLAVE_EBI_CH0,
9432 .ab = 566092800,
9433 .ib = 707616000,
9434 },
9435};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009436#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009437static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9438 {
9439 ARRAY_SIZE(dtv_bus_init_vectors),
9440 dtv_bus_init_vectors,
9441 },
9442 {
9443 ARRAY_SIZE(dtv_bus_def_vectors),
9444 dtv_bus_def_vectors,
9445 },
9446};
9447static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9448 dtv_bus_scale_usecases,
9449 ARRAY_SIZE(dtv_bus_scale_usecases),
9450 .name = "dtv",
9451};
9452
9453static struct lcdc_platform_data dtv_pdata = {
9454 .bus_scale_table = &dtv_bus_scale_pdata,
9455};
9456#endif
9457
9458
9459static struct lcdc_platform_data lcdc_pdata = {
9460 .lcdc_power_save = lcdc_panel_power,
9461};
9462
9463
9464#define MDP_VSYNC_GPIO 28
9465
9466/*
9467 * MIPI_DSI only use 8058_LDO0 which need always on
9468 * therefore it need to be put at low power mode if
9469 * it was not used instead of turn it off.
9470 */
9471static int mipi_dsi_panel_power(int on)
9472{
9473 int flag_on = !!on;
9474 static int mipi_dsi_power_save_on;
9475 static struct regulator *ldo0;
9476 int rc = 0;
9477
9478 if (mipi_dsi_power_save_on == flag_on)
9479 return 0;
9480
9481 mipi_dsi_power_save_on = flag_on;
9482
9483 if (ldo0 == NULL) { /* init */
9484 ldo0 = regulator_get(NULL, "8058_l0");
9485 if (IS_ERR(ldo0)) {
9486 pr_debug("%s: LDO0 failed\n", __func__);
9487 rc = PTR_ERR(ldo0);
9488 return rc;
9489 }
9490
9491 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9492 if (rc)
9493 goto out;
9494
9495 rc = regulator_enable(ldo0);
9496 if (rc)
9497 goto out;
9498 }
9499
9500 if (on) {
9501 /* set ldo0 to HPM */
9502 rc = regulator_set_optimum_mode(ldo0, 100000);
9503 if (rc < 0)
9504 goto out;
9505 } else {
9506 /* set ldo0 to LPM */
9507 rc = regulator_set_optimum_mode(ldo0, 9000);
9508 if (rc < 0)
9509 goto out;
9510 }
9511
9512 return 0;
9513out:
9514 regulator_disable(ldo0);
9515 regulator_put(ldo0);
9516 ldo0 = NULL;
9517 return rc;
9518}
9519
9520static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9521 .vsync_gpio = MDP_VSYNC_GPIO,
9522 .dsi_power_save = mipi_dsi_panel_power,
9523};
9524
9525#ifdef CONFIG_FB_MSM_TVOUT
9526static struct regulator *reg_8058_l13;
9527
9528static int atv_dac_power(int on)
9529{
9530 int rc = 0;
9531 #define _GET_REGULATOR(var, name) do { \
9532 var = regulator_get(NULL, name); \
9533 if (IS_ERR(var)) { \
9534 pr_info("'%s' regulator not found, rc=%ld\n", \
9535 name, IS_ERR(var)); \
9536 var = NULL; \
9537 return -ENODEV; \
9538 } \
9539 } while (0)
9540
9541 if (!reg_8058_l13)
9542 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9543 #undef _GET_REGULATOR
9544
9545 if (on) {
9546 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9547 if (rc) {
9548 pr_info("%s: '%s' regulator set voltage failed,\
9549 rc=%d\n", __func__, "8058_l13", rc);
9550 return rc;
9551 }
9552
9553 rc = regulator_enable(reg_8058_l13);
9554 if (rc) {
9555 pr_err("%s: '%s' regulator enable failed,\
9556 rc=%d\n", __func__, "8058_l13", rc);
9557 return rc;
9558 }
9559 } else {
9560 rc = regulator_force_disable(reg_8058_l13);
9561 if (rc)
9562 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9563 __func__, "8058_l13", rc);
9564 }
9565 return rc;
9566
9567}
9568#endif
9569
9570#ifdef CONFIG_FB_MSM_MIPI_DSI
9571int mdp_core_clk_rate_table[] = {
9572 85330000,
9573 85330000,
9574 160000000,
9575 200000000,
9576};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009577#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
9578int mdp_core_clk_rate_table[] = {
9579 200000000,
9580 200000000,
9581 200000000,
9582 200000000,
9583};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009584#else
9585int mdp_core_clk_rate_table[] = {
9586 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009587 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009588 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009589 200000000,
9590};
9591#endif
9592
9593static struct msm_panel_common_pdata mdp_pdata = {
9594 .gpio = MDP_VSYNC_GPIO,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009595#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9596 .mdp_core_clk_rate = 200000000,
9597#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009598 .mdp_core_clk_rate = 59080000,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009599#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009600 .mdp_core_clk_table = mdp_core_clk_rate_table,
9601 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9602#ifdef CONFIG_MSM_BUS_SCALING
9603 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9604#endif
9605 .mdp_rev = MDP_REV_41,
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07009606 .writeback_offset = writeback_offset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009607};
9608
9609#ifdef CONFIG_FB_MSM_TVOUT
9610
9611#ifdef CONFIG_MSM_BUS_SCALING
9612static struct msm_bus_vectors atv_bus_init_vectors[] = {
9613 /* For now, 0th array entry is reserved.
9614 * Please leave 0 as is and don't use it
9615 */
9616 {
9617 .src = MSM_BUS_MASTER_MDP_PORT0,
9618 .dst = MSM_BUS_SLAVE_SMI,
9619 .ab = 0,
9620 .ib = 0,
9621 },
9622 /* Master and slaves can be from different fabrics */
9623 {
9624 .src = MSM_BUS_MASTER_MDP_PORT0,
9625 .dst = MSM_BUS_SLAVE_EBI_CH0,
9626 .ab = 0,
9627 .ib = 0,
9628 },
9629};
9630static struct msm_bus_vectors atv_bus_def_vectors[] = {
9631 /* For now, 0th array entry is reserved.
9632 * Please leave 0 as is and don't use it
9633 */
9634 {
9635 .src = MSM_BUS_MASTER_MDP_PORT0,
9636 .dst = MSM_BUS_SLAVE_SMI,
9637 .ab = 236390400,
9638 .ib = 265939200,
9639 },
9640 /* Master and slaves can be from different fabrics */
9641 {
9642 .src = MSM_BUS_MASTER_MDP_PORT0,
9643 .dst = MSM_BUS_SLAVE_EBI_CH0,
9644 .ab = 236390400,
9645 .ib = 265939200,
9646 },
9647};
9648static struct msm_bus_paths atv_bus_scale_usecases[] = {
9649 {
9650 ARRAY_SIZE(atv_bus_init_vectors),
9651 atv_bus_init_vectors,
9652 },
9653 {
9654 ARRAY_SIZE(atv_bus_def_vectors),
9655 atv_bus_def_vectors,
9656 },
9657};
9658static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9659 atv_bus_scale_usecases,
9660 ARRAY_SIZE(atv_bus_scale_usecases),
9661 .name = "atv",
9662};
9663#endif
9664
9665static struct tvenc_platform_data atv_pdata = {
9666 .poll = 0,
9667 .pm_vid_en = atv_dac_power,
9668#ifdef CONFIG_MSM_BUS_SCALING
9669 .bus_scale_table = &atv_bus_scale_pdata,
9670#endif
9671};
9672#endif
9673
9674static void __init msm_fb_add_devices(void)
9675{
9676#ifdef CONFIG_FB_MSM_LCDC_DSUB
9677 mdp_pdata.mdp_core_clk_table = NULL;
9678 mdp_pdata.num_mdp_clk = 0;
9679 mdp_pdata.mdp_core_clk_rate = 200000000;
9680#endif
9681 if (machine_is_msm8x60_rumi3())
9682 msm_fb_register_device("mdp", NULL);
9683 else
9684 msm_fb_register_device("mdp", &mdp_pdata);
9685
9686 msm_fb_register_device("lcdc", &lcdc_pdata);
9687 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9688#ifdef CONFIG_MSM_BUS_SCALING
9689 msm_fb_register_device("dtv", &dtv_pdata);
9690#endif
9691#ifdef CONFIG_FB_MSM_TVOUT
9692 msm_fb_register_device("tvenc", &atv_pdata);
9693 msm_fb_register_device("tvout_device", NULL);
9694#endif
9695}
9696
9697#if (defined(CONFIG_MARIMBA_CORE)) && \
9698 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9699
9700static const struct {
9701 char *name;
9702 int vmin;
9703 int vmax;
9704} bt_regs_info[] = {
9705 { "8058_s3", 1800000, 1800000 },
9706 { "8058_s2", 1300000, 1300000 },
9707 { "8058_l8", 2900000, 3050000 },
9708};
9709
9710static struct {
9711 bool enabled;
9712} bt_regs_status[] = {
9713 { false },
9714 { false },
9715 { false },
9716};
9717static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9718
9719static int bahama_bt(int on)
9720{
9721 int rc;
9722 int i;
9723 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9724
9725 struct bahama_variant_register {
9726 const size_t size;
9727 const struct bahama_config_register *set;
9728 };
9729
9730 const struct bahama_config_register *p;
9731
9732 u8 version;
9733
9734 const struct bahama_config_register v10_bt_on[] = {
9735 { 0xE9, 0x00, 0xFF },
9736 { 0xF4, 0x80, 0xFF },
9737 { 0xE4, 0x00, 0xFF },
9738 { 0xE5, 0x00, 0x0F },
9739#ifdef CONFIG_WLAN
9740 { 0xE6, 0x38, 0x7F },
9741 { 0xE7, 0x06, 0xFF },
9742#endif
9743 { 0xE9, 0x21, 0xFF },
9744 { 0x01, 0x0C, 0x1F },
9745 { 0x01, 0x08, 0x1F },
9746 };
9747
9748 const struct bahama_config_register v20_bt_on_fm_off[] = {
9749 { 0x11, 0x0C, 0xFF },
9750 { 0x13, 0x01, 0xFF },
9751 { 0xF4, 0x80, 0xFF },
9752 { 0xF0, 0x00, 0xFF },
9753 { 0xE9, 0x00, 0xFF },
9754#ifdef CONFIG_WLAN
9755 { 0x81, 0x00, 0x7F },
9756 { 0x82, 0x00, 0xFF },
9757 { 0xE6, 0x38, 0x7F },
9758 { 0xE7, 0x06, 0xFF },
9759#endif
9760 { 0xE9, 0x21, 0xFF },
9761 };
9762
9763 const struct bahama_config_register v20_bt_on_fm_on[] = {
9764 { 0x11, 0x0C, 0xFF },
9765 { 0x13, 0x01, 0xFF },
9766 { 0xF4, 0x86, 0xFF },
9767 { 0xF0, 0x06, 0xFF },
9768 { 0xE9, 0x00, 0xFF },
9769#ifdef CONFIG_WLAN
9770 { 0x81, 0x00, 0x7F },
9771 { 0x82, 0x00, 0xFF },
9772 { 0xE6, 0x38, 0x7F },
9773 { 0xE7, 0x06, 0xFF },
9774#endif
9775 { 0xE9, 0x21, 0xFF },
9776 };
9777
9778 const struct bahama_config_register v10_bt_off[] = {
9779 { 0xE9, 0x00, 0xFF },
9780 };
9781
9782 const struct bahama_config_register v20_bt_off_fm_off[] = {
9783 { 0xF4, 0x84, 0xFF },
9784 { 0xF0, 0x04, 0xFF },
9785 { 0xE9, 0x00, 0xFF }
9786 };
9787
9788 const struct bahama_config_register v20_bt_off_fm_on[] = {
9789 { 0xF4, 0x86, 0xFF },
9790 { 0xF0, 0x06, 0xFF },
9791 { 0xE9, 0x00, 0xFF }
9792 };
9793 const struct bahama_variant_register bt_bahama[2][3] = {
9794 {
9795 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9796 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9797 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9798 },
9799 {
9800 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9801 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9802 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9803 }
9804 };
9805
9806 u8 offset = 0; /* index into bahama configs */
9807
9808 on = on ? 1 : 0;
9809 version = read_bahama_ver();
9810
9811 if (version == VER_UNSUPPORTED) {
9812 dev_err(&msm_bt_power_device.dev,
9813 "%s: unsupported version\n",
9814 __func__);
9815 return -EIO;
9816 }
9817
9818 if (version == VER_2_0) {
9819 if (marimba_get_fm_status(&config))
9820 offset = 0x01;
9821 }
9822
9823 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9824 if (on && (version == VER_2_0)) {
9825 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9826 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9827 && (bt_regs_status[i].enabled == true)) {
9828 if (regulator_disable(bt_regs[i])) {
9829 dev_err(&msm_bt_power_device.dev,
9830 "%s: regulator disable failed",
9831 __func__);
9832 }
9833 bt_regs_status[i].enabled = false;
9834 break;
9835 }
9836 }
9837 }
9838
9839 p = bt_bahama[on][version + offset].set;
9840
9841 dev_info(&msm_bt_power_device.dev,
9842 "%s: found version %d\n", __func__, version);
9843
9844 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9845 u8 value = (p+i)->value;
9846 rc = marimba_write_bit_mask(&config,
9847 (p+i)->reg,
9848 &value,
9849 sizeof((p+i)->value),
9850 (p+i)->mask);
9851 if (rc < 0) {
9852 dev_err(&msm_bt_power_device.dev,
9853 "%s: reg %d write failed: %d\n",
9854 __func__, (p+i)->reg, rc);
9855 return rc;
9856 }
9857 dev_dbg(&msm_bt_power_device.dev,
9858 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9859 __func__, (p+i)->reg,
9860 value, (p+i)->mask);
9861 }
9862 /* Update BT Status */
9863 if (on)
9864 marimba_set_bt_status(&config, true);
9865 else
9866 marimba_set_bt_status(&config, false);
9867
9868 return 0;
9869}
9870
9871static int bluetooth_use_regulators(int on)
9872{
9873 int i, recover = -1, rc = 0;
9874
9875 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9876 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9877 bt_regs_info[i].name) :
9878 (regulator_put(bt_regs[i]), NULL);
9879 if (IS_ERR(bt_regs[i])) {
9880 rc = PTR_ERR(bt_regs[i]);
9881 dev_err(&msm_bt_power_device.dev,
9882 "regulator %s get failed (%d)\n",
9883 bt_regs_info[i].name, rc);
9884 recover = i - 1;
9885 bt_regs[i] = NULL;
9886 break;
9887 }
9888
9889 if (!on)
9890 continue;
9891
9892 rc = regulator_set_voltage(bt_regs[i],
9893 bt_regs_info[i].vmin,
9894 bt_regs_info[i].vmax);
9895 if (rc < 0) {
9896 dev_err(&msm_bt_power_device.dev,
9897 "regulator %s voltage set (%d)\n",
9898 bt_regs_info[i].name, rc);
9899 recover = i;
9900 break;
9901 }
9902 }
9903
9904 if (on && (recover > -1))
9905 for (i = recover; i >= 0; i--) {
9906 regulator_put(bt_regs[i]);
9907 bt_regs[i] = NULL;
9908 }
9909
9910 return rc;
9911}
9912
9913static int bluetooth_switch_regulators(int on)
9914{
9915 int i, rc = 0;
9916
9917 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9918 if (on && (bt_regs_status[i].enabled == false)) {
9919 rc = regulator_enable(bt_regs[i]);
9920 if (rc < 0) {
9921 dev_err(&msm_bt_power_device.dev,
9922 "regulator %s %s failed (%d)\n",
9923 bt_regs_info[i].name,
9924 "enable", rc);
9925 if (i > 0) {
9926 while (--i) {
9927 regulator_disable(bt_regs[i]);
9928 bt_regs_status[i].enabled
9929 = false;
9930 }
9931 break;
9932 }
9933 }
9934 bt_regs_status[i].enabled = true;
9935 } else if (!on && (bt_regs_status[i].enabled == true)) {
9936 rc = regulator_disable(bt_regs[i]);
9937 if (rc < 0) {
9938 dev_err(&msm_bt_power_device.dev,
9939 "regulator %s %s failed (%d)\n",
9940 bt_regs_info[i].name,
9941 "disable", rc);
9942 break;
9943 }
9944 bt_regs_status[i].enabled = false;
9945 }
9946 }
9947 return rc;
9948}
9949
9950static struct msm_xo_voter *bt_clock;
9951
9952static int bluetooth_power(int on)
9953{
9954 int rc = 0;
9955 int id;
9956
9957 /* In case probe function fails, cur_connv_type would be -1 */
9958 id = adie_get_detected_connectivity_type();
9959 if (id != BAHAMA_ID) {
9960 pr_err("%s: unexpected adie connectivity type: %d\n",
9961 __func__, id);
9962 return -ENODEV;
9963 }
9964
9965 if (on) {
9966
9967 rc = bluetooth_use_regulators(1);
9968 if (rc < 0)
9969 goto out;
9970
9971 rc = bluetooth_switch_regulators(1);
9972
9973 if (rc < 0)
9974 goto fail_put;
9975
9976 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9977
9978 if (IS_ERR(bt_clock)) {
9979 pr_err("Couldn't get TCXO_D0 voter\n");
9980 goto fail_switch;
9981 }
9982
9983 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9984
9985 if (rc < 0) {
9986 pr_err("Failed to vote for TCXO_DO ON\n");
9987 goto fail_vote;
9988 }
9989
9990 rc = bahama_bt(1);
9991
9992 if (rc < 0)
9993 goto fail_clock;
9994
9995 msleep(10);
9996
9997 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9998
9999 if (rc < 0) {
10000 pr_err("Failed to vote for TCXO_DO pin control\n");
10001 goto fail_vote;
10002 }
10003 } else {
10004 /* check for initial RFKILL block (power off) */
10005 /* some RFKILL versions/configurations rfkill_register */
10006 /* calls here for an initial set_block */
10007 /* avoid calling i2c and regulator before unblock (on) */
10008 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
10009 dev_info(&msm_bt_power_device.dev,
10010 "%s: initialized OFF/blocked\n", __func__);
10011 goto out;
10012 }
10013
10014 bahama_bt(0);
10015
10016fail_clock:
10017 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
10018fail_vote:
10019 msm_xo_put(bt_clock);
10020fail_switch:
10021 bluetooth_switch_regulators(0);
10022fail_put:
10023 bluetooth_use_regulators(0);
10024 }
10025
10026out:
10027 if (rc < 0)
10028 on = 0;
10029 dev_info(&msm_bt_power_device.dev,
10030 "Bluetooth power switch: state %d result %d\n", on, rc);
10031
10032 return rc;
10033}
10034
10035#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
10036
10037static void __init msm8x60_cfg_smsc911x(void)
10038{
10039 smsc911x_resources[1].start =
10040 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10041 smsc911x_resources[1].end =
10042 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10043}
10044
10045#ifdef CONFIG_MSM_RPM
10046static struct msm_rpm_platform_data msm_rpm_data = {
10047 .reg_base_addrs = {
10048 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
10049 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
10050 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
10051 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
10052 },
10053
10054 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
10055 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
10056 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
10057 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
10058 .msm_apps_ipc_rpm_val = 4,
10059};
10060#endif
10061
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010062void msm_fusion_setup_pinctrl(void)
10063{
10064 struct msm_xo_voter *a1;
10065
10066 if (socinfo_get_platform_subtype() == 0x3) {
10067 /*
10068 * Vote for the A1 clock to be in pin control mode before
10069 * the external images are loaded.
10070 */
10071 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
10072 BUG_ON(!a1);
10073 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
10074 }
10075}
10076
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010077struct msm_board_data {
10078 struct msm_gpiomux_configs *gpiomux_cfgs;
10079};
10080
10081static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
10082 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10083};
10084
10085static struct msm_board_data msm8x60_sim_board_data __initdata = {
10086 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10087};
10088
10089static struct msm_board_data msm8x60_surf_board_data __initdata = {
10090 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10091};
10092
10093static struct msm_board_data msm8x60_ffa_board_data __initdata = {
10094 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10095};
10096
10097static struct msm_board_data msm8x60_fluid_board_data __initdata = {
10098 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
10099};
10100
10101static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
10102 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10103};
10104
10105static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
10106 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10107};
10108
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010109static struct msm_board_data msm8x60_dragon_board_data __initdata = {
10110 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
10111};
10112
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010113static void __init msm8x60_init(struct msm_board_data *board_data)
10114{
10115 uint32_t soc_platform_version;
10116
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070010117 pmic_reset_irq = PM8058_RESOUT_IRQ(PM8058_IRQ_BASE);
10118
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010119 /*
10120 * Initialize RPM first as other drivers and devices may need
10121 * it for their initialization.
10122 */
10123#ifdef CONFIG_MSM_RPM
10124 BUG_ON(msm_rpm_init(&msm_rpm_data));
10125#endif
10126 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
10127 ARRAY_SIZE(msm_rpmrs_levels)));
10128 if (msm_xo_init())
10129 pr_err("Failed to initialize XO votes\n");
10130
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010131 msm8x60_check_2d_hardware();
10132
10133 /* Change SPM handling of core 1 if PMM 8160 is present. */
10134 soc_platform_version = socinfo_get_platform_version();
10135 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
10136 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
10137 struct msm_spm_platform_data *spm_data;
10138
10139 spm_data = &msm_spm_data_v1[1];
10140 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10141 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10142
10143 spm_data = &msm_spm_data[1];
10144 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10145 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10146 }
10147
10148 /*
10149 * Initialize SPM before acpuclock as the latter calls into SPM
10150 * driver to set ACPU voltages.
10151 */
10152 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10153 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
10154 else
10155 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
10156
10157 /*
10158 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
10159 * devices so that the RPM doesn't drop into a low power mode that an
10160 * un-reworked SURF cannot resume from.
10161 */
10162 if (machine_is_msm8x60_surf()) {
David Collins6f032ba2011-08-31 14:08:15 -070010163 int i;
10164
10165 for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
10166 if (rpm_regulator_init_data[i].id
10167 == RPM_VREG_ID_PM8901_L4
10168 || rpm_regulator_init_data[i].id
10169 == RPM_VREG_ID_PM8901_L6)
10170 rpm_regulator_init_data[i]
10171 .init_data.constraints.always_on = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010172 }
10173
10174 /*
10175 * Disable regulator info printing so that regulator registration
10176 * messages do not enter the kmsg log.
10177 */
10178 regulator_suppress_info_printing();
10179
10180 /* Initialize regulators needed for clock_init. */
10181 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
10182
Stephen Boydbb600ae2011-08-02 20:11:40 -070010183 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010184
10185 /* Buses need to be initialized before early-device registration
10186 * to get the platform data for fabrics.
10187 */
10188 msm8x60_init_buses();
10189 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
10190 /* CPU frequency control is not supported on simulated targets. */
10191 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
Matt Wagantallec57f062011-08-16 23:54:46 -070010192 acpuclk_init(&acpuclk_8x60_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010193
Terence Hampsonb36a38c2011-09-19 19:10:40 -040010194 /*
10195 * Enable EBI2 only for boards which make use of it. Leave
10196 * it disabled for all others for additional power savings.
10197 */
10198 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10199 machine_is_msm8x60_rumi3() ||
10200 machine_is_msm8x60_sim() ||
10201 machine_is_msm8x60_fluid() ||
10202 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010203 msm8x60_init_ebi2();
10204 msm8x60_init_tlmm();
10205 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10206 msm8x60_init_uart12dm();
10207 msm8x60_init_mmc();
10208
10209#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10210 msm8x60_init_pm8058_othc();
10211#endif
10212
10213 if (machine_is_msm8x60_fluid()) {
10214 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10215 platform_data = &fluid_keypad_data;
10216 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10217 = sizeof(fluid_keypad_data);
Zhang Chang Ken683be172011-08-10 17:45:34 -040010218 } else if (machine_is_msm8x60_dragon()) {
10219 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10220 platform_data = &dragon_keypad_data;
10221 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10222 = sizeof(dragon_keypad_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010223 } else {
10224 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10225 platform_data = &ffa_keypad_data;
10226 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10227 = sizeof(ffa_keypad_data);
10228
10229 }
10230
10231 /* Disable END_CALL simulation function of powerkey on fluid */
10232 if (machine_is_msm8x60_fluid()) {
10233 pwrkey_pdata.pwrkey_time_ms = 0;
10234 }
10235
Jilai Wang53d27a82011-07-13 14:32:58 -040010236 /* Specify reset pin for OV9726 */
10237 if (machine_is_msm8x60_dragon()) {
10238 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10239 ov9726_sensor_8660_info.mount_angle = 270;
10240 }
10241
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010242 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10243 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010244 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010245 msm8x60_cfg_smsc911x();
10246 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10247 platform_add_devices(msm_footswitch_devices,
10248 msm_num_footswitch_devices);
10249 platform_add_devices(surf_devices,
10250 ARRAY_SIZE(surf_devices));
10251
10252#ifdef CONFIG_MSM_DSPS
10253 if (machine_is_msm8x60_fluid()) {
10254 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10255 msm8x60_init_dsps();
10256 }
10257#endif
10258
10259#ifdef CONFIG_USB_EHCI_MSM_72K
10260 /*
10261 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10262 * fluid
10263 */
10264 if (machine_is_msm8x60_fluid()) {
10265 pm8901_mpp_config_digital_out(1,
10266 PM8901_MPP_DIG_LEVEL_L5, 1);
10267 }
10268 msm_add_host(0, &msm_usb_host_pdata);
10269#endif
Lei Zhou338cab82011-08-19 13:38:17 -040010270
10271#ifdef CONFIG_SND_SOC_MSM8660_APQ
10272 if (machine_is_msm8x60_dragon())
10273 platform_add_devices(dragon_alsa_devices,
10274 ARRAY_SIZE(dragon_alsa_devices));
10275 else
10276#endif
10277 platform_add_devices(asoc_devices,
10278 ARRAY_SIZE(asoc_devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010279 } else {
10280 msm8x60_configure_smc91x();
10281 platform_add_devices(rumi_sim_devices,
10282 ARRAY_SIZE(rumi_sim_devices));
10283 }
10284#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010285 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10286 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010287 msm8x60_cfg_isp1763();
10288#endif
10289#ifdef CONFIG_BATTERY_MSM8X60
10290 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010291 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010292 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10293 platform_device_register(&msm_charger_device);
10294#endif
10295
10296 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10297 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10298
Terence Hampson90508a92011-08-09 10:40:08 -040010299 if (machine_is_msm8x60_dragon()) {
10300 pm8058_charger_sub_dev.platform_data
10301 = &pmic8058_charger_dragon;
10302 pm8058_charger_sub_dev.pdata_size
10303 = sizeof(pmic8058_charger_dragon);
10304 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010305 if (!machine_is_msm8x60_fluid())
10306 pm8058_platform_data.charger_sub_device
10307 = &pm8058_charger_sub_dev;
10308
10309#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10310 if (machine_is_msm8x60_fluid())
10311 platform_device_register(&msm_gsbi10_qup_spi_device);
10312 else
10313 platform_device_register(&msm_gsbi1_qup_spi_device);
10314#endif
10315
10316#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10317 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10318 if (machine_is_msm8x60_fluid())
10319 cyttsp_set_params();
10320#endif
10321 if (!machine_is_msm8x60_sim())
10322 msm_fb_add_devices();
10323 fixup_i2c_configs();
10324 register_i2c_devices();
10325
Terence Hampson1c73fef2011-07-19 17:10:49 -040010326 if (machine_is_msm8x60_dragon())
10327 smsc911x_config.reset_gpio
10328 = GPIO_ETHERNET_RESET_N_DRAGON;
10329
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010330 platform_device_register(&smsc911x_device);
10331
10332#if (defined(CONFIG_SPI_QUP)) && \
10333 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010334 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10335 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010336
10337 if (machine_is_msm8x60_fluid()) {
10338#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10339 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10340 spi_register_board_info(lcdc_samsung_spi_board_info,
10341 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10342 } else
10343#endif
10344 {
10345#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10346 spi_register_board_info(lcdc_auo_spi_board_info,
10347 ARRAY_SIZE(lcdc_auo_spi_board_info));
10348#endif
10349 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010350#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10351 } else if (machine_is_msm8x60_dragon()) {
10352 spi_register_board_info(lcdc_nt35582_spi_board_info,
10353 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10354#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010355 }
10356#endif
10357
10358 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10359 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10360 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10361 msm_pm_data);
10362
10363#ifdef CONFIG_SENSORS_MSM_ADC
10364 if (machine_is_msm8x60_fluid()) {
10365 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10366 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10367 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10368 msm_adc_pdata.gpio_config = APROC_CONFIG;
10369 else
10370 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10371 }
10372 msm_adc_pdata.target_hw = MSM_8x60;
10373#endif
10374#ifdef CONFIG_MSM8X60_AUDIO
10375 msm_snddev_init();
10376#endif
10377#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10378 if (machine_is_msm8x60_fluid())
10379 platform_device_register(&fluid_leds_gpio);
10380 else
10381 platform_device_register(&gpio_leds);
10382#endif
10383
10384 /* configure pmic leds */
10385 if (machine_is_msm8x60_fluid()) {
10386 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10387 platform_data = &pm8058_fluid_flash_leds_data;
10388 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10389 = sizeof(pm8058_fluid_flash_leds_data);
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -040010390 } else if (machine_is_msm8x60_dragon()) {
10391 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10392 platform_data = &pm8058_dragon_leds_data;
10393 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10394 = sizeof(pm8058_dragon_leds_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010395 } else {
10396 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10397 platform_data = &pm8058_flash_leds_data;
10398 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10399 = sizeof(pm8058_flash_leds_data);
10400 }
10401
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010402 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10403 machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010404 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10405 platform_data = &pmic_vib_pdata;
10406 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10407 pdata_size = sizeof(pmic_vib_pdata);
10408 }
10409
10410 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010411
10412 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10413 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010414}
10415
10416static void __init msm8x60_rumi3_init(void)
10417{
10418 msm8x60_init(&msm8x60_rumi3_board_data);
10419}
10420
10421static void __init msm8x60_sim_init(void)
10422{
10423 msm8x60_init(&msm8x60_sim_board_data);
10424}
10425
10426static void __init msm8x60_surf_init(void)
10427{
10428 msm8x60_init(&msm8x60_surf_board_data);
10429}
10430
10431static void __init msm8x60_ffa_init(void)
10432{
10433 msm8x60_init(&msm8x60_ffa_board_data);
10434}
10435
10436static void __init msm8x60_fluid_init(void)
10437{
10438 msm8x60_init(&msm8x60_fluid_board_data);
10439}
10440
10441static void __init msm8x60_charm_surf_init(void)
10442{
10443 msm8x60_init(&msm8x60_charm_surf_board_data);
10444}
10445
10446static void __init msm8x60_charm_ffa_init(void)
10447{
10448 msm8x60_init(&msm8x60_charm_ffa_board_data);
10449}
10450
10451static void __init msm8x60_charm_init_early(void)
10452{
10453 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010454}
10455
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010456static void __init msm8x60_dragon_init(void)
10457{
10458 msm8x60_init(&msm8x60_dragon_board_data);
10459}
10460
Steve Mucklea55df6e2010-01-07 12:43:24 -080010461MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10462 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010463 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010464 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010465 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010466 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010467 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010468MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010469
10470MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10471 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010472 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010473 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010474 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010475 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010476 .init_early = msm8x60_charm_init_early,
10477MACHINE_END
10478
10479MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10480 .map_io = msm8x60_map_io,
10481 .reserve = msm8x60_reserve,
10482 .init_irq = msm8x60_init_irq,
10483 .init_machine = msm8x60_surf_init,
10484 .timer = &msm_timer,
10485 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010486MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010487
10488MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10489 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010490 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010491 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010492 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010493 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010494 .init_early = msm8x60_charm_init_early,
10495MACHINE_END
10496
10497MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10498 .map_io = msm8x60_map_io,
10499 .reserve = msm8x60_reserve,
10500 .init_irq = msm8x60_init_irq,
10501 .init_machine = msm8x60_fluid_init,
10502 .timer = &msm_timer,
10503 .init_early = msm8x60_charm_init_early,
10504MACHINE_END
10505
10506MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10507 .map_io = msm8x60_map_io,
10508 .reserve = msm8x60_reserve,
10509 .init_irq = msm8x60_init_irq,
10510 .init_machine = msm8x60_charm_surf_init,
10511 .timer = &msm_timer,
10512 .init_early = msm8x60_charm_init_early,
10513MACHINE_END
10514
10515MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10516 .map_io = msm8x60_map_io,
10517 .reserve = msm8x60_reserve,
10518 .init_irq = msm8x60_init_irq,
10519 .init_machine = msm8x60_charm_ffa_init,
10520 .timer = &msm_timer,
10521 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010522MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010523
10524MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10525 .map_io = msm8x60_map_io,
10526 .reserve = msm8x60_reserve,
10527 .init_irq = msm8x60_init_irq,
10528 .init_machine = msm8x60_dragon_init,
10529 .timer = &msm_timer,
10530 .init_early = msm8x60_charm_init_early,
10531MACHINE_END