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review.evervolv.com / android_kernel_htc_msm8960 / 9daf6dcad633c3cf7cd32c86d6eba895d35f5a72 / . / arch / arm / mach-msm / acpuclock-copper.c
blob: f0da74c862a83170186a89ec1a0a7366b065bfc3 [file] [log] [blame]
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1/*
2 * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Steve Mucklef132c6c2012-06-06 18:30:57 -0700[diff] [blame]14#include <linux/module.h>
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]15#include <linux/platform_device.h>
16#include <linux/of.h>
17#include <mach/rpm-regulator.h>
18#include <mach/msm_bus_board.h>
19#include <mach/msm_bus.h>
20#include <mach/socinfo.h>
21
22#include "acpuclock.h"
23#include "acpuclock-krait.h"
24
25/* Corner type vreg VDD values */
26#define LVL_NONE RPM_VREG_CORNER_NONE
27#define LVL_LOW RPM_VREG_CORNER_LOW
28#define LVL_NOM RPM_VREG_CORNER_NOMINAL
29#define LVL_HIGH RPM_VREG_CORNER_HIGH
30
31static struct hfpll_data hfpll_data_cpu = {
32 .mode_offset = 0x00,
33 .l_offset = 0x04,
34 .m_offset = 0x08,
35 .n_offset = 0x0C,
36 .config_offset = 0x14,
37 /* TODO: Verify magic number for copper when available. */
38 .config_val = 0x7845C665,
39 .low_vdd_l_max = 52,
40 .vdd[HFPLL_VDD_NONE] = 0,
41 .vdd[HFPLL_VDD_LOW] = 810000,
42 .vdd[HFPLL_VDD_NOM] = 900000,
43};
44
45static struct hfpll_data hfpll_data_l2 = {
46 .mode_offset = 0x00,
47 .l_offset = 0x04,
48 .m_offset = 0x08,
49 .n_offset = 0x0C,
50 .config_offset = 0x14,
51 /* TODO: Verify magic number for copper when available. */
52 .config_val = 0x7845C665,
53 .low_vdd_l_max = 52,
54 .vdd[HFPLL_VDD_NONE] = LVL_NONE,
55 .vdd[HFPLL_VDD_LOW] = LVL_LOW,
56 .vdd[HFPLL_VDD_NOM] = LVL_NOM,
57};
58
59static struct scalable scalable[] = {
60 [CPU0] = {
61 .hfpll_phys_base = 0xF908A000,
62 .hfpll_data = &hfpll_data_cpu,
63 .l2cpmr_iaddr = 0x4501,
64 .vreg[VREG_CORE] = { "krait0", 1050000, 3200000 },
65 .vreg[VREG_MEM] = { "krait0_mem", 1050000, 0,
66 RPM_VREG_VOTER1,
67 RPM_VREG_ID_PM8941_S1 },
68 .vreg[VREG_DIG] = { "krait0_dig", 1050000, 0,
69 RPM_VREG_VOTER1,
70 RPM_VREG_ID_PM8941_S2 },
71 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
72 RPM_VREG_VOTER1,
73 RPM_VREG_ID_PM8941_L12 },
74 },
75 [CPU1] = {
76 .hfpll_phys_base = 0xF909A000,
77 .hfpll_data = &hfpll_data_cpu,
78 .l2cpmr_iaddr = 0x5501,
79 .vreg[VREG_CORE] = { "krait1", 1050000, 3200000 },
80 .vreg[VREG_MEM] = { "krait1_mem", 1050000, 0,
81 RPM_VREG_VOTER2,
82 RPM_VREG_ID_PM8941_S1 },
83 .vreg[VREG_DIG] = { "krait1_dig", 1050000, 0,
84 RPM_VREG_VOTER2,
85 RPM_VREG_ID_PM8941_S2 },
86 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
87 RPM_VREG_VOTER2,
88 RPM_VREG_ID_PM8941_L12 },
89 },
90 [CPU2] = {
91 .hfpll_phys_base = 0xF90AA000,
92 .hfpll_data = &hfpll_data_cpu,
93 .l2cpmr_iaddr = 0x6501,
94 .vreg[VREG_CORE] = { "krait2", 1050000, 3200000 },
95 .vreg[VREG_MEM] = { "krait2_mem", 1050000, 0,
96 RPM_VREG_VOTER4,
97 RPM_VREG_ID_PM8921_S1 },
98 .vreg[VREG_DIG] = { "krait2_dig", 1050000, 0,
99 RPM_VREG_VOTER4,
100 RPM_VREG_ID_PM8921_S2 },
101 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
102 RPM_VREG_VOTER4,
103 RPM_VREG_ID_PM8941_L12 },
104 },
105 [CPU3] = {
106 .hfpll_phys_base = 0xF90BA000,
107 .hfpll_data = &hfpll_data_cpu,
108 .l2cpmr_iaddr = 0x7501,
109 .vreg[VREG_CORE] = { "krait3", 1050000, 3200000 },
110 .vreg[VREG_MEM] = { "krait3_mem", 1050000, 0,
111 RPM_VREG_VOTER5,
112 RPM_VREG_ID_PM8941_S1 },
113 .vreg[VREG_DIG] = { "krait3_dig", 1050000, 0,
114 RPM_VREG_VOTER5,
115 RPM_VREG_ID_PM8941_S2 },
116 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
117 RPM_VREG_VOTER5,
118 RPM_VREG_ID_PM8941_L12 },
119 },
120 [L2] = {
121 .hfpll_phys_base = 0xF9016000,
122 .hfpll_data = &hfpll_data_l2,
123 .l2cpmr_iaddr = 0x0500,
124 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
125 RPM_VREG_VOTER6,
126 RPM_VREG_ID_PM8941_L12 },
127 },
128};
129
130static struct msm_bus_paths bw_level_tbl[] = {
131 [0] = BW_MBPS(400), /* At least 50 MHz on bus. */
132 [1] = BW_MBPS(800), /* At least 100 MHz on bus. */
133 [2] = BW_MBPS(1334), /* At least 167 MHz on bus. */
134 [3] = BW_MBPS(2666), /* At least 200 MHz on bus. */
135 [4] = BW_MBPS(3200), /* At least 333 MHz on bus. */
136};
137
138static struct msm_bus_scale_pdata bus_scale_data = {
139 .usecase = bw_level_tbl,
140 .num_usecases = ARRAY_SIZE(bw_level_tbl),
141 .active_only = 1,
142 .name = "acpuclk-copper",
143};
144
145#define L2(x) (&l2_freq_tbl[(x)])
146static struct l2_level l2_freq_tbl[] = {
147 [0] = { {STBY_KHZ, QSB, 0, 0, 0 }, LVL_NOM, 1050000, 0 },
148 [1] = { { 300000, PLL_0, 0, 2, 0 }, LVL_NOM, 1050000, 2 },
149 [2] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 1050000, 2 },
150 [3] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 1050000, 2 },
151 [4] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 1050000, 2 },
152 [5] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 1050000, 3 },
153 [6] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 1050000, 3 },
154 [7] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 1050000, 3 },
155 [8] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 1050000, 3 },
156 [9] = { { 883200, HFPLL, 1, 0, 46 }, LVL_NOM, 1050000, 4 },
157 [10] = { { 960000, HFPLL, 1, 0, 50 }, LVL_NOM, 1050000, 4 },
158 [11] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_NOM, 1050000, 4 },
159};
160
161static struct acpu_level acpu_freq_tbl[] = {
162 { 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000 },
163 { 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000 },
164 { 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000 },
165 { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000 },
166 { 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000 },
167 { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000 },
168 { 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000 },
169 { 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000 },
170 { 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000 },
171 { 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000 },
172 { 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000 },
173 { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000 },
174 { 0, { 0 } }
175};
176
177static struct acpuclk_krait_params acpuclk_copper_params = {
178 .scalable = scalable,
179 .pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,
180 .pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,
181 .pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,
182 .l2_freq_tbl = l2_freq_tbl,
183 .l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),
184 .bus_scale_data = &bus_scale_data,
185 .qfprom_phys_base = 0xFC4A8000,
186};
187
188static int __init acpuclk_copper_probe(struct platform_device *pdev)
189{
190 return acpuclk_krait_init(&pdev->dev, &acpuclk_copper_params);
191}
192
193static struct of_device_id acpuclk_copper_match_table[] = {
194 { .compatible = "qcom,acpuclk-copper" },
195 {}
196};
197
198static struct platform_driver acpuclk_copper_driver = {
199 .driver = {
200 .name = "acpuclk-copper",
201 .of_match_table = acpuclk_copper_match_table,
202 .owner = THIS_MODULE,
203 },
204};
205
206static int __init acpuclk_8960_init(void)
207{
208 return platform_driver_probe(&acpuclk_copper_driver,
209 acpuclk_copper_probe);
210}
211device_initcall(acpuclk_8960_init);