blob: 927c08b088612539e726045bd250e98011911be0 [file] [log] [blame]
Dan Williamsbf40a682009-09-08 17:42:55 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
24 *
25 * BSD LICENSE
26 *
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
31 *
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
37 * distribution.
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55/*
56 * Support routines for v3+ hardware
57 */
58
59#include <linux/pci.h>
60#include <linux/dmaengine.h>
61#include <linux/dma-mapping.h>
62#include "registers.h"
63#include "hw.h"
64#include "dma.h"
65#include "dma_v2.h"
66
Dan Williamsb094ad32009-09-08 17:42:57 -070067/* ioat hardware assumes at least two sources for raid operations */
68#define src_cnt_to_sw(x) ((x) + 2)
69#define src_cnt_to_hw(x) ((x) - 2)
70
71/* provide a lookup table for setting the source address in the base or
72 * extended descriptor of an xor descriptor
73 */
74static const u8 xor_idx_to_desc __read_mostly = 0xd0;
75static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 };
76
77static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
78{
79 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
80
81 return raw->field[xor_idx_to_field[idx]];
82}
83
84static void xor_set_src(struct ioat_raw_descriptor *descs[2],
85 dma_addr_t addr, u32 offset, int idx)
86{
87 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
88
89 raw->field[xor_idx_to_field[idx]] = addr + offset;
90}
91
Dan Williamsbf40a682009-09-08 17:42:55 -070092static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
Dan Williamsb094ad32009-09-08 17:42:57 -070093 struct ioat_ring_ent *desc, int idx)
Dan Williamsbf40a682009-09-08 17:42:55 -070094{
95 struct ioat_chan_common *chan = &ioat->base;
96 struct pci_dev *pdev = chan->device->pdev;
97 size_t len = desc->len;
98 size_t offset = len - desc->hw->size;
99 struct dma_async_tx_descriptor *tx = &desc->txd;
100 enum dma_ctrl_flags flags = tx->flags;
101
102 switch (desc->hw->ctl_f.op) {
103 case IOAT_OP_COPY:
104 ioat_dma_unmap(chan, flags, len, desc->hw);
105 break;
106 case IOAT_OP_FILL: {
107 struct ioat_fill_descriptor *hw = desc->fill;
108
109 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
110 ioat_unmap(pdev, hw->dst_addr - offset, len,
111 PCI_DMA_FROMDEVICE, flags, 1);
112 break;
113 }
Dan Williamsb094ad32009-09-08 17:42:57 -0700114 case IOAT_OP_XOR_VAL:
115 case IOAT_OP_XOR: {
116 struct ioat_xor_descriptor *xor = desc->xor;
117 struct ioat_ring_ent *ext;
118 struct ioat_xor_ext_descriptor *xor_ex = NULL;
119 int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
120 struct ioat_raw_descriptor *descs[2];
121 int i;
122
123 if (src_cnt > 5) {
124 ext = ioat2_get_ring_ent(ioat, idx + 1);
125 xor_ex = ext->xor_ex;
126 }
127
128 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
129 descs[0] = (struct ioat_raw_descriptor *) xor;
130 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
131 for (i = 0; i < src_cnt; i++) {
132 dma_addr_t src = xor_get_src(descs, i);
133
134 ioat_unmap(pdev, src - offset, len,
135 PCI_DMA_TODEVICE, flags, 0);
136 }
137
138 /* dest is a source in xor validate operations */
139 if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
140 ioat_unmap(pdev, xor->dst_addr - offset, len,
141 PCI_DMA_TODEVICE, flags, 1);
142 break;
143 }
144 }
145
146 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
147 ioat_unmap(pdev, xor->dst_addr - offset, len,
148 PCI_DMA_FROMDEVICE, flags, 1);
149 break;
150 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700151 default:
152 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
153 __func__, desc->hw->ctl_f.op);
154 }
155}
156
Dan Williamsb094ad32009-09-08 17:42:57 -0700157static bool desc_has_ext(struct ioat_ring_ent *desc)
158{
159 struct ioat_dma_descriptor *hw = desc->hw;
Dan Williamsbf40a682009-09-08 17:42:55 -0700160
Dan Williamsb094ad32009-09-08 17:42:57 -0700161 if (hw->ctl_f.op == IOAT_OP_XOR ||
162 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
163 struct ioat_xor_descriptor *xor = desc->xor;
164
165 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
166 return true;
167 }
168
169 return false;
170}
171
172/**
173 * __cleanup - reclaim used descriptors
174 * @ioat: channel (ring) to clean
175 *
176 * The difference from the dma_v2.c __cleanup() is that this routine
177 * handles extended descriptors and dma-unmapping raid operations.
178 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700179static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
180{
181 struct ioat_chan_common *chan = &ioat->base;
182 struct ioat_ring_ent *desc;
183 bool seen_current = false;
184 u16 active;
185 int i;
186
187 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
188 __func__, ioat->head, ioat->tail, ioat->issued);
189
190 active = ioat2_ring_active(ioat);
191 for (i = 0; i < active && !seen_current; i++) {
192 struct dma_async_tx_descriptor *tx;
193
194 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
195 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
196 dump_desc_dbg(ioat, desc);
197 tx = &desc->txd;
198 if (tx->cookie) {
199 chan->completed_cookie = tx->cookie;
Dan Williamsb094ad32009-09-08 17:42:57 -0700200 ioat3_dma_unmap(ioat, desc, ioat->tail + i);
Dan Williamsbf40a682009-09-08 17:42:55 -0700201 tx->cookie = 0;
202 if (tx->callback) {
203 tx->callback(tx->callback_param);
204 tx->callback = NULL;
205 }
206 }
207
208 if (tx->phys == phys_complete)
209 seen_current = true;
Dan Williamsb094ad32009-09-08 17:42:57 -0700210
211 /* skip extended descriptors */
212 if (desc_has_ext(desc)) {
213 BUG_ON(i + 1 >= active);
214 i++;
215 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700216 }
217 ioat->tail += i;
218 BUG_ON(!seen_current); /* no active descs have written a completion? */
219 chan->last_completion = phys_complete;
220 if (ioat->head == ioat->tail) {
221 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
222 __func__);
223 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
224 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
225 }
226}
227
228static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
229{
230 struct ioat_chan_common *chan = &ioat->base;
231 unsigned long phys_complete;
232
233 prefetch(chan->completion);
234
235 if (!spin_trylock_bh(&chan->cleanup_lock))
236 return;
237
238 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
239 spin_unlock_bh(&chan->cleanup_lock);
240 return;
241 }
242
243 if (!spin_trylock_bh(&ioat->ring_lock)) {
244 spin_unlock_bh(&chan->cleanup_lock);
245 return;
246 }
247
248 __cleanup(ioat, phys_complete);
249
250 spin_unlock_bh(&ioat->ring_lock);
251 spin_unlock_bh(&chan->cleanup_lock);
252}
253
254static void ioat3_cleanup_tasklet(unsigned long data)
255{
256 struct ioat2_dma_chan *ioat = (void *) data;
257
258 ioat3_cleanup(ioat);
Dan Williamse61daca2009-09-08 17:42:57 -0700259 writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN,
260 ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williamsbf40a682009-09-08 17:42:55 -0700261}
262
263static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
264{
265 struct ioat_chan_common *chan = &ioat->base;
266 unsigned long phys_complete;
267 u32 status;
268
269 status = ioat_chansts(chan);
270 if (is_ioat_active(status) || is_ioat_idle(status))
271 ioat_suspend(chan);
272 while (is_ioat_active(status) || is_ioat_idle(status)) {
273 status = ioat_chansts(chan);
274 cpu_relax();
275 }
276
277 if (ioat_cleanup_preamble(chan, &phys_complete))
278 __cleanup(ioat, phys_complete);
279
280 __ioat2_restart_chan(ioat);
281}
282
283static void ioat3_timer_event(unsigned long data)
284{
285 struct ioat2_dma_chan *ioat = (void *) data;
286 struct ioat_chan_common *chan = &ioat->base;
287
288 spin_lock_bh(&chan->cleanup_lock);
289 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
290 unsigned long phys_complete;
291 u64 status;
292
293 spin_lock_bh(&ioat->ring_lock);
294 status = ioat_chansts(chan);
295
296 /* when halted due to errors check for channel
297 * programming errors before advancing the completion state
298 */
299 if (is_ioat_halted(status)) {
300 u32 chanerr;
301
302 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
303 BUG_ON(is_ioat_bug(chanerr));
304 }
305
306 /* if we haven't made progress and we have already
307 * acknowledged a pending completion once, then be more
308 * forceful with a restart
309 */
310 if (ioat_cleanup_preamble(chan, &phys_complete))
311 __cleanup(ioat, phys_complete);
312 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
313 ioat3_restart_channel(ioat);
314 else {
315 set_bit(IOAT_COMPLETION_ACK, &chan->state);
316 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
317 }
318 spin_unlock_bh(&ioat->ring_lock);
319 } else {
320 u16 active;
321
322 /* if the ring is idle, empty, and oversized try to step
323 * down the size
324 */
325 spin_lock_bh(&ioat->ring_lock);
326 active = ioat2_ring_active(ioat);
327 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
328 reshape_ring(ioat, ioat->alloc_order-1);
329 spin_unlock_bh(&ioat->ring_lock);
330
331 /* keep shrinking until we get back to our minimum
332 * default size
333 */
334 if (ioat->alloc_order > ioat_get_alloc_order())
335 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
336 }
337 spin_unlock_bh(&chan->cleanup_lock);
338}
339
340static enum dma_status
341ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie,
342 dma_cookie_t *done, dma_cookie_t *used)
343{
344 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
345
346 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
347 return DMA_SUCCESS;
348
349 ioat3_cleanup(ioat);
350
351 return ioat_is_complete(c, cookie, done, used);
352}
353
354static struct dma_async_tx_descriptor *
355ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
356 size_t len, unsigned long flags)
357{
358 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
359 struct ioat_ring_ent *desc;
360 size_t total_len = len;
361 struct ioat_fill_descriptor *fill;
362 int num_descs;
363 u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
364 u16 idx;
365 int i;
366
367 num_descs = ioat2_xferlen_to_descs(ioat, len);
368 if (likely(num_descs) &&
369 ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
370 /* pass */;
371 else
372 return NULL;
373 for (i = 0; i < num_descs; i++) {
374 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
375
376 desc = ioat2_get_ring_ent(ioat, idx + i);
377 fill = desc->fill;
378
379 fill->size = xfer_size;
380 fill->src_data = src_data;
381 fill->dst_addr = dest;
382 fill->ctl = 0;
383 fill->ctl_f.op = IOAT_OP_FILL;
384
385 len -= xfer_size;
386 dest += xfer_size;
387 dump_desc_dbg(ioat, desc);
388 }
389
390 desc->txd.flags = flags;
391 desc->len = total_len;
392 fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
393 fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
394 fill->ctl_f.compl_write = 1;
395 dump_desc_dbg(ioat, desc);
396
397 /* we leave the channel locked to ensure in order submission */
398 return &desc->txd;
399}
400
Dan Williamsb094ad32009-09-08 17:42:57 -0700401static struct dma_async_tx_descriptor *
402__ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
403 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
404 size_t len, unsigned long flags)
405{
406 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
407 struct ioat_ring_ent *compl_desc;
408 struct ioat_ring_ent *desc;
409 struct ioat_ring_ent *ext;
410 size_t total_len = len;
411 struct ioat_xor_descriptor *xor;
412 struct ioat_xor_ext_descriptor *xor_ex = NULL;
413 struct ioat_dma_descriptor *hw;
414 u32 offset = 0;
415 int num_descs;
416 int with_ext;
417 int i;
418 u16 idx;
419 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
420
421 BUG_ON(src_cnt < 2);
422
423 num_descs = ioat2_xferlen_to_descs(ioat, len);
424 /* we need 2x the number of descriptors to cover greater than 5
425 * sources
426 */
427 if (src_cnt > 5) {
428 with_ext = 1;
429 num_descs *= 2;
430 } else
431 with_ext = 0;
432
433 /* completion writes from the raid engine may pass completion
434 * writes from the legacy engine, so we need one extra null
435 * (legacy) descriptor to ensure all completion writes arrive in
436 * order.
437 */
438 if (likely(num_descs) &&
439 ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0)
440 /* pass */;
441 else
442 return NULL;
443 for (i = 0; i < num_descs; i += 1 + with_ext) {
444 struct ioat_raw_descriptor *descs[2];
445 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
446 int s;
447
448 desc = ioat2_get_ring_ent(ioat, idx + i);
449 xor = desc->xor;
450
451 /* save a branch by unconditionally retrieving the
452 * extended descriptor xor_set_src() knows to not write
453 * to it in the single descriptor case
454 */
455 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
456 xor_ex = ext->xor_ex;
457
458 descs[0] = (struct ioat_raw_descriptor *) xor;
459 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
460 for (s = 0; s < src_cnt; s++)
461 xor_set_src(descs, src[s], offset, s);
462 xor->size = xfer_size;
463 xor->dst_addr = dest + offset;
464 xor->ctl = 0;
465 xor->ctl_f.op = op;
466 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
467
468 len -= xfer_size;
469 offset += xfer_size;
470 dump_desc_dbg(ioat, desc);
471 }
472
473 /* last xor descriptor carries the unmap parameters and fence bit */
474 desc->txd.flags = flags;
475 desc->len = total_len;
476 if (result)
477 desc->result = result;
478 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
479
480 /* completion descriptor carries interrupt bit */
481 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
482 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
483 hw = compl_desc->hw;
484 hw->ctl = 0;
485 hw->ctl_f.null = 1;
486 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
487 hw->ctl_f.compl_write = 1;
488 hw->size = NULL_DESC_BUFFER_SIZE;
489 dump_desc_dbg(ioat, compl_desc);
490
491 /* we leave the channel locked to ensure in order submission */
492 return &desc->txd;
493}
494
495static struct dma_async_tx_descriptor *
496ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
497 unsigned int src_cnt, size_t len, unsigned long flags)
498{
499 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
500}
501
502struct dma_async_tx_descriptor *
503ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
504 unsigned int src_cnt, size_t len,
505 enum sum_check_flags *result, unsigned long flags)
506{
507 /* the cleanup routine only sets bits on validate failure, it
508 * does not clear bits on validate success... so clear it here
509 */
510 *result = 0;
511
512 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
513 src_cnt - 1, len, flags);
514}
515
Dan Williams9de6fc72009-09-08 17:42:58 -0700516static void __devinit ioat3_dma_test_callback(void *dma_async_param)
517{
518 struct completion *cmp = dma_async_param;
519
520 complete(cmp);
521}
522
523#define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
524static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device)
525{
526 int i, src_idx;
527 struct page *dest;
528 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
529 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
530 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
531 dma_addr_t dma_addr, dest_dma;
532 struct dma_async_tx_descriptor *tx;
533 struct dma_chan *dma_chan;
534 dma_cookie_t cookie;
535 u8 cmp_byte = 0;
536 u32 cmp_word;
537 u32 xor_val_result;
538 int err = 0;
539 struct completion cmp;
540 unsigned long tmo;
541 struct device *dev = &device->pdev->dev;
542 struct dma_device *dma = &device->common;
543
544 dev_dbg(dev, "%s\n", __func__);
545
546 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
547 return 0;
548
549 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
550 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
551 if (!xor_srcs[src_idx]) {
552 while (src_idx--)
553 __free_page(xor_srcs[src_idx]);
554 return -ENOMEM;
555 }
556 }
557
558 dest = alloc_page(GFP_KERNEL);
559 if (!dest) {
560 while (src_idx--)
561 __free_page(xor_srcs[src_idx]);
562 return -ENOMEM;
563 }
564
565 /* Fill in src buffers */
566 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
567 u8 *ptr = page_address(xor_srcs[src_idx]);
568 for (i = 0; i < PAGE_SIZE; i++)
569 ptr[i] = (1 << src_idx);
570 }
571
572 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
573 cmp_byte ^= (u8) (1 << src_idx);
574
575 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
576 (cmp_byte << 8) | cmp_byte;
577
578 memset(page_address(dest), 0, PAGE_SIZE);
579
580 dma_chan = container_of(dma->channels.next, struct dma_chan,
581 device_node);
582 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
583 err = -ENODEV;
584 goto out;
585 }
586
587 /* test xor */
588 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
589 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
590 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
591 DMA_TO_DEVICE);
592 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
593 IOAT_NUM_SRC_TEST, PAGE_SIZE,
594 DMA_PREP_INTERRUPT);
595
596 if (!tx) {
597 dev_err(dev, "Self-test xor prep failed\n");
598 err = -ENODEV;
599 goto free_resources;
600 }
601
602 async_tx_ack(tx);
603 init_completion(&cmp);
604 tx->callback = ioat3_dma_test_callback;
605 tx->callback_param = &cmp;
606 cookie = tx->tx_submit(tx);
607 if (cookie < 0) {
608 dev_err(dev, "Self-test xor setup failed\n");
609 err = -ENODEV;
610 goto free_resources;
611 }
612 dma->device_issue_pending(dma_chan);
613
614 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
615
616 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
617 dev_err(dev, "Self-test xor timed out\n");
618 err = -ENODEV;
619 goto free_resources;
620 }
621
622 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
623 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
624 u32 *ptr = page_address(dest);
625 if (ptr[i] != cmp_word) {
626 dev_err(dev, "Self-test xor failed compare\n");
627 err = -ENODEV;
628 goto free_resources;
629 }
630 }
631 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE);
632
633 /* skip validate if the capability is not present */
634 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
635 goto free_resources;
636
637 /* validate the sources with the destintation page */
638 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
639 xor_val_srcs[i] = xor_srcs[i];
640 xor_val_srcs[i] = dest;
641
642 xor_val_result = 1;
643
644 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
645 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
646 DMA_TO_DEVICE);
647 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
648 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
649 &xor_val_result, DMA_PREP_INTERRUPT);
650 if (!tx) {
651 dev_err(dev, "Self-test zero prep failed\n");
652 err = -ENODEV;
653 goto free_resources;
654 }
655
656 async_tx_ack(tx);
657 init_completion(&cmp);
658 tx->callback = ioat3_dma_test_callback;
659 tx->callback_param = &cmp;
660 cookie = tx->tx_submit(tx);
661 if (cookie < 0) {
662 dev_err(dev, "Self-test zero setup failed\n");
663 err = -ENODEV;
664 goto free_resources;
665 }
666 dma->device_issue_pending(dma_chan);
667
668 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
669
670 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
671 dev_err(dev, "Self-test validate timed out\n");
672 err = -ENODEV;
673 goto free_resources;
674 }
675
676 if (xor_val_result != 0) {
677 dev_err(dev, "Self-test validate failed compare\n");
678 err = -ENODEV;
679 goto free_resources;
680 }
681
682 /* skip memset if the capability is not present */
683 if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask))
684 goto free_resources;
685
686 /* test memset */
687 dma_addr = dma_map_page(dev, dest, 0,
688 PAGE_SIZE, DMA_FROM_DEVICE);
689 tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
690 DMA_PREP_INTERRUPT);
691 if (!tx) {
692 dev_err(dev, "Self-test memset prep failed\n");
693 err = -ENODEV;
694 goto free_resources;
695 }
696
697 async_tx_ack(tx);
698 init_completion(&cmp);
699 tx->callback = ioat3_dma_test_callback;
700 tx->callback_param = &cmp;
701 cookie = tx->tx_submit(tx);
702 if (cookie < 0) {
703 dev_err(dev, "Self-test memset setup failed\n");
704 err = -ENODEV;
705 goto free_resources;
706 }
707 dma->device_issue_pending(dma_chan);
708
709 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
710
711 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
712 dev_err(dev, "Self-test memset timed out\n");
713 err = -ENODEV;
714 goto free_resources;
715 }
716
717 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
718 u32 *ptr = page_address(dest);
719 if (ptr[i]) {
720 dev_err(dev, "Self-test memset failed compare\n");
721 err = -ENODEV;
722 goto free_resources;
723 }
724 }
725
726 /* test for non-zero parity sum */
727 xor_val_result = 0;
728 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
729 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
730 DMA_TO_DEVICE);
731 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
732 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
733 &xor_val_result, DMA_PREP_INTERRUPT);
734 if (!tx) {
735 dev_err(dev, "Self-test 2nd zero prep failed\n");
736 err = -ENODEV;
737 goto free_resources;
738 }
739
740 async_tx_ack(tx);
741 init_completion(&cmp);
742 tx->callback = ioat3_dma_test_callback;
743 tx->callback_param = &cmp;
744 cookie = tx->tx_submit(tx);
745 if (cookie < 0) {
746 dev_err(dev, "Self-test 2nd zero setup failed\n");
747 err = -ENODEV;
748 goto free_resources;
749 }
750 dma->device_issue_pending(dma_chan);
751
752 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
753
754 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
755 dev_err(dev, "Self-test 2nd validate timed out\n");
756 err = -ENODEV;
757 goto free_resources;
758 }
759
760 if (xor_val_result != SUM_CHECK_P_RESULT) {
761 dev_err(dev, "Self-test validate failed compare\n");
762 err = -ENODEV;
763 goto free_resources;
764 }
765
766free_resources:
767 dma->device_free_chan_resources(dma_chan);
768out:
769 src_idx = IOAT_NUM_SRC_TEST;
770 while (src_idx--)
771 __free_page(xor_srcs[src_idx]);
772 __free_page(dest);
773 return err;
774}
775
776static int __devinit ioat3_dma_self_test(struct ioatdma_device *device)
777{
778 int rc = ioat_dma_self_test(device);
779
780 if (rc)
781 return rc;
782
783 rc = ioat_xor_val_self_test(device);
784 if (rc)
785 return rc;
786
787 return 0;
788}
789
Dan Williamsbf40a682009-09-08 17:42:55 -0700790int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
791{
792 struct pci_dev *pdev = device->pdev;
793 struct dma_device *dma;
794 struct dma_chan *c;
795 struct ioat_chan_common *chan;
796 int err;
797 u16 dev_id;
798 u32 cap;
799
800 device->enumerate_channels = ioat2_enumerate_channels;
801 device->cleanup_tasklet = ioat3_cleanup_tasklet;
802 device->timer_fn = ioat3_timer_event;
Dan Williams9de6fc72009-09-08 17:42:58 -0700803 device->self_test = ioat3_dma_self_test;
Dan Williamsbf40a682009-09-08 17:42:55 -0700804 dma = &device->common;
805 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
806 dma->device_issue_pending = ioat2_issue_pending;
807 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
808 dma->device_free_chan_resources = ioat2_free_chan_resources;
809 dma->device_is_tx_complete = ioat3_is_complete;
810 cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
811 if (cap & IOAT_CAP_FILL_BLOCK) {
812 dma_cap_set(DMA_MEMSET, dma->cap_mask);
813 dma->device_prep_dma_memset = ioat3_prep_memset_lock;
814 }
Dan Williamsb094ad32009-09-08 17:42:57 -0700815 if (cap & IOAT_CAP_XOR) {
816 dma->max_xor = 8;
817 dma->xor_align = 2;
818
819 dma_cap_set(DMA_XOR, dma->cap_mask);
820 dma->device_prep_dma_xor = ioat3_prep_xor;
821
822 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
823 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
824 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700825
826 /* -= IOAT ver.3 workarounds =- */
827 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
828 * that can cause stability issues for IOAT ver.3
829 */
830 pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
831
832 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
833 * (workaround for spurious config parity error after restart)
834 */
835 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
836 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
837 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
838
839 err = ioat_probe(device);
840 if (err)
841 return err;
842 ioat_set_tcp_copy_break(262144);
843
844 list_for_each_entry(c, &dma->channels, device_node) {
845 chan = to_chan_common(c);
846 writel(IOAT_DMA_DCA_ANY_CPU,
847 chan->reg_base + IOAT_DCACTRL_OFFSET);
848 }
849
850 err = ioat_register(device);
851 if (err)
852 return err;
Dan Williams5669e312009-09-08 17:42:56 -0700853
854 ioat_kobject_add(device, &ioat2_ktype);
855
Dan Williamsbf40a682009-09-08 17:42:55 -0700856 if (dca)
857 device->dca = ioat3_dca_init(pdev, device->reg_base);
858
859 return 0;
860}