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review.evervolv.com / android_kernel_htc_msm8960 / a0c246c82dc5d1a9ab857364522ec56627a858eb / . / drivers / gpu / drm / radeon / evergreend.h
blob: 81e744fab31a2ad3cf733829b4517f797aa8e1e2 [file] [log] [blame]
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]40/* Registers */
41
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]42#define RCU_IND_INDEX 0x100
43#define RCU_IND_DATA 0x104
44
45#define GRBM_GFX_INDEX 0x802C
46#define INSTANCE_INDEX(x) ((x) << 0)
47#define SE_INDEX(x) ((x) << 16)
48#define INSTANCE_BROADCAST_WRITES (1 << 30)
49#define SE_BROADCAST_WRITES (1 << 31)
50#define RLC_GFX_INDEX 0x3fC4
51#define CC_GC_SHADER_PIPE_CONFIG 0x8950
52#define WRITE_DIS (1 << 0)
53#define CC_RB_BACKEND_DISABLE 0x98F4
54#define BACKEND_DISABLE(x) ((x) << 16)
55#define GB_ADDR_CONFIG 0x98F8
56#define NUM_PIPES(x) ((x) << 0)
57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59#define NUM_SHADER_ENGINES(x) ((x) << 12)
60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61#define NUM_GPUS(x) ((x) << 20)
62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63#define ROW_SIZE(x) ((x) << 28)
64#define GB_BACKEND_MAP 0x98FC
65#define DMIF_ADDR_CONFIG 0xBD4
66#define HDP_ADDR_CONFIG 0x2F48
Alex Deucherf25a5c62011-05-19 11:07:57 -0400[diff] [blame]67#define HDP_MISC_CNTL 0x2F4C
68#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]69
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]70#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]71#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]72
73#define CGTS_SYS_TCC_DISABLE 0x3F90
74#define CGTS_TCC_DISABLE 0x9148
75#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
76#define CGTS_USER_TCC_DISABLE 0x914C
77
78#define CONFIG_MEMSIZE 0x5428
79
Alex Deuchera0c246c2012-08-15 17:18:42 -0400[diff] [blame^]80#define BIF_FB_EN 0x5490
81#define FB_READ_EN (1 << 0)
82#define FB_WRITE_EN (1 << 1)
83
Alex Deucherc436fd22012-11-08 10:08:04 -0500[diff] [blame]84#define CP_STRMOUT_CNTL 0x84FC
85
86#define CP_COHER_CNTL 0x85F0
87#define CP_COHER_SIZE 0x85F4
Marek Olšákdd220a02012-01-27 12:17:59 -0500[diff] [blame]88#define CP_COHER_BASE 0x85F8
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]89#define CP_ME_CNTL 0x86D8
90#define CP_ME_HALT (1 << 28)
91#define CP_PFP_HALT (1 << 26)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]92#define CP_ME_RAM_DATA 0xC160
93#define CP_ME_RAM_RADDR 0xC158
94#define CP_ME_RAM_WADDR 0xC15C
95#define CP_MEQ_THRESHOLDS 0x8764
96#define STQ_SPLIT(x) ((x) << 0)
97#define CP_PERFMON_CNTL 0x87FC
98#define CP_PFP_UCODE_ADDR 0xC150
99#define CP_PFP_UCODE_DATA 0xC154
100#define CP_QUEUE_THRESHOLDS 0x8760
101#define ROQ_IB1_START(x) ((x) << 0)
102#define ROQ_IB2_START(x) ((x) << 8)
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]103#define CP_RB_BASE 0xC100
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]104#define CP_RB_CNTL 0xC104
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]105#define RB_BUFSZ(x) ((x) << 0)
106#define RB_BLKSZ(x) ((x) << 8)
107#define RB_NO_UPDATE (1 << 27)
108#define RB_RPTR_WR_ENA (1 << 31)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]109#define BUF_SWAP_32BIT (2 << 16)
110#define CP_RB_RPTR 0x8700
111#define CP_RB_RPTR_ADDR 0xC10C
Alex Deucher0f234f52011-02-13 19:06:33 -0500[diff] [blame]112#define RB_RPTR_SWAP(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]113#define CP_RB_RPTR_ADDR_HI 0xC110
114#define CP_RB_RPTR_WR 0xC108
115#define CP_RB_WPTR 0xC114
116#define CP_RB_WPTR_ADDR 0xC118
117#define CP_RB_WPTR_ADDR_HI 0xC11C
118#define CP_RB_WPTR_DELAY 0x8704
119#define CP_SEM_WAIT_TIMER 0x85BC
Alex Deucher11ef3f12012-01-20 14:47:43 -0500[diff] [blame]120#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]121#define CP_DEBUG 0xC1FC
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]122
123
124#define GC_USER_SHADER_PIPE_CONFIG 0x8954
125#define INACTIVE_QD_PIPES(x) ((x) << 8)
126#define INACTIVE_QD_PIPES_MASK 0x0000FF00
127#define INACTIVE_SIMDS(x) ((x) << 16)
128#define INACTIVE_SIMDS_MASK 0x00FF0000
129
130#define GRBM_CNTL 0x8000
131#define GRBM_READ_TIMEOUT(x) ((x) << 0)
132#define GRBM_SOFT_RESET 0x8020
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]133#define SOFT_RESET_CP (1 << 0)
134#define SOFT_RESET_CB (1 << 1)
135#define SOFT_RESET_DB (1 << 3)
136#define SOFT_RESET_PA (1 << 5)
137#define SOFT_RESET_SC (1 << 6)
138#define SOFT_RESET_SPI (1 << 8)
139#define SOFT_RESET_SH (1 << 9)
140#define SOFT_RESET_SX (1 << 10)
141#define SOFT_RESET_TC (1 << 11)
142#define SOFT_RESET_TA (1 << 12)
143#define SOFT_RESET_VC (1 << 13)
144#define SOFT_RESET_VGT (1 << 14)
145
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]146#define GRBM_STATUS 0x8010
147#define CMDFIFO_AVAIL_MASK 0x0000000F
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]148#define SRBM_RQ_PENDING (1 << 5)
149#define CF_RQ_PENDING (1 << 7)
150#define PF_RQ_PENDING (1 << 8)
151#define GRBM_EE_BUSY (1 << 10)
152#define SX_CLEAN (1 << 11)
153#define DB_CLEAN (1 << 12)
154#define CB_CLEAN (1 << 13)
155#define TA_BUSY (1 << 14)
156#define VGT_BUSY_NO_DMA (1 << 16)
157#define VGT_BUSY (1 << 17)
158#define SX_BUSY (1 << 20)
159#define SH_BUSY (1 << 21)
160#define SPI_BUSY (1 << 22)
161#define SC_BUSY (1 << 24)
162#define PA_BUSY (1 << 25)
163#define DB_BUSY (1 << 26)
164#define CP_COHERENCY_BUSY (1 << 28)
165#define CP_BUSY (1 << 29)
166#define CB_BUSY (1 << 30)
167#define GUI_ACTIVE (1 << 31)
168#define GRBM_STATUS_SE0 0x8014
169#define GRBM_STATUS_SE1 0x8018
170#define SE_SX_CLEAN (1 << 0)
171#define SE_DB_CLEAN (1 << 1)
172#define SE_CB_CLEAN (1 << 2)
173#define SE_TA_BUSY (1 << 25)
174#define SE_SX_BUSY (1 << 26)
175#define SE_SPI_BUSY (1 << 27)
176#define SE_SH_BUSY (1 << 28)
177#define SE_SC_BUSY (1 << 29)
178#define SE_DB_BUSY (1 << 30)
179#define SE_CB_BUSY (1 << 31)
Alex Deuchere33df252010-11-22 17:56:32 -0500[diff] [blame]180/* evergreen */
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]181#define CG_THERMAL_CTRL 0x72c
182#define TOFFSET_MASK 0x00003FE0
183#define TOFFSET_SHIFT 5
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]184#define CG_MULT_THERMAL_STATUS 0x740
185#define ASIC_T(x) ((x) << 16)
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]186#define ASIC_T_MASK 0x07FF0000
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]187#define ASIC_T_SHIFT 16
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]188#define CG_TS0_STATUS 0x760
189#define TS0_ADC_DOUT_MASK 0x000003FF
190#define TS0_ADC_DOUT_SHIFT 0
Alex Deuchere33df252010-11-22 17:56:32 -0500[diff] [blame]191/* APU */
192#define CG_THERMAL_STATUS 0x678
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]193
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]194#define HDP_HOST_PATH_CNTL 0x2C00
195#define HDP_NONSURFACE_BASE 0x2C04
196#define HDP_NONSURFACE_INFO 0x2C08
197#define HDP_NONSURFACE_SIZE 0x2C0C
Alex Deucher6f2f48a2010-12-15 11:01:56 -0500[diff] [blame]198#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]199#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
200#define HDP_TILING_CONFIG 0x2F3C
201
202#define MC_SHARED_CHMAP 0x2004
203#define NOOFCHAN_SHIFT 12
204#define NOOFCHAN_MASK 0x00003000
Alex Deucher9535ab72010-11-22 17:56:18 -0500[diff] [blame]205#define MC_SHARED_CHREMAP 0x2008
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]206
Alex Deuchera0c246c2012-08-15 17:18:42 -0400[diff] [blame^]207#define MC_SHARED_BLACKOUT_CNTL 0x20ac
208#define BLACKOUT_MODE_MASK 0x00000007
209
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]210#define MC_ARB_RAMCFG 0x2760
211#define NOOFBANK_SHIFT 0
212#define NOOFBANK_MASK 0x00000003
213#define NOOFRANK_SHIFT 2
214#define NOOFRANK_MASK 0x00000004
215#define NOOFROWS_SHIFT 3
216#define NOOFROWS_MASK 0x00000038
217#define NOOFCOLS_SHIFT 6
218#define NOOFCOLS_MASK 0x000000C0
219#define CHANSIZE_SHIFT 8
220#define CHANSIZE_MASK 0x00000100
221#define BURSTLENGTH_SHIFT 9
222#define BURSTLENGTH_MASK 0x00000200
223#define CHANSIZE_OVERRIDE (1 << 11)
Alex Deucherd9282fc2011-05-11 03:15:24 -0400[diff] [blame]224#define FUS_MC_ARB_RAMCFG 0x2768
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]225#define MC_VM_AGP_TOP 0x2028
226#define MC_VM_AGP_BOT 0x202C
227#define MC_VM_AGP_BASE 0x2030
228#define MC_VM_FB_LOCATION 0x2024
Alex Deucherb4183e32010-12-15 11:04:10 -0500[diff] [blame]229#define MC_FUS_VM_FB_OFFSET 0x2898
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]230#define MC_VM_MB_L1_TLB0_CNTL 0x2234
231#define MC_VM_MB_L1_TLB1_CNTL 0x2238
232#define MC_VM_MB_L1_TLB2_CNTL 0x223C
233#define MC_VM_MB_L1_TLB3_CNTL 0x2240
234#define ENABLE_L1_TLB (1 << 0)
235#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
236#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
237#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
238#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
239#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
240#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
241#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
242#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
243#define MC_VM_MD_L1_TLB0_CNTL 0x2654
244#define MC_VM_MD_L1_TLB1_CNTL 0x2658
245#define MC_VM_MD_L1_TLB2_CNTL 0x265C
Alex Deucherfe3777a2012-05-31 18:54:43 -0400[diff] [blame]246#define MC_VM_MD_L1_TLB3_CNTL 0x2698
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400[diff] [blame]247
248#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
249#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
250#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
251
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]252#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
253#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
254#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
255
256#define PA_CL_ENHANCE 0x8A14
257#define CLIP_VTX_REORDER_ENA (1 << 0)
258#define NUM_CLIP_SEQ(x) ((x) << 1)
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]259#define PA_SC_ENHANCE 0x8BF0
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]260#define PA_SC_AA_CONFIG 0x28C04
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]261#define MSAA_NUM_SAMPLES_SHIFT 0
262#define MSAA_NUM_SAMPLES_MASK 0x3
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]263#define PA_SC_CLIPRECT_RULE 0x2820C
264#define PA_SC_EDGERULE 0x28230
265#define PA_SC_FIFO_SIZE 0x8BCC
266#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
267#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]268#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]269#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]270#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
271#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]272#define PA_SC_LINE_STIPPLE 0x28A0C
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]273#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]274#define PA_SC_LINE_STIPPLE_STATE 0x8B10
275
276#define SCRATCH_REG0 0x8500
277#define SCRATCH_REG1 0x8504
278#define SCRATCH_REG2 0x8508
279#define SCRATCH_REG3 0x850C
280#define SCRATCH_REG4 0x8510
281#define SCRATCH_REG5 0x8514
282#define SCRATCH_REG6 0x8518
283#define SCRATCH_REG7 0x851C
284#define SCRATCH_UMSK 0x8540
285#define SCRATCH_ADDR 0x8544
286
Alex Deucher789ed2a2012-06-14 22:06:36 +0200[diff] [blame]287#define SMX_SAR_CTL0 0xA008
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]288#define SMX_DC_CTL0 0xA020
289#define USE_HASH_FUNCTION (1 << 0)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]290#define NUMBER_OF_SETS(x) ((x) << 1)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]291#define FLUSH_ALL_ON_EVENT (1 << 10)
292#define STALL_ON_EVENT (1 << 11)
293#define SMX_EVENT_CTL 0xA02C
294#define ES_FLUSH_CTL(x) ((x) << 0)
295#define GS_FLUSH_CTL(x) ((x) << 3)
296#define ACK_FLUSH_CTL(x) ((x) << 6)
297#define SYNC_FLUSH_CTL (1 << 8)
298
299#define SPI_CONFIG_CNTL 0x9100
300#define GPR_WRITE_PRIORITY(x) ((x) << 0)
301#define SPI_CONFIG_CNTL_1 0x913C
302#define VTX_DONE_DELAY(x) ((x) << 0)
303#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
304#define SPI_INPUT_Z 0x286D8
305#define SPI_PS_IN_CONTROL_0 0x286CC
306#define NUM_INTERP(x) ((x)<<0)
307#define POSITION_ENA (1<<8)
308#define POSITION_CENTROID (1<<9)
309#define POSITION_ADDR(x) ((x)<<10)
310#define PARAM_GEN(x) ((x)<<15)
311#define PARAM_GEN_ADDR(x) ((x)<<19)
312#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
313#define PERSP_GRADIENT_ENA (1<<28)
314#define LINEAR_GRADIENT_ENA (1<<29)
315#define POSITION_SAMPLE (1<<30)
316#define BARYC_AT_SAMPLE_ENA (1<<31)
317
318#define SQ_CONFIG 0x8C00
319#define VC_ENABLE (1 << 0)
320#define EXPORT_SRC_C (1 << 1)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]321#define CS_PRIO(x) ((x) << 18)
322#define LS_PRIO(x) ((x) << 20)
323#define HS_PRIO(x) ((x) << 22)
324#define PS_PRIO(x) ((x) << 24)
325#define VS_PRIO(x) ((x) << 26)
326#define GS_PRIO(x) ((x) << 28)
327#define ES_PRIO(x) ((x) << 30)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]328#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
329#define NUM_PS_GPRS(x) ((x) << 0)
330#define NUM_VS_GPRS(x) ((x) << 16)
331#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
332#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
333#define NUM_GS_GPRS(x) ((x) << 0)
334#define NUM_ES_GPRS(x) ((x) << 16)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]335#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
336#define NUM_HS_GPRS(x) ((x) << 0)
337#define NUM_LS_GPRS(x) ((x) << 16)
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]338#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
339#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]340#define SQ_THREAD_RESOURCE_MGMT 0x8C18
341#define NUM_PS_THREADS(x) ((x) << 0)
342#define NUM_VS_THREADS(x) ((x) << 8)
343#define NUM_GS_THREADS(x) ((x) << 16)
344#define NUM_ES_THREADS(x) ((x) << 24)
345#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
346#define NUM_HS_THREADS(x) ((x) << 0)
347#define NUM_LS_THREADS(x) ((x) << 8)
348#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
349#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
350#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
351#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
352#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
353#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
354#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
355#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
356#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
357#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]358#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
359#define SQ_STATIC_THREAD_MGMT_1 0x8E20
360#define SQ_STATIC_THREAD_MGMT_2 0x8E24
361#define SQ_STATIC_THREAD_MGMT_3 0x8E28
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]362#define SQ_LDS_RESOURCE_MGMT 0x8E2C
363
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]364#define SQ_MS_FIFO_SIZES 0x8CF0
365#define CACHE_FIFO_SIZE(x) ((x) << 0)
366#define FETCH_FIFO_HIWATER(x) ((x) << 8)
367#define DONE_FIFO_HIWATER(x) ((x) << 16)
368#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
369
370#define SX_DEBUG_1 0x9058
371#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
372#define SX_EXPORT_BUFFER_SIZES 0x900C
373#define COLOR_BUFFER_SIZE(x) ((x) << 0)
374#define POSITION_BUFFER_SIZE(x) ((x) << 8)
375#define SMX_BUFFER_SIZE(x) ((x) << 16)
Alex Deucher033b5652011-06-08 15:26:45 -0400[diff] [blame]376#define SX_MEMORY_EXPORT_BASE 0x9010
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]377#define SX_MISC 0x28350
378
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]379#define CB_PERF_CTR0_SEL_0 0x9A20
380#define CB_PERF_CTR0_SEL_1 0x9A24
381#define CB_PERF_CTR1_SEL_0 0x9A28
382#define CB_PERF_CTR1_SEL_1 0x9A2C
383#define CB_PERF_CTR2_SEL_0 0x9A30
384#define CB_PERF_CTR2_SEL_1 0x9A34
385#define CB_PERF_CTR3_SEL_0 0x9A38
386#define CB_PERF_CTR3_SEL_1 0x9A3C
387
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]388#define TA_CNTL_AUX 0x9508
389#define DISABLE_CUBE_WRAP (1 << 0)
390#define DISABLE_CUBE_ANISO (1 << 1)
391#define SYNC_GRADIENT (1 << 24)
392#define SYNC_WALKER (1 << 25)
393#define SYNC_ALIGNER (1 << 26)
394
Alex Deucher9535ab72010-11-22 17:56:18 -0500[diff] [blame]395#define TCP_CHAN_STEER_LO 0x960c
396#define TCP_CHAN_STEER_HI 0x9610
397
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]398#define VGT_CACHE_INVALIDATION 0x88C4
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]399#define CACHE_INVALIDATION(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]400#define VC_ONLY 0
401#define TC_ONLY 1
402#define VC_AND_TC 2
403#define AUTO_INVLD_EN(x) ((x) << 6)
404#define NO_AUTO 0
405#define ES_AUTO 1
406#define GS_AUTO 2
407#define ES_AND_GS_AUTO 3
408#define VGT_GS_VERTEX_REUSE 0x88D4
409#define VGT_NUM_INSTANCES 0x8974
410#define VGT_OUT_DEALLOC_CNTL 0x28C5C
411#define DEALLOC_DIST_MASK 0x0000007F
412#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
413#define VTX_REUSE_DEPTH_MASK 0x000000FF
414
415#define VM_CONTEXT0_CNTL 0x1410
416#define ENABLE_CONTEXT (1 << 0)
417#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
418#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
419#define VM_CONTEXT1_CNTL 0x1414
420#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
421#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
422#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
423#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
424#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
425#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
426#define RESPONSE_TYPE_MASK 0x000000F0
427#define RESPONSE_TYPE_SHIFT 4
428#define VM_L2_CNTL 0x1400
429#define ENABLE_L2_CACHE (1 << 0)
430#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
431#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
432#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
433#define VM_L2_CNTL2 0x1404
434#define INVALIDATE_ALL_L1_TLBS (1 << 0)
435#define INVALIDATE_L2_CACHE (1 << 1)
436#define VM_L2_CNTL3 0x1408
437#define BANK_SELECT(x) ((x) << 0)
438#define CACHE_UPDATE_MODE(x) ((x) << 6)
439#define VM_L2_STATUS 0x140C
440#define L2_BUSY (1 << 0)
441
442#define WAIT_UNTIL 0x8040
443
444#define SRBM_STATUS 0x0E50
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]445#define SRBM_SOFT_RESET 0x0E60
446#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
447#define SOFT_RESET_BIF (1 << 1)
448#define SOFT_RESET_CG (1 << 2)
449#define SOFT_RESET_DC (1 << 5)
450#define SOFT_RESET_GRBM (1 << 8)
451#define SOFT_RESET_HDP (1 << 9)
452#define SOFT_RESET_IH (1 << 10)
453#define SOFT_RESET_MC (1 << 11)
454#define SOFT_RESET_RLC (1 << 13)
455#define SOFT_RESET_ROM (1 << 14)
456#define SOFT_RESET_SEM (1 << 15)
457#define SOFT_RESET_VMC (1 << 17)
458#define SOFT_RESET_TST (1 << 21)
459#define SOFT_RESET_REGBB (1 << 22)
460#define SOFT_RESET_ORB (1 << 23)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]461
Alex Deucherf9d9c362010-10-22 02:51:05 -0400[diff] [blame]462/* display watermarks */
463#define DC_LB_MEMORY_SPLIT 0x6b0c
464#define PRIORITY_A_CNT 0x6b18
465#define PRIORITY_MARK_MASK 0x7fff
466#define PRIORITY_OFF (1 << 16)
467#define PRIORITY_ALWAYS_ON (1 << 20)
468#define PRIORITY_B_CNT 0x6b1c
469#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
470# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
471#define PIPE0_LATENCY_CONTROL 0x0bf4
472# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
473# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
474
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]475#define IH_RB_CNTL 0x3e00
476# define IH_RB_ENABLE (1 << 0)
477# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
478# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
479# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
480# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
481# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
482# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
483#define IH_RB_BASE 0x3e04
484#define IH_RB_RPTR 0x3e08
485#define IH_RB_WPTR 0x3e0c
486# define RB_OVERFLOW (1 << 0)
487# define WPTR_OFFSET_MASK 0x3fffc
488#define IH_RB_WPTR_ADDR_HI 0x3e10
489#define IH_RB_WPTR_ADDR_LO 0x3e14
490#define IH_CNTL 0x3e18
491# define ENABLE_INTR (1 << 0)
Alex Deucherfcb857a2011-07-06 19:52:27 +0000[diff] [blame]492# define IH_MC_SWAP(x) ((x) << 1)
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]493# define IH_MC_SWAP_NONE 0
494# define IH_MC_SWAP_16BIT 1
495# define IH_MC_SWAP_32BIT 2
496# define IH_MC_SWAP_64BIT 3
497# define RPTR_REARM (1 << 4)
498# define MC_WRREQ_CREDIT(x) ((x) << 15)
499# define MC_WR_CLEAN_CNT(x) ((x) << 20)
500
501#define CP_INT_CNTL 0xc124
502# define CNTX_BUSY_INT_ENABLE (1 << 19)
503# define CNTX_EMPTY_INT_ENABLE (1 << 20)
504# define SCRATCH_INT_ENABLE (1 << 25)
505# define TIME_STAMP_INT_ENABLE (1 << 26)
506# define IB2_INT_ENABLE (1 << 29)
507# define IB1_INT_ENABLE (1 << 30)
508# define RB_INT_ENABLE (1 << 31)
509#define CP_INT_STATUS 0xc128
510# define SCRATCH_INT_STAT (1 << 25)
511# define TIME_STAMP_INT_STAT (1 << 26)
512# define IB2_INT_STAT (1 << 29)
513# define IB1_INT_STAT (1 << 30)
514# define RB_INT_STAT (1 << 31)
515
516#define GRBM_INT_CNTL 0x8060
517# define RDERR_INT_ENABLE (1 << 0)
518# define GUI_IDLE_INT_ENABLE (1 << 19)
519
520/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
521#define CRTC_STATUS_FRAME_COUNT 0x6e98
522
523/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
524#define VLINE_STATUS 0x6bb8
525# define VLINE_OCCURRED (1 << 0)
526# define VLINE_ACK (1 << 4)
527# define VLINE_STAT (1 << 12)
528# define VLINE_INTERRUPT (1 << 16)
529# define VLINE_INTERRUPT_TYPE (1 << 17)
530/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
531#define VBLANK_STATUS 0x6bbc
532# define VBLANK_OCCURRED (1 << 0)
533# define VBLANK_ACK (1 << 4)
534# define VBLANK_STAT (1 << 12)
535# define VBLANK_INTERRUPT (1 << 16)
536# define VBLANK_INTERRUPT_TYPE (1 << 17)
537
538/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
539#define INT_MASK 0x6b40
540# define VBLANK_INT_MASK (1 << 0)
541# define VLINE_INT_MASK (1 << 4)
542
543#define DISP_INTERRUPT_STATUS 0x60f4
544# define LB_D1_VLINE_INTERRUPT (1 << 2)
545# define LB_D1_VBLANK_INTERRUPT (1 << 3)
546# define DC_HPD1_INTERRUPT (1 << 17)
547# define DC_HPD1_RX_INTERRUPT (1 << 18)
548# define DACA_AUTODETECT_INTERRUPT (1 << 22)
549# define DACB_AUTODETECT_INTERRUPT (1 << 23)
550# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
551# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
552#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
553# define LB_D2_VLINE_INTERRUPT (1 << 2)
554# define LB_D2_VBLANK_INTERRUPT (1 << 3)
555# define DC_HPD2_INTERRUPT (1 << 17)
556# define DC_HPD2_RX_INTERRUPT (1 << 18)
557# define DISP_TIMER_INTERRUPT (1 << 24)
558#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
559# define LB_D3_VLINE_INTERRUPT (1 << 2)
560# define LB_D3_VBLANK_INTERRUPT (1 << 3)
561# define DC_HPD3_INTERRUPT (1 << 17)
562# define DC_HPD3_RX_INTERRUPT (1 << 18)
563#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
564# define LB_D4_VLINE_INTERRUPT (1 << 2)
565# define LB_D4_VBLANK_INTERRUPT (1 << 3)
566# define DC_HPD4_INTERRUPT (1 << 17)
567# define DC_HPD4_RX_INTERRUPT (1 << 18)
568#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
569# define LB_D5_VLINE_INTERRUPT (1 << 2)
570# define LB_D5_VBLANK_INTERRUPT (1 << 3)
571# define DC_HPD5_INTERRUPT (1 << 17)
572# define DC_HPD5_RX_INTERRUPT (1 << 18)
Alex Deucher37cba6c2011-07-06 19:37:47 +0000[diff] [blame]573#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]574# define LB_D6_VLINE_INTERRUPT (1 << 2)
575# define LB_D6_VBLANK_INTERRUPT (1 << 3)
576# define DC_HPD6_INTERRUPT (1 << 17)
577# define DC_HPD6_RX_INTERRUPT (1 << 18)
578
579/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
580#define GRPH_INT_STATUS 0x6858
581# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
582# define GRPH_PFLIP_INT_CLEAR (1 << 8)
583/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
584#define GRPH_INT_CONTROL 0x685c
585# define GRPH_PFLIP_INT_MASK (1 << 0)
586# define GRPH_PFLIP_INT_TYPE (1 << 8)
587
588#define DACA_AUTODETECT_INT_CONTROL 0x66c8
589#define DACB_AUTODETECT_INT_CONTROL 0x67c8
590
591#define DC_HPD1_INT_STATUS 0x601c
592#define DC_HPD2_INT_STATUS 0x6028
593#define DC_HPD3_INT_STATUS 0x6034
594#define DC_HPD4_INT_STATUS 0x6040
595#define DC_HPD5_INT_STATUS 0x604c
596#define DC_HPD6_INT_STATUS 0x6058
597# define DC_HPDx_INT_STATUS (1 << 0)
598# define DC_HPDx_SENSE (1 << 1)
599# define DC_HPDx_RX_INT_STATUS (1 << 8)
600
601#define DC_HPD1_INT_CONTROL 0x6020
602#define DC_HPD2_INT_CONTROL 0x602c
603#define DC_HPD3_INT_CONTROL 0x6038
604#define DC_HPD4_INT_CONTROL 0x6044
605#define DC_HPD5_INT_CONTROL 0x6050
606#define DC_HPD6_INT_CONTROL 0x605c
607# define DC_HPDx_INT_ACK (1 << 0)
608# define DC_HPDx_INT_POLARITY (1 << 8)
609# define DC_HPDx_INT_EN (1 << 16)
610# define DC_HPDx_RX_INT_ACK (1 << 20)
611# define DC_HPDx_RX_INT_EN (1 << 24)
612
613#define DC_HPD1_CONTROL 0x6024
614#define DC_HPD2_CONTROL 0x6030
615#define DC_HPD3_CONTROL 0x603c
616#define DC_HPD4_CONTROL 0x6048
617#define DC_HPD5_CONTROL 0x6054
618#define DC_HPD6_CONTROL 0x6060
619# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
620# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
621# define DC_HPDx_EN (1 << 28)
622
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]623/* PCIE link stuff */
624#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
625#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
626# define LC_LINK_WIDTH_SHIFT 0
627# define LC_LINK_WIDTH_MASK 0x7
628# define LC_LINK_WIDTH_X0 0
629# define LC_LINK_WIDTH_X1 1
630# define LC_LINK_WIDTH_X2 2
631# define LC_LINK_WIDTH_X4 3
632# define LC_LINK_WIDTH_X8 4
633# define LC_LINK_WIDTH_X16 6
634# define LC_LINK_WIDTH_RD_SHIFT 4
635# define LC_LINK_WIDTH_RD_MASK 0x70
636# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
637# define LC_RECONFIG_NOW (1 << 8)
638# define LC_RENEGOTIATION_SUPPORT (1 << 9)
639# define LC_RENEGOTIATE_EN (1 << 10)
640# define LC_SHORT_RECONFIG_EN (1 << 11)
641# define LC_UPCONFIGURE_SUPPORT (1 << 12)
642# define LC_UPCONFIGURE_DIS (1 << 13)
643#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
644# define LC_GEN2_EN_STRAP (1 << 0)
645# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
646# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
647# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
648# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
649# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
650# define LC_CURRENT_DATA_RATE (1 << 11)
651# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
652# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
653# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
654# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
655#define MM_CFGREGS_CNTL 0x544c
656# define MM_WR_TO_CFG_EN (1 << 3)
657#define LINK_CNTL2 0x88 /* F0 */
658# define TARGET_LINK_SPEED_MASK (0xf << 0)
659# define SELECTABLE_DEEMPHASIS (1 << 6)
660
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]661/*
662 * PM4
663 */
664#define PACKET_TYPE0 0
665#define PACKET_TYPE1 1
666#define PACKET_TYPE2 2
667#define PACKET_TYPE3 3
668
669#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
670#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
671#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
672#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
673#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
674 (((reg) >> 2) & 0xFFFF) | \
675 ((n) & 0x3FFF) << 16)
676#define CP_PACKET2 0x80000000
677#define PACKET2_PAD_SHIFT 0
678#define PACKET2_PAD_MASK (0x3fffffff << 0)
679
680#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
681
682#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
683 (((op) & 0xFF) << 8) | \
684 ((n) & 0x3FFF) << 16)
685
686/* Packet 3 types */
687#define PACKET3_NOP 0x10
688#define PACKET3_SET_BASE 0x11
689#define PACKET3_CLEAR_STATE 0x12
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]690#define PACKET3_INDEX_BUFFER_SIZE 0x13
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]691#define PACKET3_DISPATCH_DIRECT 0x15
692#define PACKET3_DISPATCH_INDIRECT 0x16
693#define PACKET3_INDIRECT_BUFFER_END 0x17
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]694#define PACKET3_MODE_CONTROL 0x18
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]695#define PACKET3_SET_PREDICATION 0x20
696#define PACKET3_REG_RMW 0x21
697#define PACKET3_COND_EXEC 0x22
698#define PACKET3_PRED_EXEC 0x23
699#define PACKET3_DRAW_INDIRECT 0x24
700#define PACKET3_DRAW_INDEX_INDIRECT 0x25
701#define PACKET3_INDEX_BASE 0x26
702#define PACKET3_DRAW_INDEX_2 0x27
703#define PACKET3_CONTEXT_CONTROL 0x28
704#define PACKET3_DRAW_INDEX_OFFSET 0x29
705#define PACKET3_INDEX_TYPE 0x2A
706#define PACKET3_DRAW_INDEX 0x2B
707#define PACKET3_DRAW_INDEX_AUTO 0x2D
708#define PACKET3_DRAW_INDEX_IMMD 0x2E
709#define PACKET3_NUM_INSTANCES 0x2F
710#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
711#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
712#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
713#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
714#define PACKET3_MEM_SEMAPHORE 0x39
715#define PACKET3_MPEG_INDEX 0x3A
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]716#define PACKET3_COPY_DW 0x3B
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]717#define PACKET3_WAIT_REG_MEM 0x3C
718#define PACKET3_MEM_WRITE 0x3D
719#define PACKET3_INDIRECT_BUFFER 0x32
720#define PACKET3_SURFACE_SYNC 0x43
721# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
722# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
723# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
724# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
725# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
726# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
727# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
728# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
729# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
730# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
731# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
732# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]733# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]734# define PACKET3_FULL_CACHE_ENA (1 << 20)
735# define PACKET3_TC_ACTION_ENA (1 << 23)
736# define PACKET3_VC_ACTION_ENA (1 << 24)
737# define PACKET3_CB_ACTION_ENA (1 << 25)
738# define PACKET3_DB_ACTION_ENA (1 << 26)
739# define PACKET3_SH_ACTION_ENA (1 << 27)
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]740# define PACKET3_SX_ACTION_ENA (1 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]741#define PACKET3_ME_INITIALIZE 0x44
742#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
743#define PACKET3_COND_WRITE 0x45
744#define PACKET3_EVENT_WRITE 0x46
745#define PACKET3_EVENT_WRITE_EOP 0x47
746#define PACKET3_EVENT_WRITE_EOS 0x48
747#define PACKET3_PREAMBLE_CNTL 0x4A
Alex Deucher2281a372010-10-21 13:31:38 -0400[diff] [blame]748# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
749# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]750#define PACKET3_RB_OFFSET 0x4B
751#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
752#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
753#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
754#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
755#define PACKET3_ONE_REG_WRITE 0x57
756#define PACKET3_SET_CONFIG_REG 0x68
757#define PACKET3_SET_CONFIG_REG_START 0x00008000
758#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
759#define PACKET3_SET_CONTEXT_REG 0x69
760#define PACKET3_SET_CONTEXT_REG_START 0x00028000
761#define PACKET3_SET_CONTEXT_REG_END 0x00029000
762#define PACKET3_SET_ALU_CONST 0x6A
763/* alu const buffers only; no reg file */
764#define PACKET3_SET_BOOL_CONST 0x6B
765#define PACKET3_SET_BOOL_CONST_START 0x0003a500
766#define PACKET3_SET_BOOL_CONST_END 0x0003a518
767#define PACKET3_SET_LOOP_CONST 0x6C
768#define PACKET3_SET_LOOP_CONST_START 0x0003a200
769#define PACKET3_SET_LOOP_CONST_END 0x0003a500
770#define PACKET3_SET_RESOURCE 0x6D
771#define PACKET3_SET_RESOURCE_START 0x00030000
772#define PACKET3_SET_RESOURCE_END 0x00038000
773#define PACKET3_SET_SAMPLER 0x6E
774#define PACKET3_SET_SAMPLER_START 0x0003c000
775#define PACKET3_SET_SAMPLER_END 0x0003c600
776#define PACKET3_SET_CTL_CONST 0x6F
777#define PACKET3_SET_CTL_CONST_START 0x0003cff0
778#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
779#define PACKET3_SET_RESOURCE_OFFSET 0x70
780#define PACKET3_SET_ALU_CONST_VS 0x71
781#define PACKET3_SET_ALU_CONST_DI 0x72
782#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
783#define PACKET3_SET_RESOURCE_INDIRECT 0x74
784#define PACKET3_SET_APPEND_CNT 0x75
785
786#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
787#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
788#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
789#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
790#define SQ_TEX_VTX_INVALID_BUFFER 0x1
791#define SQ_TEX_VTX_VALID_TEXTURE 0x2
792#define SQ_TEX_VTX_VALID_BUFFER 0x3
793
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]794#define VGT_VTX_VECT_EJECT_REG 0x88b0
795
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]796#define SQ_CONST_MEM_BASE 0x8df8
797
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]798#define SQ_ESGS_RING_BASE 0x8c40
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]799#define SQ_ESGS_RING_SIZE 0x8c44
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]800#define SQ_GSVS_RING_BASE 0x8c48
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]801#define SQ_GSVS_RING_SIZE 0x8c4c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]802#define SQ_ESTMP_RING_BASE 0x8c50
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]803#define SQ_ESTMP_RING_SIZE 0x8c54
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]804#define SQ_GSTMP_RING_BASE 0x8c58
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]805#define SQ_GSTMP_RING_SIZE 0x8c5c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]806#define SQ_VSTMP_RING_BASE 0x8c60
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]807#define SQ_VSTMP_RING_SIZE 0x8c64
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]808#define SQ_PSTMP_RING_BASE 0x8c68
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]809#define SQ_PSTMP_RING_SIZE 0x8c6c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]810#define SQ_LSTMP_RING_BASE 0x8e10
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]811#define SQ_LSTMP_RING_SIZE 0x8e14
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]812#define SQ_HSTMP_RING_BASE 0x8e18
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]813#define SQ_HSTMP_RING_SIZE 0x8e1c
814#define VGT_TF_RING_SIZE 0x8988
815
816#define SQ_ESGS_RING_ITEMSIZE 0x28900
817#define SQ_GSVS_RING_ITEMSIZE 0x28904
818#define SQ_ESTMP_RING_ITEMSIZE 0x28908
819#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
820#define SQ_VSTMP_RING_ITEMSIZE 0x28910
821#define SQ_PSTMP_RING_ITEMSIZE 0x28914
822#define SQ_LSTMP_RING_ITEMSIZE 0x28830
823#define SQ_HSTMP_RING_ITEMSIZE 0x28834
824
825#define SQ_GS_VERT_ITEMSIZE 0x2891c
826#define SQ_GS_VERT_ITEMSIZE_1 0x28920
827#define SQ_GS_VERT_ITEMSIZE_2 0x28924
828#define SQ_GS_VERT_ITEMSIZE_3 0x28928
829#define SQ_GSVS_RING_OFFSET_1 0x2892c
830#define SQ_GSVS_RING_OFFSET_2 0x28930
831#define SQ_GSVS_RING_OFFSET_3 0x28934
832
Alex Deucher60a4a3e2010-06-29 17:03:35 -0400[diff] [blame]833#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
834#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
835
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]836#define SQ_ALU_CONST_CACHE_PS_0 0x28940
837#define SQ_ALU_CONST_CACHE_PS_1 0x28944
838#define SQ_ALU_CONST_CACHE_PS_2 0x28948
839#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
840#define SQ_ALU_CONST_CACHE_PS_4 0x28950
841#define SQ_ALU_CONST_CACHE_PS_5 0x28954
842#define SQ_ALU_CONST_CACHE_PS_6 0x28958
843#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
844#define SQ_ALU_CONST_CACHE_PS_8 0x28960
845#define SQ_ALU_CONST_CACHE_PS_9 0x28964
846#define SQ_ALU_CONST_CACHE_PS_10 0x28968
847#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
848#define SQ_ALU_CONST_CACHE_PS_12 0x28970
849#define SQ_ALU_CONST_CACHE_PS_13 0x28974
850#define SQ_ALU_CONST_CACHE_PS_14 0x28978
851#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
852#define SQ_ALU_CONST_CACHE_VS_0 0x28980
853#define SQ_ALU_CONST_CACHE_VS_1 0x28984
854#define SQ_ALU_CONST_CACHE_VS_2 0x28988
855#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
856#define SQ_ALU_CONST_CACHE_VS_4 0x28990
857#define SQ_ALU_CONST_CACHE_VS_5 0x28994
858#define SQ_ALU_CONST_CACHE_VS_6 0x28998
859#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
860#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
861#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
862#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
863#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
864#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
865#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
866#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
867#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
868#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
869#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
870#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
871#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
872#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
873#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
874#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
875#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
876#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
877#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
878#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
879#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
880#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
881#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
882#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
883#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
884#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
885#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
886#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
887#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
888#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
889#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
890#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
891#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
892#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
893#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
894#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
895#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
896#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
897#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
898#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
899#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
900#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
901#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
902#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
903#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
904#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
905#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
906#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
907#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
908#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
909#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
910#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
911#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
912#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
913#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
914#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
915#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
916
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400[diff] [blame]917#define PA_SC_SCREEN_SCISSOR_TL 0x28030
918#define PA_SC_GENERIC_SCISSOR_TL 0x28240
919#define PA_SC_WINDOW_SCISSOR_TL 0x28204
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400[diff] [blame]920
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]921#define VGT_PRIMITIVE_TYPE 0x8958
922#define VGT_INDEX_TYPE 0x895C
923
924#define VGT_NUM_INDICES 0x8970
925
926#define VGT_COMPUTE_DIM_X 0x8990
927#define VGT_COMPUTE_DIM_Y 0x8994
928#define VGT_COMPUTE_DIM_Z 0x8998
929#define VGT_COMPUTE_START_X 0x899C
930#define VGT_COMPUTE_START_Y 0x89A0
931#define VGT_COMPUTE_START_Z 0x89A4
932#define VGT_COMPUTE_INDEX 0x89A8
933#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
934#define VGT_HS_OFFCHIP_PARAM 0x89B0
935
936#define DB_DEBUG 0x9830
937#define DB_DEBUG2 0x9834
938#define DB_DEBUG3 0x9838
939#define DB_DEBUG4 0x983C
940#define DB_WATERMARKS 0x9854
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]941#define DB_DEPTH_CONTROL 0x28800
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]942#define R_028800_DB_DEPTH_CONTROL 0x028800
943#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
944#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
945#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
946#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
947#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
948#define C_028800_Z_ENABLE 0xFFFFFFFD
949#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
950#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
951#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
952#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
953#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
954#define C_028800_ZFUNC 0xFFFFFF8F
955#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
956#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
957#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
958#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
959#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
960#define C_028800_STENCILFUNC 0xFFFFF8FF
961#define V_028800_STENCILFUNC_NEVER 0x00000000
962#define V_028800_STENCILFUNC_LESS 0x00000001
963#define V_028800_STENCILFUNC_EQUAL 0x00000002
964#define V_028800_STENCILFUNC_LEQUAL 0x00000003
965#define V_028800_STENCILFUNC_GREATER 0x00000004
966#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
967#define V_028800_STENCILFUNC_GEQUAL 0x00000006
968#define V_028800_STENCILFUNC_ALWAYS 0x00000007
969#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
970#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
971#define C_028800_STENCILFAIL 0xFFFFC7FF
972#define V_028800_STENCIL_KEEP 0x00000000
973#define V_028800_STENCIL_ZERO 0x00000001
974#define V_028800_STENCIL_REPLACE 0x00000002
975#define V_028800_STENCIL_INCR 0x00000003
976#define V_028800_STENCIL_DECR 0x00000004
977#define V_028800_STENCIL_INVERT 0x00000005
978#define V_028800_STENCIL_INCR_WRAP 0x00000006
979#define V_028800_STENCIL_DECR_WRAP 0x00000007
980#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
981#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
982#define C_028800_STENCILZPASS 0xFFFE3FFF
983#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
984#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
985#define C_028800_STENCILZFAIL 0xFFF1FFFF
986#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
987#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
988#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
989#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
990#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
991#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
992#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
993#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
994#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
995#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
996#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
997#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]998#define DB_DEPTH_VIEW 0x28008
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]999#define R_028008_DB_DEPTH_VIEW 0x00028008
1000#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
1001#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
1002#define C_028008_SLICE_START 0xFFFFF800
1003#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1004#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1005#define C_028008_SLICE_MAX 0xFF001FFF
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1006#define DB_HTILE_DATA_BASE 0x28014
Jerome Glisse88f50c82012-03-21 19:18:21 -0400[diff] [blame]1007#define DB_HTILE_SURFACE 0x28abc
1008#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1009#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1010#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1011#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1012#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1013#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1014#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1015#define DB_Z_INFO 0x28040
1016# define Z_ARRAY_MODE(x) ((x) << 4)
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1017# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1018# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1019# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1020# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1021# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1022#define R_028040_DB_Z_INFO 0x028040
1023#define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1024#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1025#define C_028040_FORMAT 0xFFFFFFFC
1026#define V_028040_Z_INVALID 0x00000000
1027#define V_028040_Z_16 0x00000001
1028#define V_028040_Z_24 0x00000002
1029#define V_028040_Z_32_FLOAT 0x00000003
1030#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1031#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1032#define C_028040_ARRAY_MODE 0xFFFFFF0F
1033#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1034#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1035#define C_028040_READ_SIZE 0xEFFFFFFF
1036#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1037#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1038#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1039#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1040#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1041#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1042#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1043#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1044#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1045#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1046#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1047#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1048#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1049#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1050#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1051#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1052#define DB_STENCIL_INFO 0x28044
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1053#define R_028044_DB_STENCIL_INFO 0x028044
1054#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1055#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1056#define C_028044_FORMAT 0xFFFFFFFE
1057#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1058#define DB_Z_READ_BASE 0x28048
1059#define DB_STENCIL_READ_BASE 0x2804c
1060#define DB_Z_WRITE_BASE 0x28050
1061#define DB_STENCIL_WRITE_BASE 0x28054
1062#define DB_DEPTH_SIZE 0x28058
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1063#define R_028058_DB_DEPTH_SIZE 0x028058
1064#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1065#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1066#define C_028058_PITCH_TILE_MAX 0xFFFFF800
1067#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1068#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1069#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1070#define R_02805C_DB_DEPTH_SLICE 0x02805C
1071#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1072#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1073#define C_02805C_SLICE_TILE_MAX 0xFFC00000
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1074
1075#define SQ_PGM_START_PS 0x28840
1076#define SQ_PGM_START_VS 0x2885c
1077#define SQ_PGM_START_GS 0x28874
1078#define SQ_PGM_START_ES 0x2888c
1079#define SQ_PGM_START_FS 0x288a4
1080#define SQ_PGM_START_HS 0x288b8
1081#define SQ_PGM_START_LS 0x288d0
1082
Marek Olšákdd220a02012-01-27 12:17:59 -0500[diff] [blame]1083#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1084#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1085#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1086#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1087#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1088#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1089#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1090#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1091#define VGT_STRMOUT_CONFIG 0x28b94
1092#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
1093
1094#define CB_TARGET_MASK 0x28238
1095#define CB_SHADER_MASK 0x2823c
1096
1097#define GDS_ADDR_BASE 0x28720
1098
1099#define CB_IMMED0_BASE 0x28b9c
1100#define CB_IMMED1_BASE 0x28ba0
1101#define CB_IMMED2_BASE 0x28ba4
1102#define CB_IMMED3_BASE 0x28ba8
1103#define CB_IMMED4_BASE 0x28bac
1104#define CB_IMMED5_BASE 0x28bb0
1105#define CB_IMMED6_BASE 0x28bb4
1106#define CB_IMMED7_BASE 0x28bb8
1107#define CB_IMMED8_BASE 0x28bbc
1108#define CB_IMMED9_BASE 0x28bc0
1109#define CB_IMMED10_BASE 0x28bc4
1110#define CB_IMMED11_BASE 0x28bc8
1111
1112/* all 12 CB blocks have these regs */
1113#define CB_COLOR0_BASE 0x28c60
1114#define CB_COLOR0_PITCH 0x28c64
1115#define CB_COLOR0_SLICE 0x28c68
1116#define CB_COLOR0_VIEW 0x28c6c
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1117#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
1118#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
1119#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
1120#define C_028C6C_SLICE_START 0xFFFFF800
1121#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1122#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1123#define C_028C6C_SLICE_MAX 0xFF001FFF
1124#define R_028C70_CB_COLOR0_INFO 0x028C70
1125#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
1126#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
1127#define C_028C70_ENDIAN 0xFFFFFFFC
1128#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
1129#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
1130#define C_028C70_FORMAT 0xFFFFFF03
1131#define V_028C70_COLOR_INVALID 0x00000000
1132#define V_028C70_COLOR_8 0x00000001
1133#define V_028C70_COLOR_4_4 0x00000002
1134#define V_028C70_COLOR_3_3_2 0x00000003
1135#define V_028C70_COLOR_16 0x00000005
1136#define V_028C70_COLOR_16_FLOAT 0x00000006
1137#define V_028C70_COLOR_8_8 0x00000007
1138#define V_028C70_COLOR_5_6_5 0x00000008
1139#define V_028C70_COLOR_6_5_5 0x00000009
1140#define V_028C70_COLOR_1_5_5_5 0x0000000A
1141#define V_028C70_COLOR_4_4_4_4 0x0000000B
1142#define V_028C70_COLOR_5_5_5_1 0x0000000C
1143#define V_028C70_COLOR_32 0x0000000D
1144#define V_028C70_COLOR_32_FLOAT 0x0000000E
1145#define V_028C70_COLOR_16_16 0x0000000F
1146#define V_028C70_COLOR_16_16_FLOAT 0x00000010
1147#define V_028C70_COLOR_8_24 0x00000011
1148#define V_028C70_COLOR_8_24_FLOAT 0x00000012
1149#define V_028C70_COLOR_24_8 0x00000013
1150#define V_028C70_COLOR_24_8_FLOAT 0x00000014
1151#define V_028C70_COLOR_10_11_11 0x00000015
1152#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
1153#define V_028C70_COLOR_11_11_10 0x00000017
1154#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
1155#define V_028C70_COLOR_2_10_10_10 0x00000019
1156#define V_028C70_COLOR_8_8_8_8 0x0000001A
1157#define V_028C70_COLOR_10_10_10_2 0x0000001B
1158#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
1159#define V_028C70_COLOR_32_32 0x0000001D
1160#define V_028C70_COLOR_32_32_FLOAT 0x0000001E
1161#define V_028C70_COLOR_16_16_16_16 0x0000001F
1162#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
1163#define V_028C70_COLOR_32_32_32_32 0x00000022
1164#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
1165#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
1166#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
1167#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1168#define C_028C70_ARRAY_MODE 0xFFFFF0FF
1169#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
1170#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
1171#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
1172#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
1173#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1174#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1175#define C_028C70_NUMBER_TYPE 0xFFFF8FFF
1176#define V_028C70_NUMBER_UNORM 0x00000000
1177#define V_028C70_NUMBER_SNORM 0x00000001
1178#define V_028C70_NUMBER_USCALED 0x00000002
1179#define V_028C70_NUMBER_SSCALED 0x00000003
1180#define V_028C70_NUMBER_UINT 0x00000004
1181#define V_028C70_NUMBER_SINT 0x00000005
1182#define V_028C70_NUMBER_SRGB 0x00000006
1183#define V_028C70_NUMBER_FLOAT 0x00000007
1184#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
1185#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
1186#define C_028C70_COMP_SWAP 0xFFFE7FFF
1187#define V_028C70_SWAP_STD 0x00000000
1188#define V_028C70_SWAP_ALT 0x00000001
1189#define V_028C70_SWAP_STD_REV 0x00000002
1190#define V_028C70_SWAP_ALT_REV 0x00000003
1191#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
1192#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
1193#define C_028C70_FAST_CLEAR 0xFFFDFFFF
1194#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
1195#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
1196#define C_028C70_COMPRESSION 0xFFF3FFFF
1197#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
1198#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
1199#define C_028C70_BLEND_CLAMP 0xFFF7FFFF
1200#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
1201#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
1202#define C_028C70_BLEND_BYPASS 0xFFEFFFFF
1203#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
1204#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
1205#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
1206#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
1207#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
1208#define C_028C70_ROUND_MODE 0xFFBFFFFF
1209#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
1210#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
1211#define C_028C70_TILE_COMPACT 0xFF7FFFFF
1212#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
1213#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
1214#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
1215#define V_028C70_EXPORT_4C_32BPC 0x0
1216#define V_028C70_EXPORT_4C_16BPC 0x1
1217#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
1218#define S_028C70_RAT(x) (((x) & 0x1) << 26)
1219#define G_028C70_RAT(x) (((x) >> 26) & 0x1)
1220#define C_028C70_RAT 0xFBFFFFFF
1221#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
1222#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
1223#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
1224
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1225#define CB_COLOR0_INFO 0x28c70
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1226# define CB_FORMAT(x) ((x) << 2)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1227# define CB_ARRAY_MODE(x) ((x) << 8)
1228# define ARRAY_LINEAR_GENERAL 0
1229# define ARRAY_LINEAR_ALIGNED 1
1230# define ARRAY_1D_TILED_THIN1 2
1231# define ARRAY_2D_TILED_THIN1 4
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1232# define CB_SOURCE_FORMAT(x) ((x) << 24)
1233# define CB_SF_EXPORT_FULL 0
1234# define CB_SF_EXPORT_NORM 1
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1235#define R_028C74_CB_COLOR0_ATTRIB 0x028C74
1236#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
1237#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
1238#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
1239#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
1240#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
1241#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
1242#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
1243#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
1244#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
1245#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1246#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
1247#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1248#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1249#define CB_COLOR0_ATTRIB 0x28c74
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1250# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
1251# define ADDR_SURF_TILE_SPLIT_64B 0
1252# define ADDR_SURF_TILE_SPLIT_128B 1
1253# define ADDR_SURF_TILE_SPLIT_256B 2
1254# define ADDR_SURF_TILE_SPLIT_512B 3
1255# define ADDR_SURF_TILE_SPLIT_1KB 4
1256# define ADDR_SURF_TILE_SPLIT_2KB 5
1257# define ADDR_SURF_TILE_SPLIT_4KB 6
1258# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
1259# define ADDR_SURF_2_BANK 0
1260# define ADDR_SURF_4_BANK 1
1261# define ADDR_SURF_8_BANK 2
1262# define ADDR_SURF_16_BANK 3
1263# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
1264# define ADDR_SURF_BANK_WIDTH_1 0
1265# define ADDR_SURF_BANK_WIDTH_2 1
1266# define ADDR_SURF_BANK_WIDTH_4 2
1267# define ADDR_SURF_BANK_WIDTH_8 3
1268# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1269# define ADDR_SURF_BANK_HEIGHT_1 0
1270# define ADDR_SURF_BANK_HEIGHT_2 1
1271# define ADDR_SURF_BANK_HEIGHT_4 2
1272# define ADDR_SURF_BANK_HEIGHT_8 3
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1273# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1274#define CB_COLOR0_DIM 0x28c78
1275/* only CB0-7 blocks have these regs */
1276#define CB_COLOR0_CMASK 0x28c7c
1277#define CB_COLOR0_CMASK_SLICE 0x28c80
1278#define CB_COLOR0_FMASK 0x28c84
1279#define CB_COLOR0_FMASK_SLICE 0x28c88
1280#define CB_COLOR0_CLEAR_WORD0 0x28c8c
1281#define CB_COLOR0_CLEAR_WORD1 0x28c90
1282#define CB_COLOR0_CLEAR_WORD2 0x28c94
1283#define CB_COLOR0_CLEAR_WORD3 0x28c98
1284
1285#define CB_COLOR1_BASE 0x28c9c
1286#define CB_COLOR2_BASE 0x28cd8
1287#define CB_COLOR3_BASE 0x28d14
1288#define CB_COLOR4_BASE 0x28d50
1289#define CB_COLOR5_BASE 0x28d8c
1290#define CB_COLOR6_BASE 0x28dc8
1291#define CB_COLOR7_BASE 0x28e04
1292#define CB_COLOR8_BASE 0x28e40
1293#define CB_COLOR9_BASE 0x28e5c
1294#define CB_COLOR10_BASE 0x28e78
1295#define CB_COLOR11_BASE 0x28e94
1296
1297#define CB_COLOR1_PITCH 0x28ca0
1298#define CB_COLOR2_PITCH 0x28cdc
1299#define CB_COLOR3_PITCH 0x28d18
1300#define CB_COLOR4_PITCH 0x28d54
1301#define CB_COLOR5_PITCH 0x28d90
1302#define CB_COLOR6_PITCH 0x28dcc
1303#define CB_COLOR7_PITCH 0x28e08
1304#define CB_COLOR8_PITCH 0x28e44
1305#define CB_COLOR9_PITCH 0x28e60
1306#define CB_COLOR10_PITCH 0x28e7c
1307#define CB_COLOR11_PITCH 0x28e98
1308
1309#define CB_COLOR1_SLICE 0x28ca4
1310#define CB_COLOR2_SLICE 0x28ce0
1311#define CB_COLOR3_SLICE 0x28d1c
1312#define CB_COLOR4_SLICE 0x28d58
1313#define CB_COLOR5_SLICE 0x28d94
1314#define CB_COLOR6_SLICE 0x28dd0
1315#define CB_COLOR7_SLICE 0x28e0c
1316#define CB_COLOR8_SLICE 0x28e48
1317#define CB_COLOR9_SLICE 0x28e64
1318#define CB_COLOR10_SLICE 0x28e80
1319#define CB_COLOR11_SLICE 0x28e9c
1320
1321#define CB_COLOR1_VIEW 0x28ca8
1322#define CB_COLOR2_VIEW 0x28ce4
1323#define CB_COLOR3_VIEW 0x28d20
1324#define CB_COLOR4_VIEW 0x28d5c
1325#define CB_COLOR5_VIEW 0x28d98
1326#define CB_COLOR6_VIEW 0x28dd4
1327#define CB_COLOR7_VIEW 0x28e10
1328#define CB_COLOR8_VIEW 0x28e4c
1329#define CB_COLOR9_VIEW 0x28e68
1330#define CB_COLOR10_VIEW 0x28e84
1331#define CB_COLOR11_VIEW 0x28ea0
1332
1333#define CB_COLOR1_INFO 0x28cac
1334#define CB_COLOR2_INFO 0x28ce8
1335#define CB_COLOR3_INFO 0x28d24
1336#define CB_COLOR4_INFO 0x28d60
1337#define CB_COLOR5_INFO 0x28d9c
1338#define CB_COLOR6_INFO 0x28dd8
1339#define CB_COLOR7_INFO 0x28e14
1340#define CB_COLOR8_INFO 0x28e50
1341#define CB_COLOR9_INFO 0x28e6c
1342#define CB_COLOR10_INFO 0x28e88
1343#define CB_COLOR11_INFO 0x28ea4
1344
1345#define CB_COLOR1_ATTRIB 0x28cb0
1346#define CB_COLOR2_ATTRIB 0x28cec
1347#define CB_COLOR3_ATTRIB 0x28d28
1348#define CB_COLOR4_ATTRIB 0x28d64
1349#define CB_COLOR5_ATTRIB 0x28da0
1350#define CB_COLOR6_ATTRIB 0x28ddc
1351#define CB_COLOR7_ATTRIB 0x28e18
1352#define CB_COLOR8_ATTRIB 0x28e54
1353#define CB_COLOR9_ATTRIB 0x28e70
1354#define CB_COLOR10_ATTRIB 0x28e8c
1355#define CB_COLOR11_ATTRIB 0x28ea8
1356
1357#define CB_COLOR1_DIM 0x28cb4
1358#define CB_COLOR2_DIM 0x28cf0
1359#define CB_COLOR3_DIM 0x28d2c
1360#define CB_COLOR4_DIM 0x28d68
1361#define CB_COLOR5_DIM 0x28da4
1362#define CB_COLOR6_DIM 0x28de0
1363#define CB_COLOR7_DIM 0x28e1c
1364#define CB_COLOR8_DIM 0x28e58
1365#define CB_COLOR9_DIM 0x28e74
1366#define CB_COLOR10_DIM 0x28e90
1367#define CB_COLOR11_DIM 0x28eac
1368
1369#define CB_COLOR1_CMASK 0x28cb8
1370#define CB_COLOR2_CMASK 0x28cf4
1371#define CB_COLOR3_CMASK 0x28d30
1372#define CB_COLOR4_CMASK 0x28d6c
1373#define CB_COLOR5_CMASK 0x28da8
1374#define CB_COLOR6_CMASK 0x28de4
1375#define CB_COLOR7_CMASK 0x28e20
1376
1377#define CB_COLOR1_CMASK_SLICE 0x28cbc
1378#define CB_COLOR2_CMASK_SLICE 0x28cf8
1379#define CB_COLOR3_CMASK_SLICE 0x28d34
1380#define CB_COLOR4_CMASK_SLICE 0x28d70
1381#define CB_COLOR5_CMASK_SLICE 0x28dac
1382#define CB_COLOR6_CMASK_SLICE 0x28de8
1383#define CB_COLOR7_CMASK_SLICE 0x28e24
1384
1385#define CB_COLOR1_FMASK 0x28cc0
1386#define CB_COLOR2_FMASK 0x28cfc
1387#define CB_COLOR3_FMASK 0x28d38
1388#define CB_COLOR4_FMASK 0x28d74
1389#define CB_COLOR5_FMASK 0x28db0
1390#define CB_COLOR6_FMASK 0x28dec
1391#define CB_COLOR7_FMASK 0x28e28
1392
1393#define CB_COLOR1_FMASK_SLICE 0x28cc4
1394#define CB_COLOR2_FMASK_SLICE 0x28d00
1395#define CB_COLOR3_FMASK_SLICE 0x28d3c
1396#define CB_COLOR4_FMASK_SLICE 0x28d78
1397#define CB_COLOR5_FMASK_SLICE 0x28db4
1398#define CB_COLOR6_FMASK_SLICE 0x28df0
1399#define CB_COLOR7_FMASK_SLICE 0x28e2c
1400
1401#define CB_COLOR1_CLEAR_WORD0 0x28cc8
1402#define CB_COLOR2_CLEAR_WORD0 0x28d04
1403#define CB_COLOR3_CLEAR_WORD0 0x28d40
1404#define CB_COLOR4_CLEAR_WORD0 0x28d7c
1405#define CB_COLOR5_CLEAR_WORD0 0x28db8
1406#define CB_COLOR6_CLEAR_WORD0 0x28df4
1407#define CB_COLOR7_CLEAR_WORD0 0x28e30
1408
1409#define CB_COLOR1_CLEAR_WORD1 0x28ccc
1410#define CB_COLOR2_CLEAR_WORD1 0x28d08
1411#define CB_COLOR3_CLEAR_WORD1 0x28d44
1412#define CB_COLOR4_CLEAR_WORD1 0x28d80
1413#define CB_COLOR5_CLEAR_WORD1 0x28dbc
1414#define CB_COLOR6_CLEAR_WORD1 0x28df8
1415#define CB_COLOR7_CLEAR_WORD1 0x28e34
1416
1417#define CB_COLOR1_CLEAR_WORD2 0x28cd0
1418#define CB_COLOR2_CLEAR_WORD2 0x28d0c
1419#define CB_COLOR3_CLEAR_WORD2 0x28d48
1420#define CB_COLOR4_CLEAR_WORD2 0x28d84
1421#define CB_COLOR5_CLEAR_WORD2 0x28dc0
1422#define CB_COLOR6_CLEAR_WORD2 0x28dfc
1423#define CB_COLOR7_CLEAR_WORD2 0x28e38
1424
1425#define CB_COLOR1_CLEAR_WORD3 0x28cd4
1426#define CB_COLOR2_CLEAR_WORD3 0x28d10
1427#define CB_COLOR3_CLEAR_WORD3 0x28d4c
1428#define CB_COLOR4_CLEAR_WORD3 0x28d88
1429#define CB_COLOR5_CLEAR_WORD3 0x28dc4
1430#define CB_COLOR6_CLEAR_WORD3 0x28e00
1431#define CB_COLOR7_CLEAR_WORD3 0x28e3c
1432
1433#define SQ_TEX_RESOURCE_WORD0_0 0x30000
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1434# define TEX_DIM(x) ((x) << 0)
1435# define SQ_TEX_DIM_1D 0
1436# define SQ_TEX_DIM_2D 1
1437# define SQ_TEX_DIM_3D 2
1438# define SQ_TEX_DIM_CUBEMAP 3
1439# define SQ_TEX_DIM_1D_ARRAY 4
1440# define SQ_TEX_DIM_2D_ARRAY 5
1441# define SQ_TEX_DIM_2D_MSAA 6
1442# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1443#define SQ_TEX_RESOURCE_WORD1_0 0x30004
1444# define TEX_ARRAY_MODE(x) ((x) << 28)
1445#define SQ_TEX_RESOURCE_WORD2_0 0x30008
1446#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1447#define SQ_TEX_RESOURCE_WORD4_0 0x30010
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1448# define TEX_DST_SEL_X(x) ((x) << 16)
1449# define TEX_DST_SEL_Y(x) ((x) << 19)
1450# define TEX_DST_SEL_Z(x) ((x) << 22)
1451# define TEX_DST_SEL_W(x) ((x) << 25)
1452# define SQ_SEL_X 0
1453# define SQ_SEL_Y 1
1454# define SQ_SEL_Z 2
1455# define SQ_SEL_W 3
1456# define SQ_SEL_0 4
1457# define SQ_SEL_1 5
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1458#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1459#define SQ_TEX_RESOURCE_WORD6_0 0x30018
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1460# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1461#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1462# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1463# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1464# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1465# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1466#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
1467#define S_030000_DIM(x) (((x) & 0x7) << 0)
1468#define G_030000_DIM(x) (((x) >> 0) & 0x7)
1469#define C_030000_DIM 0xFFFFFFF8
1470#define V_030000_SQ_TEX_DIM_1D 0x00000000
1471#define V_030000_SQ_TEX_DIM_2D 0x00000001
1472#define V_030000_SQ_TEX_DIM_3D 0x00000002
1473#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
1474#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1475#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1476#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
1477#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1478#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
1479#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
1480#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
1481#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
1482#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
1483#define C_030000_PITCH 0xFFFC003F
1484#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
1485#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
1486#define C_030000_TEX_WIDTH 0x0003FFFF
1487#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
1488#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
1489#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
1490#define C_030004_TEX_HEIGHT 0xFFFFC000
1491#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
1492#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
1493#define C_030004_TEX_DEPTH 0xF8003FFF
1494#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
1495#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
1496#define C_030004_ARRAY_MODE 0x0FFFFFFF
1497#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
1498#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1499#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1500#define C_030008_BASE_ADDRESS 0x00000000
1501#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
1502#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1503#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1504#define C_03000C_MIP_ADDRESS 0x00000000
1505#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
1506#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1507#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1508#define C_030010_FORMAT_COMP_X 0xFFFFFFFC
1509#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
1510#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
1511#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
1512#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1513#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1514#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
1515#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1516#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1517#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
1518#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1519#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1520#define C_030010_FORMAT_COMP_W 0xFFFFFF3F
1521#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1522#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1523#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
1524#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
1525#define V_030010_SQ_NUM_FORMAT_INT 0x00000001
1526#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
1527#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1528#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1529#define C_030010_SRF_MODE_ALL 0xFFFFFBFF
1530#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
1531#define V_030010_SRF_MODE_NO_ZERO 0x00000001
1532#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1533#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1534#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
1535#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1536#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1537#define C_030010_ENDIAN_SWAP 0xFFFFCFFF
1538#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
1539#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1540#define C_030010_DST_SEL_X 0xFFF8FFFF
1541#define V_030010_SQ_SEL_X 0x00000000
1542#define V_030010_SQ_SEL_Y 0x00000001
1543#define V_030010_SQ_SEL_Z 0x00000002
1544#define V_030010_SQ_SEL_W 0x00000003
1545#define V_030010_SQ_SEL_0 0x00000004
1546#define V_030010_SQ_SEL_1 0x00000005
1547#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1548#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1549#define C_030010_DST_SEL_Y 0xFFC7FFFF
1550#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1551#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1552#define C_030010_DST_SEL_Z 0xFE3FFFFF
1553#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
1554#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1555#define C_030010_DST_SEL_W 0xF1FFFFFF
1556#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1557#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1558#define C_030010_BASE_LEVEL 0x0FFFFFFF
1559#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
1560#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1561#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1562#define C_030014_LAST_LEVEL 0xFFFFFFF0
1563#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1564#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1565#define C_030014_BASE_ARRAY 0xFFFE000F
1566#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1567#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1568#define C_030014_LAST_ARRAY 0xC001FFFF
1569#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
1570#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
1571#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
1572#define C_030018_MAX_ANISO 0xFFFFFFF8
1573#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
1574#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
1575#define C_030018_PERF_MODULATION 0xFFFFFFC7
1576#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
1577#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
1578#define C_030018_INTERLACED 0xFFFFFFBF
1579#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
1580#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
1581#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
1582#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
1583#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
1584#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
1585#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
1586#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1587#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
1588#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
1589#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
1590#define S_03001C_TYPE(x) (((x) & 0x3) << 30)
1591#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
1592#define C_03001C_TYPE 0x3FFFFFFF
1593#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
1594#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
1595#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
1596#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
1597#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
1598#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
1599#define C_03001C_DATA_FORMAT 0xFFFFFFC0
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1600
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1601#define SQ_VTX_CONSTANT_WORD0_0 0x30000
1602#define SQ_VTX_CONSTANT_WORD1_0 0x30004
1603#define SQ_VTX_CONSTANT_WORD2_0 0x30008
1604# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
1605# define SQ_VTXC_STRIDE(x) ((x) << 8)
1606# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
1607# define SQ_ENDIAN_NONE 0
1608# define SQ_ENDIAN_8IN16 1
1609# define SQ_ENDIAN_8IN32 2
1610#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
1611# define SQ_VTCX_SEL_X(x) ((x) << 3)
1612# define SQ_VTCX_SEL_Y(x) ((x) << 6)
1613# define SQ_VTCX_SEL_Z(x) ((x) << 9)
1614# define SQ_VTCX_SEL_W(x) ((x) << 12)
1615#define SQ_VTX_CONSTANT_WORD4_0 0x30010
1616#define SQ_VTX_CONSTANT_WORD5_0 0x30014
1617#define SQ_VTX_CONSTANT_WORD6_0 0x30018
1618#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
1619
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]1620#define TD_PS_BORDER_COLOR_INDEX 0xA400
1621#define TD_PS_BORDER_COLOR_RED 0xA404
1622#define TD_PS_BORDER_COLOR_GREEN 0xA408
1623#define TD_PS_BORDER_COLOR_BLUE 0xA40C
1624#define TD_PS_BORDER_COLOR_ALPHA 0xA410
1625#define TD_VS_BORDER_COLOR_INDEX 0xA414
1626#define TD_VS_BORDER_COLOR_RED 0xA418
1627#define TD_VS_BORDER_COLOR_GREEN 0xA41C
1628#define TD_VS_BORDER_COLOR_BLUE 0xA420
1629#define TD_VS_BORDER_COLOR_ALPHA 0xA424
1630#define TD_GS_BORDER_COLOR_INDEX 0xA428
1631#define TD_GS_BORDER_COLOR_RED 0xA42C
1632#define TD_GS_BORDER_COLOR_GREEN 0xA430
1633#define TD_GS_BORDER_COLOR_BLUE 0xA434
1634#define TD_GS_BORDER_COLOR_ALPHA 0xA438
1635#define TD_HS_BORDER_COLOR_INDEX 0xA43C
1636#define TD_HS_BORDER_COLOR_RED 0xA440
1637#define TD_HS_BORDER_COLOR_GREEN 0xA444
1638#define TD_HS_BORDER_COLOR_BLUE 0xA448
1639#define TD_HS_BORDER_COLOR_ALPHA 0xA44C
1640#define TD_LS_BORDER_COLOR_INDEX 0xA450
1641#define TD_LS_BORDER_COLOR_RED 0xA454
1642#define TD_LS_BORDER_COLOR_GREEN 0xA458
1643#define TD_LS_BORDER_COLOR_BLUE 0xA45C
1644#define TD_LS_BORDER_COLOR_ALPHA 0xA460
1645#define TD_CS_BORDER_COLOR_INDEX 0xA464
1646#define TD_CS_BORDER_COLOR_RED 0xA468
1647#define TD_CS_BORDER_COLOR_GREEN 0xA46C
1648#define TD_CS_BORDER_COLOR_BLUE 0xA470
1649#define TD_CS_BORDER_COLOR_ALPHA 0xA474
1650
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1651/* cayman 3D regs */
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]1652#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
1653#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1654#define CAYMAN_DB_EQAA 0x28804
1655#define CAYMAN_DB_DEPTH_INFO 0x2803C
1656#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1657#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1658#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
Alex Deucher033b5652011-06-08 15:26:45 -0400[diff] [blame]1659#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1660/* cayman packet3 addition */
1661#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1662
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]1663#endif