| Stepan Moskovchenko | a1424c7 | 2012-07-23 17:22:51 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | / { |
| 14 | jpeg_iommu: qcom,iommu@fda64000 { |
| 15 | compatible = "qcom,msm-smmu-v2"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | ranges; |
| 19 | reg = <0xfda64000 0x10000>; |
| 20 | vdd-supply = <&gdsc_jpeg>; |
| 21 | qcom,iommu-smt-size = <16>; |
| 22 | status = "disabled"; |
| 23 | |
| 24 | qcom,iommu-ctx@fda6c000 { |
| 25 | reg = <0xfda6c000 0x1000>; |
| 26 | interrupts = <0 69 0>; |
| 27 | qcom,iommu-ctx-sids = <0>; |
| 28 | label = "jpeg_enc0"; |
| 29 | }; |
| 30 | |
| 31 | qcom,iommu-ctx@fda6d000 { |
| 32 | reg = <0xfda6d000 0x1000>; |
| 33 | interrupts = <0 70 0>; |
| 34 | qcom,iommu-ctx-sids = <1>; |
| 35 | label = "jpeg_enc1"; |
| 36 | }; |
| 37 | |
| 38 | qcom,iommu-ctx@fda6e000 { |
| 39 | reg = <0xfda6e000 0x1000>; |
| 40 | interrupts = <0 71 0>; |
| 41 | qcom,iommu-ctx-sids = <2>; |
| 42 | label = "jpeg_dec"; |
| 43 | }; |
| 44 | }; |
| 45 | |
| 46 | mdp_iommu: qcom,iommu@fd928000 { |
| 47 | compatible = "qcom,msm-smmu-v2"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | ranges; |
| 51 | reg = <0xfd928000 0x10000>; |
| 52 | vdd-supply = <&gdsc_mdss>; |
| 53 | qcom,iommu-smt-size = <16>; |
| 54 | status = "disabled"; |
| 55 | |
| 56 | qcom,iommu-ctx@fd930000 { |
| 57 | reg = <0xfd930000 0x1000>; |
| 58 | interrupts = <0 46 0>; |
| 59 | qcom,iommu-ctx-sids = <0>; |
| 60 | label = "mdp_0"; |
| 61 | }; |
| 62 | |
| 63 | qcom,iommu-ctx@fd931000 { |
| 64 | reg = <0xfd931000 0x1000>; |
| 65 | interrupts = <0 47 0>; |
| 66 | qcom,iommu-ctx-sids = <1>; |
| 67 | label = "mdp_1"; |
| 68 | }; |
| 69 | }; |
| 70 | |
| 71 | venus_iommu: qcom,iommu@fdc84000 { |
| 72 | compatible = "qcom,msm-smmu-v2"; |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <1>; |
| 75 | ranges; |
| 76 | reg = <0xfdc84000 0x10000>; |
| 77 | vdd-supply = <&gdsc_venus>; |
| 78 | qcom,iommu-smt-size = <16>; |
| 79 | status = "disabled"; |
| 80 | |
| 81 | qcom,iommu-ctx@fdc8c000 { |
| 82 | reg = <0xfdc8c000 0x1000>; |
| 83 | interrupts = <0 43 0>; |
| 84 | qcom,iommu-ctx-sids = <0 1 2 3 4 5>; |
| 85 | label = "venus_ns"; |
| 86 | }; |
| 87 | |
| 88 | qcom,iommu-ctx@fdc8d000 { |
| 89 | reg = <0xfdc8d000 0x1000>; |
| 90 | interrupts = <0 42 0>; |
| 91 | qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84 0x85>; |
| 92 | label = "venus_cp"; |
| 93 | }; |
| 94 | |
| 95 | qcom,iommu-ctx@fdc8e000 { |
| 96 | reg = <0xfdc8e000 0x1000>; |
| 97 | interrupts = <0 41 0>; |
| 98 | qcom,iommu-ctx-sids = <0xc0 0xc6>; |
| 99 | label = "venus_fw"; |
| 100 | }; |
| 101 | }; |
| 102 | |
| 103 | kgsl_iommu: qcom,iommu@fdb10000 { |
| 104 | compatible = "qcom,msm-smmu-v2"; |
| 105 | #address-cells = <1>; |
| 106 | #size-cells = <1>; |
| 107 | ranges; |
| 108 | reg = <0xfdb10000 0x10000>; |
| 109 | vdd-supply = <&gdsc_oxili_cx>; |
| 110 | qcom,iommu-smt-size = <32>; |
| 111 | status = "disabled"; |
| 112 | |
| 113 | qcom,iommu-ctx@fdb18000 { |
| 114 | reg = <0xfdb18000 0x1000>; |
| 115 | interrupts = <0 240 0>; |
| 116 | qcom,iommu-ctx-sids = <0>; |
| 117 | label = "gfx3d_user"; |
| 118 | }; |
| 119 | |
| 120 | qcom,iommu-ctx@fdb19000 { |
| 121 | reg = <0xfdb19000 0x1000>; |
| 122 | interrupts = <0 241 0>; |
| 123 | qcom,iommu-ctx-sids = <1>; |
| 124 | label = "gfx3d_priv"; |
| 125 | }; |
| 126 | }; |
| 127 | |
| 128 | vfe_iommu: qcom,iommu@fda44000 { |
| 129 | compatible = "qcom,msm-smmu-v2"; |
| 130 | #address-cells = <1>; |
| 131 | #size-cells = <1>; |
| 132 | ranges; |
| 133 | reg = <0xfda44000 0x10000>; |
| 134 | vdd-supply = <&gdsc_vfe>; |
| 135 | qcom,iommu-smt-size = <32>; |
| 136 | status = "disabled"; |
| 137 | |
| 138 | qcom,iommu-ctx@fda4c000 { |
| 139 | reg = <0xfda4c000 0x1000>; |
| 140 | interrupts = <0 64 0>; |
| 141 | qcom,iommu-ctx-sids = <0>; |
| 142 | label = "vfe0"; |
| 143 | }; |
| 144 | |
| 145 | qcom,iommu-ctx@fda4d000 { |
| 146 | reg = <0xfda4d000 0x1000>; |
| 147 | interrupts = <0 65 0>; |
| 148 | qcom,iommu-ctx-sids = <1>; |
| 149 | label = "vfe1"; |
| 150 | }; |
| 151 | |
| 152 | qcom,iommu-ctx@fda4e000 { |
| 153 | reg = <0xfda4e000 0x1000>; |
| 154 | interrupts = <0 66 0>; |
| 155 | qcom,iommu-ctx-sids = <2>; |
| 156 | label = "cpp"; |
| 157 | }; |
| 158 | }; |
| 159 | }; |