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Linus Torvalds1da177e2005-04-16 15:20:36 -07001menu "DMA support"
2
Manuel Laussfc467a22007-05-09 17:36:15 +09003config SH_DMA_API
4 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -07005
Manuel Laussfc467a22007-05-09 17:36:15 +09006config SH_DMA
7 bool "SuperH on-chip DMA controller (DMAC) support"
Paul Mundt3e767832007-07-20 14:23:04 +09008 depends on CPU_SH3 || CPU_SH4
Manuel Laussfc467a22007-05-09 17:36:15 +09009 select SH_DMA_API
10 default n
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
Nobuhiro Iwamatsu988f8312009-03-16 03:22:07 +000012config SH_DMA_IRQ_MULTI
13 bool
14 depends on SH_DMA
Paul Mundta27873c2009-04-04 11:40:22 -040015 default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \
16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \
17 CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \
18 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \
19 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
Nobuhiro Iwamatsu988f8312009-03-16 03:22:07 +000020
Linus Torvalds1da177e2005-04-16 15:20:36 -070021config NR_ONCHIP_DMA_CHANNELS
Paul Mundtfc100202007-07-20 14:24:57 +090022 int
Linus Torvalds1da177e2005-04-16 15:20:36 -070023 depends on SH_DMA
Paul Mundta27873c2009-04-04 11:40:22 -040024 default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \
25 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091
26 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
27 CPU_SUBTYPE_SH7760
28 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \
29 CPU_SUBTYPE_SH7785
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +090030 default "6"
Linus Torvalds1da177e2005-04-16 15:20:36 -070031 help
32 This allows you to specify the number of channels that the on-chip
Paul Mundta27873c2009-04-04 11:40:22 -040033 DMAC supports. This will be 4 for SH7091/SH7750/SH7751 and 8 for the
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 SH7750R/SH7751R.
35
36config NR_DMA_CHANNELS_BOOL
37 depends on SH_DMA
38 bool "Override default number of maximum DMA channels"
39 help
40 This allows you to forcibly update the maximum number of supported
41 DMA channels for a given board. If this is unset, this will default
42 to the number of channels that the on-chip DMAC has.
43
44config NR_DMA_CHANNELS
45 int "Maximum number of DMA channels"
46 depends on SH_DMA && NR_DMA_CHANNELS_BOOL
47 default NR_ONCHIP_DMA_CHANNELS
48 help
49 This allows you to specify the maximum number of DMA channels to
50 support. Setting this to a higher value allows for cascading DMACs
51 with additional channels.
52
Manuel Laussfc467a22007-05-09 17:36:15 +090053config SH_DMABRG
54 bool "SH7760 DMABRG support"
55 depends on CPU_SUBTYPE_SH7760
56 help
57 The DMABRG does data transfers from main memory to Audio/USB units
58 of the SH7760.
59 Say Y if you want to use Audio/USB DMA on your SH7760 board.
60
Paul Mundtda62e712009-03-17 09:30:36 +090061config PVR2_DMA
62 tristate "PowerVR 2 DMAC support"
63 depends on SH_DREAMCAST && SH_DMA
64 help
65 Selecting this will enable support for the PVR2 DMA controller.
66 As this chains off of the on-chip DMAC, that must also be
67 enabled by default.
68
69 This is primarily used by the pvr2fb framebuffer driver for
70 certain optimizations, but is not necessary for functionality.
71
72 If in doubt, say N.
73
Paul Mundt40f49e72009-03-17 12:47:56 +090074config G2_DMA
75 tristate "G2 Bus DMA support"
76 depends on SH_DREAMCAST
77 select SH_DMA_API
78 help
79 This enables support for the DMA controller for the Dreamcast's
80 G2 bus. Drivers that want this will generally enable this on
81 their own.
82
83 If in doubt, say N.
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085endmenu