| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  *  Header file for AT91/AT32 LCD Controller | 
 | 3 |  * | 
 | 4 |  *  Data structure and register user interface | 
 | 5 |  * | 
 | 6 |  *  Copyright (C) 2007 Atmel Corporation | 
 | 7 |  * | 
 | 8 |  * This program is free software; you can redistribute it and/or modify | 
 | 9 |  * it under the terms of the GNU General Public License as published by | 
 | 10 |  * the Free Software Foundation; either version 2 of the License, or | 
 | 11 |  * (at your option) any later version. | 
 | 12 |  * | 
 | 13 |  * This program is distributed in the hope that it will be useful, | 
 | 14 |  * but WITHOUT ANY WARRANTY; without even the implied warranty of | 
 | 15 |  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
 | 16 |  * GNU General Public License for more details. | 
 | 17 |  * | 
 | 18 |  * You should have received a copy of the GNU General Public License | 
 | 19 |  * along with this program; if not, write to the Free Software | 
 | 20 |  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA | 
 | 21 |  */ | 
 | 22 | #ifndef __ATMEL_LCDC_H__ | 
 | 23 | #define __ATMEL_LCDC_H__ | 
 | 24 |  | 
| Adrian Bunk | 44ccac1 | 2008-07-25 19:44:38 -0700 | [diff] [blame] | 25 | #include <linux/workqueue.h> | 
| Nicolas Ferre | fd08580 | 2008-04-28 02:15:21 -0700 | [diff] [blame] | 26 |  | 
 | 27 | /* Way LCD wires are connected to the chip: | 
 | 28 |  * Some Atmel chips use BGR color mode (instead of standard RGB) | 
 | 29 |  * A swapped wiring onboard can bring to RGB mode. | 
 | 30 |  */ | 
 | 31 | #define ATMEL_LCDC_WIRING_BGR	0 | 
 | 32 | #define ATMEL_LCDC_WIRING_RGB	1 | 
| Guillaume GARDET | fbd03a1 | 2008-08-29 10:11:24 +0100 | [diff] [blame] | 33 | #define ATMEL_LCDC_WIRING_RGB555	2 | 
| Nicolas Ferre | fd08580 | 2008-04-28 02:15:21 -0700 | [diff] [blame] | 34 |  | 
 | 35 |  | 
| David Brownell | a9a84c3 | 2008-02-06 01:39:26 -0800 | [diff] [blame] | 36 |  /* LCD Controller info data structure, stored in device platform_data */ | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 37 | struct atmel_lcdfb_info { | 
 | 38 | 	spinlock_t		lock; | 
 | 39 | 	struct fb_info		*info; | 
 | 40 | 	void __iomem		*mmio; | 
| Nicolas Ferre | 722facc | 2008-11-12 13:24:59 -0800 | [diff] [blame] | 41 | 	int			irq_base; | 
| Nicolas Ferre | d22579b | 2008-07-23 21:31:20 -0700 | [diff] [blame] | 42 | 	struct work_struct	task; | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 43 |  | 
 | 44 | 	unsigned int		guard_time; | 
| Haavard Skinnemoen | ea757ac | 2008-08-12 15:08:57 -0700 | [diff] [blame] | 45 | 	unsigned int 		smem_len; | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 46 | 	struct platform_device	*pdev; | 
 | 47 | 	struct clk		*bus_clk; | 
 | 48 | 	struct clk		*lcdc_clk; | 
| David Brownell | a9a84c3 | 2008-02-06 01:39:26 -0800 | [diff] [blame] | 49 |  | 
 | 50 | #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC | 
 | 51 | 	struct backlight_device	*backlight; | 
 | 52 | 	u8			bl_power; | 
 | 53 | #endif | 
 | 54 | 	bool			lcdcon_is_backlight; | 
| David Brownell | cf19a37 | 2008-04-28 02:15:20 -0700 | [diff] [blame] | 55 | 	u8			saved_lcdcon; | 
| David Brownell | a9a84c3 | 2008-02-06 01:39:26 -0800 | [diff] [blame] | 56 |  | 
 | 57 | 	u8			default_bpp; | 
| Nicolas Ferre | fd08580 | 2008-04-28 02:15:21 -0700 | [diff] [blame] | 58 | 	u8			lcd_wiring_mode; | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 59 | 	unsigned int		default_lcdcon2; | 
 | 60 | 	unsigned int		default_dmacon; | 
 | 61 | 	void (*atmel_lcdfb_power_control)(int on); | 
 | 62 | 	struct fb_monspecs	*default_monspecs; | 
 | 63 | 	u32			pseudo_palette[16]; | 
 | 64 | }; | 
 | 65 |  | 
 | 66 | #define ATMEL_LCDC_DMABADDR1	0x00 | 
 | 67 | #define ATMEL_LCDC_DMABADDR2	0x04 | 
 | 68 | #define ATMEL_LCDC_DMAFRMPT1	0x08 | 
 | 69 | #define ATMEL_LCDC_DMAFRMPT2	0x0c | 
 | 70 | #define ATMEL_LCDC_DMAFRMADD1	0x10 | 
 | 71 | #define ATMEL_LCDC_DMAFRMADD2	0x14 | 
 | 72 |  | 
 | 73 | #define ATMEL_LCDC_DMAFRMCFG	0x18 | 
 | 74 | #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0) | 
 | 75 | #define	ATMEL_LCDC_BLENGTH_OFFSET	24 | 
 | 76 | #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET) | 
 | 77 |  | 
 | 78 | #define ATMEL_LCDC_DMACON	0x1c | 
 | 79 | #define	ATMEL_LCDC_DMAEN	(0x1 << 0) | 
 | 80 | #define	ATMEL_LCDC_DMARST	(0x1 << 1) | 
 | 81 | #define	ATMEL_LCDC_DMABUSY	(0x1 << 2) | 
 | 82 | #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3) | 
 | 83 | #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4) | 
 | 84 |  | 
 | 85 | #define ATMEL_LCDC_DMA2DCFG	0x20 | 
 | 86 | #define		ATMEL_LCDC_ADDRINC_OFFSET	0 | 
 | 87 | #define		ATMEL_LCDC_ADDRINC		(0xffff) | 
 | 88 | #define		ATMEL_LCDC_PIXELOFF_OFFSET	24 | 
 | 89 | #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24) | 
 | 90 |  | 
 | 91 | #define ATMEL_LCDC_LCDCON1	0x0800 | 
 | 92 | #define	ATMEL_LCDC_BYPASS	(1     <<  0) | 
 | 93 | #define	ATMEL_LCDC_CLKVAL_OFFSET	12 | 
 | 94 | #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) | 
 | 95 | #define	ATMEL_LCDC_LINCNT	(0x7ff << 21) | 
 | 96 |  | 
 | 97 | #define ATMEL_LCDC_LCDCON2	0x0804 | 
 | 98 | #define	ATMEL_LCDC_DISTYPE	(3 << 0) | 
 | 99 | #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0) | 
 | 100 | #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0) | 
 | 101 | #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0) | 
 | 102 | #define	ATMEL_LCDC_SCANMOD	(1 << 2) | 
 | 103 | #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2) | 
 | 104 | #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2) | 
 | 105 | #define	ATMEL_LCDC_IFWIDTH	(3 << 3) | 
 | 106 | #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3) | 
 | 107 | #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3) | 
 | 108 | #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3) | 
 | 109 | #define	ATMEL_LCDC_PIXELSIZE	(7 << 5) | 
 | 110 | #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5) | 
 | 111 | #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5) | 
 | 112 | #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5) | 
 | 113 | #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5) | 
 | 114 | #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5) | 
 | 115 | #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5) | 
 | 116 | #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5) | 
 | 117 | #define	ATMEL_LCDC_INVVD	(1 << 8) | 
 | 118 | #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8) | 
 | 119 | #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8) | 
 | 120 | #define	ATMEL_LCDC_INVFRAME	(1 << 9 ) | 
 | 121 | #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9) | 
 | 122 | #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9) | 
 | 123 | #define	ATMEL_LCDC_INVLINE	(1 << 10) | 
 | 124 | #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10) | 
 | 125 | #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10) | 
 | 126 | #define	ATMEL_LCDC_INVCLK	(1 << 11) | 
 | 127 | #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11) | 
 | 128 | #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11) | 
 | 129 | #define	ATMEL_LCDC_INVDVAL	(1 << 12) | 
 | 130 | #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12) | 
 | 131 | #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12) | 
 | 132 | #define	ATMEL_LCDC_CLKMOD	(1 << 15) | 
 | 133 | #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15) | 
 | 134 | #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15) | 
 | 135 | #define	ATMEL_LCDC_MEMOR	(1 << 31) | 
 | 136 | #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31) | 
 | 137 | #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31) | 
 | 138 |  | 
 | 139 | #define ATMEL_LCDC_TIM1		0x0808 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 140 | #define	ATMEL_LCDC_VFP		(0xffU <<  0) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 141 | #define	ATMEL_LCDC_VBP_OFFSET		8 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 142 | #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 143 | #define	ATMEL_LCDC_VPW_OFFSET		16 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 144 | #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 145 | #define	ATMEL_LCDC_VHDLY_OFFSET		24 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 146 | #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 147 |  | 
 | 148 | #define ATMEL_LCDC_TIM2		0x080c | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 149 | #define	ATMEL_LCDC_HBP		(0xffU  <<  0) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 150 | #define	ATMEL_LCDC_HPW_OFFSET		8 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 151 | #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 152 | #define	ATMEL_LCDC_HFP_OFFSET		21 | 
| Haavard Skinnemoen | 162b3a0 | 2008-02-06 01:39:11 -0800 | [diff] [blame] | 153 | #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET) | 
| Nicolas Ferre | 1434058 | 2007-05-10 22:23:26 -0700 | [diff] [blame] | 154 |  | 
 | 155 | #define ATMEL_LCDC_LCDFRMCFG	0x0810 | 
 | 156 | #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0) | 
 | 157 | #define	ATMEL_LCDC_HOZVAL_OFFSET	21 | 
 | 158 | #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) | 
 | 159 |  | 
 | 160 | #define ATMEL_LCDC_FIFO		0x0814 | 
 | 161 | #define	ATMEL_LCDC_FIFOTH	(0xffff) | 
 | 162 |  | 
 | 163 | #define ATMEL_LCDC_MVAL		0x0818 | 
 | 164 |  | 
 | 165 | #define ATMEL_LCDC_DP1_2	0x081c | 
 | 166 | #define ATMEL_LCDC_DP4_7	0x0820 | 
 | 167 | #define ATMEL_LCDC_DP3_5	0x0824 | 
 | 168 | #define ATMEL_LCDC_DP2_3	0x0828 | 
 | 169 | #define ATMEL_LCDC_DP5_7	0x082c | 
 | 170 | #define ATMEL_LCDC_DP3_4	0x0830 | 
 | 171 | #define ATMEL_LCDC_DP4_5	0x0834 | 
 | 172 | #define ATMEL_LCDC_DP6_7	0x0838 | 
 | 173 | #define	ATMEL_LCDC_DP1_2_VAL	(0xff) | 
 | 174 | #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff) | 
 | 175 | #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff) | 
 | 176 | #define	ATMEL_LCDC_DP2_3_VAL	(0xfff) | 
 | 177 | #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff) | 
 | 178 | #define	ATMEL_LCDC_DP3_4_VAL	(0xffff) | 
 | 179 | #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff) | 
 | 180 | #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff) | 
 | 181 |  | 
 | 182 | #define ATMEL_LCDC_PWRCON	0x083c | 
 | 183 | #define	ATMEL_LCDC_PWR		(1    <<  0) | 
 | 184 | #define	ATMEL_LCDC_GUARDT_OFFSET	1 | 
 | 185 | #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET) | 
 | 186 | #define	ATMEL_LCDC_BUSY		(1    << 31) | 
 | 187 |  | 
 | 188 | #define ATMEL_LCDC_CONTRAST_CTR	0x0840 | 
 | 189 | #define	ATMEL_LCDC_PS		(3 << 0) | 
 | 190 | #define		ATMEL_LCDC_PS_DIV1		(0 << 0) | 
 | 191 | #define		ATMEL_LCDC_PS_DIV2		(1 << 0) | 
 | 192 | #define		ATMEL_LCDC_PS_DIV4		(2 << 0) | 
 | 193 | #define		ATMEL_LCDC_PS_DIV8		(3 << 0) | 
 | 194 | #define	ATMEL_LCDC_POL		(1 << 2) | 
 | 195 | #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2) | 
 | 196 | #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2) | 
 | 197 | #define	ATMEL_LCDC_ENA		(1 << 3) | 
 | 198 | #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3) | 
 | 199 | #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3) | 
 | 200 |  | 
 | 201 | #define ATMEL_LCDC_CONTRAST_VAL	0x0844 | 
 | 202 | #define	ATMEL_LCDC_CVAL	(0xff) | 
 | 203 |  | 
 | 204 | #define ATMEL_LCDC_IER		0x0848 | 
 | 205 | #define ATMEL_LCDC_IDR		0x084c | 
 | 206 | #define ATMEL_LCDC_IMR		0x0850 | 
 | 207 | #define ATMEL_LCDC_ISR		0x0854 | 
 | 208 | #define ATMEL_LCDC_ICR		0x0858 | 
 | 209 | #define	ATMEL_LCDC_LNI		(1 << 0) | 
 | 210 | #define	ATMEL_LCDC_LSTLNI	(1 << 1) | 
 | 211 | #define	ATMEL_LCDC_EOFI		(1 << 2) | 
 | 212 | #define	ATMEL_LCDC_UFLWI	(1 << 4) | 
 | 213 | #define	ATMEL_LCDC_OWRI		(1 << 5) | 
 | 214 | #define	ATMEL_LCDC_MERI		(1 << 6) | 
 | 215 |  | 
 | 216 | #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4)) | 
 | 217 |  | 
 | 218 | #endif /* __ATMEL_LCDC_H__ */ |