| Vitaly Wool | a5a5030 | 2006-05-16 11:54:36 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * include/asm-arm/arch-pnx4008/gpio.h |
| 3 | * |
| 4 | * PNX4008 GPIO driver - header file |
| 5 | * |
| 6 | * Author: Dmitry Chigirev <source@mvista.com> |
| 7 | * |
| 8 | * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: |
| 9 | * Copyright (c) 2005 Koninklijke Philips Electronics N.V. |
| 10 | * |
| 11 | * 2005 (c) MontaVista Software, Inc. This file is licensed under |
| 12 | * the terms of the GNU General Public License version 2. This program |
| 13 | * is licensed "as is" without any warranty of any kind, whether express |
| 14 | * or implied. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _PNX4008_GPIO_H_ |
| 18 | #define _PNX4008_GPIO_H_ |
| 19 | |
| 20 | |
| 21 | /* Block numbers */ |
| 22 | #define GPIO_IN (0) |
| 23 | #define GPIO_OUT (0x100) |
| 24 | #define GPIO_BID (0x200) |
| 25 | #define GPIO_RAM (0x300) |
| 26 | #define GPIO_MUX (0x400) |
| 27 | |
| 28 | #define GPIO_TYPE_MASK(K) ((K) & 0x700) |
| 29 | |
| 30 | /* INPUT GPIOs */ |
| 31 | /* GPI */ |
| 32 | #define GPI_00 (GPIO_IN | 0) |
| 33 | #define GPI_01 (GPIO_IN | 1) |
| 34 | #define GPI_02 (GPIO_IN | 2) |
| 35 | #define GPI_03 (GPIO_IN | 3) |
| 36 | #define GPI_04 (GPIO_IN | 4) |
| 37 | #define GPI_05 (GPIO_IN | 5) |
| 38 | #define GPI_06 (GPIO_IN | 6) |
| 39 | #define GPI_07 (GPIO_IN | 7) |
| 40 | #define GPI_08 (GPIO_IN | 8) |
| 41 | #define GPI_09 (GPIO_IN | 9) |
| 42 | #define U1_RX (GPIO_IN | 15) |
| 43 | #define U2_HTCS (GPIO_IN | 16) |
| 44 | #define U2_RX (GPIO_IN | 17) |
| 45 | #define U3_RX (GPIO_IN | 18) |
| 46 | #define U4_RX (GPIO_IN | 19) |
| 47 | #define U5_RX (GPIO_IN | 20) |
| 48 | #define U6_IRRX (GPIO_IN | 21) |
| 49 | #define U7_HCTS (GPIO_IN | 22) |
| 50 | #define U7_RX (GPIO_IN | 23) |
| 51 | /* MISC IN */ |
| 52 | #define SPI1_DATIN (GPIO_IN | 25) |
| 53 | #define DISP_SYNC (GPIO_IN | 26) |
| 54 | #define SPI2_DATIN (GPIO_IN | 27) |
| 55 | #define GPI_11 (GPIO_IN | 28) |
| 56 | |
| 57 | #define GPIO_IN_MASK 0x1eff83ff |
| 58 | |
| 59 | /* OUTPUT GPIOs */ |
| 60 | /* GPO */ |
| 61 | #define GPO_00 (GPIO_OUT | 0) |
| 62 | #define GPO_01 (GPIO_OUT | 1) |
| 63 | #define GPO_02 (GPIO_OUT | 2) |
| 64 | #define GPO_03 (GPIO_OUT | 3) |
| 65 | #define GPO_04 (GPIO_OUT | 4) |
| 66 | #define GPO_05 (GPIO_OUT | 5) |
| 67 | #define GPO_06 (GPIO_OUT | 6) |
| 68 | #define GPO_07 (GPIO_OUT | 7) |
| 69 | #define GPO_08 (GPIO_OUT | 8) |
| 70 | #define GPO_09 (GPIO_OUT | 9) |
| 71 | #define GPO_10 (GPIO_OUT | 10) |
| 72 | #define GPO_11 (GPIO_OUT | 11) |
| 73 | #define GPO_12 (GPIO_OUT | 12) |
| 74 | #define GPO_13 (GPIO_OUT | 13) |
| 75 | #define GPO_14 (GPIO_OUT | 14) |
| 76 | #define GPO_15 (GPIO_OUT | 15) |
| 77 | #define GPO_16 (GPIO_OUT | 16) |
| 78 | #define GPO_17 (GPIO_OUT | 17) |
| 79 | #define GPO_18 (GPIO_OUT | 18) |
| 80 | #define GPO_19 (GPIO_OUT | 19) |
| 81 | #define GPO_20 (GPIO_OUT | 20) |
| 82 | #define GPO_21 (GPIO_OUT | 21) |
| 83 | #define GPO_22 (GPIO_OUT | 22) |
| 84 | #define GPO_23 (GPIO_OUT | 23) |
| 85 | |
| 86 | #define GPIO_OUT_MASK 0xffffff |
| 87 | |
| 88 | /* BIDIRECTIONAL GPIOs */ |
| 89 | /* RAM pins */ |
| 90 | #define RAM_D19 (GPIO_RAM | 0) |
| 91 | #define RAM_D20 (GPIO_RAM | 1) |
| 92 | #define RAM_D21 (GPIO_RAM | 2) |
| 93 | #define RAM_D22 (GPIO_RAM | 3) |
| 94 | #define RAM_D23 (GPIO_RAM | 4) |
| 95 | #define RAM_D24 (GPIO_RAM | 5) |
| 96 | #define RAM_D25 (GPIO_RAM | 6) |
| 97 | #define RAM_D26 (GPIO_RAM | 7) |
| 98 | #define RAM_D27 (GPIO_RAM | 8) |
| 99 | #define RAM_D28 (GPIO_RAM | 9) |
| 100 | #define RAM_D29 (GPIO_RAM | 10) |
| 101 | #define RAM_D30 (GPIO_RAM | 11) |
| 102 | #define RAM_D31 (GPIO_RAM | 12) |
| 103 | |
| 104 | #define GPIO_RAM_MASK 0x1fff |
| 105 | |
| 106 | /* I/O pins */ |
| 107 | #define GPIO_00 (GPIO_BID | 25) |
| 108 | #define GPIO_01 (GPIO_BID | 26) |
| 109 | #define GPIO_02 (GPIO_BID | 27) |
| 110 | #define GPIO_03 (GPIO_BID | 28) |
| 111 | #define GPIO_04 (GPIO_BID | 29) |
| 112 | #define GPIO_05 (GPIO_BID | 30) |
| 113 | |
| 114 | #define GPIO_BID_MASK 0x7e000000 |
| 115 | |
| 116 | /* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */ |
| 117 | #define GPIO_SDRAM_SEL (GPIO_MUX | 3) |
| 118 | |
| 119 | #define GPIO_MUX_MASK 0x8 |
| 120 | |
| 121 | /* Extraction/assembly macros */ |
| 122 | #define GPIO_BIT_MASK(K) ((K) & 0x1F) |
| 123 | #define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K)) |
| 124 | #define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK)) |
| 125 | #define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK)) |
| 126 | #define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK)) |
| 127 | #define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK)) |
| 128 | #define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK)) |
| 129 | |
| 130 | extern int pnx4008_gpio_register_pin(unsigned short pin); |
| 131 | extern int pnx4008_gpio_unregister_pin(unsigned short pin); |
| 132 | extern unsigned long pnx4008_gpio_read_pin(unsigned short pin); |
| 133 | extern int pnx4008_gpio_write_pin(unsigned short pin, int output); |
| 134 | extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output); |
| 135 | extern int pnx4008_gpio_read_pin_direction(unsigned short pin); |
| 136 | extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output); |
| 137 | extern int pnx4008_gpio_read_pin_mux(unsigned short pin); |
| 138 | |
| 139 | #endif /* _PNX4008_GPIO_H_ */ |