blob: ad1a5b422c8c8c6e2a9ee9d23519da0130837500 [file] [log] [blame]
Joe Perchese9010e22008-03-07 14:21:16 -08001/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23/*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27#include <linux/pci.h>
28#include <linux/delay.h>
29
30#include "reg.h"
31#include "base.h"
32#include "debug.h"
33
Pavel Macheke292c732008-06-25 12:25:53 +020034/* Rate tables */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020035static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
Pavel Macheke292c732008-06-25 12:25:53 +020041/* Prototypes */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020042static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
Jiri Slabyb9887632008-02-15 21:58:52 +010048static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
Jiri Slabyfa1c1142007-08-12 17:33:16 +020049 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
Bruno Randolfb47f4072008-03-05 18:35:45 +090051static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
52 struct ath5k_tx_status *);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020053static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
54 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
55 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int);
Bruno Randolfb47f4072008-03-05 18:35:45 +090057static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
58 struct ath5k_tx_status *);
59static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
60 struct ath5k_rx_status *);
61static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
62 struct ath5k_rx_status *);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020063static int ath5k_hw_get_capabilities(struct ath5k_hw *);
64
65static int ath5k_eeprom_init(struct ath5k_hw *);
66static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
67
68static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
69static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
70
71/*
72 * Enable to overwrite the country code (use "00" for debug)
73 */
74#if 0
75#define COUNTRYCODE "00"
76#endif
77
78/*******************\
79 General Functions
80\*******************/
81
82/*
83 * Functions used internaly
84 */
85
86static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87{
Joe Perchese9010e22008-03-07 14:21:16 -080088 return turbo ? (usec * 80) : (usec * 40);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020089}
90
91static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92{
Joe Perchese9010e22008-03-07 14:21:16 -080093 return turbo ? (clock / 80) : (clock / 40);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020094}
95
96/*
97 * Check if a register write has been completed
98 */
99int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 bool is_set)
101{
102 int i;
103 u32 data;
104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg);
Joe Perchese9010e22008-03-07 14:21:16 -0800107 if (is_set && (data & flag))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200108 break;
109 else if ((data & flag) == val)
110 break;
111 udelay(15);
112 }
113
114 return (i <= 0) ? -EAGAIN : 0;
115}
116
117
118/***************************************\
119 Attach/Detach Functions
120\***************************************/
121
122/*
Nick Kossifidis194828a2008-04-16 18:49:02 +0300123 * Power On Self Test helper function
124 */
125static int ath5k_hw_post(struct ath5k_hw *ah)
126{
127
128 int i, c;
129 u16 cur_reg;
130 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
131 u32 var_pattern;
132 u32 static_pattern[4] = {
133 0x55555555, 0xaaaaaaaa,
134 0x66666666, 0x99999999
135 };
136 u32 init_val;
137 u32 cur_val;
138
139 for (c = 0; c < 2; c++) {
140
141 cur_reg = regs[c];
Nick Kossifidisba377462008-07-20 06:32:32 +0300142
143 /* Save previous value */
Nick Kossifidis194828a2008-04-16 18:49:02 +0300144 init_val = ath5k_hw_reg_read(ah, cur_reg);
145
146 for (i = 0; i < 256; i++) {
147 var_pattern = i << 16 | i;
148 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
149 cur_val = ath5k_hw_reg_read(ah, cur_reg);
150
151 if (cur_val != var_pattern) {
152 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
153 return -EAGAIN;
154 }
155
156 /* Found on ndiswrapper dumps */
157 var_pattern = 0x0039080f;
158 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
159 }
160
161 for (i = 0; i < 4; i++) {
162 var_pattern = static_pattern[i];
163 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
164 cur_val = ath5k_hw_reg_read(ah, cur_reg);
165
166 if (cur_val != var_pattern) {
167 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
168 return -EAGAIN;
169 }
170
171 /* Found on ndiswrapper dumps */
172 var_pattern = 0x003b080f;
173 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
174 }
Nick Kossifidisba377462008-07-20 06:32:32 +0300175
176 /* Restore previous value */
177 ath5k_hw_reg_write(ah, init_val, cur_reg);
178
Nick Kossifidis194828a2008-04-16 18:49:02 +0300179 }
180
181 return 0;
182
183}
184
185/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200186 * Check if the device is supported and initialize the needed structs
187 */
188struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
189{
190 struct ath5k_hw *ah;
Nick Kossifidis194828a2008-04-16 18:49:02 +0300191 struct pci_dev *pdev = sc->pdev;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200192 u8 mac[ETH_ALEN];
193 int ret;
194 u32 srev;
195
196 /*If we passed the test malloc a ath5k_hw struct*/
197 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
198 if (ah == NULL) {
199 ret = -ENOMEM;
200 ATH5K_ERR(sc, "out of memory\n");
201 goto err;
202 }
203
204 ah->ah_sc = sc;
205 ah->ah_iobase = sc->iobase;
206
207 /*
208 * HW information
209 */
210
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200211 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
212 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
213 ah->ah_turbo = false;
214 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
215 ah->ah_imr = 0;
216 ah->ah_atim_window = 0;
217 ah->ah_aifs = AR5K_TUNE_AIFS;
218 ah->ah_cw_min = AR5K_TUNE_CWMIN;
219 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
220 ah->ah_software_retry = false;
221 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
222
223 /*
224 * Set the mac revision based on the pci id
225 */
226 ah->ah_version = mac_version;
227
228 /*Fill the ath5k_hw struct with the needed functions*/
229 if (ah->ah_version == AR5K_AR5212)
230 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
231 else if (ah->ah_version == AR5K_AR5211)
232 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
233
234 if (ah->ah_version == AR5K_AR5212) {
235 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
236 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
237 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
238 } else {
239 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
240 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
241 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
242 }
243
244 if (ah->ah_version == AR5K_AR5212)
Bruno Randolf19fd6e52008-03-05 18:35:23 +0900245 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200246 else if (ah->ah_version <= AR5K_AR5211)
Bruno Randolf19fd6e52008-03-05 18:35:23 +0900247 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200248
249 /* Bring device out of sleep and reset it's units */
250 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
251 if (ret)
252 goto err_free;
253
254 /* Get MAC, PHY and RADIO revisions */
255 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
256 ah->ah_mac_srev = srev;
257 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
258 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
259 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
260 0xffffffff;
261 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
262 CHANNEL_5GHZ);
263
264 if (ah->ah_version == AR5K_AR5210)
265 ah->ah_radio_2ghz_revision = 0;
266 else
267 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
268 CHANNEL_2GHZ);
269
270 /* Return on unsuported chips (unsupported eeprom etc) */
Nick Kossifidis194828a2008-04-16 18:49:02 +0300271 if ((srev >= AR5K_SREV_VER_AR5416) &&
272 (srev < AR5K_SREV_VER_AR2425)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200273 ATH5K_ERR(sc, "Device not yet supported.\n");
274 ret = -ENODEV;
275 goto err_free;
Nick Kossifidis194828a2008-04-16 18:49:02 +0300276 } else if (srev == AR5K_SREV_VER_AR2425) {
277 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200278 }
279
280 /* Identify single chip solutions */
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300281 if (((srev <= AR5K_SREV_VER_AR5414) &&
282 (srev >= AR5K_SREV_VER_AR2413)) ||
283 (srev == AR5K_SREV_VER_AR2425)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200284 ah->ah_single_chip = true;
285 } else {
286 ah->ah_single_chip = false;
287 }
288
289 /* Single chip radio */
290 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
291 ah->ah_radio_2ghz_revision = 0;
292
293 /* Identify the radio chip*/
294 if (ah->ah_version == AR5K_AR5210) {
295 ah->ah_radio = AR5K_RF5110;
Nick Kossifidis194828a2008-04-16 18:49:02 +0300296 /*
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300297 * Register returns 0x0/0x04 for radio revision
Nick Kossifidis194828a2008-04-16 18:49:02 +0300298 * so ath5k_hw_radio_revision doesn't parse the value
299 * correctly. For now we are based on mac's srev to
300 * identify RF2425 radio.
301 */
302 } else if (srev == AR5K_SREV_VER_AR2425) {
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300303 ah->ah_radio = AR5K_RF2425;
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300304 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
305 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
306 ah->ah_radio = AR5K_RF5111;
307 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
308 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
309 ah->ah_radio = AR5K_RF5112;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300310 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300311 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
312 ah->ah_radio = AR5K_RF2413;
313 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
314 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
315 ah->ah_radio = AR5K_RF5413;
316 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
317 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
318 /* AR5424 */
319 if (srev >= AR5K_SREV_VER_AR5424) {
320 ah->ah_radio = AR5K_RF5413;
321 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
322 /* AR2424 */
323 } else {
324 ah->ah_radio = AR5K_RF2413; /* For testing */
325 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
326 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200327 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200328 ah->ah_phy = AR5K_PHY(0);
329
330 /*
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300331 * Write PCI-E power save settings
Nick Kossifidis194828a2008-04-16 18:49:02 +0300332 */
333 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
334 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
335 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
336 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
337 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
338 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
339 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
340 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
341 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
342 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
343 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
344 }
345
346 /*
347 * POST
348 */
349 ret = ath5k_hw_post(ah);
350 if (ret)
351 goto err_free;
352
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300353 /* Write AR5K_PCICFG_UNK on 2112B and later chips */
354 if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
355 srev > AR5K_SREV_VER_AR2413) {
356 ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG);
357 }
358
Nick Kossifidis194828a2008-04-16 18:49:02 +0300359 /*
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200360 * Get card capabilities, values, ...
361 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200362 ret = ath5k_eeprom_init(ah);
363 if (ret) {
364 ATH5K_ERR(sc, "unable to init EEPROM\n");
365 goto err_free;
366 }
367
368 /* Get misc capabilities */
369 ret = ath5k_hw_get_capabilities(ah);
370 if (ret) {
371 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
372 sc->pdev->device);
373 goto err_free;
374 }
375
376 /* Get MAC address */
377 ret = ath5k_eeprom_read_mac(ah, mac);
378 if (ret) {
379 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
380 sc->pdev->device);
381 goto err_free;
382 }
383
384 ath5k_hw_set_lladdr(ah, mac);
385 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
386 memset(ah->ah_bssid, 0xff, ETH_ALEN);
387 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
388 ath5k_hw_set_opmode(ah);
389
390 ath5k_hw_set_rfgain_opt(ah);
391
392 return ah;
393err_free:
394 kfree(ah);
395err:
396 return ERR_PTR(ret);
397}
398
399/*
400 * Bring up MAC + PHY Chips
401 */
402static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
403{
Nick Kossifidis56c90542008-02-28 16:20:52 -0500404 struct pci_dev *pdev = ah->ah_sc->pdev;
405 u32 turbo, mode, clock, bus_flags;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200406 int ret;
407
408 turbo = 0;
409 mode = 0;
410 clock = 0;
411
412 ATH5K_TRACE(ah->ah_sc);
413
414 /* Wakeup the device */
415 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
416 if (ret) {
417 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
418 return ret;
419 }
420
421 if (ah->ah_version != AR5K_AR5210) {
422 /*
423 * Get channel mode flags
424 */
425
426 if (ah->ah_radio >= AR5K_RF5112) {
427 mode = AR5K_PHY_MODE_RAD_RF5112;
428 clock = AR5K_PHY_PLL_RF5112;
429 } else {
430 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
431 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
432 }
433
434 if (flags & CHANNEL_2GHZ) {
435 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
436 clock |= AR5K_PHY_PLL_44MHZ;
437
438 if (flags & CHANNEL_CCK) {
439 mode |= AR5K_PHY_MODE_MOD_CCK;
440 } else if (flags & CHANNEL_OFDM) {
441 /* XXX Dynamic OFDM/CCK is not supported by the
442 * AR5211 so we set MOD_OFDM for plain g (no
443 * CCK headers) operation. We need to test
444 * this, 5211 might support ofdm-only g after
445 * all, there are also initial register values
446 * in the code for g mode (see initvals.c). */
447 if (ah->ah_version == AR5K_AR5211)
448 mode |= AR5K_PHY_MODE_MOD_OFDM;
449 else
450 mode |= AR5K_PHY_MODE_MOD_DYN;
451 } else {
452 ATH5K_ERR(ah->ah_sc,
453 "invalid radio modulation mode\n");
454 return -EINVAL;
455 }
456 } else if (flags & CHANNEL_5GHZ) {
457 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
458 clock |= AR5K_PHY_PLL_40MHZ;
459
460 if (flags & CHANNEL_OFDM)
461 mode |= AR5K_PHY_MODE_MOD_OFDM;
462 else {
463 ATH5K_ERR(ah->ah_sc,
464 "invalid radio modulation mode\n");
465 return -EINVAL;
466 }
467 } else {
468 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
469 return -EINVAL;
470 }
471
472 if (flags & CHANNEL_TURBO)
473 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
474 } else { /* Reset the device */
475
476 /* ...enable Atheros turbo mode if requested */
477 if (flags & CHANNEL_TURBO)
478 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
479 AR5K_PHY_TURBO);
480 }
481
Nick Kossifidis56c90542008-02-28 16:20:52 -0500482 /* reseting PCI on PCI-E cards results card to hang
483 * and always return 0xffff... so we ingore that flag
484 * for PCI-E cards */
485 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
486
487 /* Reset chipset */
488 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
489 AR5K_RESET_CTL_BASEBAND | bus_flags);
490 if (ret) {
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300491 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200492 return -EIO;
493 }
494
495 if (ah->ah_version == AR5K_AR5210)
496 udelay(2300);
497
498 /* ...wakeup again!*/
499 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
500 if (ret) {
501 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
502 return ret;
503 }
504
505 /* ...final warm reset */
506 if (ath5k_hw_nic_reset(ah, 0)) {
507 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
508 return -EIO;
509 }
510
511 if (ah->ah_version != AR5K_AR5210) {
512 /* ...set the PHY operating mode */
513 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
514 udelay(300);
515
516 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
517 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
518 }
519
520 return 0;
521}
522
523/*
524 * Get the rate table for a specific operation mode
525 */
526const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
527 unsigned int mode)
528{
529 ATH5K_TRACE(ah->ah_sc);
530
531 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
532 return NULL;
533
534 /* Get rate tables */
535 switch (mode) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500536 case AR5K_MODE_11A:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200537 return &ath5k_rt_11a;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500538 case AR5K_MODE_11A_TURBO:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200539 return &ath5k_rt_turbo;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500540 case AR5K_MODE_11B:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200541 return &ath5k_rt_11b;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500542 case AR5K_MODE_11G:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200543 return &ath5k_rt_11g;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500544 case AR5K_MODE_11G_TURBO:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200545 return &ath5k_rt_xr;
546 }
547
548 return NULL;
549}
550
551/*
552 * Free the ath5k_hw struct
553 */
554void ath5k_hw_detach(struct ath5k_hw *ah)
555{
556 ATH5K_TRACE(ah->ah_sc);
557
Pavel Roskinf50e4a82008-03-12 16:13:31 -0400558 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
559
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200560 if (ah->ah_rf_banks != NULL)
561 kfree(ah->ah_rf_banks);
562
563 /* assume interrupts are down */
564 kfree(ah);
565}
566
567/****************************\
568 Reset function and helpers
569\****************************/
570
571/**
572 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
573 *
574 * @ah: the &struct ath5k_hw
575 * @channel: the currently set channel upon reset
576 *
577 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
578 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
579 * depending on the bandwidth of the channel.
580 *
581 */
582static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
583 struct ieee80211_channel *channel)
584{
585 /* Get exponent and mantissa and set it */
586 u32 coef_scaled, coef_exp, coef_man,
587 ds_coef_exp, ds_coef_man, clock;
588
589 if (!(ah->ah_version == AR5K_AR5212) ||
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500590 !(channel->hw_value & CHANNEL_OFDM))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200591 BUG();
592
593 /* Seems there are two PLLs, one for baseband sampling and one
594 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
595 * turbo. */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500596 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200597 coef_scaled = ((5 * (clock << 24)) / 2) /
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500598 channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200599
600 for (coef_exp = 31; coef_exp > 0; coef_exp--)
601 if ((coef_scaled >> coef_exp) & 0x1)
602 break;
603
604 if (!coef_exp)
605 return -EINVAL;
606
607 coef_exp = 14 - (coef_exp - 24);
608 coef_man = coef_scaled +
609 (1 << (24 - coef_exp - 1));
610 ds_coef_man = coef_man >> (24 - coef_exp);
611 ds_coef_exp = coef_exp - 16;
612
613 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
614 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
615 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
616 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
617
618 return 0;
619}
620
621/**
622 * ath5k_hw_write_rate_duration - set rate duration during hw resets
623 *
624 * @ah: the &struct ath5k_hw
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500625 * @mode: one of enum ath5k_driver_mode
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200626 *
627 * Write the rate duration table for the current mode upon hw reset. This
628 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
629 * an ACK timeout for the hardware for the current mode for each rate. The
630 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
631 * and 11Mbps) have another register for the short preamble ACK timeout
632 * calculation.
633 *
634 */
635static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500636 unsigned int mode)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200637{
638 struct ath5k_softc *sc = ah->ah_sc;
639 const struct ath5k_rate_table *rt;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500640 struct ieee80211_rate srate = {};
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200641 unsigned int i;
642
643 /* Get rate table for the current operating mode */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500644 rt = ath5k_hw_get_rate_table(ah, mode);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200645
646 /* Write rate duration table */
647 for (i = 0; i < rt->rate_count; i++) {
648 const struct ath5k_rate *rate, *control_rate;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500649
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200650 u32 reg;
651 u16 tx_time;
652
653 rate = &rt->rates[i];
654 control_rate = &rt->rates[rate->control_rate];
655
656 /* Set ACK timeout */
657 reg = AR5K_RATE_DUR(rate->rate_code);
658
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500659 srate.bitrate = control_rate->rate_kbps/100;
660
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200661 /* An ACK frame consists of 10 bytes. If you add the FCS,
662 * which ieee80211_generic_frame_duration() adds,
663 * its 14 bytes. Note we use the control rate and not the
664 * actual rate for this rate. See mac80211 tx.c
665 * ieee80211_duration() for a brief description of
666 * what rate we should choose to TX ACKs. */
Pavel Roskin38c07b42008-02-26 17:59:14 -0500667 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
668 sc->vif, 10, &srate));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200669
670 ath5k_hw_reg_write(ah, tx_time, reg);
671
672 if (!HAS_SHPREAMBLE(i))
673 continue;
674
675 /*
676 * We're not distinguishing short preamble here,
677 * This is true, all we'll get is a longer value here
678 * which is not necessarilly bad. We could use
679 * export ieee80211_frame_duration() but that needs to be
680 * fixed first to be properly used by mac802111 drivers:
681 *
682 * - remove erp stuff and let the routine figure ofdm
683 * erp rates
684 * - remove passing argument ieee80211_local as
685 * drivers don't have access to it
686 * - move drivers using ieee80211_generic_frame_duration()
687 * to this
688 */
689 ath5k_hw_reg_write(ah, tx_time,
690 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
691 }
692}
693
694/*
695 * Main reset function
696 */
697int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
698 struct ieee80211_channel *channel, bool change_channel)
699{
700 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
Nick Kossifidis56c90542008-02-28 16:20:52 -0500701 struct pci_dev *pdev = ah->ah_sc->pdev;
702 u32 data, s_seq, s_ant, s_led[3], dma_size;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500703 unsigned int i, mode, freq, ee_mode, ant[2];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200704 int ret;
705
706 ATH5K_TRACE(ah->ah_sc);
707
708 s_seq = 0;
709 s_ant = 0;
710 ee_mode = 0;
711 freq = 0;
712 mode = 0;
713
714 /*
715 * Save some registers before a reset
716 */
717 /*DCU/Antenna selection not available on 5210*/
718 if (ah->ah_version != AR5K_AR5210) {
Joe Perchese9010e22008-03-07 14:21:16 -0800719 if (change_channel) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200720 /* Seq number for queue 0 -do this for all queues ? */
721 s_seq = ath5k_hw_reg_read(ah,
722 AR5K_QUEUE_DFS_SEQNUM(0));
723 /*Default antenna*/
724 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
725 }
726 }
727
728 /*GPIOs*/
729 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
730 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
731 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
732
Joe Perchese9010e22008-03-07 14:21:16 -0800733 if (change_channel && ah->ah_rf_banks != NULL)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200734 ath5k_hw_get_rf_gain(ah);
735
736
737 /*Wakeup the device*/
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500738 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200739 if (ret)
740 return ret;
741
742 /*
743 * Initialize operating mode
744 */
745 ah->ah_op_mode = op_mode;
746
747 /*
748 * 5111/5112 Settings
749 * 5210 only comes with RF5110
750 */
751 if (ah->ah_version != AR5K_AR5210) {
752 if (ah->ah_radio != AR5K_RF5111 &&
753 ah->ah_radio != AR5K_RF5112 &&
Nick Kossifidis903b4742008-02-28 14:50:50 -0500754 ah->ah_radio != AR5K_RF5413 &&
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300755 ah->ah_radio != AR5K_RF2413 &&
756 ah->ah_radio != AR5K_RF2425) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200757 ATH5K_ERR(ah->ah_sc,
758 "invalid phy radio: %u\n", ah->ah_radio);
759 return -EINVAL;
760 }
761
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500762 switch (channel->hw_value & CHANNEL_MODES) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200763 case CHANNEL_A:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500764 mode = AR5K_MODE_11A;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200765 freq = AR5K_INI_RFGAIN_5GHZ;
766 ee_mode = AR5K_EEPROM_MODE_11A;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200767 break;
768 case CHANNEL_G:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500769 mode = AR5K_MODE_11G;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200770 freq = AR5K_INI_RFGAIN_2GHZ;
771 ee_mode = AR5K_EEPROM_MODE_11G;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200772 break;
773 case CHANNEL_B:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500774 mode = AR5K_MODE_11B;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200775 freq = AR5K_INI_RFGAIN_2GHZ;
776 ee_mode = AR5K_EEPROM_MODE_11B;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200777 break;
778 case CHANNEL_T:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500779 mode = AR5K_MODE_11A_TURBO;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200780 freq = AR5K_INI_RFGAIN_5GHZ;
781 ee_mode = AR5K_EEPROM_MODE_11A;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200782 break;
783 /*Is this ok on 5211 too ?*/
784 case CHANNEL_TG:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500785 mode = AR5K_MODE_11G_TURBO;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200786 freq = AR5K_INI_RFGAIN_2GHZ;
787 ee_mode = AR5K_EEPROM_MODE_11G;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200788 break;
789 case CHANNEL_XR:
790 if (ah->ah_version == AR5K_AR5211) {
791 ATH5K_ERR(ah->ah_sc,
792 "XR mode not available on 5211");
793 return -EINVAL;
794 }
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500795 mode = AR5K_MODE_XR;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200796 freq = AR5K_INI_RFGAIN_5GHZ;
797 ee_mode = AR5K_EEPROM_MODE_11A;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200798 break;
799 default:
800 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500801 "invalid channel: %d\n", channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200802 return -EINVAL;
803 }
804
805 /* PHY access enable */
806 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
807
808 }
809
810 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
811 if (ret)
812 return ret;
813
814 /*
815 * 5211/5212 Specific
816 */
817 if (ah->ah_version != AR5K_AR5210) {
818 /*
819 * Write initial RF gain settings
820 * This should work for both 5111/5112
821 */
822 ret = ath5k_hw_rfgain(ah, freq);
823 if (ret)
824 return ret;
825
826 mdelay(1);
827
828 /*
829 * Write some more initial register settings
830 */
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -0500831 if (ah->ah_version == AR5K_AR5212) {
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300832 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200833
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500834 if (channel->hw_value == CHANNEL_G)
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -0500835 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
836 ath5k_hw_reg_write(ah, 0x00f80d80,
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300837 0x994c);
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -0500838 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
839 ath5k_hw_reg_write(ah, 0x00380140,
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300840 0x994c);
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -0500841 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
842 ath5k_hw_reg_write(ah, 0x00fc0ec0,
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300843 0x994c);
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -0500844 else /* 2425 */
845 ath5k_hw_reg_write(ah, 0x00fc0fc0,
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300846 0x994c);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200847 else
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300848 ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200849
Nick Kossifidis2203d6b2008-07-20 06:36:52 +0300850 /* Some bits are disabled here, we know nothing about
851 * register 0xa228 yet, most of the times this ends up
852 * with a value 0x9b5 -haven't seen any dump with
853 * a different value- */
854 /* Got this from decompiling binary HAL */
855 data = ath5k_hw_reg_read(ah, 0xa228);
856 data &= 0xfffffdff;
857 ath5k_hw_reg_write(ah, data, 0xa228);
858
859 data = ath5k_hw_reg_read(ah, 0xa228);
860 data &= 0xfffe03ff;
861 ath5k_hw_reg_write(ah, data, 0xa228);
862 data = 0;
863
864 /* Just write 0x9b5 ? */
865 /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300866 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200867 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
868 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
869 }
870
871 /* Fix for first revision of the RF5112 RF chipset */
872 if (ah->ah_radio >= AR5K_RF5112 &&
873 ah->ah_radio_5ghz_revision <
874 AR5K_SREV_RAD_5112A) {
875 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
876 AR5K_PHY_CCKTXCTL);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500877 if (channel->hw_value & CHANNEL_5GHZ)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200878 data = 0xffb81020;
879 else
880 data = 0xffb80d20;
881 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
Nick Kossifidis2203d6b2008-07-20 06:36:52 +0300882 data = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200883 }
884
885 /*
886 * Set TX power (FIXME)
887 */
888 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
889 if (ret)
890 return ret;
891
Luis R. Rodriguez132127e2008-01-04 02:21:05 -0500892 /* Write rate duration table only on AR5212 and if
893 * virtual interface has already been brought up
894 * XXX: rethink this after new mode changes to
895 * mac80211 are integrated */
896 if (ah->ah_version == AR5K_AR5212 &&
897 ah->ah_sc->vif != NULL)
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500898 ath5k_hw_write_rate_duration(ah, mode);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200899
900 /*
901 * Write RF registers
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200902 */
903 ret = ath5k_hw_rfregs(ah, channel, mode);
904 if (ret)
905 return ret;
906
907 /*
908 * Configure additional registers
909 */
910
911 /* Write OFDM timings on 5212*/
912 if (ah->ah_version == AR5K_AR5212 &&
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500913 channel->hw_value & CHANNEL_OFDM) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200914 ret = ath5k_hw_write_ofdm_timings(ah, channel);
915 if (ret)
916 return ret;
917 }
918
919 /*Enable/disable 802.11b mode on 5111
920 (enable 2111 frequency converter + CCK)*/
921 if (ah->ah_radio == AR5K_RF5111) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500922 if (mode == AR5K_MODE_11B)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200923 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
924 AR5K_TXCFG_B_MODE);
925 else
926 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
927 AR5K_TXCFG_B_MODE);
928 }
929
930 /*
931 * Set channel and calibrate the PHY
932 */
933 ret = ath5k_hw_channel(ah, channel);
934 if (ret)
935 return ret;
936
937 /* Set antenna mode */
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300938 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200939 ah->ah_antenna[ee_mode][0], 0xfffffc06);
940
941 /*
942 * In case a fixed antenna was set as default
943 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
944 * registers.
945 */
946 if (s_ant != 0){
947 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
948 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
949 else /* 2 - Aux */
950 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
951 } else {
952 ant[0] = AR5K_ANT_FIXED_A;
953 ant[1] = AR5K_ANT_FIXED_B;
954 }
955
956 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
957 AR5K_PHY_ANT_SWITCH_TABLE_0);
958 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
959 AR5K_PHY_ANT_SWITCH_TABLE_1);
960
961 /* Commit values from EEPROM */
962 if (ah->ah_radio == AR5K_RF5111)
963 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
964 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
965
966 ath5k_hw_reg_write(ah,
967 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300968 AR5K_PHY_NFTHRES);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200969
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300970 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200971 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
972 0xffffc07f);
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300973 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200974 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
975 0xfffc0fff);
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300976 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200977 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
978 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
979 0xffff0000);
980
981 ath5k_hw_reg_write(ah,
982 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
983 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
984 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300985 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200986
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300987 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200988 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300989 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200990 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
Nick Kossifidis0bacdf32008-07-30 13:18:59 +0300991 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200992
993 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
994 AR5K_PHY_IQ_CORR_ENABLE |
995 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
996 ee->ee_q_cal[ee_mode]);
997
998 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
999 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1000 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1001 ee->ee_margin_tx_rx[ee_mode]);
1002
1003 } else {
1004 mdelay(1);
1005 /* Disable phy and wait */
1006 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1007 mdelay(1);
1008 }
1009
1010 /*
1011 * Restore saved values
1012 */
1013 /*DCU/Antenna selection not available on 5210*/
1014 if (ah->ah_version != AR5K_AR5210) {
1015 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
1016 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
1017 }
1018 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1019 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1020 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1021
1022 /*
1023 * Misc
1024 */
1025 /* XXX: add ah->aid once mac80211 gives this to us */
1026 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
1027
1028 ath5k_hw_set_opmode(ah);
1029 /*PISR/SISR Not available on 5210*/
1030 if (ah->ah_version != AR5K_AR5210) {
1031 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1032 /* If we later allow tuning for this, store into sc structure */
1033 data = AR5K_TUNE_RSSI_THRES |
1034 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
1035 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
1036 }
1037
1038 /*
1039 * Set Rx/Tx DMA Configuration
Nick Kossifidis56c90542008-02-28 16:20:52 -05001040 *
1041 * Set maximum DMA size (512) except for PCI-E cards since
1042 * it causes rx overruns and tx errors (tested on 5424 but since
1043 * rx overruns also occur on 5416/5418 with madwifi we set 128
1044 * for all PCI-E cards to be safe).
1045 *
1046 * In dumps this is 128 for allchips.
1047 *
1048 * XXX: need to check 5210 for this
1049 * TODO: Check out tx triger level, it's always 64 on dumps but I
1050 * guess we can tweak it and see how it goes ;-)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001051 */
Nick Kossifidis56c90542008-02-28 16:20:52 -05001052 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001053 if (ah->ah_version != AR5K_AR5210) {
Nick Kossifidis56c90542008-02-28 16:20:52 -05001054 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1055 AR5K_TXCFG_SDMAMR, dma_size);
1056 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1057 AR5K_RXCFG_SDMAMW, dma_size);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001058 }
1059
1060 /*
1061 * Enable the PHY and wait until completion
1062 */
1063 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1064
1065 /*
Nick Kossifidis2203d6b2008-07-20 06:36:52 +03001066 * On 5211+ read activation -> rx delay
1067 * and use it.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001068 */
1069 if (ah->ah_version != AR5K_AR5210) {
1070 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1071 AR5K_PHY_RX_DELAY_M;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001072 data = (channel->hw_value & CHANNEL_CCK) ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001073 ((data << 2) / 22) : (data / 10);
1074
Nick Kossifidis2203d6b2008-07-20 06:36:52 +03001075 udelay(100 + (2 * data));
1076 data = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001077 } else {
1078 mdelay(1);
1079 }
1080
1081 /*
Nick Kossifidise2a0cce2008-07-20 06:38:16 +03001082 * Perform ADC test (?)
1083 */
1084 data = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1085 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1086 for (i = 0; i <= 20; i++) {
1087 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1088 break;
1089 udelay(200);
1090 }
1091 ath5k_hw_reg_write(ah, data, AR5K_PHY_TST1);
1092 data = 0;
1093
1094 /*
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001095 * Start automatic gain calibration
1096 *
1097 * During AGC calibration RX path is re-routed to
1098 * a signal detector so we don't receive anything.
1099 *
1100 * This method is used to calibrate some static offsets
1101 * used together with on-the fly I/Q calibration (the
1102 * one performed via ath5k_hw_phy_calibrate), that doesn't
1103 * interrupt rx path.
1104 *
1105 * If we are in a noisy environment AGC calibration may time
1106 * out.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001107 */
1108 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1109 AR5K_PHY_AGCCTL_CAL);
1110
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001111 /* At the same time start I/Q calibration for QAM constellation
1112 * -no need for CCK- */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001113 ah->ah_calibration = false;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001114 if (!(mode == AR5K_MODE_11B)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001115 ah->ah_calibration = true;
1116 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1117 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1118 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1119 AR5K_PHY_IQ_RUN);
1120 }
1121
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001122 /* Wait for gain calibration to finish (we check for I/Q calibration
1123 * during ath5k_phy_calibrate) */
1124 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1125 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1126 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1127 channel->center_freq);
1128 return -EAGAIN;
1129 }
1130
1131 /*
1132 * Start noise floor calibration
1133 *
1134 * If we run NF calibration before AGC, it always times out.
1135 * Binary HAL starts NF and AGC calibration at the same time
1136 * and only waits for AGC to finish. I believe that's wrong because
1137 * during NF calibration, rx path is also routed to a detector, so if
1138 * it doesn't finish we won't have RX.
1139 *
1140 * XXX: Find an interval that's OK for all cards...
1141 */
1142 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1143 if (ret)
1144 return ret;
1145
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001146 /*
1147 * Reset queues and start beacon timers at the end of the reset routine
1148 */
1149 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1150 /*No QCU on 5210*/
1151 if (ah->ah_version != AR5K_AR5210)
1152 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
1153
1154 ret = ath5k_hw_reset_tx_queue(ah, i);
1155 if (ret) {
1156 ATH5K_ERR(ah->ah_sc,
1157 "failed to reset TX queue #%d\n", i);
1158 return ret;
1159 }
1160 }
1161
1162 /* Pre-enable interrupts on 5211/5212*/
1163 if (ah->ah_version != AR5K_AR5210)
1164 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
1165 AR5K_INT_FATAL);
1166
1167 /*
1168 * Set RF kill flags if supported by the device (read from the EEPROM)
1169 * Disable gpio_intr for now since it results system hang.
1170 * TODO: Handle this in ath5k_intr
1171 */
1172#if 0
1173 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1174 ath5k_hw_set_gpio_input(ah, 0);
1175 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1176 if (ah->ah_gpio[0] == 0)
1177 ath5k_hw_set_gpio_intr(ah, 0, 1);
1178 else
1179 ath5k_hw_set_gpio_intr(ah, 0, 0);
1180 }
1181#endif
1182
1183 /*
1184 * Set the 32MHz reference clock on 5212 phy clock sleep register
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -05001185 *
1186 * TODO: Find out how to switch to external 32Khz clock to save power
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001187 */
1188 if (ah->ah_version == AR5K_AR5212) {
1189 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1190 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1191 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1192 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1193 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
Nick Kossifidis903b4742008-02-28 14:50:50 -05001194 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
Nick Kossifidis2203d6b2008-07-20 06:36:52 +03001195
1196 data = ath5k_hw_reg_read(ah, AR5K_USEC_5211) & 0xffffc07f ;
1197 data |= (ah->ah_phy_spending == AR5K_PHY_SPENDING_18) ?
1198 0x00000f80 : 0x00001380 ;
1199 ath5k_hw_reg_write(ah, data, AR5K_USEC_5211);
1200 data = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001201 }
1202
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -05001203 if (ah->ah_version == AR5K_AR5212) {
1204 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1205 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1206 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1207 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1208 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
1209 }
1210
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001211 /*
1212 * Disable beacons and reset the register
1213 */
1214 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1215 AR5K_BEACON_RESET_TSF);
1216
1217 return 0;
1218}
1219
1220/*
1221 * Reset chipset
1222 */
1223static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1224{
1225 int ret;
1226 u32 mask = val ? val : ~0U;
1227
1228 ATH5K_TRACE(ah->ah_sc);
1229
1230 /* Read-and-clear RX Descriptor Pointer*/
1231 ath5k_hw_reg_read(ah, AR5K_RXDP);
1232
1233 /*
1234 * Reset the device and wait until success
1235 */
1236 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1237
1238 /* Wait at least 128 PCI clocks */
1239 udelay(15);
1240
1241 if (ah->ah_version == AR5K_AR5210) {
1242 val &= AR5K_RESET_CTL_CHIP;
1243 mask &= AR5K_RESET_CTL_CHIP;
1244 } else {
1245 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1246 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1247 }
1248
1249 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1250
1251 /*
1252 * Reset configuration register (for hw byte-swap). Note that this
1253 * is only set for big endian. We do the necessary magic in
1254 * AR5K_INIT_CFG.
1255 */
1256 if ((val & AR5K_RESET_CTL_PCU) == 0)
1257 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1258
1259 return ret;
1260}
1261
1262/*
1263 * Power management functions
1264 */
1265
1266/*
1267 * Sleep control
1268 */
1269int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1270 bool set_chip, u16 sleep_duration)
1271{
1272 unsigned int i;
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001273 u32 staid, data;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001274
1275 ATH5K_TRACE(ah->ah_sc);
1276 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1277
1278 switch (mode) {
1279 case AR5K_PM_AUTO:
1280 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1281 /* fallthrough */
1282 case AR5K_PM_NETWORK_SLEEP:
Joe Perchese9010e22008-03-07 14:21:16 -08001283 if (set_chip)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001284 ath5k_hw_reg_write(ah,
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001285 AR5K_SLEEP_CTL_SLE_ALLOW |
1286 sleep_duration,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001287 AR5K_SLEEP_CTL);
1288
1289 staid |= AR5K_STA_ID1_PWR_SV;
1290 break;
1291
1292 case AR5K_PM_FULL_SLEEP:
Joe Perchese9010e22008-03-07 14:21:16 -08001293 if (set_chip)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001294 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1295 AR5K_SLEEP_CTL);
1296
1297 staid |= AR5K_STA_ID1_PWR_SV;
1298 break;
1299
1300 case AR5K_PM_AWAKE:
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001301
1302 staid &= ~AR5K_STA_ID1_PWR_SV;
1303
Joe Perchese9010e22008-03-07 14:21:16 -08001304 if (!set_chip)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001305 goto commit;
1306
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001307 /* Preserve sleep duration */
1308 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
1309 if( data & 0xffc00000 ){
1310 data = 0;
1311 } else {
1312 data = data & 0xfffcffff;
1313 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001314
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001315 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
1316 udelay(15);
1317
1318 for (i = 50; i > 0; i--) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001319 /* Check if the chip did wake up */
1320 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1321 AR5K_PCICFG_SPWR_DN) == 0)
1322 break;
1323
1324 /* Wait a bit and retry */
1325 udelay(200);
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001326 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001327 }
1328
1329 /* Fail if the chip didn't wake up */
1330 if (i <= 0)
1331 return -EIO;
1332
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001333 break;
1334
1335 default:
1336 return -EINVAL;
1337 }
1338
1339commit:
1340 ah->ah_power_mode = mode;
1341 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1342
1343 return 0;
1344}
1345
1346/***********************\
1347 DMA Related Functions
1348\***********************/
1349
1350/*
1351 * Receive functions
1352 */
1353
1354/*
1355 * Start DMA receive
1356 */
1357void ath5k_hw_start_rx(struct ath5k_hw *ah)
1358{
1359 ATH5K_TRACE(ah->ah_sc);
1360 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001361 ath5k_hw_reg_read(ah, AR5K_CR);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001362}
1363
1364/*
1365 * Stop DMA receive
1366 */
1367int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1368{
1369 unsigned int i;
1370
1371 ATH5K_TRACE(ah->ah_sc);
1372 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1373
1374 /*
1375 * It may take some time to disable the DMA receive unit
1376 */
1377 for (i = 2000; i > 0 &&
1378 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1379 i--)
1380 udelay(10);
1381
1382 return i ? 0 : -EBUSY;
1383}
1384
1385/*
1386 * Get the address of the RX Descriptor
1387 */
1388u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1389{
1390 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1391}
1392
1393/*
1394 * Set the address of the RX Descriptor
1395 */
1396void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1397{
1398 ATH5K_TRACE(ah->ah_sc);
1399
1400 /*TODO:Shouldn't we check if RX is enabled first ?*/
1401 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1402}
1403
1404/*
1405 * Transmit functions
1406 */
1407
1408/*
1409 * Start DMA transmit for a specific queue
1410 * (see also QCU/DCU functions)
1411 */
1412int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1413{
1414 u32 tx_queue;
1415
1416 ATH5K_TRACE(ah->ah_sc);
1417 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1418
1419 /* Return if queue is declared inactive */
1420 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1421 return -EIO;
1422
1423 if (ah->ah_version == AR5K_AR5210) {
1424 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1425
1426 /*
1427 * Set the queue by type on 5210
1428 */
1429 switch (ah->ah_txq[queue].tqi_type) {
1430 case AR5K_TX_QUEUE_DATA:
1431 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1432 break;
1433 case AR5K_TX_QUEUE_BEACON:
1434 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1435 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1436 AR5K_BSR);
1437 break;
1438 case AR5K_TX_QUEUE_CAB:
1439 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1440 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1441 AR5K_BCR_BDMAE, AR5K_BSR);
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446 /* Start queue */
1447 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001448 ath5k_hw_reg_read(ah, AR5K_CR);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001449 } else {
1450 /* Return if queue is disabled */
1451 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1452 return -EIO;
1453
1454 /* Start queue */
1455 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1456 }
1457
1458 return 0;
1459}
1460
1461/*
1462 * Stop DMA transmit for a specific queue
1463 * (see also QCU/DCU functions)
1464 */
1465int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1466{
1467 unsigned int i = 100;
1468 u32 tx_queue, pending;
1469
1470 ATH5K_TRACE(ah->ah_sc);
1471 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1472
1473 /* Return if queue is declared inactive */
1474 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1475 return -EIO;
1476
1477 if (ah->ah_version == AR5K_AR5210) {
1478 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1479
1480 /*
1481 * Set by queue type
1482 */
1483 switch (ah->ah_txq[queue].tqi_type) {
1484 case AR5K_TX_QUEUE_DATA:
1485 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1486 break;
1487 case AR5K_TX_QUEUE_BEACON:
1488 case AR5K_TX_QUEUE_CAB:
1489 /* XXX Fix me... */
1490 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1491 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
1497 /* Stop queue */
1498 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
Jiri Slaby274c7c32008-07-15 17:44:20 +02001499 ath5k_hw_reg_read(ah, AR5K_CR);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001500 } else {
1501 /*
1502 * Schedule TX disable and wait until queue is empty
1503 */
1504 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1505
1506 /*Check for pending frames*/
1507 do {
1508 pending = ath5k_hw_reg_read(ah,
1509 AR5K_QUEUE_STATUS(queue)) &
1510 AR5K_QCU_STS_FRMPENDCNT;
1511 udelay(100);
1512 } while (--i && pending);
1513
1514 /* Clear register */
1515 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
Jiri Slaby274c7c32008-07-15 17:44:20 +02001516 if (pending)
1517 return -EBUSY;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001518 }
1519
1520 /* TODO: Check for success else return error */
1521 return 0;
1522}
1523
1524/*
1525 * Get the address of the TX Descriptor for a specific queue
1526 * (see also QCU/DCU functions)
1527 */
1528u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1529{
1530 u16 tx_reg;
1531
1532 ATH5K_TRACE(ah->ah_sc);
1533 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1534
1535 /*
1536 * Get the transmit queue descriptor pointer from the selected queue
1537 */
1538 /*5210 doesn't have QCU*/
1539 if (ah->ah_version == AR5K_AR5210) {
1540 switch (ah->ah_txq[queue].tqi_type) {
1541 case AR5K_TX_QUEUE_DATA:
1542 tx_reg = AR5K_NOQCU_TXDP0;
1543 break;
1544 case AR5K_TX_QUEUE_BEACON:
1545 case AR5K_TX_QUEUE_CAB:
1546 tx_reg = AR5K_NOQCU_TXDP1;
1547 break;
1548 default:
1549 return 0xffffffff;
1550 }
1551 } else {
1552 tx_reg = AR5K_QUEUE_TXDP(queue);
1553 }
1554
1555 return ath5k_hw_reg_read(ah, tx_reg);
1556}
1557
1558/*
1559 * Set the address of the TX Descriptor for a specific queue
1560 * (see also QCU/DCU functions)
1561 */
1562int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1563{
1564 u16 tx_reg;
1565
1566 ATH5K_TRACE(ah->ah_sc);
1567 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1568
1569 /*
1570 * Set the transmit queue descriptor pointer register by type
1571 * on 5210
1572 */
1573 if (ah->ah_version == AR5K_AR5210) {
1574 switch (ah->ah_txq[queue].tqi_type) {
1575 case AR5K_TX_QUEUE_DATA:
1576 tx_reg = AR5K_NOQCU_TXDP0;
1577 break;
1578 case AR5K_TX_QUEUE_BEACON:
1579 case AR5K_TX_QUEUE_CAB:
1580 tx_reg = AR5K_NOQCU_TXDP1;
1581 break;
1582 default:
1583 return -EINVAL;
1584 }
1585 } else {
1586 /*
1587 * Set the transmit queue descriptor pointer for
1588 * the selected queue on QCU for 5211+
1589 * (this won't work if the queue is still active)
1590 */
1591 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1592 return -EIO;
1593
1594 tx_reg = AR5K_QUEUE_TXDP(queue);
1595 }
1596
1597 /* Set descriptor pointer */
1598 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1599
1600 return 0;
1601}
1602
1603/*
1604 * Update tx trigger level
1605 */
1606int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1607{
1608 u32 trigger_level, imr;
1609 int ret = -EIO;
1610
1611 ATH5K_TRACE(ah->ah_sc);
1612
1613 /*
1614 * Disable interrupts by setting the mask
1615 */
1616 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1617
1618 /*TODO: Boundary check on trigger_level*/
1619 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1620 AR5K_TXCFG_TXFULL);
1621
Joe Perchese9010e22008-03-07 14:21:16 -08001622 if (!increase) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001623 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1624 goto done;
1625 } else
1626 trigger_level +=
1627 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1628
1629 /*
1630 * Update trigger level on success
1631 */
1632 if (ah->ah_version == AR5K_AR5210)
1633 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1634 else
1635 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1636 AR5K_TXCFG_TXFULL, trigger_level);
1637
1638 ret = 0;
1639
1640done:
1641 /*
1642 * Restore interrupt mask
1643 */
1644 ath5k_hw_set_intr(ah, imr);
1645
1646 return ret;
1647}
1648
1649/*
1650 * Interrupt handling
1651 */
1652
1653/*
1654 * Check if we have pending interrupts
1655 */
1656bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1657{
1658 ATH5K_TRACE(ah->ah_sc);
1659 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1660}
1661
1662/*
1663 * Get interrupt mask (ISR)
1664 */
1665int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1666{
1667 u32 data;
1668
1669 ATH5K_TRACE(ah->ah_sc);
1670
1671 /*
1672 * Read interrupt status from the Interrupt Status register
1673 * on 5210
1674 */
1675 if (ah->ah_version == AR5K_AR5210) {
1676 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1677 if (unlikely(data == AR5K_INT_NOCARD)) {
1678 *interrupt_mask = data;
1679 return -ENODEV;
1680 }
1681 } else {
1682 /*
1683 * Read interrupt status from the Read-And-Clear shadow register
1684 * Note: PISR/SISR Not available on 5210
1685 */
1686 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1687 }
1688
1689 /*
1690 * Get abstract interrupt mask (driver-compatible)
1691 */
1692 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1693
1694 if (unlikely(data == AR5K_INT_NOCARD))
1695 return -ENODEV;
1696
1697 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1698 *interrupt_mask |= AR5K_INT_RX;
1699
1700 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1701 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1702 *interrupt_mask |= AR5K_INT_TX;
1703
1704 if (ah->ah_version != AR5K_AR5210) {
1705 /*HIU = Host Interface Unit (PCI etc)*/
1706 if (unlikely(data & (AR5K_ISR_HIUERR)))
1707 *interrupt_mask |= AR5K_INT_FATAL;
1708
1709 /*Beacon Not Ready*/
1710 if (unlikely(data & (AR5K_ISR_BNR)))
1711 *interrupt_mask |= AR5K_INT_BNR;
1712 }
1713
1714 /*
1715 * XXX: BMISS interrupts may occur after association.
1716 * I found this on 5210 code but it needs testing. If this is
1717 * true we should disable them before assoc and re-enable them
1718 * after a successfull assoc + some jiffies.
1719 */
1720#if 0
1721 interrupt_mask &= ~AR5K_INT_BMISS;
1722#endif
1723
1724 /*
1725 * In case we didn't handle anything,
1726 * print the register value.
1727 */
1728 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1729 ATH5K_PRINTF("0x%08x\n", data);
1730
1731 return 0;
1732}
1733
1734/*
1735 * Set interrupt mask
1736 */
1737enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1738{
1739 enum ath5k_int old_mask, int_mask;
1740
1741 /*
1742 * Disable card interrupts to prevent any race conditions
1743 * (they will be re-enabled afterwards).
1744 */
1745 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03001746 ath5k_hw_reg_read(ah, AR5K_IER);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001747
1748 old_mask = ah->ah_imr;
1749
1750 /*
1751 * Add additional, chipset-dependent interrupt mask flags
1752 * and write them to the IMR (interrupt mask register).
1753 */
1754 int_mask = new_mask & AR5K_INT_COMMON;
1755
1756 if (new_mask & AR5K_INT_RX)
1757 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1758 AR5K_IMR_RXDESC;
1759
1760 if (new_mask & AR5K_INT_TX)
1761 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1762 AR5K_IMR_TXURN;
1763
1764 if (ah->ah_version != AR5K_AR5210) {
1765 if (new_mask & AR5K_INT_FATAL) {
1766 int_mask |= AR5K_IMR_HIUERR;
1767 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1768 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1769 }
1770 }
1771
1772 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1773
1774 /* Store new interrupt mask */
1775 ah->ah_imr = new_mask;
1776
1777 /* ..re-enable interrupts */
1778 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
Jiri Slaby274c7c32008-07-15 17:44:20 +02001779 ath5k_hw_reg_read(ah, AR5K_IER);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001780
1781 return old_mask;
1782}
1783
1784
1785/*************************\
1786 EEPROM access functions
1787\*************************/
1788
1789/*
1790 * Read from eeprom
1791 */
1792static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1793{
1794 u32 status, timeout;
1795
1796 ATH5K_TRACE(ah->ah_sc);
1797 /*
1798 * Initialize EEPROM access
1799 */
1800 if (ah->ah_version == AR5K_AR5210) {
1801 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1802 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1803 } else {
1804 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1805 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1806 AR5K_EEPROM_CMD_READ);
1807 }
1808
1809 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1810 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1811 if (status & AR5K_EEPROM_STAT_RDDONE) {
1812 if (status & AR5K_EEPROM_STAT_RDERR)
1813 return -EIO;
1814 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1815 0xffff);
1816 return 0;
1817 }
1818 udelay(15);
1819 }
1820
1821 return -ETIMEDOUT;
1822}
1823
1824/*
1825 * Write to eeprom - currently disabled, use at your own risk
1826 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001827#if 0
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001828static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1829{
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001830
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001831 u32 status, timeout;
1832
1833 ATH5K_TRACE(ah->ah_sc);
1834
1835 /*
1836 * Initialize eeprom access
1837 */
1838
1839 if (ah->ah_version == AR5K_AR5210) {
1840 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1841 } else {
1842 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1843 AR5K_EEPROM_CMD_RESET);
1844 }
1845
1846 /*
1847 * Write data to data register
1848 */
1849
1850 if (ah->ah_version == AR5K_AR5210) {
1851 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1852 } else {
1853 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1854 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1855 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1856 AR5K_EEPROM_CMD_WRITE);
1857 }
1858
1859 /*
1860 * Check status
1861 */
1862
1863 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1864 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1865 if (status & AR5K_EEPROM_STAT_WRDONE) {
1866 if (status & AR5K_EEPROM_STAT_WRERR)
1867 return EIO;
1868 return 0;
1869 }
1870 udelay(15);
1871 }
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001872
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001873 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1874 return -EIO;
1875}
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001876#endif
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001877
1878/*
1879 * Translate binary channel representation in EEPROM to frequency
1880 */
1881static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1882{
1883 u16 val;
1884
1885 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1886 return bin;
1887
1888 if (mode == AR5K_EEPROM_MODE_11A) {
1889 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1890 val = (5 * bin) + 4800;
1891 else
1892 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1893 (bin * 10) + 5100;
1894 } else {
1895 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1896 val = bin + 2300;
1897 else
1898 val = bin + 2400;
1899 }
1900
1901 return val;
1902}
1903
1904/*
1905 * Read antenna infos from eeprom
1906 */
1907static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1908 unsigned int mode)
1909{
1910 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1911 u32 o = *offset;
1912 u16 val;
1913 int ret, i = 0;
1914
1915 AR5K_EEPROM_READ(o++, val);
1916 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1917 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1918 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1919
1920 AR5K_EEPROM_READ(o++, val);
1921 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1922 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1923 ee->ee_ant_control[mode][i++] = val & 0x3f;
1924
1925 AR5K_EEPROM_READ(o++, val);
1926 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1927 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1928 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1929
1930 AR5K_EEPROM_READ(o++, val);
1931 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1932 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1933 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1934 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1935
1936 AR5K_EEPROM_READ(o++, val);
1937 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1938 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1939 ee->ee_ant_control[mode][i++] = val & 0x3f;
1940
1941 /* Get antenna modes */
1942 ah->ah_antenna[mode][0] =
1943 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1944 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1945 ee->ee_ant_control[mode][1] |
1946 (ee->ee_ant_control[mode][2] << 6) |
1947 (ee->ee_ant_control[mode][3] << 12) |
1948 (ee->ee_ant_control[mode][4] << 18) |
1949 (ee->ee_ant_control[mode][5] << 24);
1950 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1951 ee->ee_ant_control[mode][6] |
1952 (ee->ee_ant_control[mode][7] << 6) |
1953 (ee->ee_ant_control[mode][8] << 12) |
1954 (ee->ee_ant_control[mode][9] << 18) |
1955 (ee->ee_ant_control[mode][10] << 24);
1956
1957 /* return new offset */
1958 *offset = o;
1959
1960 return 0;
1961}
1962
1963/*
1964 * Read supported modes from eeprom
1965 */
1966static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1967 unsigned int mode)
1968{
1969 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1970 u32 o = *offset;
1971 u16 val;
1972 int ret;
1973
1974 AR5K_EEPROM_READ(o++, val);
1975 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1976 ee->ee_thr_62[mode] = val & 0xff;
1977
1978 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1979 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1980
1981 AR5K_EEPROM_READ(o++, val);
1982 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1983 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1984
1985 AR5K_EEPROM_READ(o++, val);
1986 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1987
1988 if ((val & 0xff) & 0x80)
1989 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1990 else
1991 ee->ee_noise_floor_thr[mode] = val & 0xff;
1992
1993 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1994 ee->ee_noise_floor_thr[mode] =
1995 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1996
1997 AR5K_EEPROM_READ(o++, val);
1998 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1999 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
2000 ee->ee_xpd[mode] = val & 0x1;
2001
2002 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
2003 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
2004
2005 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
2006 AR5K_EEPROM_READ(o++, val);
2007 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
2008
2009 if (mode == AR5K_EEPROM_MODE_11A)
2010 ee->ee_xr_power[mode] = val & 0x3f;
2011 else {
2012 ee->ee_ob[mode][0] = val & 0x7;
2013 ee->ee_db[mode][0] = (val >> 3) & 0x7;
2014 }
2015 }
2016
2017 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
2018 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
2019 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
2020 } else {
2021 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
2022
2023 AR5K_EEPROM_READ(o++, val);
2024 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
2025
2026 if (mode == AR5K_EEPROM_MODE_11G)
2027 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
2028 }
2029
2030 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
2031 mode == AR5K_EEPROM_MODE_11A) {
2032 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2033 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2034 }
2035
2036 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
2037 mode == AR5K_EEPROM_MODE_11G)
2038 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
2039
2040 /* return new offset */
2041 *offset = o;
2042
2043 return 0;
2044}
2045
2046/*
2047 * Initialize eeprom & capabilities structs
2048 */
2049static int ath5k_eeprom_init(struct ath5k_hw *ah)
2050{
2051 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2052 unsigned int mode, i;
2053 int ret;
2054 u32 offset;
2055 u16 val;
2056
2057 /* Initial TX thermal adjustment values */
2058 ee->ee_tx_clip = 4;
2059 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
2060 ee->ee_gain_select = 1;
2061
2062 /*
2063 * Read values from EEPROM and store them in the capability structure
2064 */
2065 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
2066 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
2067 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
2068 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
2069 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
2070
2071 /* Return if we have an old EEPROM */
2072 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
2073 return 0;
2074
2075#ifdef notyet
2076 /*
2077 * Validate the checksum of the EEPROM date. There are some
2078 * devices with invalid EEPROMs.
2079 */
2080 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
2081 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
2082 cksum ^= val;
2083 }
2084 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
2085 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
2086 return -EIO;
2087 }
2088#endif
2089
2090 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
2091 ee_ant_gain);
2092
2093 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2094 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
2095 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
2096 }
2097
2098 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
2099 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
2100 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
2101 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
2102
2103 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
2104 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
2105 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
2106 }
2107
2108 /*
2109 * Get conformance test limit values
2110 */
2111 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
2112 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
2113
2114 for (i = 0; i < ee->ee_ctls; i++) {
2115 AR5K_EEPROM_READ(offset++, val);
2116 ee->ee_ctl[i] = (val >> 8) & 0xff;
2117 ee->ee_ctl[i + 1] = val & 0xff;
2118 }
2119
2120 /*
2121 * Get values for 802.11a (5GHz)
2122 */
2123 mode = AR5K_EEPROM_MODE_11A;
2124
2125 ee->ee_turbo_max_power[mode] =
2126 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
2127
2128 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
2129
2130 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2131 if (ret)
2132 return ret;
2133
2134 AR5K_EEPROM_READ(offset++, val);
2135 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2136 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
2137 ee->ee_db[mode][3] = (val >> 2) & 0x7;
2138 ee->ee_ob[mode][2] = (val << 1) & 0x7;
2139
2140 AR5K_EEPROM_READ(offset++, val);
2141 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
2142 ee->ee_db[mode][2] = (val >> 12) & 0x7;
2143 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
2144 ee->ee_db[mode][1] = (val >> 6) & 0x7;
2145 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
2146 ee->ee_db[mode][0] = val & 0x7;
2147
2148 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2149 if (ret)
2150 return ret;
2151
2152 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
2153 AR5K_EEPROM_READ(offset++, val);
2154 ee->ee_margin_tx_rx[mode] = val & 0x3f;
2155 }
2156
2157 /*
2158 * Get values for 802.11b (2.4GHz)
2159 */
2160 mode = AR5K_EEPROM_MODE_11B;
2161 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
2162
2163 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2164 if (ret)
2165 return ret;
2166
2167 AR5K_EEPROM_READ(offset++, val);
2168 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2169 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2170 ee->ee_db[mode][1] = val & 0x7;
2171
2172 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2173 if (ret)
2174 return ret;
2175
2176 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2177 AR5K_EEPROM_READ(offset++, val);
2178 ee->ee_cal_pier[mode][0] =
2179 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2180 ee->ee_cal_pier[mode][1] =
2181 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2182
2183 AR5K_EEPROM_READ(offset++, val);
2184 ee->ee_cal_pier[mode][2] =
2185 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2186 }
2187
2188 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2189 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2190
2191 /*
2192 * Get values for 802.11g (2.4GHz)
2193 */
2194 mode = AR5K_EEPROM_MODE_11G;
2195 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
2196
2197 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2198 if (ret)
2199 return ret;
2200
2201 AR5K_EEPROM_READ(offset++, val);
2202 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2203 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2204 ee->ee_db[mode][1] = val & 0x7;
2205
2206 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2207 if (ret)
2208 return ret;
2209
2210 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2211 AR5K_EEPROM_READ(offset++, val);
2212 ee->ee_cal_pier[mode][0] =
2213 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2214 ee->ee_cal_pier[mode][1] =
2215 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2216
2217 AR5K_EEPROM_READ(offset++, val);
2218 ee->ee_turbo_max_power[mode] = val & 0x7f;
2219 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2220
2221 AR5K_EEPROM_READ(offset++, val);
2222 ee->ee_cal_pier[mode][2] =
2223 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2224
2225 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2226 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2227
2228 AR5K_EEPROM_READ(offset++, val);
2229 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2230 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2231
2232 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2233 AR5K_EEPROM_READ(offset++, val);
2234 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2235 }
2236 }
2237
2238 /*
2239 * Read 5GHz EEPROM channels
2240 */
2241
2242 return 0;
2243}
2244
2245/*
2246 * Read the MAC address from eeprom
2247 */
2248static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2249{
2250 u8 mac_d[ETH_ALEN];
2251 u32 total, offset;
2252 u16 data;
2253 int octet, ret;
2254
2255 memset(mac, 0, ETH_ALEN);
2256 memset(mac_d, 0, ETH_ALEN);
2257
2258 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2259 if (ret)
2260 return ret;
2261
2262 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2263 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2264 if (ret)
2265 return ret;
2266
2267 total += data;
2268 mac_d[octet + 1] = data & 0xff;
2269 mac_d[octet] = data >> 8;
2270 octet += 2;
2271 }
2272
2273 memcpy(mac, mac_d, ETH_ALEN);
2274
2275 if (!total || total == 3 * 0xffff)
2276 return -EINVAL;
2277
2278 return 0;
2279}
2280
2281/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002282 * Fill the capabilities struct
2283 */
2284static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2285{
2286 u16 ee_header;
2287
2288 ATH5K_TRACE(ah->ah_sc);
2289 /* Capabilities stored in the EEPROM */
2290 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2291
2292 if (ah->ah_version == AR5K_AR5210) {
2293 /*
2294 * Set radio capabilities
2295 * (The AR5110 only supports the middle 5GHz band)
2296 */
2297 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2298 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2299 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2300 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2301
2302 /* Set supported modes */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002303 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2304 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002305 } else {
2306 /*
2307 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2308 * XXX and from 2312 to 2732GHz. There are problems with the
2309 * XXX current ieee80211 implementation because the IEEE
2310 * XXX channel mapping does not support negative channel
2311 * XXX numbers (2312MHz is channel -19). Of course, this
2312 * XXX doesn't matter because these channels are out of range
2313 * XXX but some regulation domains like MKK (Japan) will
2314 * XXX support frequencies somewhere around 4.8GHz.
2315 */
2316
2317 /*
2318 * Set radio capabilities
2319 */
2320
2321 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2322 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2323 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2324
2325 /* Set supported modes */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002326 __set_bit(AR5K_MODE_11A,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002327 ah->ah_capabilities.cap_mode);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002328 __set_bit(AR5K_MODE_11A_TURBO,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002329 ah->ah_capabilities.cap_mode);
2330 if (ah->ah_version == AR5K_AR5212)
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002331 __set_bit(AR5K_MODE_11G_TURBO,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002332 ah->ah_capabilities.cap_mode);
2333 }
2334
2335 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2336 * connected */
2337 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2338 AR5K_EEPROM_HDR_11G(ee_header)) {
2339 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2340 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2341
2342 if (AR5K_EEPROM_HDR_11B(ee_header))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002343 __set_bit(AR5K_MODE_11B,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002344 ah->ah_capabilities.cap_mode);
2345
2346 if (AR5K_EEPROM_HDR_11G(ee_header))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002347 __set_bit(AR5K_MODE_11G,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002348 ah->ah_capabilities.cap_mode);
2349 }
2350 }
2351
2352 /* GPIO */
2353 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2354
2355 /* Set number of supported TX queues */
2356 if (ah->ah_version == AR5K_AR5210)
2357 ah->ah_capabilities.cap_queues.q_tx_num =
2358 AR5K_NUM_TX_QUEUES_NOQCU;
2359 else
2360 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2361
2362 return 0;
2363}
2364
2365/*********************************\
2366 Protocol Control Unit Functions
2367\*********************************/
2368
2369/*
2370 * Set Operation mode
2371 */
2372int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2373{
2374 u32 pcu_reg, beacon_reg, low_id, high_id;
2375
2376 pcu_reg = 0;
2377 beacon_reg = 0;
2378
2379 ATH5K_TRACE(ah->ah_sc);
2380
2381 switch (ah->ah_op_mode) {
2382 case IEEE80211_IF_TYPE_IBSS:
2383 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2384 (ah->ah_version == AR5K_AR5210 ?
2385 AR5K_STA_ID1_NO_PSPOLL : 0);
2386 beacon_reg |= AR5K_BCR_ADHOC;
2387 break;
2388
2389 case IEEE80211_IF_TYPE_AP:
2390 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2391 (ah->ah_version == AR5K_AR5210 ?
2392 AR5K_STA_ID1_NO_PSPOLL : 0);
2393 beacon_reg |= AR5K_BCR_AP;
2394 break;
2395
2396 case IEEE80211_IF_TYPE_STA:
2397 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2398 (ah->ah_version == AR5K_AR5210 ?
2399 AR5K_STA_ID1_PWR_SV : 0);
2400 case IEEE80211_IF_TYPE_MNTR:
2401 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2402 (ah->ah_version == AR5K_AR5210 ?
2403 AR5K_STA_ID1_NO_PSPOLL : 0);
2404 break;
2405
2406 default:
2407 return -EINVAL;
2408 }
2409
2410 /*
2411 * Set PCU registers
2412 */
2413 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2414 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2415 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2416 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2417
2418 /*
2419 * Set Beacon Control Register on 5210
2420 */
2421 if (ah->ah_version == AR5K_AR5210)
2422 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2423
2424 return 0;
2425}
2426
2427/*
2428 * BSSID Functions
2429 */
2430
2431/*
2432 * Get station id
2433 */
2434void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2435{
2436 ATH5K_TRACE(ah->ah_sc);
2437 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2438}
2439
2440/*
2441 * Set station id
2442 */
2443int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2444{
2445 u32 low_id, high_id;
2446
2447 ATH5K_TRACE(ah->ah_sc);
2448 /* Set new station ID */
2449 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2450
2451 low_id = AR5K_LOW_ID(mac);
2452 high_id = AR5K_HIGH_ID(mac);
2453
2454 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2455 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2456
2457 return 0;
2458}
2459
2460/*
2461 * Set BSSID
2462 */
2463void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2464{
2465 u32 low_id, high_id;
2466 u16 tim_offset = 0;
2467
2468 /*
2469 * Set simple BSSID mask on 5212
2470 */
2471 if (ah->ah_version == AR5K_AR5212) {
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -05002472 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2473 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002474 }
2475
2476 /*
2477 * Set BSSID which triggers the "SME Join" operation
2478 */
2479 low_id = AR5K_LOW_ID(bssid);
2480 high_id = AR5K_HIGH_ID(bssid);
2481 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2482 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2483 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2484
2485 if (assoc_id == 0) {
2486 ath5k_hw_disable_pspoll(ah);
2487 return;
2488 }
2489
2490 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2491 tim_offset ? tim_offset + 4 : 0);
2492
2493 ath5k_hw_enable_pspoll(ah, NULL, 0);
2494}
2495/**
2496 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2497 *
2498 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2499 * which bits of the interface's MAC address should be looked at when trying
2500 * to decide which packets to ACK. In station mode every bit matters. In AP
2501 * mode with a single BSS every bit matters as well. In AP mode with
2502 * multiple BSSes not every bit matters.
2503 *
2504 * @ah: the &struct ath5k_hw
2505 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2506 *
2507 * Note that this is a simple filter and *does* not filter out all
2508 * relevant frames. Some non-relevant frames will get through, probability
2509 * jocks are welcomed to compute.
2510 *
2511 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2512 * computing the set of:
2513 *
2514 * ~ ( MAC XOR BSSID )
2515 *
2516 * When you do this you are essentially computing the common bits. Later it
2517 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2518 * to obtain the relevant bits which should match on the destination frame.
2519 *
2520 * Simple example: on your card you have have two BSSes you have created with
2521 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2522 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2523 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2524 *
2525 * \
2526 * MAC: 0001 |
2527 * BSSID-01: 0100 | --> Belongs to us
2528 * BSSID-02: 1001 |
2529 * /
2530 * -------------------
2531 * BSSID-03: 0110 | --> External
2532 * -------------------
2533 *
2534 * Our bssid_mask would then be:
2535 *
2536 * On loop iteration for BSSID-01:
2537 * ~(0001 ^ 0100) -> ~(0101)
2538 * -> 1010
2539 * bssid_mask = 1010
2540 *
2541 * On loop iteration for BSSID-02:
2542 * bssid_mask &= ~(0001 ^ 1001)
2543 * bssid_mask = (1010) & ~(0001 ^ 1001)
2544 * bssid_mask = (1010) & ~(1001)
2545 * bssid_mask = (1010) & (0110)
2546 * bssid_mask = 0010
2547 *
2548 * A bssid_mask of 0010 means "only pay attention to the second least
2549 * significant bit". This is because its the only bit common
2550 * amongst the MAC and all BSSIDs we support. To findout what the real
2551 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2552 * or our MAC address (we assume the hardware uses the MAC address).
2553 *
2554 * Now, suppose there's an incoming frame for BSSID-03:
2555 *
2556 * IFRAME-01: 0110
2557 *
2558 * An easy eye-inspeciton of this already should tell you that this frame
2559 * will not pass our check. This is beacuse the bssid_mask tells the
2560 * hardware to only look at the second least significant bit and the
2561 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2562 * as 1, which does not match 0.
2563 *
2564 * So with IFRAME-01 we *assume* the hardware will do:
2565 *
2566 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2567 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2568 * --> allow = (0010) == 0000 ? 1 : 0;
2569 * --> allow = 0
2570 *
2571 * Lets now test a frame that should work:
2572 *
2573 * IFRAME-02: 0001 (we should allow)
2574 *
2575 * allow = (0001 & 1010) == 1010
2576 *
2577 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2578 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2579 * --> allow = (0010) == (0010)
2580 * --> allow = 1
2581 *
2582 * Other examples:
2583 *
2584 * IFRAME-03: 0100 --> allowed
2585 * IFRAME-04: 1001 --> allowed
2586 * IFRAME-05: 1101 --> allowed but its not for us!!!
2587 *
2588 */
2589int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2590{
2591 u32 low_id, high_id;
2592 ATH5K_TRACE(ah->ah_sc);
2593
2594 if (ah->ah_version == AR5K_AR5212) {
2595 low_id = AR5K_LOW_ID(mask);
2596 high_id = AR5K_HIGH_ID(mask);
2597
2598 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2599 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2600
2601 return 0;
2602 }
2603
2604 return -EIO;
2605}
2606
2607/*
2608 * Receive start/stop functions
2609 */
2610
2611/*
2612 * Start receive on PCU
2613 */
2614void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2615{
2616 ATH5K_TRACE(ah->ah_sc);
2617 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -05002618
2619 /* TODO: ANI Support */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002620}
2621
2622/*
2623 * Stop receive on PCU
2624 */
2625void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2626{
2627 ATH5K_TRACE(ah->ah_sc);
2628 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
Nick Kossifidisc87cdfd2008-03-07 11:48:21 -05002629
2630 /* TODO: ANI Support */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002631}
2632
2633/*
2634 * RX Filter functions
2635 */
2636
2637/*
2638 * Set multicast filter
2639 */
2640void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2641{
2642 ATH5K_TRACE(ah->ah_sc);
2643 /* Set the multicat filter */
2644 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2645 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2646}
2647
2648/*
2649 * Set multicast filter by index
2650 */
2651int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2652{
2653
2654 ATH5K_TRACE(ah->ah_sc);
2655 if (index >= 64)
2656 return -EINVAL;
2657 else if (index >= 32)
2658 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2659 (1 << (index - 32)));
2660 else
2661 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2662
2663 return 0;
2664}
2665
2666/*
2667 * Clear Multicast filter by index
2668 */
2669int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2670{
2671
2672 ATH5K_TRACE(ah->ah_sc);
2673 if (index >= 64)
2674 return -EINVAL;
2675 else if (index >= 32)
2676 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2677 (1 << (index - 32)));
2678 else
2679 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2680
2681 return 0;
2682}
2683
2684/*
2685 * Get current rx filter
2686 */
2687u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2688{
2689 u32 data, filter = 0;
2690
2691 ATH5K_TRACE(ah->ah_sc);
2692 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2693
2694 /*Radar detection for 5212*/
2695 if (ah->ah_version == AR5K_AR5212) {
2696 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2697
2698 if (data & AR5K_PHY_ERR_FIL_RADAR)
2699 filter |= AR5K_RX_FILTER_RADARERR;
2700 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2701 filter |= AR5K_RX_FILTER_PHYERR;
2702 }
2703
2704 return filter;
2705}
2706
2707/*
2708 * Set rx filter
2709 */
2710void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2711{
2712 u32 data = 0;
2713
2714 ATH5K_TRACE(ah->ah_sc);
2715
2716 /* Set PHY error filter register on 5212*/
2717 if (ah->ah_version == AR5K_AR5212) {
2718 if (filter & AR5K_RX_FILTER_RADARERR)
2719 data |= AR5K_PHY_ERR_FIL_RADAR;
2720 if (filter & AR5K_RX_FILTER_PHYERR)
2721 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2722 }
2723
2724 /*
2725 * The AR5210 uses promiscous mode to detect radar activity
2726 */
2727 if (ah->ah_version == AR5K_AR5210 &&
2728 (filter & AR5K_RX_FILTER_RADARERR)) {
2729 filter &= ~AR5K_RX_FILTER_RADARERR;
2730 filter |= AR5K_RX_FILTER_PROM;
2731 }
2732
2733 /*Zero length DMA*/
2734 if (data)
2735 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2736 else
2737 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2738
2739 /*Write RX Filter register*/
2740 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2741
2742 /*Write PHY error filter register on 5212*/
2743 if (ah->ah_version == AR5K_AR5212)
2744 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2745
2746}
2747
2748/*
2749 * Beacon related functions
2750 */
2751
2752/*
2753 * Get a 32bit TSF
2754 */
2755u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2756{
2757 ATH5K_TRACE(ah->ah_sc);
2758 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2759}
2760
2761/*
2762 * Get the full 64bit TSF
2763 */
2764u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2765{
2766 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2767 ATH5K_TRACE(ah->ah_sc);
2768
2769 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2770}
2771
2772/*
2773 * Force a TSF reset
2774 */
2775void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2776{
2777 ATH5K_TRACE(ah->ah_sc);
2778 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2779}
2780
2781/*
2782 * Initialize beacon timers
2783 */
2784void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2785{
2786 u32 timer1, timer2, timer3;
2787
2788 ATH5K_TRACE(ah->ah_sc);
2789 /*
2790 * Set the additional timers by mode
2791 */
2792 switch (ah->ah_op_mode) {
2793 case IEEE80211_IF_TYPE_STA:
2794 if (ah->ah_version == AR5K_AR5210) {
2795 timer1 = 0xffffffff;
2796 timer2 = 0xffffffff;
2797 } else {
2798 timer1 = 0x0000ffff;
2799 timer2 = 0x0007ffff;
2800 }
2801 break;
2802
2803 default:
Bruno Randolf1008e0f2008-01-18 21:51:19 +09002804 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2805 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002806 }
2807
2808 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2809
2810 /*
2811 * Set the beacon register and enable all timers.
2812 * (next beacon, DMA beacon, software beacon, ATIM window time)
2813 */
2814 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2815 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2816 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2817 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2818
2819 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2820 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2821 AR5K_BEACON);
2822}
2823
2824#if 0
2825/*
2826 * Set beacon timers
2827 */
2828int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2829 const struct ath5k_beacon_state *state)
2830{
2831 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2832
2833 /*
2834 * TODO: should be changed through *state
2835 * review struct ath5k_beacon_state struct
2836 *
2837 * XXX: These are used for cfp period bellow, are they
2838 * ok ? Is it O.K. for tsf here to be 0 or should we use
2839 * get_tsf ?
2840 */
2841 u32 dtim_count = 0; /* XXX */
2842 u32 cfp_count = 0; /* XXX */
2843 u32 tsf = 0; /* XXX */
2844
2845 ATH5K_TRACE(ah->ah_sc);
2846 /* Return on an invalid beacon state */
2847 if (state->bs_interval < 1)
2848 return -EINVAL;
2849
2850 interval = state->bs_interval;
2851 dtim = state->bs_dtim_period;
2852
2853 /*
2854 * PCF support?
2855 */
2856 if (state->bs_cfp_period > 0) {
2857 /*
2858 * Enable PCF mode and set the CFP
2859 * (Contention Free Period) and timer registers
2860 */
2861 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2862 state->bs_interval;
2863 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2864 state->bs_interval;
2865
2866 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2867 AR5K_STA_ID1_DEFAULT_ANTENNA |
2868 AR5K_STA_ID1_PCF);
2869 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2870 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2871 AR5K_CFP_DUR);
2872 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2873 next_cfp)) << 3, AR5K_TIMER2);
2874 } else {
2875 /* Disable PCF mode */
2876 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2877 AR5K_STA_ID1_DEFAULT_ANTENNA |
2878 AR5K_STA_ID1_PCF);
2879 }
2880
2881 /*
2882 * Enable the beacon timer register
2883 */
2884 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2885
2886 /*
2887 * Start the beacon timers
2888 */
2889 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2890 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2891 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2892 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2893 AR5K_BEACON_PERIOD), AR5K_BEACON);
2894
2895 /*
2896 * Write new beacon miss threshold, if it appears to be valid
2897 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2898 * and return if its not in range. We can test this by reading value and
2899 * setting value to a largest value and seeing which values register.
2900 */
2901
2902 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2903 state->bs_bmiss_threshold);
2904
2905 /*
2906 * Set sleep control register
2907 * XXX: Didn't find this in 5210 code but since this register
2908 * exists also in ar5k's 5210 headers i leave it as common code.
2909 */
2910 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2911 (state->bs_sleep_duration - 3) << 3);
2912
2913 /*
2914 * Set enhanced sleep registers on 5212
2915 */
2916 if (ah->ah_version == AR5K_AR5212) {
2917 if (state->bs_sleep_duration > state->bs_interval &&
2918 roundup(state->bs_sleep_duration, interval) ==
2919 state->bs_sleep_duration)
2920 interval = state->bs_sleep_duration;
2921
2922 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2923 roundup(state->bs_sleep_duration, dtim) ==
2924 state->bs_sleep_duration))
2925 dtim = state->bs_sleep_duration;
2926
2927 if (interval > dtim)
2928 return -EINVAL;
2929
2930 next_beacon = interval == dtim ? state->bs_next_dtim :
2931 state->bs_next_beacon;
2932
2933 ath5k_hw_reg_write(ah,
2934 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2935 AR5K_SLEEP0_NEXT_DTIM) |
2936 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2937 AR5K_SLEEP0_ENH_SLEEP_EN |
2938 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2939
2940 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2941 AR5K_SLEEP1_NEXT_TIM) |
2942 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2943
2944 ath5k_hw_reg_write(ah,
2945 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2946 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2947 }
2948
2949 return 0;
2950}
2951
2952/*
2953 * Reset beacon timers
2954 */
2955void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2956{
2957 ATH5K_TRACE(ah->ah_sc);
2958 /*
2959 * Disable beacon timer
2960 */
2961 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2962
2963 /*
2964 * Disable some beacon register values
2965 */
2966 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2967 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2968 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2969}
2970
2971/*
2972 * Wait for beacon queue to finish
2973 */
2974int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2975{
2976 unsigned int i;
2977 int ret;
2978
2979 ATH5K_TRACE(ah->ah_sc);
2980
2981 /* 5210 doesn't have QCU*/
2982 if (ah->ah_version == AR5K_AR5210) {
2983 /*
2984 * Wait for beaconn queue to finish by checking
2985 * Control Register and Beacon Status Register.
2986 */
2987 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2988 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2989 ||
2990 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2991 break;
2992 udelay(10);
2993 }
2994
2995 /* Timeout... */
2996 if (i <= 0) {
2997 /*
2998 * Re-schedule the beacon queue
2999 */
3000 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
3001 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
3002 AR5K_BCR);
3003
3004 return -EIO;
3005 }
3006 ret = 0;
3007 } else {
3008 /*5211/5212*/
3009 ret = ath5k_hw_register_timeout(ah,
3010 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
3011 AR5K_QCU_STS_FRMPENDCNT, 0, false);
3012
3013 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
3014 return -EIO;
3015 }
3016
3017 return ret;
3018}
3019#endif
3020
3021/*
3022 * Update mib counters (statistics)
3023 */
3024void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
Nick Kossifidis194828a2008-04-16 18:49:02 +03003025 struct ieee80211_low_level_stats *stats)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003026{
3027 ATH5K_TRACE(ah->ah_sc);
Nick Kossifidis194828a2008-04-16 18:49:02 +03003028
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003029 /* Read-And-Clear */
Nick Kossifidis194828a2008-04-16 18:49:02 +03003030 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
3031 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
3032 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
3033 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
3034
3035 /* XXX: Should we use this to track beacon count ?
3036 * -we read it anyway to clear the register */
3037 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003038
3039 /* Reset profile count registers on 5212*/
3040 if (ah->ah_version == AR5K_AR5212) {
3041 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
3042 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
3043 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
3044 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
3045 }
3046}
3047
3048/** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
3049 *
3050 * @ah: the &struct ath5k_hw
3051 * @high: determines if to use low bit rate or now
3052 */
3053void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
3054{
3055 if (ah->ah_version != AR5K_AR5212)
3056 return;
3057 else {
3058 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
3059 if (high)
3060 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
3061 else
3062 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
3063 }
3064}
3065
3066
3067/*
3068 * ACK/CTS Timeouts
3069 */
3070
3071/*
3072 * Set ACK timeout on PCU
3073 */
3074int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
3075{
3076 ATH5K_TRACE(ah->ah_sc);
3077 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
3078 ah->ah_turbo) <= timeout)
3079 return -EINVAL;
3080
3081 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
3082 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3083
3084 return 0;
3085}
3086
3087/*
3088 * Read the ACK timeout from PCU
3089 */
3090unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
3091{
3092 ATH5K_TRACE(ah->ah_sc);
3093
3094 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3095 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
3096}
3097
3098/*
3099 * Set CTS timeout on PCU
3100 */
3101int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
3102{
3103 ATH5K_TRACE(ah->ah_sc);
3104 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
3105 ah->ah_turbo) <= timeout)
3106 return -EINVAL;
3107
3108 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
3109 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3110
3111 return 0;
3112}
3113
3114/*
3115 * Read CTS timeout from PCU
3116 */
3117unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
3118{
3119 ATH5K_TRACE(ah->ah_sc);
3120 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3121 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
3122}
3123
3124/*
3125 * Key table (WEP) functions
3126 */
3127
3128int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
3129{
3130 unsigned int i;
3131
3132 ATH5K_TRACE(ah->ah_sc);
3133 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3134
3135 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
3136 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
3137
Nick Kossifidis194828a2008-04-16 18:49:02 +03003138 /*
3139 * Set NULL encryption on AR5212+
3140 *
3141 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3142 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3143 *
3144 * Note2: Windows driver (ndiswrapper) sets this to
3145 * 0x00000714 instead of 0x00000007
3146 */
3147 if (ah->ah_version > AR5K_AR5211)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003148 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
3149 AR5K_KEYTABLE_TYPE(entry));
3150
3151 return 0;
3152}
3153
3154int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
3155{
3156 ATH5K_TRACE(ah->ah_sc);
3157 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3158
3159 /* Check the validation flag at the end of the entry */
3160 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
3161 AR5K_KEYTABLE_VALID;
3162}
3163
3164int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
3165 const struct ieee80211_key_conf *key, const u8 *mac)
3166{
3167 unsigned int i;
3168 __le32 key_v[5] = {};
3169 u32 keytype;
3170
3171 ATH5K_TRACE(ah->ah_sc);
3172
3173 /* key->keylen comes in from mac80211 in bytes */
3174
3175 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
3176 return -EOPNOTSUPP;
3177
3178 switch (key->keylen) {
3179 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
3180 case 40 / 8:
3181 memcpy(&key_v[0], key->key, 5);
3182 keytype = AR5K_KEYTABLE_TYPE_40;
3183 break;
3184
3185 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
3186 case 104 / 8:
3187 memcpy(&key_v[0], &key->key[0], 6);
3188 memcpy(&key_v[2], &key->key[6], 6);
3189 memcpy(&key_v[4], &key->key[12], 1);
3190 keytype = AR5K_KEYTABLE_TYPE_104;
3191 break;
3192 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
3193 case 128 / 8:
3194 memcpy(&key_v[0], &key->key[0], 6);
3195 memcpy(&key_v[2], &key->key[6], 6);
3196 memcpy(&key_v[4], &key->key[12], 4);
3197 keytype = AR5K_KEYTABLE_TYPE_128;
3198 break;
3199
3200 default:
3201 return -EINVAL; /* shouldn't happen */
3202 }
3203
3204 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3205 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3206 AR5K_KEYTABLE_OFF(entry, i));
3207
3208 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3209
3210 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3211}
3212
3213int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3214{
3215 u32 low_id, high_id;
3216
3217 ATH5K_TRACE(ah->ah_sc);
3218 /* Invalid entry (key table overflow) */
3219 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3220
3221 /* MAC may be NULL if it's a broadcast key. In this case no need to
3222 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3223 if (unlikely(mac == NULL)) {
3224 low_id = 0xffffffff;
3225 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3226 } else {
3227 low_id = AR5K_LOW_ID(mac);
3228 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3229 }
3230
3231 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3232 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3233
3234 return 0;
3235}
3236
3237
3238/********************************************\
3239Queue Control Unit, DFS Control Unit Functions
3240\********************************************/
3241
3242/*
3243 * Initialize a transmit queue
3244 */
3245int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3246 struct ath5k_txq_info *queue_info)
3247{
3248 unsigned int queue;
3249 int ret;
3250
3251 ATH5K_TRACE(ah->ah_sc);
3252
3253 /*
3254 * Get queue by type
3255 */
3256 /*5210 only has 2 queues*/
3257 if (ah->ah_version == AR5K_AR5210) {
3258 switch (queue_type) {
3259 case AR5K_TX_QUEUE_DATA:
3260 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3261 break;
3262 case AR5K_TX_QUEUE_BEACON:
3263 case AR5K_TX_QUEUE_CAB:
3264 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3265 break;
3266 default:
3267 return -EINVAL;
3268 }
3269 } else {
3270 switch (queue_type) {
3271 case AR5K_TX_QUEUE_DATA:
3272 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3273 ah->ah_txq[queue].tqi_type !=
3274 AR5K_TX_QUEUE_INACTIVE; queue++) {
3275
3276 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3277 return -EINVAL;
3278 }
3279 break;
3280 case AR5K_TX_QUEUE_UAPSD:
3281 queue = AR5K_TX_QUEUE_ID_UAPSD;
3282 break;
3283 case AR5K_TX_QUEUE_BEACON:
3284 queue = AR5K_TX_QUEUE_ID_BEACON;
3285 break;
3286 case AR5K_TX_QUEUE_CAB:
3287 queue = AR5K_TX_QUEUE_ID_CAB;
3288 break;
3289 case AR5K_TX_QUEUE_XR_DATA:
3290 if (ah->ah_version != AR5K_AR5212)
3291 ATH5K_ERR(ah->ah_sc,
3292 "XR data queues only supported in"
3293 " 5212!\n");
3294 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3295 break;
3296 default:
3297 return -EINVAL;
3298 }
3299 }
3300
3301 /*
3302 * Setup internal queue structure
3303 */
3304 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3305 ah->ah_txq[queue].tqi_type = queue_type;
3306
3307 if (queue_info != NULL) {
3308 queue_info->tqi_type = queue_type;
3309 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3310 if (ret)
3311 return ret;
3312 }
3313 /*
3314 * We use ah_txq_status to hold a temp value for
3315 * the Secondary interrupt mask registers on 5211+
3316 * check out ath5k_hw_reset_tx_queue
3317 */
3318 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3319
3320 return queue;
3321}
3322
3323/*
3324 * Setup a transmit queue
3325 */
3326int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3327 const struct ath5k_txq_info *queue_info)
3328{
3329 ATH5K_TRACE(ah->ah_sc);
3330 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3331
3332 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3333 return -EIO;
3334
3335 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3336
3337 /*XXX: Is this supported on 5210 ?*/
3338 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3339 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3340 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3341 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3342 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3343
3344 return 0;
3345}
3346
3347/*
3348 * Get properties for a specific transmit queue
3349 */
3350int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3351 struct ath5k_txq_info *queue_info)
3352{
3353 ATH5K_TRACE(ah->ah_sc);
3354 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3355 return 0;
3356}
3357
3358/*
3359 * Set a transmit queue inactive
3360 */
3361void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3362{
3363 ATH5K_TRACE(ah->ah_sc);
3364 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3365 return;
3366
3367 /* This queue will be skipped in further operations */
3368 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3369 /*For SIMR setup*/
3370 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3371}
3372
3373/*
3374 * Set DFS params for a transmit queue
3375 */
3376int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3377{
3378 u32 cw_min, cw_max, retry_lg, retry_sh;
3379 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3380
3381 ATH5K_TRACE(ah->ah_sc);
3382 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3383
3384 tq = &ah->ah_txq[queue];
3385
3386 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3387 return 0;
3388
3389 if (ah->ah_version == AR5K_AR5210) {
3390 /* Only handle data queues, others will be ignored */
3391 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3392 return 0;
3393
3394 /* Set Slot time */
Joe Perchese9010e22008-03-07 14:21:16 -08003395 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003396 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3397 AR5K_SLOT_TIME);
3398 /* Set ACK_CTS timeout */
Joe Perchese9010e22008-03-07 14:21:16 -08003399 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003400 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3401 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3402 /* Set Transmit Latency */
Joe Perchese9010e22008-03-07 14:21:16 -08003403 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003404 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3405 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3406 /* Set IFS0 */
Joe Perchese9010e22008-03-07 14:21:16 -08003407 if (ah->ah_turbo)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003408 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3409 (ah->ah_aifs + tq->tqi_aifs) *
3410 AR5K_INIT_SLOT_TIME_TURBO) <<
3411 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3412 AR5K_IFS0);
3413 else
3414 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3415 (ah->ah_aifs + tq->tqi_aifs) *
3416 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3417 AR5K_INIT_SIFS, AR5K_IFS0);
3418
3419 /* Set IFS1 */
Joe Perchese9010e22008-03-07 14:21:16 -08003420 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003421 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3422 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
Nick Kossifidis0bacdf32008-07-30 13:18:59 +03003423 /* Set AR5K_PHY_SETTLING */
Joe Perchese9010e22008-03-07 14:21:16 -08003424 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Nick Kossifidis0bacdf32008-07-30 13:18:59 +03003425 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3426 | 0x38 :
3427 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3428 | 0x1C,
3429 AR5K_PHY_SETTLING);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003430 /* Set Frame Control Register */
Joe Perchese9010e22008-03-07 14:21:16 -08003431 ath5k_hw_reg_write(ah, ah->ah_turbo ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003432 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3433 AR5K_PHY_TURBO_SHORT | 0x2020) :
3434 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3435 AR5K_PHY_FRAME_CTL_5210);
3436 }
3437
3438 /*
3439 * Calculate cwmin/max by channel mode
3440 */
3441 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3442 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3443 ah->ah_aifs = AR5K_TUNE_AIFS;
3444 /*XR is only supported on 5212*/
3445 if (IS_CHAN_XR(ah->ah_current_channel) &&
3446 ah->ah_version == AR5K_AR5212) {
3447 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3448 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3449 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3450 /*B mode is not supported on 5210*/
3451 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3452 ah->ah_version != AR5K_AR5210) {
3453 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3454 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3455 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3456 }
3457
3458 cw_min = 1;
3459 while (cw_min < ah->ah_cw_min)
3460 cw_min = (cw_min << 1) | 1;
3461
3462 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3463 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3464 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3465 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3466
3467 /*
3468 * Calculate and set retry limits
3469 */
Joe Perchese9010e22008-03-07 14:21:16 -08003470 if (ah->ah_software_retry) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003471 /* XXX Need to test this */
3472 retry_lg = ah->ah_limit_tx_retries;
3473 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3474 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3475 } else {
3476 retry_lg = AR5K_INIT_LG_RETRY;
3477 retry_sh = AR5K_INIT_SH_RETRY;
3478 }
3479
3480 /*No QCU/DCU [5210]*/
3481 if (ah->ah_version == AR5K_AR5210) {
3482 ath5k_hw_reg_write(ah,
3483 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3484 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3485 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3486 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3487 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3488 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3489 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3490 AR5K_NODCU_RETRY_LMT);
3491 } else {
3492 /*QCU/DCU [5211+]*/
3493 ath5k_hw_reg_write(ah,
3494 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3495 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3496 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3497 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3498 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3499 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3500 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3501
3502 /*===Rest is also for QCU/DCU only [5211+]===*/
3503
3504 /*
3505 * Set initial content window (cw_min/cw_max)
3506 * and arbitrated interframe space (aifs)...
3507 */
3508 ath5k_hw_reg_write(ah,
3509 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3510 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3511 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3512 AR5K_DCU_LCL_IFS_AIFS),
3513 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3514
3515 /*
3516 * Set misc registers
3517 */
3518 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3519 AR5K_QUEUE_MISC(queue));
3520
3521 if (tq->tqi_cbr_period) {
3522 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3523 AR5K_QCU_CBRCFG_INTVAL) |
3524 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3525 AR5K_QCU_CBRCFG_ORN_THRES),
3526 AR5K_QUEUE_CBRCFG(queue));
3527 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3528 AR5K_QCU_MISC_FRSHED_CBR);
3529 if (tq->tqi_cbr_overflow_limit)
3530 AR5K_REG_ENABLE_BITS(ah,
3531 AR5K_QUEUE_MISC(queue),
3532 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3533 }
3534
3535 if (tq->tqi_ready_time)
3536 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3537 AR5K_QCU_RDYTIMECFG_INTVAL) |
3538 AR5K_QCU_RDYTIMECFG_ENABLE,
3539 AR5K_QUEUE_RDYTIMECFG(queue));
3540
3541 if (tq->tqi_burst_time) {
3542 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3543 AR5K_DCU_CHAN_TIME_DUR) |
3544 AR5K_DCU_CHAN_TIME_ENABLE,
3545 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3546
3547 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3548 AR5K_REG_ENABLE_BITS(ah,
3549 AR5K_QUEUE_MISC(queue),
Nick Kossifidisdf75dcd2008-07-20 06:41:26 +03003550 AR5K_QCU_MISC_RDY_VEOL_POLICY);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003551 }
3552
3553 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3554 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3555 AR5K_QUEUE_DFS_MISC(queue));
3556
3557 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3558 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3559 AR5K_QUEUE_DFS_MISC(queue));
3560
3561 /*
3562 * Set registers by queue type
3563 */
3564 switch (tq->tqi_type) {
3565 case AR5K_TX_QUEUE_BEACON:
3566 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3567 AR5K_QCU_MISC_FRSHED_DBA_GT |
3568 AR5K_QCU_MISC_CBREXP_BCN |
3569 AR5K_QCU_MISC_BCN_ENABLE);
3570
3571 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3572 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3573 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3574 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3575 AR5K_DCU_MISC_BCN_ENABLE);
3576
3577 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3578 (AR5K_TUNE_SW_BEACON_RESP -
3579 AR5K_TUNE_DMA_BEACON_RESP) -
3580 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3581 AR5K_QCU_RDYTIMECFG_ENABLE,
3582 AR5K_QUEUE_RDYTIMECFG(queue));
3583 break;
3584
3585 case AR5K_TX_QUEUE_CAB:
3586 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3587 AR5K_QCU_MISC_FRSHED_DBA_GT |
3588 AR5K_QCU_MISC_CBREXP |
3589 AR5K_QCU_MISC_CBREXP_BCN);
3590
3591 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3592 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3593 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3594 break;
3595
3596 case AR5K_TX_QUEUE_UAPSD:
3597 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3598 AR5K_QCU_MISC_CBREXP);
3599 break;
3600
3601 case AR5K_TX_QUEUE_DATA:
3602 default:
3603 break;
3604 }
3605
3606 /*
3607 * Enable interrupts for this tx queue
3608 * in the secondary interrupt mask registers
3609 */
3610 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3611 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3612
3613 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3614 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3615
3616 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3617 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3618
3619 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3620 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3621
3622 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3623 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3624
3625
3626 /* Update secondary interrupt mask registers */
3627 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3628 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3629 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3630 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3631 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3632
3633 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3634 AR5K_SIMR0_QCU_TXOK) |
3635 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3636 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3637 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3638 AR5K_SIMR1_QCU_TXERR) |
3639 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3640 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3641 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3642 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3643 }
3644
3645 return 0;
3646}
3647
3648/*
3649 * Get number of pending frames
3650 * for a specific queue [5211+]
3651 */
3652u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3653 ATH5K_TRACE(ah->ah_sc);
3654 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3655
3656 /* Return if queue is declared inactive */
3657 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3658 return false;
3659
3660 /* XXX: How about AR5K_CFG_TXCNT ? */
3661 if (ah->ah_version == AR5K_AR5210)
3662 return false;
3663
3664 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3665}
3666
3667/*
3668 * Set slot time
3669 */
3670int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3671{
3672 ATH5K_TRACE(ah->ah_sc);
3673 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3674 return -EINVAL;
3675
3676 if (ah->ah_version == AR5K_AR5210)
3677 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3678 ah->ah_turbo), AR5K_SLOT_TIME);
3679 else
3680 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3681
3682 return 0;
3683}
3684
3685/*
3686 * Get slot time
3687 */
3688unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3689{
3690 ATH5K_TRACE(ah->ah_sc);
3691 if (ah->ah_version == AR5K_AR5210)
3692 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3693 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3694 else
3695 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3696}
3697
3698
3699/******************************\
3700 Hardware Descriptor Functions
3701\******************************/
3702
3703/*
3704 * TX Descriptor
3705 */
3706
3707/*
3708 * Initialize the 2-word tx descriptor on 5210/5211
3709 */
3710static int
3711ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3712 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3713 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3714 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3715 unsigned int rtscts_rate, unsigned int rtscts_duration)
3716{
3717 u32 frame_type;
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003718 struct ath5k_hw_2w_tx_ctl *tx_ctl;
Bruno Randolf281c56d2008-02-05 18:44:55 +09003719 unsigned int frame_len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003720
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003721 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003722
3723 /*
3724 * Validate input
3725 * - Zero retries don't make sense.
3726 * - A zero rate will put the HW into a mode where it continously sends
3727 * noise on the channel, so it is important to avoid this.
3728 */
3729 if (unlikely(tx_tries0 == 0)) {
3730 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3731 WARN_ON(1);
3732 return -EINVAL;
3733 }
3734 if (unlikely(tx_rate0 == 0)) {
3735 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3736 WARN_ON(1);
3737 return -EINVAL;
3738 }
3739
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003740 /* Clear descriptor */
3741 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003742
3743 /* Setup control descriptor */
3744
3745 /* Verify and set frame length */
Bruno Randolf281c56d2008-02-05 18:44:55 +09003746
3747 /* remove padding we might have added before */
3748 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3749
3750 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003751 return -EINVAL;
3752
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003753 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003754
3755 /* Verify and set buffer length */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003756
3757 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3758 if(type == AR5K_PKT_TYPE_BEACON)
Bruno Randolf281c56d2008-02-05 18:44:55 +09003759 pkt_len = roundup(pkt_len, 4);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003760
Bruno Randolf281c56d2008-02-05 18:44:55 +09003761 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003762 return -EINVAL;
3763
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003764 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003765
3766 /*
3767 * Verify and set header length
3768 * XXX: I only found that on 5210 code, does it work on 5211 ?
3769 */
3770 if (ah->ah_version == AR5K_AR5210) {
3771 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3772 return -EINVAL;
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003773 tx_ctl->tx_control_0 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003774 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3775 }
3776
3777 /*Diferences between 5210-5211*/
3778 if (ah->ah_version == AR5K_AR5210) {
3779 switch (type) {
3780 case AR5K_PKT_TYPE_BEACON:
3781 case AR5K_PKT_TYPE_PROBE_RESP:
3782 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3783 case AR5K_PKT_TYPE_PIFS:
3784 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3785 default:
3786 frame_type = type /*<< 2 ?*/;
3787 }
3788
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003789 tx_ctl->tx_control_0 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003790 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3791 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3792 } else {
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003793 tx_ctl->tx_control_0 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003794 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3795 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003796 tx_ctl->tx_control_1 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003797 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3798 }
3799#define _TX_FLAGS(_c, _flag) \
3800 if (flags & AR5K_TXDESC_##_flag) \
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003801 tx_ctl->tx_control_##_c |= \
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003802 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3803
3804 _TX_FLAGS(0, CLRDMASK);
3805 _TX_FLAGS(0, VEOL);
3806 _TX_FLAGS(0, INTREQ);
3807 _TX_FLAGS(0, RTSENA);
3808 _TX_FLAGS(1, NOACK);
3809
3810#undef _TX_FLAGS
3811
3812 /*
3813 * WEP crap
3814 */
3815 if (key_index != AR5K_TXKEYIX_INVALID) {
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003816 tx_ctl->tx_control_0 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003817 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003818 tx_ctl->tx_control_1 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003819 AR5K_REG_SM(key_index,
3820 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3821 }
3822
3823 /*
3824 * RTS/CTS Duration [5210 ?]
3825 */
3826 if ((ah->ah_version == AR5K_AR5210) &&
3827 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003828 tx_ctl->tx_control_1 |= rtscts_duration &
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003829 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3830
3831 return 0;
3832}
3833
3834/*
3835 * Initialize the 4-word tx descriptor on 5212
3836 */
3837static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3838 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3839 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3840 unsigned int tx_tries0, unsigned int key_index,
3841 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3842 unsigned int rtscts_duration)
3843{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003844 struct ath5k_hw_4w_tx_ctl *tx_ctl;
Bruno Randolf281c56d2008-02-05 18:44:55 +09003845 unsigned int frame_len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003846
3847 ATH5K_TRACE(ah->ah_sc);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003848 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003849
3850 /*
3851 * Validate input
3852 * - Zero retries don't make sense.
3853 * - A zero rate will put the HW into a mode where it continously sends
3854 * noise on the channel, so it is important to avoid this.
3855 */
3856 if (unlikely(tx_tries0 == 0)) {
3857 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3858 WARN_ON(1);
3859 return -EINVAL;
3860 }
3861 if (unlikely(tx_rate0 == 0)) {
3862 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3863 WARN_ON(1);
3864 return -EINVAL;
3865 }
3866
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003867 /* Clear descriptor */
3868 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003869
3870 /* Setup control descriptor */
3871
3872 /* Verify and set frame length */
Bruno Randolf281c56d2008-02-05 18:44:55 +09003873
3874 /* remove padding we might have added before */
3875 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3876
3877 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003878 return -EINVAL;
3879
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003880 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003881
3882 /* Verify and set buffer length */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003883
3884 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3885 if(type == AR5K_PKT_TYPE_BEACON)
Bruno Randolf281c56d2008-02-05 18:44:55 +09003886 pkt_len = roundup(pkt_len, 4);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003887
Bruno Randolf281c56d2008-02-05 18:44:55 +09003888 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003889 return -EINVAL;
3890
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003891 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003892
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003893 tx_ctl->tx_control_0 |=
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003894 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3895 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003896 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003897 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003898 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003899 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003900 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003901
3902#define _TX_FLAGS(_c, _flag) \
3903 if (flags & AR5K_TXDESC_##_flag) \
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003904 tx_ctl->tx_control_##_c |= \
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003905 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3906
3907 _TX_FLAGS(0, CLRDMASK);
3908 _TX_FLAGS(0, VEOL);
3909 _TX_FLAGS(0, INTREQ);
3910 _TX_FLAGS(0, RTSENA);
3911 _TX_FLAGS(0, CTSENA);
3912 _TX_FLAGS(1, NOACK);
3913
3914#undef _TX_FLAGS
3915
3916 /*
3917 * WEP crap
3918 */
3919 if (key_index != AR5K_TXKEYIX_INVALID) {
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003920 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3921 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003922 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3923 }
3924
3925 /*
3926 * RTS/CTS
3927 */
3928 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3929 if ((flags & AR5K_TXDESC_RTSENA) &&
3930 (flags & AR5K_TXDESC_CTSENA))
3931 return -EINVAL;
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003932 tx_ctl->tx_control_2 |= rtscts_duration &
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003933 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003934 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003935 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3936 }
3937
3938 return 0;
3939}
3940
3941/*
3942 * Initialize a 4-word multirate tx descriptor on 5212
3943 */
Jiri Slabyb9887632008-02-15 21:58:52 +01003944static int
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003945ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3946 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3947 unsigned int tx_rate3, u_int tx_tries3)
3948{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003949 struct ath5k_hw_4w_tx_ctl *tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003950
3951 /*
3952 * Rates can be 0 as long as the retry count is 0 too.
3953 * A zero rate and nonzero retry count will put the HW into a mode where
3954 * it continously sends noise on the channel, so it is important to
3955 * avoid this.
3956 */
3957 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3958 (tx_rate2 == 0 && tx_tries2 != 0) ||
3959 (tx_rate3 == 0 && tx_tries3 != 0))) {
3960 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3961 WARN_ON(1);
3962 return -EINVAL;
3963 }
3964
3965 if (ah->ah_version == AR5K_AR5212) {
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003966 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003967
3968#define _XTX_TRIES(_n) \
3969 if (tx_tries##_n) { \
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003970 tx_ctl->tx_control_2 |= \
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003971 AR5K_REG_SM(tx_tries##_n, \
3972 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003973 tx_ctl->tx_control_3 |= \
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003974 AR5K_REG_SM(tx_rate##_n, \
3975 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3976 }
3977
3978 _XTX_TRIES(1);
3979 _XTX_TRIES(2);
3980 _XTX_TRIES(3);
3981
3982#undef _XTX_TRIES
3983
Jiri Slabyb9887632008-02-15 21:58:52 +01003984 return 1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003985 }
3986
Jiri Slabyb9887632008-02-15 21:58:52 +01003987 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003988}
3989
3990/*
3991 * Proccess the tx status descriptor on 5210/5211
3992 */
3993static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
Bruno Randolfb47f4072008-03-05 18:35:45 +09003994 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003995{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003996 struct ath5k_hw_2w_tx_ctl *tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003997 struct ath5k_hw_tx_status *tx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003998
Bruno Randolf19fd6e52008-03-05 18:35:23 +09003999 ATH5K_TRACE(ah->ah_sc);
4000
4001 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
4002 tx_status = &desc->ud.ds_tx5210.tx_stat;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004003
4004 /* No frame has been send or error */
4005 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
4006 return -EINPROGRESS;
4007
4008 /*
4009 * Get descriptor status
4010 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09004011 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004012 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004013 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004014 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004015 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004016 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004017 /*TODO: ts->ts_virtcol + test*/
4018 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004019 AR5K_DESC_TX_STATUS1_SEQ_NUM);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004020 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004021 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004022 ts->ts_antenna = 1;
4023 ts->ts_status = 0;
4024 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004025 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
4026
4027 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
4028 if (tx_status->tx_status_0 &
4029 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004030 ts->ts_status |= AR5K_TXERR_XRETRY;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004031
4032 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004033 ts->ts_status |= AR5K_TXERR_FIFO;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004034
4035 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004036 ts->ts_status |= AR5K_TXERR_FILT;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004037 }
4038
4039 return 0;
4040}
4041
4042/*
4043 * Proccess a tx descriptor on 5212
4044 */
4045static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
Bruno Randolfb47f4072008-03-05 18:35:45 +09004046 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004047{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004048 struct ath5k_hw_4w_tx_ctl *tx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004049 struct ath5k_hw_tx_status *tx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004050
4051 ATH5K_TRACE(ah->ah_sc);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004052
4053 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
4054 tx_status = &desc->ud.ds_tx5212.tx_stat;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004055
4056 /* No frame has been send or error */
4057 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
4058 return -EINPROGRESS;
4059
4060 /*
4061 * Get descriptor status
4062 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09004063 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004064 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004065 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004066 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004067 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004068 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004069 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004070 AR5K_DESC_TX_STATUS1_SEQ_NUM);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004071 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004072 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004073 ts->ts_antenna = (tx_status->tx_status_1 &
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004074 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004075 ts->ts_status = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004076
4077 switch (AR5K_REG_MS(tx_status->tx_status_1,
4078 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
4079 case 0:
Bruno Randolfb47f4072008-03-05 18:35:45 +09004080 ts->ts_rate = tx_ctl->tx_control_3 &
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004081 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
4082 break;
4083 case 1:
Bruno Randolfb47f4072008-03-05 18:35:45 +09004084 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004085 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004086 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004087 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
4088 break;
4089 case 2:
Bruno Randolfb47f4072008-03-05 18:35:45 +09004090 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004091 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004092 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004093 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
4094 break;
4095 case 3:
Bruno Randolfb47f4072008-03-05 18:35:45 +09004096 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004097 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004098 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004099 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
4100 break;
4101 }
4102
4103 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
4104 if (tx_status->tx_status_0 &
4105 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004106 ts->ts_status |= AR5K_TXERR_XRETRY;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004107
4108 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004109 ts->ts_status |= AR5K_TXERR_FIFO;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004110
4111 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004112 ts->ts_status |= AR5K_TXERR_FILT;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004113 }
4114
4115 return 0;
4116}
4117
4118/*
4119 * RX Descriptor
4120 */
4121
4122/*
4123 * Initialize an rx descriptor
4124 */
4125int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
4126 u32 size, unsigned int flags)
4127{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004128 struct ath5k_hw_rx_ctl *rx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004129
4130 ATH5K_TRACE(ah->ah_sc);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004131 rx_ctl = &desc->ud.ds_rx.rx_ctl;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004132
4133 /*
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004134 * Clear the descriptor
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004135 * If we don't clean the status descriptor,
4136 * while scanning we get too many results,
4137 * most of them virtual, after some secs
4138 * of scanning system hangs. M.F.
4139 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004140 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004141
4142 /* Setup descriptor */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004143 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
4144 if (unlikely(rx_ctl->rx_control_1 != size))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004145 return -EINVAL;
4146
4147 if (flags & AR5K_RXDESC_INTREQ)
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004148 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004149
4150 return 0;
4151}
4152
4153/*
4154 * Proccess the rx status descriptor on 5210/5211
4155 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004156static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
Bruno Randolfb47f4072008-03-05 18:35:45 +09004157 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004158{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004159 struct ath5k_hw_rx_status *rx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004160
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004161 rx_status = &desc->ud.ds_rx.u.rx_stat;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004162
4163 /* No frame received / not ready */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004164 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004165 == 0))
4166 return -EINPROGRESS;
4167
4168 /*
4169 * Frame receive status
4170 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09004171 rs->rs_datalen = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004172 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004173 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004174 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004175 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004176 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004177 rs->rs_antenna = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004178 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004179 rs->rs_more = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004180 AR5K_5210_RX_DESC_STATUS0_MORE;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004181 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
4182 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004183 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004184 rs->rs_status = 0;
Bob Copelandd6894b52008-05-12 21:16:44 -04004185 rs->rs_phyerr = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004186
4187 /*
4188 * Key table status
4189 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004190 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004191 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004192 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004193 else
Bruno Randolfb47f4072008-03-05 18:35:45 +09004194 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004195
4196 /*
4197 * Receive/descriptor errors
4198 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004199 if ((rx_status->rx_status_1 &
4200 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4201 if (rx_status->rx_status_1 &
4202 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004203 rs->rs_status |= AR5K_RXERR_CRC;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004204
4205 if (rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004206 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004207 rs->rs_status |= AR5K_RXERR_FIFO;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004208
4209 if (rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004210 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
Bruno Randolfb47f4072008-03-05 18:35:45 +09004211 rs->rs_status |= AR5K_RXERR_PHY;
Bob Copelandd6894b52008-05-12 21:16:44 -04004212 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
Bruno Randolfb47f4072008-03-05 18:35:45 +09004213 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004214 }
4215
4216 if (rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004217 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004218 rs->rs_status |= AR5K_RXERR_DECRYPT;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004219 }
4220
4221 return 0;
4222}
4223
4224/*
4225 * Proccess the rx status descriptor on 5212
4226 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004227static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
Bruno Randolfb47f4072008-03-05 18:35:45 +09004228 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004229{
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004230 struct ath5k_hw_rx_status *rx_status;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004231 struct ath5k_hw_rx_error *rx_err;
4232
4233 ATH5K_TRACE(ah->ah_sc);
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004234 rx_status = &desc->ud.ds_rx.u.rx_stat;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004235
4236 /* Overlay on error */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004237 rx_err = &desc->ud.ds_rx.u.rx_err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004238
4239 /* No frame received / not ready */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004240 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004241 == 0))
4242 return -EINPROGRESS;
4243
4244 /*
4245 * Frame receive status
4246 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09004247 rs->rs_datalen = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004248 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004249 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004250 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004251 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004252 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004253 rs->rs_antenna = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004254 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004255 rs->rs_more = rx_status->rx_status_0 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004256 AR5K_5212_RX_DESC_STATUS0_MORE;
Bruno Randolfb47f4072008-03-05 18:35:45 +09004257 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004258 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
Bruno Randolfb47f4072008-03-05 18:35:45 +09004259 rs->rs_status = 0;
Bob Copelandd6894b52008-05-12 21:16:44 -04004260 rs->rs_phyerr = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004261
4262 /*
4263 * Key table status
4264 */
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004265 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004266 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004267 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004268 else
Bruno Randolfb47f4072008-03-05 18:35:45 +09004269 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004270
4271 /*
4272 * Receive/descriptor errors
4273 */
4274 if ((rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004275 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4276 if (rx_status->rx_status_1 &
4277 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004278 rs->rs_status |= AR5K_RXERR_CRC;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004279
4280 if (rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004281 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
Bruno Randolfb47f4072008-03-05 18:35:45 +09004282 rs->rs_status |= AR5K_RXERR_PHY;
Bob Copelandd6894b52008-05-12 21:16:44 -04004283 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
Bruno Randolfb47f4072008-03-05 18:35:45 +09004284 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004285 }
4286
4287 if (rx_status->rx_status_1 &
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004288 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004289 rs->rs_status |= AR5K_RXERR_DECRYPT;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004290
Bruno Randolf19fd6e52008-03-05 18:35:23 +09004291 if (rx_status->rx_status_1 &
4292 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
Bruno Randolfb47f4072008-03-05 18:35:45 +09004293 rs->rs_status |= AR5K_RXERR_MIC;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004294 }
4295
4296 return 0;
4297}
4298
4299
4300/****************\
4301 GPIO Functions
4302\****************/
4303
4304/*
4305 * Set led state
4306 */
4307void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4308{
4309 u32 led;
4310 /*5210 has different led mode handling*/
4311 u32 led_5210;
4312
4313 ATH5K_TRACE(ah->ah_sc);
4314
4315 /*Reset led status*/
4316 if (ah->ah_version != AR5K_AR5210)
4317 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4318 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4319 else
4320 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4321
4322 /*
4323 * Some blinking values, define at your wish
4324 */
4325 switch (state) {
4326 case AR5K_LED_SCAN:
4327 case AR5K_LED_AUTH:
4328 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4329 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4330 break;
4331
4332 case AR5K_LED_INIT:
4333 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4334 led_5210 = AR5K_PCICFG_LED_PEND;
4335 break;
4336
4337 case AR5K_LED_ASSOC:
4338 case AR5K_LED_RUN:
4339 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4340 led_5210 = AR5K_PCICFG_LED_ASSOC;
4341 break;
4342
4343 default:
4344 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4345 led_5210 = AR5K_PCICFG_LED_PEND;
4346 break;
4347 }
4348
4349 /*Write new status to the register*/
4350 if (ah->ah_version != AR5K_AR5210)
4351 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4352 else
4353 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4354}
4355
4356/*
4357 * Set GPIO outputs
4358 */
4359int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4360{
4361 ATH5K_TRACE(ah->ah_sc);
4362 if (gpio > AR5K_NUM_GPIO)
4363 return -EINVAL;
4364
4365 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4366 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4367
4368 return 0;
4369}
4370
4371/*
4372 * Set GPIO inputs
4373 */
4374int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4375{
4376 ATH5K_TRACE(ah->ah_sc);
4377 if (gpio > AR5K_NUM_GPIO)
4378 return -EINVAL;
4379
4380 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4381 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4382
4383 return 0;
4384}
4385
4386/*
4387 * Get GPIO state
4388 */
4389u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4390{
4391 ATH5K_TRACE(ah->ah_sc);
4392 if (gpio > AR5K_NUM_GPIO)
4393 return 0xffffffff;
4394
4395 /* GPIO input magic */
4396 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4397 0x1;
4398}
4399
4400/*
4401 * Set GPIO state
4402 */
4403int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4404{
4405 u32 data;
4406 ATH5K_TRACE(ah->ah_sc);
4407
4408 if (gpio > AR5K_NUM_GPIO)
4409 return -EINVAL;
4410
4411 /* GPIO output magic */
4412 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4413
4414 data &= ~(1 << gpio);
4415 data |= (val & 1) << gpio;
4416
4417 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4418
4419 return 0;
4420}
4421
4422/*
4423 * Initialize the GPIO interrupt (RFKill switch)
4424 */
4425void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4426 u32 interrupt_level)
4427{
4428 u32 data;
4429
4430 ATH5K_TRACE(ah->ah_sc);
4431 if (gpio > AR5K_NUM_GPIO)
4432 return;
4433
4434 /*
4435 * Set the GPIO interrupt
4436 */
4437 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4438 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4439 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4440 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4441
4442 ath5k_hw_reg_write(ah, interrupt_level ? data :
4443 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4444
4445 ah->ah_imr |= AR5K_IMR_GPIO;
4446
4447 /* Enable GPIO interrupts */
4448 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4449}
4450
4451
Jiri Slabyfa1c1142007-08-12 17:33:16 +02004452
4453
4454/****************\
4455 Misc functions
4456\****************/
4457
4458int ath5k_hw_get_capability(struct ath5k_hw *ah,
4459 enum ath5k_capability_type cap_type,
4460 u32 capability, u32 *result)
4461{
4462 ATH5K_TRACE(ah->ah_sc);
4463
4464 switch (cap_type) {
4465 case AR5K_CAP_NUM_TXQUEUES:
4466 if (result) {
4467 if (ah->ah_version == AR5K_AR5210)
4468 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4469 else
4470 *result = AR5K_NUM_TX_QUEUES;
4471 goto yes;
4472 }
4473 case AR5K_CAP_VEOL:
4474 goto yes;
4475 case AR5K_CAP_COMPRESSION:
4476 if (ah->ah_version == AR5K_AR5212)
4477 goto yes;
4478 else
4479 goto no;
4480 case AR5K_CAP_BURST:
4481 goto yes;
4482 case AR5K_CAP_TPC:
4483 goto yes;
4484 case AR5K_CAP_BSSIDMASK:
4485 if (ah->ah_version == AR5K_AR5212)
4486 goto yes;
4487 else
4488 goto no;
4489 case AR5K_CAP_XR:
4490 if (ah->ah_version == AR5K_AR5212)
4491 goto yes;
4492 else
4493 goto no;
4494 default:
4495 goto no;
4496 }
4497
4498no:
4499 return -EINVAL;
4500yes:
4501 return 0;
4502}
4503
4504static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4505 u16 assoc_id)
4506{
4507 ATH5K_TRACE(ah->ah_sc);
4508
4509 if (ah->ah_version == AR5K_AR5210) {
4510 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4511 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4512 return 0;
4513 }
4514
4515 return -EIO;
4516}
4517
4518static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4519{
4520 ATH5K_TRACE(ah->ah_sc);
4521
4522 if (ah->ah_version == AR5K_AR5210) {
4523 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4524 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4525 return 0;
4526 }
4527
4528 return -EIO;
4529}