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review.evervolv.com / android_kernel_htc_msm8960 / a6d377b6969235a3b5a6e87bdcef387d0976b41c / . / arch / sh / drivers / pci / fixups-r7780rp.c
blob: 864e92f69702a105fba87216e7aa9b320efece45 [file] [log] [blame]
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]1/*
2 * arch/sh/drivers/pci/fixups-r7780rp.c
3 *
4 * Highlander R7780RP-1 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]7 * Copyright (C) 2004 - 2006 Paul Mundt
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]13#include <linux/pci.h>
Paul Mundta6d377b2009-04-17 20:11:44 +0900[diff] [blame^]14#include <linux/io.h>
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]15#include "pci-sh4.h"
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]16
Paul Mundta6d377b2009-04-17 20:11:44 +0900[diff] [blame^]17static char irq_tab[] __initdata = {
18 65, 66, 67, 68,
19};
20
21int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
22{
23 return irq_tab[slot];
24}
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]25int pci_fixup_pcic(struct pci_channel *chan)
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]26{
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]27 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
28 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]29
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]30 pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
31 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]32
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]33 pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
34 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
35 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
36 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
37 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]38
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]39 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
40 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]41
42#ifdef CONFIG_32BIT
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]43 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
44 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]45#endif
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]46
47 /* Set IOBR for windows containing area specified in pci.h */
Magnus Damm710fa3c2009-03-11 15:47:23 +0900[diff] [blame]48 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]49 SH7780_PCIIOBR);
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]50 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
51 SH7780_PCIIOBMR);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]52
53 return 0;
54}