blob: da60e99894b855c475861fc1bf53221271570eb4 [file] [log] [blame]
Nicholas Beck4862ec02008-01-23 12:50:51 +09001/*
2 * arch/sh/drivers/pci/fixups-sdk7780.c
3 *
4 * PCI fixups for the SDK7780SE03
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
Paul Mundta6d377b2009-04-17 20:11:44 +09008 * Copyright (C) 2006 Nobuhiro Iwamatsu
Nicholas Beck4862ec02008-01-23 12:50:51 +09009 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
Paul Mundta6d377b2009-04-17 20:11:44 +090015#include <linux/io.h>
Nicholas Beck4862ec02008-01-23 12:50:51 +090016#include "pci-sh4.h"
Nicholas Beck4862ec02008-01-23 12:50:51 +090017
Paul Mundta6d377b2009-04-17 20:11:44 +090018/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
19static char sdk7780_irq_tab[4][16] __initdata = {
20 /* INTA */
21 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
22 /* INTB */
23 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTC */
25 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTD */
27 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28};
29
30int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
31{
32 return sdk7780_irq_tab[pin-1][slot];
33}
Magnus Dammb8b47bf2009-03-11 15:41:51 +090034int pci_fixup_pcic(struct pci_channel *chan)
Nicholas Beck4862ec02008-01-23 12:50:51 +090035{
Nicholas Beck4862ec02008-01-23 12:50:51 +090036 /* Enable all interrupts, so we know what to fix */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090037 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
38 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
Nicholas Beck4862ec02008-01-23 12:50:51 +090039
40 /* Set up standard PCI config registers */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090041 pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
42 pci_write_reg(chan, 0x0047, SH7780_PCICMD);
43 pci_write_reg(chan, 0x00, SH7780_PCIPIF);
Magnus Dammb8b47bf2009-03-11 15:41:51 +090044 pci_write_reg(chan, 0x1912, SH7780_PCISVID);
45 pci_write_reg(chan, 0x0001, SH7780_PCISID);
Nicholas Beck4862ec02008-01-23 12:50:51 +090046
Magnus Dammb8b47bf2009-03-11 15:41:51 +090047 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
48 pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
49 pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
Nicholas Beck4862ec02008-01-23 12:50:51 +090050
Magnus Dammb8b47bf2009-03-11 15:41:51 +090051 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
52 pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
53 pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
Nicholas Beck4862ec02008-01-23 12:50:51 +090054
Magnus Dammb8b47bf2009-03-11 15:41:51 +090055 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
Nicholas Beck4862ec02008-01-23 12:50:51 +090056
57 /*
58 * Set the MBR so PCI address is one-to-one with window,
59 * meaning all calls go straight through... use ifdef to
60 * catch erroneous assumption.
61 */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090062 pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
63 pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
Nicholas Beck4862ec02008-01-23 12:50:51 +090064
65 /* Set IOBR for window containing area specified in pci.h */
Magnus Damm710fa3c2009-03-11 15:47:23 +090066 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
Magnus Dammb8b47bf2009-03-11 15:41:51 +090067 SH7780_PCIIOBR);
68 pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
69 SH7780_PCIIOBMR);
Nicholas Beck4862ec02008-01-23 12:50:51 +090070
Magnus Dammb8b47bf2009-03-11 15:41:51 +090071 pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
Nicholas Beck4862ec02008-01-23 12:50:51 +090072
73 return 0;
74}