Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 22 | * set_irq_chip - set the irq chip for an irq |
| 23 | * @irq: irq number |
| 24 | * @chip: pointer to irq chip description structure |
| 25 | */ |
| 26 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) |
| 27 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 28 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 29 | unsigned long flags; |
| 30 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 31 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 | return -EINVAL; |
| 34 | } |
| 35 | |
| 36 | if (!chip) |
| 37 | chip = &no_irq_chip; |
| 38 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 40 | irq_chip_set_defaults(chip); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 41 | desc->irq_data.chip = chip; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | EXPORT_SYMBOL(set_irq_chip); |
| 47 | |
| 48 | /** |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 49 | * set_irq_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 52 | */ |
| 53 | int set_irq_type(unsigned int irq, unsigned int type) |
| 54 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 55 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 56 | unsigned long flags; |
| 57 | int ret = -ENXIO; |
| 58 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 59 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
| 61 | return -ENODEV; |
| 62 | } |
| 63 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 64 | type &= IRQ_TYPE_SENSE_MASK; |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 65 | if (type == IRQ_TYPE_NONE) |
| 66 | return 0; |
| 67 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 68 | raw_spin_lock_irqsave(&desc->lock, flags); |
Chris Friesen | 0b3682b | 2008-10-20 12:41:58 -0600 | [diff] [blame] | 69 | ret = __irq_set_trigger(desc, irq, type); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 70 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 | return ret; |
| 72 | } |
| 73 | EXPORT_SYMBOL(set_irq_type); |
| 74 | |
| 75 | /** |
| 76 | * set_irq_data - set irq type data for an irq |
| 77 | * @irq: Interrupt number |
| 78 | * @data: Pointer to interrupt specific data |
| 79 | * |
| 80 | * Set the hardware irq controller data for an irq |
| 81 | */ |
| 82 | int set_irq_data(unsigned int irq, void *data) |
| 83 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 84 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 | unsigned long flags; |
| 86 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 87 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 88 | printk(KERN_ERR |
| 89 | "Trying to install controller data for IRQ%d\n", irq); |
| 90 | return -EINVAL; |
| 91 | } |
| 92 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 93 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 94 | desc->irq_data.handler_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 95 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 96 | return 0; |
| 97 | } |
| 98 | EXPORT_SYMBOL(set_irq_data); |
| 99 | |
| 100 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 101 | * set_irq_msi - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 102 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 103 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 104 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 105 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 106 | */ |
| 107 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) |
| 108 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 109 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 110 | unsigned long flags; |
| 111 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 112 | if (!desc) { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 113 | printk(KERN_ERR |
| 114 | "Trying to install msi data for IRQ%d\n", irq); |
| 115 | return -EINVAL; |
| 116 | } |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 117 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 118 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 119 | desc->irq_data.msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 120 | if (entry) |
| 121 | entry->irq = irq; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 122 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | /** |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 127 | * set_irq_chip_data - set irq chip data for an irq |
| 128 | * @irq: Interrupt number |
| 129 | * @data: Pointer to chip specific data |
| 130 | * |
| 131 | * Set the hardware irq chip data for an irq |
| 132 | */ |
| 133 | int set_irq_chip_data(unsigned int irq, void *data) |
| 134 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 135 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 136 | unsigned long flags; |
| 137 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 138 | if (!desc) { |
| 139 | printk(KERN_ERR |
| 140 | "Trying to install chip data for IRQ%d\n", irq); |
| 141 | return -EINVAL; |
| 142 | } |
| 143 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 144 | if (!desc->irq_data.chip) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 145 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
| 146 | return -EINVAL; |
| 147 | } |
| 148 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 149 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 150 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 151 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | EXPORT_SYMBOL(set_irq_chip_data); |
| 156 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 157 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 158 | { |
| 159 | struct irq_desc *desc = irq_to_desc(irq); |
| 160 | |
| 161 | return desc ? &desc->irq_data : NULL; |
| 162 | } |
| 163 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 164 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 165 | /** |
| 166 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq |
| 167 | * |
| 168 | * @irq: Interrupt number |
| 169 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag |
| 170 | * |
| 171 | * The IRQ_NESTED_THREAD flag indicates that on |
| 172 | * request_threaded_irq() no separate interrupt thread should be |
| 173 | * created for the irq as the handler are called nested in the |
| 174 | * context of a demultiplexing interrupt handler thread. |
| 175 | */ |
| 176 | void set_irq_nested_thread(unsigned int irq, int nest) |
| 177 | { |
| 178 | struct irq_desc *desc = irq_to_desc(irq); |
| 179 | unsigned long flags; |
| 180 | |
| 181 | if (!desc) |
| 182 | return; |
| 183 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 184 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 185 | if (nest) |
| 186 | desc->status |= IRQ_NESTED_THREAD; |
| 187 | else |
| 188 | desc->status &= ~IRQ_NESTED_THREAD; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 189 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 190 | } |
| 191 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); |
| 192 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 193 | /* |
| 194 | * default enable function |
| 195 | */ |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 196 | static void default_enable(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 197 | { |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 198 | struct irq_desc *desc = irq_data_to_desc(data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 199 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 200 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 201 | desc->status &= ~IRQ_MASKED; |
| 202 | } |
| 203 | |
| 204 | /* |
| 205 | * default disable function |
| 206 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 207 | static void default_disable(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 208 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /* |
| 212 | * default startup function |
| 213 | */ |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 214 | static unsigned int default_startup(struct irq_data *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 215 | { |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 216 | struct irq_desc *desc = irq_data_to_desc(data); |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 217 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 218 | desc->irq_data.chip->irq_enable(data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | /* |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 223 | * default shutdown function |
| 224 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 225 | static void default_shutdown(struct irq_data *data) |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 226 | { |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 227 | struct irq_desc *desc = irq_data_to_desc(data); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 228 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 229 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 230 | desc->status |= IRQ_MASKED; |
| 231 | } |
| 232 | |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 233 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 234 | /* Temporary migration helpers */ |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 235 | static void compat_irq_mask(struct irq_data *data) |
| 236 | { |
| 237 | data->chip->mask(data->irq); |
| 238 | } |
| 239 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 240 | static void compat_irq_unmask(struct irq_data *data) |
| 241 | { |
| 242 | data->chip->unmask(data->irq); |
| 243 | } |
| 244 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 245 | static void compat_irq_ack(struct irq_data *data) |
| 246 | { |
| 247 | data->chip->ack(data->irq); |
| 248 | } |
| 249 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 250 | static void compat_irq_mask_ack(struct irq_data *data) |
| 251 | { |
| 252 | data->chip->mask_ack(data->irq); |
| 253 | } |
| 254 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 255 | static void compat_irq_eoi(struct irq_data *data) |
| 256 | { |
| 257 | data->chip->eoi(data->irq); |
| 258 | } |
| 259 | |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 260 | static void compat_irq_enable(struct irq_data *data) |
| 261 | { |
| 262 | data->chip->enable(data->irq); |
| 263 | } |
| 264 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 265 | static void compat_irq_disable(struct irq_data *data) |
| 266 | { |
| 267 | data->chip->disable(data->irq); |
| 268 | } |
| 269 | |
| 270 | static void compat_irq_shutdown(struct irq_data *data) |
| 271 | { |
| 272 | data->chip->shutdown(data->irq); |
| 273 | } |
| 274 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 275 | static unsigned int compat_irq_startup(struct irq_data *data) |
| 276 | { |
| 277 | return data->chip->startup(data->irq); |
| 278 | } |
| 279 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 280 | static int compat_irq_set_affinity(struct irq_data *data, |
| 281 | const struct cpumask *dest, bool force) |
| 282 | { |
| 283 | return data->chip->set_affinity(data->irq, dest); |
| 284 | } |
| 285 | |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 286 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
| 287 | { |
| 288 | return data->chip->set_type(data->irq, type); |
| 289 | } |
| 290 | |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 291 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
| 292 | { |
| 293 | return data->chip->set_wake(data->irq, on); |
| 294 | } |
| 295 | |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 296 | static int compat_irq_retrigger(struct irq_data *data) |
| 297 | { |
| 298 | return data->chip->retrigger(data->irq); |
| 299 | } |
| 300 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 301 | static void compat_bus_lock(struct irq_data *data) |
| 302 | { |
| 303 | data->chip->bus_lock(data->irq); |
| 304 | } |
| 305 | |
| 306 | static void compat_bus_sync_unlock(struct irq_data *data) |
| 307 | { |
| 308 | data->chip->bus_sync_unlock(data->irq); |
| 309 | } |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 310 | #endif |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 311 | |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 312 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 313 | * Fixup enable/disable function pointers |
| 314 | */ |
| 315 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 316 | { |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 317 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 318 | /* |
| 319 | * Compat fixup functions need to be before we set the |
| 320 | * defaults for enable/disable/startup/shutdown |
| 321 | */ |
| 322 | if (chip->enable) |
| 323 | chip->irq_enable = compat_irq_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 324 | if (chip->disable) |
| 325 | chip->irq_disable = compat_irq_disable; |
| 326 | if (chip->shutdown) |
| 327 | chip->irq_shutdown = compat_irq_shutdown; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 328 | if (chip->startup) |
| 329 | chip->irq_startup = compat_irq_startup; |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 330 | #endif |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 331 | /* |
| 332 | * The real defaults |
| 333 | */ |
| 334 | if (!chip->irq_enable) |
| 335 | chip->irq_enable = default_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 336 | if (!chip->irq_disable) |
| 337 | chip->irq_disable = default_disable; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 338 | if (!chip->irq_startup) |
| 339 | chip->irq_startup = default_startup; |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 340 | /* |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 341 | * We use chip->irq_disable, when the user provided its own. When |
| 342 | * we have default_disable set for chip->irq_disable, then we need |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 343 | * to use default_shutdown, otherwise the irq line is not |
| 344 | * disabled on free_irq(): |
| 345 | */ |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 346 | if (!chip->irq_shutdown) |
| 347 | chip->irq_shutdown = chip->irq_disable != default_disable ? |
| 348 | chip->irq_disable : default_shutdown; |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 349 | |
| 350 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 351 | if (!chip->end) |
| 352 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 353 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 354 | /* |
| 355 | * Now fix up the remaining compat handlers |
| 356 | */ |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 357 | if (chip->bus_lock) |
| 358 | chip->irq_bus_lock = compat_bus_lock; |
| 359 | if (chip->bus_sync_unlock) |
| 360 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 361 | if (chip->mask) |
| 362 | chip->irq_mask = compat_irq_mask; |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 363 | if (chip->unmask) |
| 364 | chip->irq_unmask = compat_irq_unmask; |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 365 | if (chip->ack) |
| 366 | chip->irq_ack = compat_irq_ack; |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 367 | if (chip->mask_ack) |
| 368 | chip->irq_mask_ack = compat_irq_mask_ack; |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 369 | if (chip->eoi) |
| 370 | chip->irq_eoi = compat_irq_eoi; |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 371 | if (chip->set_affinity) |
| 372 | chip->irq_set_affinity = compat_irq_set_affinity; |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 373 | if (chip->set_type) |
| 374 | chip->irq_set_type = compat_irq_set_type; |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 375 | if (chip->set_wake) |
| 376 | chip->irq_set_wake = compat_irq_set_wake; |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 377 | if (chip->retrigger) |
| 378 | chip->irq_retrigger = compat_irq_retrigger; |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 379 | #endif |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 382 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 383 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 384 | if (desc->irq_data.chip->irq_mask_ack) |
| 385 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 386 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 387 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 388 | if (desc->irq_data.chip->irq_ack) |
| 389 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 390 | } |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 391 | desc->status |= IRQ_MASKED; |
| 392 | } |
| 393 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 394 | static inline void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 395 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 396 | if (desc->irq_data.chip->irq_mask) { |
| 397 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 398 | desc->status |= IRQ_MASKED; |
| 399 | } |
| 400 | } |
| 401 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 402 | static inline void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 403 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 404 | if (desc->irq_data.chip->irq_unmask) { |
| 405 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 406 | desc->status &= ~IRQ_MASKED; |
| 407 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 408 | } |
| 409 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 410 | /* |
| 411 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 412 | * @irq: the interrupt number |
| 413 | * |
| 414 | * Handle interrupts which are nested into a threaded interrupt |
| 415 | * handler. The handler function is called inside the calling |
| 416 | * threads context. |
| 417 | */ |
| 418 | void handle_nested_irq(unsigned int irq) |
| 419 | { |
| 420 | struct irq_desc *desc = irq_to_desc(irq); |
| 421 | struct irqaction *action; |
| 422 | irqreturn_t action_ret; |
| 423 | |
| 424 | might_sleep(); |
| 425 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 426 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 427 | |
| 428 | kstat_incr_irqs_this_cpu(irq, desc); |
| 429 | |
| 430 | action = desc->action; |
| 431 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
| 432 | goto out_unlock; |
| 433 | |
| 434 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 435 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 436 | |
| 437 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 438 | if (!noirqdebug) |
| 439 | note_interrupt(irq, desc, action_ret); |
| 440 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 441 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 442 | desc->status &= ~IRQ_INPROGRESS; |
| 443 | |
| 444 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 445 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 446 | } |
| 447 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 448 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 449 | /** |
| 450 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 451 | * @irq: the interrupt number |
| 452 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 453 | * |
| 454 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 455 | * handler or come from hardware, where no interrupt hardware control |
| 456 | * is necessary. |
| 457 | * |
| 458 | * Note: The caller is expected to handle the ack, clear, mask and |
| 459 | * unmask issues if necessary. |
| 460 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 461 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 462 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 463 | { |
| 464 | struct irqaction *action; |
| 465 | irqreturn_t action_ret; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 466 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 467 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 468 | |
| 469 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 470 | goto out_unlock; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 471 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 472 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 473 | |
| 474 | action = desc->action; |
Steven Rostedt | 971e5b35f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 475 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 476 | goto out_unlock; |
| 477 | |
| 478 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 479 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 480 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 481 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 482 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 483 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 484 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 485 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 486 | desc->status &= ~IRQ_INPROGRESS; |
| 487 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 488 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /** |
| 492 | * handle_level_irq - Level type irq handler |
| 493 | * @irq: the interrupt number |
| 494 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 495 | * |
| 496 | * Level type interrupts are active as long as the hardware line has |
| 497 | * the active level. This may require to mask the interrupt and unmask |
| 498 | * it after the associated handler has acknowledged the device, so the |
| 499 | * interrupt line is back to inactive. |
| 500 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 501 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 502 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 503 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 504 | struct irqaction *action; |
| 505 | irqreturn_t action_ret; |
| 506 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 507 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 508 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 509 | |
| 510 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 511 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 512 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 513 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 514 | |
| 515 | /* |
| 516 | * If its disabled or no action available |
| 517 | * keep it masked and get out of here |
| 518 | */ |
| 519 | action = desc->action; |
Thomas Gleixner | 4966342 | 2007-08-12 15:46:34 +0000 | [diff] [blame] | 520 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 521 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 522 | |
| 523 | desc->status |= IRQ_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 524 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 525 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 526 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 527 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 528 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 529 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 530 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 531 | desc->status &= ~IRQ_INPROGRESS; |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 532 | |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 533 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 534 | unmask_irq(desc); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 535 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 536 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 537 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 538 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 | |
| 540 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 541 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 542 | * @irq: the interrupt number |
| 543 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 545 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 546 | * call when the interrupt has been serviced. This enables support |
| 547 | * for modern forms of interrupt handlers, which handle the flow |
| 548 | * details in hardware, transparently. |
| 549 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 550 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 551 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 552 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 553 | struct irqaction *action; |
| 554 | irqreturn_t action_ret; |
| 555 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 556 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 557 | |
| 558 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 559 | goto out; |
| 560 | |
| 561 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 562 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 563 | |
| 564 | /* |
| 565 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 566 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 567 | */ |
| 568 | action = desc->action; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 569 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
| 570 | desc->status |= IRQ_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 571 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 572 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 573 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 574 | |
| 575 | desc->status |= IRQ_INPROGRESS; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 576 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 577 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 578 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 579 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 580 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 581 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 582 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 583 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | desc->status &= ~IRQ_INPROGRESS; |
| 585 | out: |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 586 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 587 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 588 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 589 | } |
| 590 | |
| 591 | /** |
| 592 | * handle_edge_irq - edge type IRQ handler |
| 593 | * @irq: the interrupt number |
| 594 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 595 | * |
| 596 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 597 | * signal. The occurence is latched into the irq controller hardware |
| 598 | * and must be acked in order to be reenabled. After the ack another |
| 599 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 600 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 601 | * might be necessary to disable (mask) the interrupt depending on the |
| 602 | * controller hardware. This requires to reenable the interrupt inside |
| 603 | * of the loop which handles the interrupts which have arrived while |
| 604 | * the handler was running. If all pending interrupts are handled, the |
| 605 | * loop is left. |
| 606 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 607 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 608 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 609 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 610 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 611 | |
| 612 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
| 613 | |
| 614 | /* |
| 615 | * If we're currently running this IRQ, or its disabled, |
| 616 | * we shouldn't process the IRQ. Mark it pending, handle |
| 617 | * the necessary masking and go out |
| 618 | */ |
| 619 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || |
| 620 | !desc->action)) { |
| 621 | desc->status |= (IRQ_PENDING | IRQ_MASKED); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 622 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 623 | goto out_unlock; |
| 624 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 625 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 626 | |
| 627 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 628 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 629 | |
| 630 | /* Mark the IRQ currently in progress.*/ |
| 631 | desc->status |= IRQ_INPROGRESS; |
| 632 | |
| 633 | do { |
| 634 | struct irqaction *action = desc->action; |
| 635 | irqreturn_t action_ret; |
| 636 | |
| 637 | if (unlikely(!action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 638 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 639 | goto out_unlock; |
| 640 | } |
| 641 | |
| 642 | /* |
| 643 | * When another irq arrived while we were handling |
| 644 | * one, we could have masked the irq. |
| 645 | * Renable it, if it was not disabled in meantime. |
| 646 | */ |
| 647 | if (unlikely((desc->status & |
| 648 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == |
| 649 | (IRQ_PENDING | IRQ_MASKED))) { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 650 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 651 | } |
| 652 | |
| 653 | desc->status &= ~IRQ_PENDING; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 654 | raw_spin_unlock(&desc->lock); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 655 | action_ret = handle_IRQ_event(irq, action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 656 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 657 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 658 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 659 | |
| 660 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); |
| 661 | |
| 662 | desc->status &= ~IRQ_INPROGRESS; |
| 663 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 664 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 665 | } |
| 666 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 667 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 668 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 669 | * @irq: the interrupt number |
| 670 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 671 | * |
| 672 | * Per CPU interrupts on SMP machines without locking requirements |
| 673 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 674 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 675 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 676 | { |
| 677 | irqreturn_t action_ret; |
| 678 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 679 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 680 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 681 | if (desc->irq_data.chip->irq_ack) |
| 682 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 683 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 684 | action_ret = handle_IRQ_event(irq, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 685 | if (!noirqdebug) |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 686 | note_interrupt(irq, desc, action_ret); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 687 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 688 | if (desc->irq_data.chip->irq_eoi) |
| 689 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 690 | } |
| 691 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 692 | void |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 693 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 694 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 695 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 696 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 697 | unsigned long flags; |
| 698 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 699 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 700 | printk(KERN_ERR |
| 701 | "Trying to install type control for IRQ%d\n", irq); |
| 702 | return; |
| 703 | } |
| 704 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 705 | if (!handle) |
| 706 | handle = handle_bad_irq; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 707 | else if (desc->irq_data.chip == &no_irq_chip) { |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 708 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
Geert Uytterhoeven | b039db8 | 2006-12-20 15:59:48 +0100 | [diff] [blame] | 709 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 710 | /* |
| 711 | * Some ARM implementations install a handler for really dumb |
| 712 | * interrupt hardware without setting an irq_chip. This worked |
| 713 | * with the ARM no_irq_chip but the check in setup_irq would |
| 714 | * prevent us to setup the interrupt at all. Switch it to |
| 715 | * dummy_irq_chip for easy transition. |
| 716 | */ |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 717 | desc->irq_data.chip = &dummy_irq_chip; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 718 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 719 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 720 | chip_bus_lock(desc); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 721 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 722 | |
| 723 | /* Uninstall? */ |
| 724 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 725 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 726 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 727 | desc->status |= IRQ_DISABLED; |
| 728 | desc->depth = 1; |
| 729 | } |
| 730 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 731 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 732 | |
| 733 | if (handle != handle_bad_irq && is_chained) { |
| 734 | desc->status &= ~IRQ_DISABLED; |
| 735 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
| 736 | desc->depth = 0; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 737 | desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 738 | } |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 739 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 740 | chip_bus_sync_unlock(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 741 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 742 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 743 | |
| 744 | void |
| 745 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 746 | irq_flow_handler_t handle) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 747 | { |
| 748 | set_irq_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 749 | __set_irq_handler(irq, handle, 0, NULL); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 750 | } |
| 751 | |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 752 | void |
| 753 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
| 754 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 755 | { |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 756 | set_irq_chip(irq, chip); |
| 757 | __set_irq_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 758 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 759 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 760 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 761 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 762 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 763 | unsigned long flags; |
| 764 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 765 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 766 | return; |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 767 | |
| 768 | /* Sanitize flags */ |
| 769 | set &= IRQF_MODIFY_MASK; |
| 770 | clr &= IRQF_MODIFY_MASK; |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 771 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 772 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 773 | desc->status &= ~clr; |
| 774 | desc->status |= set; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 775 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 776 | } |