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Sathish Ambley9d69ac32012-03-21 10:28:26 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -070012
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070014/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070015/include/ "msm8974-iommu.dtsi"
Kevin Chan350b6932012-08-01 02:21:00 -070016/include/ "msm8974-camera.dtsi"
Pratik Patelf20bacb2012-07-21 14:46:36 -070017/include/ "msm8974-coresight.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -080018/include/ "msm-gdsc.dtsi"
Olav Haugan49173442012-08-01 13:23:18 -070019/include/ "msm8974-ion.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -060020/include/ "msm8974-gpu.dtsi"
Adrian Salido-Morenoa80c69e2012-07-31 18:11:09 -070021/include/ "msm8974-mdss.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -070022
23/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070024 model = "Qualcomm MSM 8974";
25 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -070026 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@F9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -080031 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -070032 reg = <0xF9000000 0x1000>,
33 <0xF9002000 0x1000>;
34 };
Sathish Ambley3d50c762011-10-25 15:26:00 -070035
Sathish Ambleye046b242012-04-09 12:38:05 -070036 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -080037 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -070038 gpio-controller;
39 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -080040 interrupt-controller;
41 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -070042 reg = <0xfd510000 0x4000>;
Michael Bohan0425f6f2012-01-17 14:36:39 -080043 };
44
Sathish Ambley098f9bd2011-11-09 16:32:53 -080045 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -070046 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -070047 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -070048 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -080049 };
50
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -080051 qcom,vidc@fdc00000 {
52 compatible = "qcom,msm-vidc";
53 reg = <0xfdc00000 0xff000>;
54 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -070055 vidc-cp-map = <0x1000000 0x40000000>;
56 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -070057 load-freq-tbl = <979200 410000000>,
58 <560145 266670000>,
59 <421161 200000000>,
60 <243000 133330000>,
61 <108000 100000000>,
62 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -080063 };
64
David Brown225abee2012-02-09 22:28:50 -080065 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -070066 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -080067 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080068 interrupts = <0 109 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -070069 status = "disabled";
Sathish Ambley3d50c762011-10-25 15:26:00 -070070 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053071
Sathish Ambley9d69ac32012-03-21 10:28:26 -070072 serial@f995e000 {
73 compatible = "qcom,msm-lsuart-v14";
74 reg = <0xf995e000 0x1000>;
75 interrupts = <0 114 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -070076 status = "disabled";
Sathish Ambley9d69ac32012-03-21 10:28:26 -070077 };
78
Stepan Moskovchenko5269b602012-08-08 17:57:09 -070079 serial@f991e000 {
80 compatible = "qcom,msm-lsuart-v14";
81 reg = <0xf991e000 0x1000>;
82 interrupts = <0 108 0>;
83 status = "disabled";
84 };
85
David Brown225abee2012-02-09 22:28:50 -080086 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053087 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -080088 reg = <0xf9a55000 0x400>;
Manu Gautamf8c45642012-08-10 10:20:56 -070089 interrupts = <0 134 0 0 140 0>;
90 interrupt-names = "core_irq", "async_irq";
Michael Bohane66a3a92012-03-26 12:47:28 -070091 HSUSB_VDDCX-supply = <&pm8841_s2>;
92 HSUSB_1p8-supply = <&pm8941_l6>;
93 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053094
95 qcom,hsusb-otg-phy-type = <2>;
96 qcom,hsusb-otg-mode = <1>;
97 qcom,hsusb-otg-otg-control = <1>;
Manu Gautambd53fba2012-07-31 16:13:06 +053098 qcom,hsusb-otg-disable-reset;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053099 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530100
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530101 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530102 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530103 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530104 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530105 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800106 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530107 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530108 vdd-supply = <&pm8941_l20>;
109 vdd-io-supply = <&pm8941_s3>;
110
111 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
112 qcom,sdcc-vdd-current_level = <800 500000>;
113
114 qcom,sdcc-vdd-io-always_on;
115 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
116 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530117
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530118 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
119 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
120 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
121 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
122
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530123 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
124 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530125 qcom,sdcc-bus-width = <8>;
126 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530127 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530128 };
129
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530130 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530131 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530132 compatible = "qcom,msm-sdcc";
133 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530134 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530135 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530136 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530137 vdd-supply = <&pm8941_l21>;
138 vdd-io-supply = <&pm8941_l13>;
139
140 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
141 qcom,sdcc-vdd-current_level = <9000 800000>;
142
143 qcom,sdcc-vdd-io-always_on;
144 qcom,sdcc-vdd-io-lpm_sup;
145 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
146 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530147
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530148 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
149 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
150 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
151 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
152
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530153 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
154 qcom,sdcc-sup-voltages = <2950 2950>;
155 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530156 qcom,sdcc-xpc;
157 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
158 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530159 };
160
161 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530162 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530163 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530164 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530165 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800166 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530167 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530168
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530169 gpios = <&msmgpio 40 0>, /* CLK */
170 <&msmgpio 39 0>, /* CMD */
171 <&msmgpio 38 0>, /* DATA0 */
172 <&msmgpio 37 0>, /* DATA1 */
173 <&msmgpio 36 0>, /* DATA2 */
174 <&msmgpio 35 0>; /* DATA3 */
175 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
176
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530177 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
178 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530179 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530180 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530181 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530182 };
183
184 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530185 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530186 compatible = "qcom,msm-sdcc";
187 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530188 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530189 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530190 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530191
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530192 gpios = <&msmgpio 93 0>, /* CLK */
193 <&msmgpio 91 0>, /* CMD */
194 <&msmgpio 96 0>, /* DATA0 */
195 <&msmgpio 95 0>, /* DATA1 */
196 <&msmgpio 94 0>, /* DATA2 */
197 <&msmgpio 92 0>; /* DATA3 */
198 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
199
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530200 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
201 qcom,sdcc-sup-voltages = <1800 1800>;
202 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530203 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530204 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530205 };
Yan He1466daa2011-11-30 17:25:38 -0800206
David Brown225abee2012-02-09 22:28:50 -0800207 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800208 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800209 reg = <0xf9984000 0x15000>,
210 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800211 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800212
213 qcom,bam-dma-res-pipes = <6>;
214 };
215
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700216
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700217 spi@f9924000 {
218 compatible = "qcom,spi-qup-v2";
219 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800220 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700221 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700222 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700223
Sagar Dhariaa316a962012-03-21 16:13:22 -0600224 slim@fe12f000 {
225 cell-index = <1>;
226 compatible = "qcom,slim-msm";
227 reg = <0xfe12f000 0x35000>,
228 <0xfe104000 0x20000>;
229 reg-names = "slimbus_physical", "slimbus_bam_physical";
230 interrupts = <0 163 0 0 164 0>;
231 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
232 qcom,min-clk-gear = <10>;
Sagar Dhariac0d6cf52012-07-31 19:17:26 -0600233 qcom,rxreg-access;
Kiran Kandie8bf5d52012-08-06 16:03:16 -0700234
235 taiko_codec {
236 compatible = "qcom,taiko-slim-pgd";
237 elemental-addr = [00 01 A0 00 17 02];
238
239 qcom,cdc-reset-gpio = <&msmgpio 63 0>;
240
241 cdc-vdd-buck-supply = <&pm8941_s2>;
242 qcom,cdc-vdd-buck-voltage = <2150000 2150000>;
243 qcom,cdc-vdd-buck-current = <650000>;
244
245 cdc-vdd-tx-h-supply = <&pm8941_s3>;
246 qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
247 qcom,cdc-vdd-tx-h-current = <25000>;
248
249 cdc-vdd-rx-h-supply = <&pm8941_s3>;
250 qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
251 qcom,cdc-vdd-rx-h-current = <25000>;
252
253 cdc-vddpx-1-supply = <&pm8941_s3>;
254 qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
255 qcom,cdc-vddpx-1-current = <10000>;
256
257 cdc-vdd-a-1p2v-supply = <&pm8941_l1>;
258 qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>;
259 qcom,cdc-vdd-a-1p2v-current = <10000>;
260
261 cdc-vddcx-1-supply = <&pm8941_l1>;
262 qcom,cdc-vddcx-1-voltage = <1225000 1225000>;
263 qcom,cdc-vddcx-1-current = <10000>;
264
265 cdc-vddcx-2-supply = <&pm8941_l1>;
266 qcom,cdc-vddcx-2-voltage = <1225000 1225000>;
267 qcom,cdc-vddcx-2-current = <10000>;
268
269 qcom,cdc-micbias-ldoh-v = <0x3>;
270 qcom,cdc-micbias-cfilt1-mv = <1800>;
271 qcom,cdc-micbias-cfilt2-mv = <2700>;
272 qcom,cdc-micbias-cfilt3-mv = <1800>;
273 qcom,cdc-micbias1-cfilt-sel = <0x0>;
274 qcom,cdc-micbias2-cfilt-sel = <0x1>;
275 qcom,cdc-micbias3-cfilt-sel = <0x2>;
276 qcom,cdc-micbias4-cfilt-sel = <0x2>;
277
278 qcom,cdc-slim-ifd = "taiko-slim-ifd";
279 qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02];
280 };
Sagar Dhariaa316a962012-03-21 16:13:22 -0600281 };
282
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700283 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700284 cell-index = <0>;
285 compatible = "qcom,spmi-pmic-arb";
286 reg = <0xfc4cf000 0x1000>,
287 <0Xfc4cb000 0x1000>;
288 /* 190,ee0_krait_hlos_spmi_periph_irq */
289 /* 187,channel_0_krait_hlos_trans_done_irq */
290 interrupts = <0 190 0 0 187 0>;
291 qcom,pmic-arb-ee = <0>;
292 qcom,pmic-arb-channel = <0>;
Gilad Avidov1d175ba2012-08-06 17:05:22 -0600293 qcom,pmic-arb-ppid-map = <0x40400000>, /* BUS */
294 <0x40500001>, /* INT */
295 <0x40600002>, /* SPMI */
296 <0x40800003>, /* PON */
297 <0x42400004>, /* TEMP_ALARM */
298 <0x47000005>, /* PBS_CORE */
299 <0x47100006>, /* PBS_CLIENT0 */
300 <0x47200007>, /* PBS_CLIENT1 */
301 <0x47300008>, /* PBS_CLIENT2 */
302 <0x47400009>, /* PBS_CLIENT3 */
303 <0x4750000a>, /* PBS_CLIENT4 */
304 <0x4760000b>, /* PBS_CLIENT5 */
305 <0x4770000c>, /* PBS_CLIENT6 */
306 <0x4780000d>, /* PBS_CLIENT7 */
307 <0x4a00000e>, /* MPP1 */
308 <0x4a100021>, /* MPP2 */
309 <0x4a20000f>, /* MPP3 */
310 <0x4a300010>, /* MPP4 */
311 <0x51000011>, /* BCLK_GEN_MAIN */
312 <0x51d00012>, /* S4_CTRL */
313 <0x51e00013>, /* S4_PS */
314 <0x51f00014>, /* S4_FREQ */
315 <0x52000015>, /* S5_CTRL */
316 <0x52100016>, /* S5_PS */
317 <0x52200017>, /* S5_FREQ */
318 <0x52300018>, /* S6_CTRL */
319 <0x52400019>, /* S6_PS */
320 <0x5250001a>, /* S6_FREQ */
321 <0x5260001b>, /* S7_CTRL */
322 <0x5270001c>, /* S7_PS */
323 <0x5280001d>, /* S7_FREQ */
324 <0x5290001e>, /* S8_CTRL */
325 <0x52a0001f>, /* S8_PS */
326 <0x52b00020>, /* S8_FREQ */
327 <0x00400022>, /* BUS */
328 <0x00500023>, /* INT */
329 <0x00600024>, /* SPMI */
330 <0x00800025>, /* PON */
331 <0x00b00027>, /* VREG_TFT */
332 <0x01000028>, /* SMBB_CHGR */
333 <0x01100029>, /* SMBB_BUCK */
334 <0x0120002a>, /* SMBB_BAT_IF */
335 <0x0130002b>, /* SMBB_USB_CHGPTH */
336 <0x0140002c>, /* SMBB_DC_CHGPTH */
337 <0x0150002d>, /* SMBB_BOOST */
338 <0x0160002e>, /* SMBB_MISC */
339 <0x0170002f>, /* SMBB_FREQ */
340 <0x02400030>, /* TEMP_ALARM */
341 <0x02800031>, /* COIN */
342 <0x03100032>, /* VADC1_USR */
343 <0x03300033>, /* VADC1_BMS */
344 <0x03400034>, /* VADC2_BTM */
345 <0x03600035>, /* IADC1_USR */
346 <0x03800036>, /* IADC1_BMS */
347 <0x04000037>, /* BMS1 */
348 <0x05700039>, /* DIFF_CLK1 */
349 <0x05c0003b>, /* DIV_CLK2 */
350 <0x0610003d>, /* RTC_ALARM */
351 <0x0620003e>, /* RTC_TIMER */
352 <0x07100040>, /* PBS_CLIENT0 */
353 <0x07200041>, /* PBS_CLIENT1 */
354 <0x07300042>, /* PBS_CLIENT2 */
355 <0x07400043>, /* PBS_CLIENT3 */
356 <0x07500044>, /* PBS_CLIENT4 */
357 <0x07600045>, /* PBS_CLIENT5 */
358 <0x07700046>, /* PBS_CLIENT6 */
359 <0x07800047>, /* PBS_CLIENT7 */
360 <0x07900048>, /* PBS_CLIENT8 */
361 <0x07a00049>, /* PBS_CLIENT9 */
362 <0x07b0004a>, /* PBS_CLIENT10 */
363 <0x07c0004b>, /* PBS_CLIENT11 */
364 <0x07d0004c>, /* PBS_CLIENT12 */
365 <0x07e0004d>, /* PBS_CLIENT13 */
366 <0x07f0004e>, /* PBS_CLIENT14 */
367 <0x0800004f>, /* PBS_CLIENT15 */
368 <0x0a100050>, /* MPP2 */
369 <0x0a300051>, /* MPP4 */
370 <0x0a400052>, /* MPP5 */
371 <0x0a500053>, /* MPP6 */
372 <0x0a600054>, /* MPP7 */
373 <0x0a700055>, /* MPP8 */
374 <0x0c000056>, /* GPIO1 */
375 <0x0c100057>, /* GPIO2 */
376 <0x0c200058>, /* GPIO3 */
377 <0x0c300059>, /* GPIO4 */
378 <0x0c40005a>, /* GPIO5 */
379 <0x0c50005b>, /* GPIO6 */
380 <0x0c60005c>, /* GPIO7 */
381 <0x0c70005d>, /* GPIO8 */
382 <0x0c80005e>, /* GPIO9 */
383 <0x0c90005f>, /* GPIO10 */
384 <0x0ca00060>, /* GPIO11 */
385 <0x0cb00061>, /* GPIO12 */
386 <0x0cc00062>, /* GPIO13 */
387 <0x0cd00063>, /* GPIO14 */
388 <0x0ce00064>, /* GPIO15 */
389 <0x0cf00065>, /* GPIO16 */
390 <0x0d200066>, /* GPIO19 */
391 <0x0d300067>, /* GPIO20 */
392 <0x0d500068>, /* GPIO22 */
393 <0x0d600069>, /* GPIO23 */
394 <0x0d70006a>, /* GPIO24 */
395 <0x0d80006b>, /* GPIO25 */
396 <0x0d90006c>, /* GPIO26 */
397 <0x0da0006d>, /* GPIO27 */
398 <0x0dc0006e>, /* GPIO29 */
399 <0x0dd0006f>, /* GPIO30 */
400 <0x0df00070>, /* GPIO32 */
401 <0x0e000071>, /* GPIO33 */
402 <0x0e100072>, /* GPIO34 */
403 <0x0e200073>, /* GPIO35 */
404 <0x0e300074>, /* GPIO36 */
405 <0x11000075>, /* BUCK_CMN */
406 <0x1a000076>, /* BOOST */
407 <0x1a100077>, /* BOOST_FREQ */
408 <0x1a800078>, /* KEYPAD1 */
409 <0x1b000079>, /* LPG_LUT */
410 <0x1b10007a>, /* LPG_CHAN1 */
411 <0x1b20007b>, /* LPG_CHAN2 */
412 <0x1b30007c>, /* LPG_CHAN3 */
413 <0x1b40007d>, /* LPG_CHAN4 */
414 <0x1b50007e>, /* LPG_CHAN5 */
415 <0x1b60007f>, /* LPG_CHAN6 */
416 <0x1b700080>, /* LPG_CHAN7 */
417 <0x1b800081>, /* LPG_CHAN8 */
418 <0x1bc00082>, /* PWM_3D */
419 <0x1c000083>, /* VIB1 */
420 <0x1d000084>, /* TRI_LED */
421 <0x1d300085>, /* FLASH1 */
422 <0x1d800086>, /* WLED1 */
423 <0x1e200087>, /* KPDBL_MAIN */
424 <0x1e300088>, /* KPDBL_LUT */
425 <0x1e400089>, /* LPG_CHAN9 */
426 <0x1e50008a>, /* LPG_CHAN10 */
427 <0x1e60008b>, /* LPG_CHAN11 */
428 <0x1e70008c>; /* LPG_CHAN12 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700429 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700430
431 i2c@f9966000 {
432 cell-index = <0>;
433 compatible = "qcom,i2c-qup";
434 reg = <0Xf9966000 0x1000>;
435 reg-names = "qup_phys_addr";
436 interrupts = <0 104 0>;
437 interrupt-names = "qup_err_intr";
438 qcom,i2c-bus-freq = <100000>;
439 qcom,i2c-src-freq = <24000000>;
440 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800441
Matt Wagantall48523022012-04-23 13:28:42 -0700442 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700443 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700444 krait0-supply = <&krait0_vreg>;
445 krait1-supply = <&krait1_vreg>;
446 krait2-supply = <&krait2_vreg>;
447 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700448 krait0_mem-supply = <&pm8841_s1_ao>;
449 krait1_mem-supply = <&pm8841_s1_ao>;
450 krait2_mem-supply = <&pm8841_s1_ao>;
451 krait3_mem-supply = <&pm8841_s1_ao>;
452 krait0_dig-supply = <&pm8841_s2_corner_ao>;
453 krait1_dig-supply = <&pm8841_s2_corner_ao>;
454 krait2_dig-supply = <&pm8841_s2_corner_ao>;
455 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700456 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
457 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
458 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
459 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
460 l2_hfpll_a-supply = <&pm8941_s2_ao>;
461 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
462 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
463 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
464 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
465 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800466 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200467
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300468 qcom,ssusb@f9200000 {
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200469 compatible = "qcom,dwc-usb3-msm";
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300470 reg = <0xf9200000 0xfc000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530471 interrupts = <0 131 0 0 179 0>;
472 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530473 SSUSB_VDDCX-supply = <&pm8841_s2>;
474 SSUSB_1p8-supply = <&pm8941_l6>;
475 HSUSB_VDDCX-supply = <&pm8841_s2>;
476 HSUSB_1p8-supply = <&pm8941_l6>;
477 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200478 qcom,dwc-usb3-msm-dbm-eps = <4>;
479 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700480
Matt Wagantallfc727212012-01-06 18:18:25 -0800481 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
482 parent-supply = <&pm8841_s4>;
483 };
484
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700485 qcom,lpass@fe200000 {
486 compatible = "qcom,pil-q6v5-lpass";
487 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700488 <0xfd485100 0x00010>;
489
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700490 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700491 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800492
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700493 qcom,msm-pcm {
494 compatible = "qcom,msm-pcm-dsp";
495 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700496
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700497 qcom,msm-pcm-routing {
498 compatible = "qcom,msm-pcm-routing";
499 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700500
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700501 qcom,msm-pcm-lpa {
502 compatible = "qcom,msm-pcm-lpa";
503 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700504
Harmandeep Singha3453a72012-07-03 12:31:09 -0700505 qcom,msm-compr-dsp {
506 compatible = "qcom,msm-compr-dsp";
507 };
508
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700509 qcom,msm-voip-dsp {
510 compatible = "qcom,msm-voip-dsp";
511 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700512
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700513 qcom,msm-stub-codec {
514 compatible = "qcom,msm-stub-codec";
515 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700516
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700517 qcom,msm-dai-fe {
518 compatible = "qcom,msm-dai-fe";
519 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700520
Joonwoo Park6572ac52012-07-10 17:17:00 -0700521 qcom,msm-dai-q6 {
522 compatible = "qcom,msm-dai-q6";
523 qcom,msm-dai-q6-sb-0-rx {
524 compatible = "qcom,msm-dai-q6-dev";
525 qcom,msm-dai-q6-dev-id = <16384>;
526 };
527
528 qcom,msm-dai-q6-sb-0-tx {
529 compatible = "qcom,msm-dai-q6-dev";
530 qcom,msm-dai-q6-dev-id = <16385>;
531 };
532 };
533
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700534 qcom,msm-auxpcm {
535 compatible = "qcom,msm-auxpcm-resource";
536 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
537 qcom,msm-cpudai-auxpcm-mode = <0>;
538 qcom,msm-cpudai-auxpcm-sync = <1>;
539 qcom,msm-cpudai-auxpcm-frame = <5>;
540 qcom,msm-cpudai-auxpcm-quant = <2>;
541 qcom,msm-cpudai-auxpcm-slot = <1>;
542 qcom,msm-cpudai-auxpcm-data = <0>;
543 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700544
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700545 qcom,msm-auxpcm-rx {
546 qcom,msm-auxpcm-dev-id = <4106>;
547 compatible = "qcom,msm-auxpcm-dev";
548 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700549
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700550 qcom,msm-auxpcm-tx {
551 qcom,msm-auxpcm-dev-id = <4107>;
552 compatible = "qcom,msm-auxpcm-dev";
553 };
554 };
555
556 qcom,msm-pcm-hostless {
557 compatible = "qcom,msm-pcm-hostless";
558 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700559
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700560 qcom,msm-ocmem-audio {
561 compatible = "qcom,msm-ocmem-audio";
562 qcom,msm-ocmem-audio-src-id = <11>;
563 qcom,msm-ocmem-audio-dst-id = <604>;
564 qcom,msm-ocmem-audio-ab = <32505856>;
565 qcom,msm-ocmem-audio-ib = <32505856>;
566 };
567
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700568 qcom,mss@fc880000 {
569 compatible = "qcom,pil-q6v5-mss";
570 reg = <0xfc880000 0x100>,
571 <0xfd485000 0x400>,
572 <0xfc820000 0x020>,
Matt Wagantall16bc5cc2012-08-09 21:33:23 -0700573 <0xfc401680 0x004>,
574 <0xfc980008 0x004>;
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700575 vdd_mss-supply = <&pm8841_s3>;
576
577 qcom,firmware-name = "mba";
578 qcom,pil-self-auth = <1>;
579 };
580
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800581 qcom,mba@fc820000 {
582 compatible = "qcom,pil-mba";
583 reg = <0xfc820000 0x0020>,
584 <0x0d1fc000 0x4000>;
585
586 qcom,firmware-name = "modem";
587 qcom,depends-on = "mba";
588 };
589
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800590 qcom,pronto@fb21b000 {
591 compatible = "qcom,pil-pronto";
592 reg = <0xfb21b000 0x3000>,
593 <0xfc401700 0x4>,
594 <0xfd485300 0xc>;
595 vdd_pronto_pll-supply = <&pm8941_l12>;
596
597 qcom,firmware-name = "wcnss";
598 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700599
600 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700601 compatible = "qcom,msm-ocmem";
602 reg = <0xfdd00000 0x2000>,
603 <0xfdd02000 0x2000>,
604 <0xfe039000 0x400>,
605 <0xfec00000 0x180000>;
606 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
607 interrupts = <0 76 0 0 77 0>;
608 interrupt-names = "ocmem_irq", "dm_irq";
609 qcom,ocmem-num-regions = <0x3>;
Naveen Ramarajba3a6262012-08-02 17:14:27 -0700610 qcom,resource-type = <0x706d636f>;
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges = <0x0 0xfec00000 0x180000>;
614
615 partition@0 {
616 reg = <0x0 0x100000>;
617 qcom,ocmem-part-name = "graphics";
618 qcom,ocmem-part-min = <0x80000>;
619 };
620
621 partition@80000 {
622 reg = <0x80000 0xA0000>;
623 qcom,ocmem-part-name = "lp_audio";
624 qcom,ocmem-part-min = <0xA0000>;
625 };
626
627 partition@E0000 {
628 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700629 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700630 qcom,ocmem-part-min = <0x20000>;
631 };
632
633 partition@100000 {
634 reg = <0x100000 0x80000>;
635 qcom,ocmem-part-name = "video";
636 qcom,ocmem-part-min = <0x55000>;
637 };
638
639 partition@140000 {
640 reg = <0x140000 0x40000>;
641 qcom,ocmem-part-name = "sensors";
642 qcom,ocmem-part-min = <0x40000>;
643 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700644 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600645
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700646 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600647 compatible = "qcom,rpm-smd";
648 rpm-channel-name = "rpm_requests";
649 rpm-channel-type = <15>; /* SMD_APPS_RPM */
650 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700651
652 qcom,msm-rng@f9bff000 {
653 compatible = "qcom,msm-rng";
654 reg = <0xf9bff000 0x200>;
655 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700656
657 qcom,qseecom@fe806000 {
658 compatible = "qcom,qseecom";
659 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700660
Hanumant72aec702012-06-25 11:51:07 -0700661 qcom,wdt@f9017000 {
662 compatible = "qcom,msm-watchdog";
663 reg = <0xf9017000 0x1000>;
664 interrupts = <0 3 0 0 4 0>;
665 qcom,bark-time = <11000>;
666 qcom,pet-time = <10000>;
667 qcom,ipi-ping = <1>;
668 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700669
670 qcom,tz-log@fe805720 {
671 compatible = "qcom,tz-log";
672 reg = <0xfe805720 0x1000>;
673 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700674
675 qcom,venus@fdce0000 {
676 compatible = "qcom,pil-venus";
677 reg = <0xfdce0000 0x4000>,
678 <0xfdc80208 0x8>;
679 vdd-supply = <&gdsc_venus>;
680
681 qcom,firmware-name = "venus";
682 qcom,firmware-min-paddr = <0xF500000>;
683 qcom,firmware-max-paddr = <0xFA00000>;
684 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700685
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700686 qcom,cache_erp {
687 compatible = "qcom,cache_erp";
688 interrupts = <1 9 0>, <0 2 0>;
689 interrupt-names = "l1_irq", "l2_irq";
690 };
691
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700692 tsens@fc4a8000 {
693 compatible = "qcom,msm-tsens";
694 reg = <0xfc4a8000 0x2000>,
695 <0xfc4b80d0 0x5>;
696 reg-names = "tsens_physical", "tsens_eeprom_physical";
697 interrupts = <0 184 0>;
698 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700699 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
700 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700701 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700702
703 qcom,msm-rtb {
704 compatible = "qcom,msm-rtb";
705 qcom,memory-reservation-type = "EBI1";
706 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
707 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700708
709 qcom,qcedev@fd440000 {
710 compatible = "qcom,qcedev";
711 reg = <0xfd440000 0x20000>,
712 <0xfd444000 0x8000>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700713 reg-names = "crypto-base","crypto-bam-base";
Mona Hossainb43e94b2012-05-07 08:52:06 -0700714 interrupts = <0 235 0>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700715 qcom,bam-pipe-pair = <0>;
Mona Hossainb43e94b2012-05-07 08:52:06 -0700716 };
717
718 qcom,qcrypto@fd444000 {
719 compatible = "qcom,qcrypto";
720 reg = <0xfd440000 0x20000>,
721 <0xfd444000 0x8000>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700722 reg-names = "crypto-base","crypto-bam-base";
Mona Hossainb43e94b2012-05-07 08:52:06 -0700723 interrupts = <0 235 0>;
Ramesh Masavarapu97ad00d2012-08-06 16:47:26 -0700724 qcom,bam-pipe-pair = <1>;
Mona Hossainb43e94b2012-05-07 08:52:06 -0700725 };
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300726
727 qcom,usbbam@f9304000 {
728 compatible = "qcom,usb-bam-msm";
729 reg = <0xf9304000 0x9000>;
730 interrupts = <0 132 0>;
731 qcom,usb-active-bam = <0>;
732 qcom,usb-total-bam-num = <1>;
733 qcom,usb-bam-num-pipes = <16>;
734 qcom,usb-base-address = <0xf9200000>;
735
736 qcom,pipe1 {
737 label = "usb-to-peri-qdss-dwc3";
738 qcom,usb-bam-type = <0>;
739 qcom,src-bam-physical-address = <0>;
740 qcom,src-bam-pipe-index = <0>;
741 qcom,dst-bam-physical-address = <0>;
742 qcom,dst-bam-pipe-index = <0>;
743 qcom,data-fifo-offset = <0>;
744 qcom,data-fifo-size = <0>;
745 qcom,descriptor-fifo-offset = <0>;
746 qcom,descriptor-fifo-size = <0>;
747 };
748
749 qcom,pipe2 {
750 label = "peri-to-usb-qdss-dwc3";
751 qcom,usb-bam-type = <0>;
752 qcom,src-bam-physical-address = <0xfc37C000>;
753 qcom,src-bam-pipe-index = <0>;
754 qcom,dst-bam-physical-address = <0xf9304000>;
755 qcom,dst-bam-pipe-index = <2>;
756 qcom,data-fifo-offset = <0xf0000>;
757 qcom,data-fifo-size = <0x4000>;
758 qcom,descriptor-fifo-offset = <0xf4000>;
759 qcom,descriptor-fifo-size = <0x1400>;
760 };
761 };
Eugene Seahce52ef22012-07-12 12:40:38 -0600762
763 qcom,msm-thermal {
764 compatible = "qcom,msm-thermal";
765 qcom,sensor-id = <0>;
766 qcom,poll-ms = <250>;
767 qcom,limit-temp = <60>;
768 qcom,temp-hysteresis = <10>;
769 qcom,freq-step = <2>;
770 };
Anirudh Ghayalb70740f2012-08-01 09:00:49 +0530771
772 gpio_keys {
773 compatible = "gpio-keys";
774
775 camera_snapshot {
776 label = "camera_snapshot";
777 gpios = <&pm8941_gpios 3 0x1>;
778 linux,input-type = <1>;
779 linux,code = <0x2fe>;
780 gpio-key,wakeup;
781 debounce-interval = <15>;
782 };
783
784 camera_focus {
785 label = "camera_focus";
786 gpios = <&pm8941_gpios 4 0x1>;
787 linux,input-type = <1>;
788 linux,code = <0x210>;
789 gpio-key,wakeup;
790 debounce-interval = <15>;
791 };
792
793 vol_up {
794 label = "volume_up";
795 gpios = <&pm8941_gpios 5 0x1>;
796 linux,input-type = <1>;
797 linux,code = <115>;
798 gpio-key,wakeup;
799 debounce-interval = <15>;
800 };
801 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700802};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700803
804/include/ "msm-pm8x41-rpm-regulator.dtsi"
805/include/ "msm-pm8841.dtsi"
806/include/ "msm-pm8941.dtsi"
807/include/ "msm8974-regulator.dtsi"
808/include/ "msm8974-gpio.dtsi"