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review.evervolv.com / android_kernel_htc_msm8960 / a8214d48e6d41f3a16c1023ca4f30bbd140ba756 / . / drivers / media / common / tuners / mxl5005s.c
blob: 2af14de737e9c778fd806280901501943c6547e1 [file] [log] [blame]
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1/*
2 * For the Realtek RTL chip RTL2831U
3 * Realtek Release Date: 2008-03-14, ver 080314
4 * Realtek version RTL2831 Linux driver version 080314
5 * ver 080314
6 *
7 * for linux kernel version 2.6.21.4 - 2.6.22-14
8 * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
9 * support two IR types -- RC5 and NEC
10 *
11 * Known boards with Realtek RTL chip RTL2821U
12 * Freecom USB stick 14aa:0160 (version 4)
13 * Conceptronic CTVDIGRCU
14 *
15 * Copyright (c) 2008 Realtek
16 * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
17 * This code is placed under the terms of the GNU General Public License
18 *
19 * Released by Realtek under GPLv2.
20 * Thanks to Realtek for a lot of support we received !
21 *
22 * Revision: 080314 - original version
23 */
24
Steven Toth2637d5b2008-05-01 05:01:31 -0300[diff] [blame]25#include "mxl5005s.h"
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]26
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]27
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]28void BuildMxl5005sModule(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]29 TUNER_MODULE **ppTuner,
30 TUNER_MODULE *pTunerModuleMemory,
31 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory,
32 BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory,
33 I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory,
34 unsigned char DeviceAddr,
35 int StandardMode
36 )
37{
38 MXL5005S_EXTRA_MODULE *pExtra;
39
40 int MxlModMode;
41 int MxlIfMode;
42 unsigned long MxlBandwitdh;
43 unsigned long MxlIfFreqHz;
44 unsigned long MxlCrystalFreqHz;
45 int MxlAgcMode;
46 unsigned short MxlTop;
47 unsigned short MxlIfOutputLoad;
48 int MxlClockOut;
49 int MxlDivOut;
50 int MxlCapSel;
51 int MxlRssiOnOff;
52 unsigned char MxlStandard;
53 unsigned char MxlTfType;
54
55
56
57 // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer.
58 *ppTuner = pTunerModuleMemory;
59 (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory;
60 (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory;
61 (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory;
62
63 // Get tuner extra module pointer.
64 pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra;
65
66
67 // Set I2C bridge tuner arguments.
68 mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner);
69
70
71 // Set tuner module manipulating function pointers.
72 (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr;
73
74 (*ppTuner)->GetTunerType = mxl5005s_GetTunerType;
75 (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr;
76
77 (*ppTuner)->Initialize = mxl5005s_Initialize;
78 (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz;
79 (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz;
80
81
82 // Set tuner extra module manipulating function pointers.
83 pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable;
84 pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits;
85 pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode;
86 pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz;
87
88
89 // Initialize tuner parameter setting status.
90 (*ppTuner)->IsDeviceAddrSet = NO;
91 (*ppTuner)->IsRfFreqHzSet = NO;
92
93
94 // Set MxL5005S parameters.
95 MxlModMode = MXL_DIGITAL_MODE;
96 MxlIfMode = MXL_ZERO_IF;
97 MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
98 MxlIfFreqHz = IF_FREQ_4570000HZ;
99 MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ;
100 MxlAgcMode = MXL_SINGLE_AGC;
101 MxlTop = MXL5005S_TOP_25P2;
102 MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
103 MxlClockOut = MXL_CLOCK_OUT_DISABLE;
104 MxlDivOut = MXL_DIV_OUT_4;
105 MxlCapSel = MXL_CAP_SEL_ENABLE;
106 MxlRssiOnOff = MXL_RSSI_ENABLE;
107 MxlTfType = MXL_TF_C_H;
108
109
110 // Set MxL5005S parameters according to standard mode
111 switch(StandardMode)
112 {
113 default:
114 case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break;
115 case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break;
116 }
117
118
119 // Set MxL5005S extra module.
120 pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
121
122 MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode,
123 MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad,
124 (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff,
125 MxlStandard, MxlTfType);
126
127
128
129 // Note: Need to set all module arguments before using module functions.
130
131
132 // Set tuner type.
133 (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S;
134
135 // Set tuner I2C device address.
136 (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr);
137
138
139 return;
140}
141
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]142void mxl5005s_SetDeviceAddr(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]143 TUNER_MODULE *pTuner,
144 unsigned char DeviceAddr
145 )
146{
147 // Set tuner I2C device address.
148 pTuner->DeviceAddr = DeviceAddr;
149 pTuner->IsDeviceAddrSet = YES;
150
151
152 return;
153}
154
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]155void mxl5005s_GetTunerType(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]156 TUNER_MODULE *pTuner,
157 int *pTunerType
158 )
159{
160 // Get tuner type from tuner module.
161 *pTunerType = pTuner->TunerType;
162
163
164 return;
165}
166
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]167int mxl5005s_GetDeviceAddr(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]168 TUNER_MODULE *pTuner,
169 unsigned char *pDeviceAddr
170 )
171{
172 // Get tuner I2C device address from tuner module.
173 if(pTuner->IsDeviceAddrSet != YES)
174 goto error_status_get_tuner_i2c_device_addr;
175
176 *pDeviceAddr = pTuner->DeviceAddr;
177
178
179 return FUNCTION_SUCCESS;
180
181
182error_status_get_tuner_i2c_device_addr:
183 return FUNCTION_ERROR;
184}
185
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]186int mxl5005s_Initialize(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]187 struct dvb_usb_device* dib,
188 TUNER_MODULE *pTuner
189 )
190{
191 MXL5005S_EXTRA_MODULE *pExtra;
192
193 unsigned char AgcMasterByte;
194 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
195 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
196 int TableLen;
197
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]198 // Get tuner extra module.
199 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
200
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]201 // Get AGC master byte
202 AgcMasterByte = pExtra->AgcMasterByte;
203
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]204 // Initialize MxL5005S tuner according to MxL5005S tuner example code.
205
206 // Tuner initialization stage 0
207 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
208 AddrTable[0] = MASTER_CONTROL_ADDR;
209 ByteTable[0] |= AgcMasterByte;
210
211 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
212 goto error_status_set_tuner_registers;
213
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]214 // Tuner initialization stage 1
215 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen);
216
217 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
218 goto error_status_set_tuner_registers;
219
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]220 return FUNCTION_SUCCESS;
221
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]222error_status_set_tuner_registers:
223 return FUNCTION_ERROR;
224}
225
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]226int mxl5005s_SetRfFreqHz(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]227 struct dvb_usb_device* dib,
228 TUNER_MODULE *pTuner,
229 unsigned long RfFreqHz
230 )
231{
232 MXL5005S_EXTRA_MODULE *pExtra;
233 BASE_INTERFACE_MODULE *pBaseInterface;
234
235 unsigned char AgcMasterByte;
236 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
237 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
238 int TableLen;
239
240 unsigned long IfDivval;
241 unsigned char MasterControlByte;
242
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]243 // Get tuner extra module and base interface module.
244 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
245 pBaseInterface = pTuner->pBaseInterface;
246
247
248 // Get AGC master byte
249 AgcMasterByte = pExtra->AgcMasterByte;
250
251
252 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
253
254 // Tuner RF frequency setting stage 0
255 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
256 AddrTable[0] = MASTER_CONTROL_ADDR;
257 ByteTable[0] |= AgcMasterByte;
258
259 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
260 goto error_status_set_tuner_registers;
261
262
263 // Tuner RF frequency setting stage 1
264 MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz);
265
266 MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval);
267
268 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0);
269 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1);
270 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8);
271
272 MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ;
273
274 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
275 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
276 ByteTable[TableLen] = MasterControlByte | AgcMasterByte;
277 TableLen += 1;
278
279 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
280 goto error_status_set_tuner_registers;
281
282
283 // Wait 30 ms.
284 pBaseInterface->WaitMs(pBaseInterface, 30);
285
286
287 // Tuner RF frequency setting stage 2
288 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ;
289 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ;
290 MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ;
291
292 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
293 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
294 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ;
295 TableLen += 1;
296
297 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
298 goto error_status_set_tuner_registers;
299
300
301 // Set tuner RF frequency parameter.
302 pTuner->RfFreqHz = RfFreqHz;
303 pTuner->IsRfFreqHzSet = YES;
304
305
306 return FUNCTION_SUCCESS;
307
308
309error_status_set_tuner_registers:
310 return FUNCTION_ERROR;
311}
312
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]313int mxl5005s_GetRfFreqHz(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]314 struct dvb_usb_device* dib,
315 TUNER_MODULE *pTuner,
316 unsigned long *pRfFreqHz
317 )
318{
319 // Get tuner RF frequency in Hz from tuner module.
320 if(pTuner->IsRfFreqHzSet != YES)
321 goto error_status_get_tuner_rf_frequency;
322
323 *pRfFreqHz = pTuner->RfFreqHz;
324
325
326 return FUNCTION_SUCCESS;
327
328
329error_status_get_tuner_rf_frequency:
330 return FUNCTION_ERROR;
331}
332
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]333int mxl5005s_SetRegsWithTable(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]334 struct dvb_usb_device* dib,
335 TUNER_MODULE *pTuner,
336 unsigned char *pAddrTable,
337 unsigned char *pByteTable,
338 int TableLen
339 )
340{
341 BASE_INTERFACE_MODULE *pBaseInterface;
342 I2C_BRIDGE_MODULE *pI2cBridge;
343 unsigned char WritingByteNumMax;
344
345 int i;
346 unsigned char WritingBuffer[I2C_BUFFER_LEN];
347 unsigned char WritingIndex;
348
349
350
351 // Get base interface, I2C bridge, and maximum writing byte number.
352 pBaseInterface = pTuner->pBaseInterface;
353 pI2cBridge = pTuner->pI2cBridge;
354 WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax;
355
356
357 // Set registers with table.
358 // Note: 1. The I2C format of MxL5005S is described as follows:
359 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit
360 // ...
361 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit
362 // 2. The latch_byte is 0xfe.
363 // 3. The following writing byte separating scheme takes latch_byte as two byte data.
364 for(i = 0, WritingIndex = 0; i < TableLen; i++)
365 {
366 // Put register address and register byte value into writing buffer.
367 WritingBuffer[WritingIndex] = pAddrTable[i];
368 WritingBuffer[WritingIndex + 1] = pByteTable[i];
369 WritingIndex += 2;
370
371 // If writing buffer is full, send the I2C writing command with writing buffer.
372 if(WritingIndex > (WritingByteNumMax - 2))
373 {
374 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
375 goto error_status_set_tuner_registers;
376
377 WritingIndex = 0;
378 }
379 }
380
381
382 // Send the last I2C writing command with writing buffer and latch byte.
383 WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE;
384 WritingIndex += 1;
385
386 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
387 goto error_status_set_tuner_registers;
388
389
390 return FUNCTION_SUCCESS;
391
392
393error_status_set_tuner_registers:
394 return FUNCTION_ERROR;
395}
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]396
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]397int mxl5005s_SetRegsWithTable(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]398 struct dvb_usb_device* dib,
399 TUNER_MODULE *pTuner,
400 unsigned char *pAddrTable,
401 unsigned char *pByteTable,
402 int TableLen
403 )
404{
405 int i;
406 u8 end_two_bytes_buf[]={ 0 , 0 };
407 u8 tuner_addr=0x00;
408
409 pTuner->GetDeviceAddr(pTuner , &tuner_addr);
410
411 for( i = 0 ; i < TableLen - 1 ; i++)
412 {
413 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) )
414 return FUNCTION_ERROR;
415 }
416
417 end_two_bytes_buf[0] = pByteTable[i];
418 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
419
420 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) )
421 return FUNCTION_ERROR;
422
423 return FUNCTION_SUCCESS;
424}
425
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]426int mxl5005s_SetRegMaskBits(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]427 struct dvb_usb_device* dib,
428 TUNER_MODULE *pTuner,
429 unsigned char RegAddr,
430 unsigned char Msb,
431 unsigned char Lsb,
432 const unsigned char WritingValue
433 )
434{
435 MXL5005S_EXTRA_MODULE *pExtra;
436
437 int i;
438
439 unsigned char Mask;
440 unsigned char Shift;
441
442 unsigned char RegByte;
443
444
445
446 // Get tuner extra module.
447 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
448
449
450 // Generate mask and shift according to MSB and LSB.
451 Mask = 0;
452 for(i = Lsb; i < (unsigned char)(Msb + 1); i++)
453 Mask |= 0x1 << i;
454
455 Shift = Lsb;
456
457
458 // Get tuner register byte according to register adddress.
459 MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte);
460
461
462 // Reserve register byte unmask bit with mask and inlay writing value into it.
463 RegByte &= ~Mask;
464 RegByte |= (WritingValue << Shift) & Mask;
465
466
467 // Update tuner register byte table.
468 MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte);
469
470
471 // Write tuner register byte with writing byte.
472 if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS)
473 goto error_status_set_tuner_registers;
474
475
476 return FUNCTION_SUCCESS;
477
478
479error_status_set_tuner_registers:
480 return FUNCTION_ERROR;
481}
482
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]483int mxl5005s_SetSpectrumMode(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]484 struct dvb_usb_device* dib,
485 TUNER_MODULE *pTuner,
486 int SpectrumMode
487 )
488{
489 static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] =
490 {
491 // BB_IQSWAP
492 0, // Normal spectrum
493 1, // Inverse spectrum
494 };
495
496
497 MXL5005S_EXTRA_MODULE *pExtra;
498
499
500
501 // Get tuner extra module.
502 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
503
504
505 // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode.
506 if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB,
507 MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS)
508 goto error_status_set_tuner_registers;
509
510
511 return FUNCTION_SUCCESS;
512
513
514error_status_set_tuner_registers:
515 return FUNCTION_ERROR;
516}
517
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]518int mxl5005s_SetBandwidthHz(
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]519 struct dvb_usb_device* dib,
520 TUNER_MODULE *pTuner,
521 unsigned long BandwidthHz
522 )
523{
524 MXL5005S_EXTRA_MODULE *pExtra;
525
526 unsigned char BbDlpfBandsel;
527
528
529
530 // Get tuner extra module.
531 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
532
533
534 // Set BB_DLPF_BANDSEL according to bandwidth.
535 switch(BandwidthHz)
536 {
537 default:
538 case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break;
539 case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break;
540 case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break;
541 }
542
543 if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB,
544 MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS)
545 goto error_status_set_tuner_registers;
546
547
548 return FUNCTION_SUCCESS;
549
550
551error_status_set_tuner_registers:
552 return FUNCTION_ERROR;
553}
554
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]555void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]556{
557 I2C_BRIDGE_MODULE *pI2cBridge;
558
559
560
561 // Get I2C bridge module.
562 pI2cBridge = pTuner->pI2cBridge;
563
564 // Set I2C bridge module tuner arguments.
565 pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr;
566
567
568 return;
569}
570
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]571// The following context is source code provided by MaxLinear.
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]572// MaxLinear source code - MXL5005_Initialize.cpp
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]573u16 MXL5005_RegisterInit(Tuner_struct *Tuner)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]574{
575 Tuner->TunerRegs_Num = TUNER_REGS_NUM ;
576// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
577
578 Tuner->TunerRegs[0].Reg_Num = 9 ;
579 Tuner->TunerRegs[0].Reg_Val = 0x40 ;
580
581 Tuner->TunerRegs[1].Reg_Num = 11 ;
582 Tuner->TunerRegs[1].Reg_Val = 0x19 ;
583
584 Tuner->TunerRegs[2].Reg_Num = 12 ;
585 Tuner->TunerRegs[2].Reg_Val = 0x60 ;
586
587 Tuner->TunerRegs[3].Reg_Num = 13 ;
588 Tuner->TunerRegs[3].Reg_Val = 0x00 ;
589
590 Tuner->TunerRegs[4].Reg_Num = 14 ;
591 Tuner->TunerRegs[4].Reg_Val = 0x00 ;
592
593 Tuner->TunerRegs[5].Reg_Num = 15 ;
594 Tuner->TunerRegs[5].Reg_Val = 0xC0 ;
595
596 Tuner->TunerRegs[6].Reg_Num = 16 ;
597 Tuner->TunerRegs[6].Reg_Val = 0x00 ;
598
599 Tuner->TunerRegs[7].Reg_Num = 17 ;
600 Tuner->TunerRegs[7].Reg_Val = 0x00 ;
601
602 Tuner->TunerRegs[8].Reg_Num = 18 ;
603 Tuner->TunerRegs[8].Reg_Val = 0x00 ;
604
605 Tuner->TunerRegs[9].Reg_Num = 19 ;
606 Tuner->TunerRegs[9].Reg_Val = 0x34 ;
607
608 Tuner->TunerRegs[10].Reg_Num = 21 ;
609 Tuner->TunerRegs[10].Reg_Val = 0x00 ;
610
611 Tuner->TunerRegs[11].Reg_Num = 22 ;
612 Tuner->TunerRegs[11].Reg_Val = 0x6B ;
613
614 Tuner->TunerRegs[12].Reg_Num = 23 ;
615 Tuner->TunerRegs[12].Reg_Val = 0x35 ;
616
617 Tuner->TunerRegs[13].Reg_Num = 24 ;
618 Tuner->TunerRegs[13].Reg_Val = 0x70 ;
619
620 Tuner->TunerRegs[14].Reg_Num = 25 ;
621 Tuner->TunerRegs[14].Reg_Val = 0x3E ;
622
623 Tuner->TunerRegs[15].Reg_Num = 26 ;
624 Tuner->TunerRegs[15].Reg_Val = 0x82 ;
625
626 Tuner->TunerRegs[16].Reg_Num = 31 ;
627 Tuner->TunerRegs[16].Reg_Val = 0x00 ;
628
629 Tuner->TunerRegs[17].Reg_Num = 32 ;
630 Tuner->TunerRegs[17].Reg_Val = 0x40 ;
631
632 Tuner->TunerRegs[18].Reg_Num = 33 ;
633 Tuner->TunerRegs[18].Reg_Val = 0x53 ;
634
635 Tuner->TunerRegs[19].Reg_Num = 34 ;
636 Tuner->TunerRegs[19].Reg_Val = 0x81 ;
637
638 Tuner->TunerRegs[20].Reg_Num = 35 ;
639 Tuner->TunerRegs[20].Reg_Val = 0xC9 ;
640
641 Tuner->TunerRegs[21].Reg_Num = 36 ;
642 Tuner->TunerRegs[21].Reg_Val = 0x01 ;
643
644 Tuner->TunerRegs[22].Reg_Num = 37 ;
645 Tuner->TunerRegs[22].Reg_Val = 0x00 ;
646
647 Tuner->TunerRegs[23].Reg_Num = 41 ;
648 Tuner->TunerRegs[23].Reg_Val = 0x00 ;
649
650 Tuner->TunerRegs[24].Reg_Num = 42 ;
651 Tuner->TunerRegs[24].Reg_Val = 0xF8 ;
652
653 Tuner->TunerRegs[25].Reg_Num = 43 ;
654 Tuner->TunerRegs[25].Reg_Val = 0x43 ;
655
656 Tuner->TunerRegs[26].Reg_Num = 44 ;
657 Tuner->TunerRegs[26].Reg_Val = 0x20 ;
658
659 Tuner->TunerRegs[27].Reg_Num = 45 ;
660 Tuner->TunerRegs[27].Reg_Val = 0x80 ;
661
662 Tuner->TunerRegs[28].Reg_Num = 46 ;
663 Tuner->TunerRegs[28].Reg_Val = 0x88 ;
664
665 Tuner->TunerRegs[29].Reg_Num = 47 ;
666 Tuner->TunerRegs[29].Reg_Val = 0x86 ;
667
668 Tuner->TunerRegs[30].Reg_Num = 48 ;
669 Tuner->TunerRegs[30].Reg_Val = 0x00 ;
670
671 Tuner->TunerRegs[31].Reg_Num = 49 ;
672 Tuner->TunerRegs[31].Reg_Val = 0x00 ;
673
674 Tuner->TunerRegs[32].Reg_Num = 53 ;
675 Tuner->TunerRegs[32].Reg_Val = 0x94 ;
676
677 Tuner->TunerRegs[33].Reg_Num = 54 ;
678 Tuner->TunerRegs[33].Reg_Val = 0xFA ;
679
680 Tuner->TunerRegs[34].Reg_Num = 55 ;
681 Tuner->TunerRegs[34].Reg_Val = 0x92 ;
682
683 Tuner->TunerRegs[35].Reg_Num = 56 ;
684 Tuner->TunerRegs[35].Reg_Val = 0x80 ;
685
686 Tuner->TunerRegs[36].Reg_Num = 57 ;
687 Tuner->TunerRegs[36].Reg_Val = 0x41 ;
688
689 Tuner->TunerRegs[37].Reg_Num = 58 ;
690 Tuner->TunerRegs[37].Reg_Val = 0xDB ;
691
692 Tuner->TunerRegs[38].Reg_Num = 59 ;
693 Tuner->TunerRegs[38].Reg_Val = 0x00 ;
694
695 Tuner->TunerRegs[39].Reg_Num = 60 ;
696 Tuner->TunerRegs[39].Reg_Val = 0x00 ;
697
698 Tuner->TunerRegs[40].Reg_Num = 61 ;
699 Tuner->TunerRegs[40].Reg_Val = 0x00 ;
700
701 Tuner->TunerRegs[41].Reg_Num = 62 ;
702 Tuner->TunerRegs[41].Reg_Val = 0x00 ;
703
704 Tuner->TunerRegs[42].Reg_Num = 65 ;
705 Tuner->TunerRegs[42].Reg_Val = 0xF8 ;
706
707 Tuner->TunerRegs[43].Reg_Num = 66 ;
708 Tuner->TunerRegs[43].Reg_Val = 0xE4 ;
709
710 Tuner->TunerRegs[44].Reg_Num = 67 ;
711 Tuner->TunerRegs[44].Reg_Val = 0x90 ;
712
713 Tuner->TunerRegs[45].Reg_Num = 68 ;
714 Tuner->TunerRegs[45].Reg_Val = 0xC0 ;
715
716 Tuner->TunerRegs[46].Reg_Num = 69 ;
717 Tuner->TunerRegs[46].Reg_Val = 0x01 ;
718
719 Tuner->TunerRegs[47].Reg_Num = 70 ;
720 Tuner->TunerRegs[47].Reg_Val = 0x50 ;
721
722 Tuner->TunerRegs[48].Reg_Num = 71 ;
723 Tuner->TunerRegs[48].Reg_Val = 0x06 ;
724
725 Tuner->TunerRegs[49].Reg_Num = 72 ;
726 Tuner->TunerRegs[49].Reg_Val = 0x00 ;
727
728 Tuner->TunerRegs[50].Reg_Num = 73 ;
729 Tuner->TunerRegs[50].Reg_Val = 0x20 ;
730
731 Tuner->TunerRegs[51].Reg_Num = 76 ;
732 Tuner->TunerRegs[51].Reg_Val = 0xBB ;
733
734 Tuner->TunerRegs[52].Reg_Num = 77 ;
735 Tuner->TunerRegs[52].Reg_Val = 0x13 ;
736
737 Tuner->TunerRegs[53].Reg_Num = 81 ;
738 Tuner->TunerRegs[53].Reg_Val = 0x04 ;
739
740 Tuner->TunerRegs[54].Reg_Num = 82 ;
741 Tuner->TunerRegs[54].Reg_Val = 0x75 ;
742
743 Tuner->TunerRegs[55].Reg_Num = 83 ;
744 Tuner->TunerRegs[55].Reg_Val = 0x00 ;
745
746 Tuner->TunerRegs[56].Reg_Num = 84 ;
747 Tuner->TunerRegs[56].Reg_Val = 0x00 ;
748
749 Tuner->TunerRegs[57].Reg_Num = 85 ;
750 Tuner->TunerRegs[57].Reg_Val = 0x00 ;
751
752 Tuner->TunerRegs[58].Reg_Num = 91 ;
753 Tuner->TunerRegs[58].Reg_Val = 0x70 ;
754
755 Tuner->TunerRegs[59].Reg_Num = 92 ;
756 Tuner->TunerRegs[59].Reg_Val = 0x00 ;
757
758 Tuner->TunerRegs[60].Reg_Num = 93 ;
759 Tuner->TunerRegs[60].Reg_Val = 0x00 ;
760
761 Tuner->TunerRegs[61].Reg_Num = 94 ;
762 Tuner->TunerRegs[61].Reg_Val = 0x00 ;
763
764 Tuner->TunerRegs[62].Reg_Num = 95 ;
765 Tuner->TunerRegs[62].Reg_Val = 0x0C ;
766
767 Tuner->TunerRegs[63].Reg_Num = 96 ;
768 Tuner->TunerRegs[63].Reg_Val = 0x00 ;
769
770 Tuner->TunerRegs[64].Reg_Num = 97 ;
771 Tuner->TunerRegs[64].Reg_Val = 0x00 ;
772
773 Tuner->TunerRegs[65].Reg_Num = 98 ;
774 Tuner->TunerRegs[65].Reg_Val = 0xE2 ;
775
776 Tuner->TunerRegs[66].Reg_Num = 99 ;
777 Tuner->TunerRegs[66].Reg_Val = 0x00 ;
778
779 Tuner->TunerRegs[67].Reg_Num = 100 ;
780 Tuner->TunerRegs[67].Reg_Val = 0x00 ;
781
782 Tuner->TunerRegs[68].Reg_Num = 101 ;
783 Tuner->TunerRegs[68].Reg_Val = 0x12 ;
784
785 Tuner->TunerRegs[69].Reg_Num = 102 ;
786 Tuner->TunerRegs[69].Reg_Val = 0x80 ;
787
788 Tuner->TunerRegs[70].Reg_Num = 103 ;
789 Tuner->TunerRegs[70].Reg_Val = 0x32 ;
790
791 Tuner->TunerRegs[71].Reg_Num = 104 ;
792 Tuner->TunerRegs[71].Reg_Val = 0xB4 ;
793
794 Tuner->TunerRegs[72].Reg_Num = 105 ;
795 Tuner->TunerRegs[72].Reg_Val = 0x60 ;
796
797 Tuner->TunerRegs[73].Reg_Num = 106 ;
798 Tuner->TunerRegs[73].Reg_Val = 0x83 ;
799
800 Tuner->TunerRegs[74].Reg_Num = 107 ;
801 Tuner->TunerRegs[74].Reg_Val = 0x84 ;
802
803 Tuner->TunerRegs[75].Reg_Num = 108 ;
804 Tuner->TunerRegs[75].Reg_Val = 0x9C ;
805
806 Tuner->TunerRegs[76].Reg_Num = 109 ;
807 Tuner->TunerRegs[76].Reg_Val = 0x02 ;
808
809 Tuner->TunerRegs[77].Reg_Num = 110 ;
810 Tuner->TunerRegs[77].Reg_Val = 0x81 ;
811
812 Tuner->TunerRegs[78].Reg_Num = 111 ;
813 Tuner->TunerRegs[78].Reg_Val = 0xC0 ;
814
815 Tuner->TunerRegs[79].Reg_Num = 112 ;
816 Tuner->TunerRegs[79].Reg_Val = 0x10 ;
817
818 Tuner->TunerRegs[80].Reg_Num = 131 ;
819 Tuner->TunerRegs[80].Reg_Val = 0x8A ;
820
821 Tuner->TunerRegs[81].Reg_Num = 132 ;
822 Tuner->TunerRegs[81].Reg_Val = 0x10 ;
823
824 Tuner->TunerRegs[82].Reg_Num = 133 ;
825 Tuner->TunerRegs[82].Reg_Val = 0x24 ;
826
827 Tuner->TunerRegs[83].Reg_Num = 134 ;
828 Tuner->TunerRegs[83].Reg_Val = 0x00 ;
829
830 Tuner->TunerRegs[84].Reg_Num = 135 ;
831 Tuner->TunerRegs[84].Reg_Val = 0x00 ;
832
833 Tuner->TunerRegs[85].Reg_Num = 136 ;
834 Tuner->TunerRegs[85].Reg_Val = 0x7E ;
835
836 Tuner->TunerRegs[86].Reg_Num = 137 ;
837 Tuner->TunerRegs[86].Reg_Val = 0x40 ;
838
839 Tuner->TunerRegs[87].Reg_Num = 138 ;
840 Tuner->TunerRegs[87].Reg_Val = 0x38 ;
841
842 Tuner->TunerRegs[88].Reg_Num = 146 ;
843 Tuner->TunerRegs[88].Reg_Val = 0xF6 ;
844
845 Tuner->TunerRegs[89].Reg_Num = 147 ;
846 Tuner->TunerRegs[89].Reg_Val = 0x1A ;
847
848 Tuner->TunerRegs[90].Reg_Num = 148 ;
849 Tuner->TunerRegs[90].Reg_Val = 0x62 ;
850
851 Tuner->TunerRegs[91].Reg_Num = 149 ;
852 Tuner->TunerRegs[91].Reg_Val = 0x33 ;
853
854 Tuner->TunerRegs[92].Reg_Num = 150 ;
855 Tuner->TunerRegs[92].Reg_Val = 0x80 ;
856
857 Tuner->TunerRegs[93].Reg_Num = 156 ;
858 Tuner->TunerRegs[93].Reg_Val = 0x56 ;
859
860 Tuner->TunerRegs[94].Reg_Num = 157 ;
861 Tuner->TunerRegs[94].Reg_Val = 0x17 ;
862
863 Tuner->TunerRegs[95].Reg_Num = 158 ;
864 Tuner->TunerRegs[95].Reg_Val = 0xA9 ;
865
866 Tuner->TunerRegs[96].Reg_Num = 159 ;
867 Tuner->TunerRegs[96].Reg_Val = 0x00 ;
868
869 Tuner->TunerRegs[97].Reg_Num = 160 ;
870 Tuner->TunerRegs[97].Reg_Val = 0x00 ;
871
872 Tuner->TunerRegs[98].Reg_Num = 161 ;
873 Tuner->TunerRegs[98].Reg_Val = 0x00 ;
874
875 Tuner->TunerRegs[99].Reg_Num = 162 ;
876 Tuner->TunerRegs[99].Reg_Val = 0x40 ;
877
878 Tuner->TunerRegs[100].Reg_Num = 166 ;
879 Tuner->TunerRegs[100].Reg_Val = 0xAE ;
880
881 Tuner->TunerRegs[101].Reg_Num = 167 ;
882 Tuner->TunerRegs[101].Reg_Val = 0x1B ;
883
884 Tuner->TunerRegs[102].Reg_Num = 168 ;
885 Tuner->TunerRegs[102].Reg_Val = 0xF2 ;
886
887 Tuner->TunerRegs[103].Reg_Num = 195 ;
888 Tuner->TunerRegs[103].Reg_Val = 0x00 ;
889
890 return 0 ;
891}
892
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]893u16 MXL5005_ControlInit(Tuner_struct *Tuner)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]894{
895 Tuner->Init_Ctrl_Num = INITCTRL_NUM ;
896
897 Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
898 Tuner->Init_Ctrl[0].size = 1 ;
899 Tuner->Init_Ctrl[0].addr[0] = 73;
900 Tuner->Init_Ctrl[0].bit[0] = 7;
901 Tuner->Init_Ctrl[0].val[0] = 0;
902
903 Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
904 Tuner->Init_Ctrl[1].size = 1 ;
905 Tuner->Init_Ctrl[1].addr[0] = 53;
906 Tuner->Init_Ctrl[1].bit[0] = 2;
907 Tuner->Init_Ctrl[1].val[0] = 1;
908
909 Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
910 Tuner->Init_Ctrl[2].size = 2 ;
911 Tuner->Init_Ctrl[2].addr[0] = 53;
912 Tuner->Init_Ctrl[2].bit[0] = 1;
913 Tuner->Init_Ctrl[2].val[0] = 0;
914 Tuner->Init_Ctrl[2].addr[1] = 57;
915 Tuner->Init_Ctrl[2].bit[1] = 0;
916 Tuner->Init_Ctrl[2].val[1] = 1;
917
918 Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
919 Tuner->Init_Ctrl[3].size = 1 ;
920 Tuner->Init_Ctrl[3].addr[0] = 53;
921 Tuner->Init_Ctrl[3].bit[0] = 0;
922 Tuner->Init_Ctrl[3].val[0] = 0;
923
924 Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
925 Tuner->Init_Ctrl[4].size = 3 ;
926 Tuner->Init_Ctrl[4].addr[0] = 53;
927 Tuner->Init_Ctrl[4].bit[0] = 5;
928 Tuner->Init_Ctrl[4].val[0] = 0;
929 Tuner->Init_Ctrl[4].addr[1] = 53;
930 Tuner->Init_Ctrl[4].bit[1] = 6;
931 Tuner->Init_Ctrl[4].val[1] = 0;
932 Tuner->Init_Ctrl[4].addr[2] = 53;
933 Tuner->Init_Ctrl[4].bit[2] = 7;
934 Tuner->Init_Ctrl[4].val[2] = 1;
935
936 Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
937 Tuner->Init_Ctrl[5].size = 1 ;
938 Tuner->Init_Ctrl[5].addr[0] = 59;
939 Tuner->Init_Ctrl[5].bit[0] = 0;
940 Tuner->Init_Ctrl[5].val[0] = 0;
941
942 Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
943 Tuner->Init_Ctrl[6].size = 2 ;
944 Tuner->Init_Ctrl[6].addr[0] = 53;
945 Tuner->Init_Ctrl[6].bit[0] = 3;
946 Tuner->Init_Ctrl[6].val[0] = 0;
947 Tuner->Init_Ctrl[6].addr[1] = 53;
948 Tuner->Init_Ctrl[6].bit[1] = 4;
949 Tuner->Init_Ctrl[6].val[1] = 1;
950
951 Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
952 Tuner->Init_Ctrl[7].size = 4 ;
953 Tuner->Init_Ctrl[7].addr[0] = 22;
954 Tuner->Init_Ctrl[7].bit[0] = 4;
955 Tuner->Init_Ctrl[7].val[0] = 0;
956 Tuner->Init_Ctrl[7].addr[1] = 22;
957 Tuner->Init_Ctrl[7].bit[1] = 5;
958 Tuner->Init_Ctrl[7].val[1] = 1;
959 Tuner->Init_Ctrl[7].addr[2] = 22;
960 Tuner->Init_Ctrl[7].bit[2] = 6;
961 Tuner->Init_Ctrl[7].val[2] = 1;
962 Tuner->Init_Ctrl[7].addr[3] = 22;
963 Tuner->Init_Ctrl[7].bit[3] = 7;
964 Tuner->Init_Ctrl[7].val[3] = 0;
965
966 Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
967 Tuner->Init_Ctrl[8].size = 1 ;
968 Tuner->Init_Ctrl[8].addr[0] = 22;
969 Tuner->Init_Ctrl[8].bit[0] = 2;
970 Tuner->Init_Ctrl[8].val[0] = 0;
971
972 Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
973 Tuner->Init_Ctrl[9].size = 4 ;
974 Tuner->Init_Ctrl[9].addr[0] = 76;
975 Tuner->Init_Ctrl[9].bit[0] = 0;
976 Tuner->Init_Ctrl[9].val[0] = 1;
977 Tuner->Init_Ctrl[9].addr[1] = 76;
978 Tuner->Init_Ctrl[9].bit[1] = 1;
979 Tuner->Init_Ctrl[9].val[1] = 1;
980 Tuner->Init_Ctrl[9].addr[2] = 76;
981 Tuner->Init_Ctrl[9].bit[2] = 2;
982 Tuner->Init_Ctrl[9].val[2] = 0;
983 Tuner->Init_Ctrl[9].addr[3] = 76;
984 Tuner->Init_Ctrl[9].bit[3] = 3;
985 Tuner->Init_Ctrl[9].val[3] = 1;
986
987 Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
988 Tuner->Init_Ctrl[10].size = 4 ;
989 Tuner->Init_Ctrl[10].addr[0] = 76;
990 Tuner->Init_Ctrl[10].bit[0] = 4;
991 Tuner->Init_Ctrl[10].val[0] = 1;
992 Tuner->Init_Ctrl[10].addr[1] = 76;
993 Tuner->Init_Ctrl[10].bit[1] = 5;
994 Tuner->Init_Ctrl[10].val[1] = 1;
995 Tuner->Init_Ctrl[10].addr[2] = 76;
996 Tuner->Init_Ctrl[10].bit[2] = 6;
997 Tuner->Init_Ctrl[10].val[2] = 0;
998 Tuner->Init_Ctrl[10].addr[3] = 76;
999 Tuner->Init_Ctrl[10].bit[3] = 7;
1000 Tuner->Init_Ctrl[10].val[3] = 1;
1001
1002 Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
1003 Tuner->Init_Ctrl[11].size = 5 ;
1004 Tuner->Init_Ctrl[11].addr[0] = 43;
1005 Tuner->Init_Ctrl[11].bit[0] = 3;
1006 Tuner->Init_Ctrl[11].val[0] = 0;
1007 Tuner->Init_Ctrl[11].addr[1] = 43;
1008 Tuner->Init_Ctrl[11].bit[1] = 4;
1009 Tuner->Init_Ctrl[11].val[1] = 0;
1010 Tuner->Init_Ctrl[11].addr[2] = 43;
1011 Tuner->Init_Ctrl[11].bit[2] = 5;
1012 Tuner->Init_Ctrl[11].val[2] = 0;
1013 Tuner->Init_Ctrl[11].addr[3] = 43;
1014 Tuner->Init_Ctrl[11].bit[3] = 6;
1015 Tuner->Init_Ctrl[11].val[3] = 1;
1016 Tuner->Init_Ctrl[11].addr[4] = 43;
1017 Tuner->Init_Ctrl[11].bit[4] = 7;
1018 Tuner->Init_Ctrl[11].val[4] = 0;
1019
1020 Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
1021 Tuner->Init_Ctrl[12].size = 6 ;
1022 Tuner->Init_Ctrl[12].addr[0] = 44;
1023 Tuner->Init_Ctrl[12].bit[0] = 2;
1024 Tuner->Init_Ctrl[12].val[0] = 0;
1025 Tuner->Init_Ctrl[12].addr[1] = 44;
1026 Tuner->Init_Ctrl[12].bit[1] = 3;
1027 Tuner->Init_Ctrl[12].val[1] = 0;
1028 Tuner->Init_Ctrl[12].addr[2] = 44;
1029 Tuner->Init_Ctrl[12].bit[2] = 4;
1030 Tuner->Init_Ctrl[12].val[2] = 0;
1031 Tuner->Init_Ctrl[12].addr[3] = 44;
1032 Tuner->Init_Ctrl[12].bit[3] = 5;
1033 Tuner->Init_Ctrl[12].val[3] = 1;
1034 Tuner->Init_Ctrl[12].addr[4] = 44;
1035 Tuner->Init_Ctrl[12].bit[4] = 6;
1036 Tuner->Init_Ctrl[12].val[4] = 0;
1037 Tuner->Init_Ctrl[12].addr[5] = 44;
1038 Tuner->Init_Ctrl[12].bit[5] = 7;
1039 Tuner->Init_Ctrl[12].val[5] = 0;
1040
1041 Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
1042 Tuner->Init_Ctrl[13].size = 7 ;
1043 Tuner->Init_Ctrl[13].addr[0] = 11;
1044 Tuner->Init_Ctrl[13].bit[0] = 0;
1045 Tuner->Init_Ctrl[13].val[0] = 1;
1046 Tuner->Init_Ctrl[13].addr[1] = 11;
1047 Tuner->Init_Ctrl[13].bit[1] = 1;
1048 Tuner->Init_Ctrl[13].val[1] = 0;
1049 Tuner->Init_Ctrl[13].addr[2] = 11;
1050 Tuner->Init_Ctrl[13].bit[2] = 2;
1051 Tuner->Init_Ctrl[13].val[2] = 0;
1052 Tuner->Init_Ctrl[13].addr[3] = 11;
1053 Tuner->Init_Ctrl[13].bit[3] = 3;
1054 Tuner->Init_Ctrl[13].val[3] = 1;
1055 Tuner->Init_Ctrl[13].addr[4] = 11;
1056 Tuner->Init_Ctrl[13].bit[4] = 4;
1057 Tuner->Init_Ctrl[13].val[4] = 1;
1058 Tuner->Init_Ctrl[13].addr[5] = 11;
1059 Tuner->Init_Ctrl[13].bit[5] = 5;
1060 Tuner->Init_Ctrl[13].val[5] = 0;
1061 Tuner->Init_Ctrl[13].addr[6] = 11;
1062 Tuner->Init_Ctrl[13].bit[6] = 6;
1063 Tuner->Init_Ctrl[13].val[6] = 0;
1064
1065 Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
1066 Tuner->Init_Ctrl[14].size = 16 ;
1067 Tuner->Init_Ctrl[14].addr[0] = 13;
1068 Tuner->Init_Ctrl[14].bit[0] = 0;
1069 Tuner->Init_Ctrl[14].val[0] = 0;
1070 Tuner->Init_Ctrl[14].addr[1] = 13;
1071 Tuner->Init_Ctrl[14].bit[1] = 1;
1072 Tuner->Init_Ctrl[14].val[1] = 0;
1073 Tuner->Init_Ctrl[14].addr[2] = 13;
1074 Tuner->Init_Ctrl[14].bit[2] = 2;
1075 Tuner->Init_Ctrl[14].val[2] = 0;
1076 Tuner->Init_Ctrl[14].addr[3] = 13;
1077 Tuner->Init_Ctrl[14].bit[3] = 3;
1078 Tuner->Init_Ctrl[14].val[3] = 0;
1079 Tuner->Init_Ctrl[14].addr[4] = 13;
1080 Tuner->Init_Ctrl[14].bit[4] = 4;
1081 Tuner->Init_Ctrl[14].val[4] = 0;
1082 Tuner->Init_Ctrl[14].addr[5] = 13;
1083 Tuner->Init_Ctrl[14].bit[5] = 5;
1084 Tuner->Init_Ctrl[14].val[5] = 0;
1085 Tuner->Init_Ctrl[14].addr[6] = 13;
1086 Tuner->Init_Ctrl[14].bit[6] = 6;
1087 Tuner->Init_Ctrl[14].val[6] = 0;
1088 Tuner->Init_Ctrl[14].addr[7] = 13;
1089 Tuner->Init_Ctrl[14].bit[7] = 7;
1090 Tuner->Init_Ctrl[14].val[7] = 0;
1091 Tuner->Init_Ctrl[14].addr[8] = 12;
1092 Tuner->Init_Ctrl[14].bit[8] = 0;
1093 Tuner->Init_Ctrl[14].val[8] = 0;
1094 Tuner->Init_Ctrl[14].addr[9] = 12;
1095 Tuner->Init_Ctrl[14].bit[9] = 1;
1096 Tuner->Init_Ctrl[14].val[9] = 0;
1097 Tuner->Init_Ctrl[14].addr[10] = 12;
1098 Tuner->Init_Ctrl[14].bit[10] = 2;
1099 Tuner->Init_Ctrl[14].val[10] = 0;
1100 Tuner->Init_Ctrl[14].addr[11] = 12;
1101 Tuner->Init_Ctrl[14].bit[11] = 3;
1102 Tuner->Init_Ctrl[14].val[11] = 0;
1103 Tuner->Init_Ctrl[14].addr[12] = 12;
1104 Tuner->Init_Ctrl[14].bit[12] = 4;
1105 Tuner->Init_Ctrl[14].val[12] = 0;
1106 Tuner->Init_Ctrl[14].addr[13] = 12;
1107 Tuner->Init_Ctrl[14].bit[13] = 5;
1108 Tuner->Init_Ctrl[14].val[13] = 1;
1109 Tuner->Init_Ctrl[14].addr[14] = 12;
1110 Tuner->Init_Ctrl[14].bit[14] = 6;
1111 Tuner->Init_Ctrl[14].val[14] = 1;
1112 Tuner->Init_Ctrl[14].addr[15] = 12;
1113 Tuner->Init_Ctrl[14].bit[15] = 7;
1114 Tuner->Init_Ctrl[14].val[15] = 0;
1115
1116 Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
1117 Tuner->Init_Ctrl[15].size = 3 ;
1118 Tuner->Init_Ctrl[15].addr[0] = 147;
1119 Tuner->Init_Ctrl[15].bit[0] = 2;
1120 Tuner->Init_Ctrl[15].val[0] = 0;
1121 Tuner->Init_Ctrl[15].addr[1] = 147;
1122 Tuner->Init_Ctrl[15].bit[1] = 3;
1123 Tuner->Init_Ctrl[15].val[1] = 1;
1124 Tuner->Init_Ctrl[15].addr[2] = 147;
1125 Tuner->Init_Ctrl[15].bit[2] = 4;
1126 Tuner->Init_Ctrl[15].val[2] = 1;
1127
1128 Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
1129 Tuner->Init_Ctrl[16].size = 2 ;
1130 Tuner->Init_Ctrl[16].addr[0] = 147;
1131 Tuner->Init_Ctrl[16].bit[0] = 0;
1132 Tuner->Init_Ctrl[16].val[0] = 0;
1133 Tuner->Init_Ctrl[16].addr[1] = 147;
1134 Tuner->Init_Ctrl[16].bit[1] = 1;
1135 Tuner->Init_Ctrl[16].val[1] = 1;
1136
1137 Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
1138 Tuner->Init_Ctrl[17].size = 1 ;
1139 Tuner->Init_Ctrl[17].addr[0] = 147;
1140 Tuner->Init_Ctrl[17].bit[0] = 7;
1141 Tuner->Init_Ctrl[17].val[0] = 0;
1142
1143 Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ;
1144 Tuner->Init_Ctrl[18].size = 1 ;
1145 Tuner->Init_Ctrl[18].addr[0] = 147;
1146 Tuner->Init_Ctrl[18].bit[0] = 6;
1147 Tuner->Init_Ctrl[18].val[0] = 0;
1148
1149 Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
1150 Tuner->Init_Ctrl[19].size = 1 ;
1151 Tuner->Init_Ctrl[19].addr[0] = 156;
1152 Tuner->Init_Ctrl[19].bit[0] = 0;
1153 Tuner->Init_Ctrl[19].val[0] = 0;
1154
1155 Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
1156 Tuner->Init_Ctrl[20].size = 1 ;
1157 Tuner->Init_Ctrl[20].addr[0] = 147;
1158 Tuner->Init_Ctrl[20].bit[0] = 5;
1159 Tuner->Init_Ctrl[20].val[0] = 0;
1160
1161 Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
1162 Tuner->Init_Ctrl[21].size = 1 ;
1163 Tuner->Init_Ctrl[21].addr[0] = 137;
1164 Tuner->Init_Ctrl[21].bit[0] = 4;
1165 Tuner->Init_Ctrl[21].val[0] = 0;
1166
1167 Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
1168 Tuner->Init_Ctrl[22].size = 1 ;
1169 Tuner->Init_Ctrl[22].addr[0] = 137;
1170 Tuner->Init_Ctrl[22].bit[0] = 7;
1171 Tuner->Init_Ctrl[22].val[0] = 0;
1172
1173 Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1174 Tuner->Init_Ctrl[23].size = 1 ;
1175 Tuner->Init_Ctrl[23].addr[0] = 91;
1176 Tuner->Init_Ctrl[23].bit[0] = 5;
1177 Tuner->Init_Ctrl[23].val[0] = 1;
1178
1179 Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1180 Tuner->Init_Ctrl[24].size = 1 ;
1181 Tuner->Init_Ctrl[24].addr[0] = 43;
1182 Tuner->Init_Ctrl[24].bit[0] = 0;
1183 Tuner->Init_Ctrl[24].val[0] = 1;
1184
1185 Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1186 Tuner->Init_Ctrl[25].size = 2 ;
1187 Tuner->Init_Ctrl[25].addr[0] = 22;
1188 Tuner->Init_Ctrl[25].bit[0] = 0;
1189 Tuner->Init_Ctrl[25].val[0] = 1;
1190 Tuner->Init_Ctrl[25].addr[1] = 22;
1191 Tuner->Init_Ctrl[25].bit[1] = 1;
1192 Tuner->Init_Ctrl[25].val[1] = 1;
1193
1194 Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1195 Tuner->Init_Ctrl[26].size = 1 ;
1196 Tuner->Init_Ctrl[26].addr[0] = 134;
1197 Tuner->Init_Ctrl[26].bit[0] = 2;
1198 Tuner->Init_Ctrl[26].val[0] = 0;
1199
1200 Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1201 Tuner->Init_Ctrl[27].size = 1 ;
1202 Tuner->Init_Ctrl[27].addr[0] = 137;
1203 Tuner->Init_Ctrl[27].bit[0] = 3;
1204 Tuner->Init_Ctrl[27].val[0] = 0;
1205
1206 Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1207 Tuner->Init_Ctrl[28].size = 1 ;
1208 Tuner->Init_Ctrl[28].addr[0] = 77;
1209 Tuner->Init_Ctrl[28].bit[0] = 7;
1210 Tuner->Init_Ctrl[28].val[0] = 0;
1211
1212 Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1213 Tuner->Init_Ctrl[29].size = 1 ;
1214 Tuner->Init_Ctrl[29].addr[0] = 166;
1215 Tuner->Init_Ctrl[29].bit[0] = 7;
1216 Tuner->Init_Ctrl[29].val[0] = 1;
1217
1218 Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1219 Tuner->Init_Ctrl[30].size = 3 ;
1220 Tuner->Init_Ctrl[30].addr[0] = 166;
1221 Tuner->Init_Ctrl[30].bit[0] = 0;
1222 Tuner->Init_Ctrl[30].val[0] = 0;
1223 Tuner->Init_Ctrl[30].addr[1] = 166;
1224 Tuner->Init_Ctrl[30].bit[1] = 1;
1225 Tuner->Init_Ctrl[30].val[1] = 1;
1226 Tuner->Init_Ctrl[30].addr[2] = 166;
1227 Tuner->Init_Ctrl[30].bit[2] = 2;
1228 Tuner->Init_Ctrl[30].val[2] = 1;
1229
1230 Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1231 Tuner->Init_Ctrl[31].size = 3 ;
1232 Tuner->Init_Ctrl[31].addr[0] = 166;
1233 Tuner->Init_Ctrl[31].bit[0] = 3;
1234 Tuner->Init_Ctrl[31].val[0] = 1;
1235 Tuner->Init_Ctrl[31].addr[1] = 166;
1236 Tuner->Init_Ctrl[31].bit[1] = 4;
1237 Tuner->Init_Ctrl[31].val[1] = 0;
1238 Tuner->Init_Ctrl[31].addr[2] = 166;
1239 Tuner->Init_Ctrl[31].bit[2] = 5;
1240 Tuner->Init_Ctrl[31].val[2] = 1;
1241
1242 Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1243 Tuner->Init_Ctrl[32].size = 3 ;
1244 Tuner->Init_Ctrl[32].addr[0] = 167;
1245 Tuner->Init_Ctrl[32].bit[0] = 0;
1246 Tuner->Init_Ctrl[32].val[0] = 1;
1247 Tuner->Init_Ctrl[32].addr[1] = 167;
1248 Tuner->Init_Ctrl[32].bit[1] = 1;
1249 Tuner->Init_Ctrl[32].val[1] = 1;
1250 Tuner->Init_Ctrl[32].addr[2] = 167;
1251 Tuner->Init_Ctrl[32].bit[2] = 2;
1252 Tuner->Init_Ctrl[32].val[2] = 0;
1253
1254 Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1255 Tuner->Init_Ctrl[33].size = 4 ;
1256 Tuner->Init_Ctrl[33].addr[0] = 168;
1257 Tuner->Init_Ctrl[33].bit[0] = 0;
1258 Tuner->Init_Ctrl[33].val[0] = 0;
1259 Tuner->Init_Ctrl[33].addr[1] = 168;
1260 Tuner->Init_Ctrl[33].bit[1] = 1;
1261 Tuner->Init_Ctrl[33].val[1] = 1;
1262 Tuner->Init_Ctrl[33].addr[2] = 168;
1263 Tuner->Init_Ctrl[33].bit[2] = 2;
1264 Tuner->Init_Ctrl[33].val[2] = 0;
1265 Tuner->Init_Ctrl[33].addr[3] = 168;
1266 Tuner->Init_Ctrl[33].bit[3] = 3;
1267 Tuner->Init_Ctrl[33].val[3] = 0;
1268
1269 Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1270 Tuner->Init_Ctrl[34].size = 4 ;
1271 Tuner->Init_Ctrl[34].addr[0] = 168;
1272 Tuner->Init_Ctrl[34].bit[0] = 4;
1273 Tuner->Init_Ctrl[34].val[0] = 1;
1274 Tuner->Init_Ctrl[34].addr[1] = 168;
1275 Tuner->Init_Ctrl[34].bit[1] = 5;
1276 Tuner->Init_Ctrl[34].val[1] = 1;
1277 Tuner->Init_Ctrl[34].addr[2] = 168;
1278 Tuner->Init_Ctrl[34].bit[2] = 6;
1279 Tuner->Init_Ctrl[34].val[2] = 1;
1280 Tuner->Init_Ctrl[34].addr[3] = 168;
1281 Tuner->Init_Ctrl[34].bit[3] = 7;
1282 Tuner->Init_Ctrl[34].val[3] = 1;
1283
1284 Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1285 Tuner->Init_Ctrl[35].size = 1 ;
1286 Tuner->Init_Ctrl[35].addr[0] = 135;
1287 Tuner->Init_Ctrl[35].bit[0] = 0;
1288 Tuner->Init_Ctrl[35].val[0] = 0;
1289
1290 Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1291 Tuner->Init_Ctrl[36].size = 1 ;
1292 Tuner->Init_Ctrl[36].addr[0] = 56;
1293 Tuner->Init_Ctrl[36].bit[0] = 3;
1294 Tuner->Init_Ctrl[36].val[0] = 0;
1295
1296 Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1297 Tuner->Init_Ctrl[37].size = 7 ;
1298 Tuner->Init_Ctrl[37].addr[0] = 59;
1299 Tuner->Init_Ctrl[37].bit[0] = 1;
1300 Tuner->Init_Ctrl[37].val[0] = 0;
1301 Tuner->Init_Ctrl[37].addr[1] = 59;
1302 Tuner->Init_Ctrl[37].bit[1] = 2;
1303 Tuner->Init_Ctrl[37].val[1] = 0;
1304 Tuner->Init_Ctrl[37].addr[2] = 59;
1305 Tuner->Init_Ctrl[37].bit[2] = 3;
1306 Tuner->Init_Ctrl[37].val[2] = 0;
1307 Tuner->Init_Ctrl[37].addr[3] = 59;
1308 Tuner->Init_Ctrl[37].bit[3] = 4;
1309 Tuner->Init_Ctrl[37].val[3] = 0;
1310 Tuner->Init_Ctrl[37].addr[4] = 59;
1311 Tuner->Init_Ctrl[37].bit[4] = 5;
1312 Tuner->Init_Ctrl[37].val[4] = 0;
1313 Tuner->Init_Ctrl[37].addr[5] = 59;
1314 Tuner->Init_Ctrl[37].bit[5] = 6;
1315 Tuner->Init_Ctrl[37].val[5] = 0;
1316 Tuner->Init_Ctrl[37].addr[6] = 59;
1317 Tuner->Init_Ctrl[37].bit[6] = 7;
1318 Tuner->Init_Ctrl[37].val[6] = 0;
1319
1320 Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1321 Tuner->Init_Ctrl[38].size = 6 ;
1322 Tuner->Init_Ctrl[38].addr[0] = 32;
1323 Tuner->Init_Ctrl[38].bit[0] = 2;
1324 Tuner->Init_Ctrl[38].val[0] = 0;
1325 Tuner->Init_Ctrl[38].addr[1] = 32;
1326 Tuner->Init_Ctrl[38].bit[1] = 3;
1327 Tuner->Init_Ctrl[38].val[1] = 0;
1328 Tuner->Init_Ctrl[38].addr[2] = 32;
1329 Tuner->Init_Ctrl[38].bit[2] = 4;
1330 Tuner->Init_Ctrl[38].val[2] = 0;
1331 Tuner->Init_Ctrl[38].addr[3] = 32;
1332 Tuner->Init_Ctrl[38].bit[3] = 5;
1333 Tuner->Init_Ctrl[38].val[3] = 0;
1334 Tuner->Init_Ctrl[38].addr[4] = 32;
1335 Tuner->Init_Ctrl[38].bit[4] = 6;
1336 Tuner->Init_Ctrl[38].val[4] = 1;
1337 Tuner->Init_Ctrl[38].addr[5] = 32;
1338 Tuner->Init_Ctrl[38].bit[5] = 7;
1339 Tuner->Init_Ctrl[38].val[5] = 0;
1340
1341 Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1342 Tuner->Init_Ctrl[39].size = 1 ;
1343 Tuner->Init_Ctrl[39].addr[0] = 25;
1344 Tuner->Init_Ctrl[39].bit[0] = 3;
1345 Tuner->Init_Ctrl[39].val[0] = 1;
1346
1347
1348 Tuner->CH_Ctrl_Num = CHCTRL_NUM ;
1349
1350 Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1351 Tuner->CH_Ctrl[0].size = 2 ;
1352 Tuner->CH_Ctrl[0].addr[0] = 68;
1353 Tuner->CH_Ctrl[0].bit[0] = 6;
1354 Tuner->CH_Ctrl[0].val[0] = 1;
1355 Tuner->CH_Ctrl[0].addr[1] = 68;
1356 Tuner->CH_Ctrl[0].bit[1] = 7;
1357 Tuner->CH_Ctrl[0].val[1] = 1;
1358
1359 Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1360 Tuner->CH_Ctrl[1].size = 2 ;
1361 Tuner->CH_Ctrl[1].addr[0] = 70;
1362 Tuner->CH_Ctrl[1].bit[0] = 6;
1363 Tuner->CH_Ctrl[1].val[0] = 1;
1364 Tuner->CH_Ctrl[1].addr[1] = 70;
1365 Tuner->CH_Ctrl[1].bit[1] = 7;
1366 Tuner->CH_Ctrl[1].val[1] = 0;
1367
1368 Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1369 Tuner->CH_Ctrl[2].size = 9 ;
1370 Tuner->CH_Ctrl[2].addr[0] = 69;
1371 Tuner->CH_Ctrl[2].bit[0] = 5;
1372 Tuner->CH_Ctrl[2].val[0] = 0;
1373 Tuner->CH_Ctrl[2].addr[1] = 69;
1374 Tuner->CH_Ctrl[2].bit[1] = 6;
1375 Tuner->CH_Ctrl[2].val[1] = 0;
1376 Tuner->CH_Ctrl[2].addr[2] = 69;
1377 Tuner->CH_Ctrl[2].bit[2] = 7;
1378 Tuner->CH_Ctrl[2].val[2] = 0;
1379 Tuner->CH_Ctrl[2].addr[3] = 68;
1380 Tuner->CH_Ctrl[2].bit[3] = 0;
1381 Tuner->CH_Ctrl[2].val[3] = 0;
1382 Tuner->CH_Ctrl[2].addr[4] = 68;
1383 Tuner->CH_Ctrl[2].bit[4] = 1;
1384 Tuner->CH_Ctrl[2].val[4] = 0;
1385 Tuner->CH_Ctrl[2].addr[5] = 68;
1386 Tuner->CH_Ctrl[2].bit[5] = 2;
1387 Tuner->CH_Ctrl[2].val[5] = 0;
1388 Tuner->CH_Ctrl[2].addr[6] = 68;
1389 Tuner->CH_Ctrl[2].bit[6] = 3;
1390 Tuner->CH_Ctrl[2].val[6] = 0;
1391 Tuner->CH_Ctrl[2].addr[7] = 68;
1392 Tuner->CH_Ctrl[2].bit[7] = 4;
1393 Tuner->CH_Ctrl[2].val[7] = 0;
1394 Tuner->CH_Ctrl[2].addr[8] = 68;
1395 Tuner->CH_Ctrl[2].bit[8] = 5;
1396 Tuner->CH_Ctrl[2].val[8] = 0;
1397
1398 Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1399 Tuner->CH_Ctrl[3].size = 1 ;
1400 Tuner->CH_Ctrl[3].addr[0] = 70;
1401 Tuner->CH_Ctrl[3].bit[0] = 5;
1402 Tuner->CH_Ctrl[3].val[0] = 0;
1403
1404 Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1405 Tuner->CH_Ctrl[4].size = 3 ;
1406 Tuner->CH_Ctrl[4].addr[0] = 73;
1407 Tuner->CH_Ctrl[4].bit[0] = 4;
1408 Tuner->CH_Ctrl[4].val[0] = 0;
1409 Tuner->CH_Ctrl[4].addr[1] = 73;
1410 Tuner->CH_Ctrl[4].bit[1] = 5;
1411 Tuner->CH_Ctrl[4].val[1] = 1;
1412 Tuner->CH_Ctrl[4].addr[2] = 73;
1413 Tuner->CH_Ctrl[4].bit[2] = 6;
1414 Tuner->CH_Ctrl[4].val[2] = 0;
1415
1416 Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1417 Tuner->CH_Ctrl[5].size = 4 ;
1418 Tuner->CH_Ctrl[5].addr[0] = 70;
1419 Tuner->CH_Ctrl[5].bit[0] = 0;
1420 Tuner->CH_Ctrl[5].val[0] = 0;
1421 Tuner->CH_Ctrl[5].addr[1] = 70;
1422 Tuner->CH_Ctrl[5].bit[1] = 1;
1423 Tuner->CH_Ctrl[5].val[1] = 0;
1424 Tuner->CH_Ctrl[5].addr[2] = 70;
1425 Tuner->CH_Ctrl[5].bit[2] = 2;
1426 Tuner->CH_Ctrl[5].val[2] = 0;
1427 Tuner->CH_Ctrl[5].addr[3] = 70;
1428 Tuner->CH_Ctrl[5].bit[3] = 3;
1429 Tuner->CH_Ctrl[5].val[3] = 0;
1430
1431 Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1432 Tuner->CH_Ctrl[6].size = 1 ;
1433 Tuner->CH_Ctrl[6].addr[0] = 70;
1434 Tuner->CH_Ctrl[6].bit[0] = 4;
1435 Tuner->CH_Ctrl[6].val[0] = 1;
1436
1437 Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1438 Tuner->CH_Ctrl[7].size = 1 ;
1439 Tuner->CH_Ctrl[7].addr[0] = 111;
1440 Tuner->CH_Ctrl[7].bit[0] = 4;
1441 Tuner->CH_Ctrl[7].val[0] = 0;
1442
1443 Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1444 Tuner->CH_Ctrl[8].size = 1 ;
1445 Tuner->CH_Ctrl[8].addr[0] = 111;
1446 Tuner->CH_Ctrl[8].bit[0] = 7;
1447 Tuner->CH_Ctrl[8].val[0] = 1;
1448
1449 Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1450 Tuner->CH_Ctrl[9].size = 1 ;
1451 Tuner->CH_Ctrl[9].addr[0] = 111;
1452 Tuner->CH_Ctrl[9].bit[0] = 6;
1453 Tuner->CH_Ctrl[9].val[0] = 1;
1454
1455 Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1456 Tuner->CH_Ctrl[10].size = 1 ;
1457 Tuner->CH_Ctrl[10].addr[0] = 111;
1458 Tuner->CH_Ctrl[10].bit[0] = 5;
1459 Tuner->CH_Ctrl[10].val[0] = 0;
1460
1461 Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1462 Tuner->CH_Ctrl[11].size = 2 ;
1463 Tuner->CH_Ctrl[11].addr[0] = 110;
1464 Tuner->CH_Ctrl[11].bit[0] = 0;
1465 Tuner->CH_Ctrl[11].val[0] = 1;
1466 Tuner->CH_Ctrl[11].addr[1] = 110;
1467 Tuner->CH_Ctrl[11].bit[1] = 1;
1468 Tuner->CH_Ctrl[11].val[1] = 0;
1469
1470 Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1471 Tuner->CH_Ctrl[12].size = 3 ;
1472 Tuner->CH_Ctrl[12].addr[0] = 69;
1473 Tuner->CH_Ctrl[12].bit[0] = 2;
1474 Tuner->CH_Ctrl[12].val[0] = 0;
1475 Tuner->CH_Ctrl[12].addr[1] = 69;
1476 Tuner->CH_Ctrl[12].bit[1] = 3;
1477 Tuner->CH_Ctrl[12].val[1] = 0;
1478 Tuner->CH_Ctrl[12].addr[2] = 69;
1479 Tuner->CH_Ctrl[12].bit[2] = 4;
1480 Tuner->CH_Ctrl[12].val[2] = 0;
1481
1482 Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1483 Tuner->CH_Ctrl[13].size = 6 ;
1484 Tuner->CH_Ctrl[13].addr[0] = 110;
1485 Tuner->CH_Ctrl[13].bit[0] = 2;
1486 Tuner->CH_Ctrl[13].val[0] = 0;
1487 Tuner->CH_Ctrl[13].addr[1] = 110;
1488 Tuner->CH_Ctrl[13].bit[1] = 3;
1489 Tuner->CH_Ctrl[13].val[1] = 0;
1490 Tuner->CH_Ctrl[13].addr[2] = 110;
1491 Tuner->CH_Ctrl[13].bit[2] = 4;
1492 Tuner->CH_Ctrl[13].val[2] = 0;
1493 Tuner->CH_Ctrl[13].addr[3] = 110;
1494 Tuner->CH_Ctrl[13].bit[3] = 5;
1495 Tuner->CH_Ctrl[13].val[3] = 0;
1496 Tuner->CH_Ctrl[13].addr[4] = 110;
1497 Tuner->CH_Ctrl[13].bit[4] = 6;
1498 Tuner->CH_Ctrl[13].val[4] = 0;
1499 Tuner->CH_Ctrl[13].addr[5] = 110;
1500 Tuner->CH_Ctrl[13].bit[5] = 7;
1501 Tuner->CH_Ctrl[13].val[5] = 1;
1502
1503 Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1504 Tuner->CH_Ctrl[14].size = 7 ;
1505 Tuner->CH_Ctrl[14].addr[0] = 14;
1506 Tuner->CH_Ctrl[14].bit[0] = 0;
1507 Tuner->CH_Ctrl[14].val[0] = 0;
1508 Tuner->CH_Ctrl[14].addr[1] = 14;
1509 Tuner->CH_Ctrl[14].bit[1] = 1;
1510 Tuner->CH_Ctrl[14].val[1] = 0;
1511 Tuner->CH_Ctrl[14].addr[2] = 14;
1512 Tuner->CH_Ctrl[14].bit[2] = 2;
1513 Tuner->CH_Ctrl[14].val[2] = 0;
1514 Tuner->CH_Ctrl[14].addr[3] = 14;
1515 Tuner->CH_Ctrl[14].bit[3] = 3;
1516 Tuner->CH_Ctrl[14].val[3] = 0;
1517 Tuner->CH_Ctrl[14].addr[4] = 14;
1518 Tuner->CH_Ctrl[14].bit[4] = 4;
1519 Tuner->CH_Ctrl[14].val[4] = 0;
1520 Tuner->CH_Ctrl[14].addr[5] = 14;
1521 Tuner->CH_Ctrl[14].bit[5] = 5;
1522 Tuner->CH_Ctrl[14].val[5] = 0;
1523 Tuner->CH_Ctrl[14].addr[6] = 14;
1524 Tuner->CH_Ctrl[14].bit[6] = 6;
1525 Tuner->CH_Ctrl[14].val[6] = 0;
1526
1527 Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1528 Tuner->CH_Ctrl[15].size = 18 ;
1529 Tuner->CH_Ctrl[15].addr[0] = 17;
1530 Tuner->CH_Ctrl[15].bit[0] = 6;
1531 Tuner->CH_Ctrl[15].val[0] = 0;
1532 Tuner->CH_Ctrl[15].addr[1] = 17;
1533 Tuner->CH_Ctrl[15].bit[1] = 7;
1534 Tuner->CH_Ctrl[15].val[1] = 0;
1535 Tuner->CH_Ctrl[15].addr[2] = 16;
1536 Tuner->CH_Ctrl[15].bit[2] = 0;
1537 Tuner->CH_Ctrl[15].val[2] = 0;
1538 Tuner->CH_Ctrl[15].addr[3] = 16;
1539 Tuner->CH_Ctrl[15].bit[3] = 1;
1540 Tuner->CH_Ctrl[15].val[3] = 0;
1541 Tuner->CH_Ctrl[15].addr[4] = 16;
1542 Tuner->CH_Ctrl[15].bit[4] = 2;
1543 Tuner->CH_Ctrl[15].val[4] = 0;
1544 Tuner->CH_Ctrl[15].addr[5] = 16;
1545 Tuner->CH_Ctrl[15].bit[5] = 3;
1546 Tuner->CH_Ctrl[15].val[5] = 0;
1547 Tuner->CH_Ctrl[15].addr[6] = 16;
1548 Tuner->CH_Ctrl[15].bit[6] = 4;
1549 Tuner->CH_Ctrl[15].val[6] = 0;
1550 Tuner->CH_Ctrl[15].addr[7] = 16;
1551 Tuner->CH_Ctrl[15].bit[7] = 5;
1552 Tuner->CH_Ctrl[15].val[7] = 0;
1553 Tuner->CH_Ctrl[15].addr[8] = 16;
1554 Tuner->CH_Ctrl[15].bit[8] = 6;
1555 Tuner->CH_Ctrl[15].val[8] = 0;
1556 Tuner->CH_Ctrl[15].addr[9] = 16;
1557 Tuner->CH_Ctrl[15].bit[9] = 7;
1558 Tuner->CH_Ctrl[15].val[9] = 0;
1559 Tuner->CH_Ctrl[15].addr[10] = 15;
1560 Tuner->CH_Ctrl[15].bit[10] = 0;
1561 Tuner->CH_Ctrl[15].val[10] = 0;
1562 Tuner->CH_Ctrl[15].addr[11] = 15;
1563 Tuner->CH_Ctrl[15].bit[11] = 1;
1564 Tuner->CH_Ctrl[15].val[11] = 0;
1565 Tuner->CH_Ctrl[15].addr[12] = 15;
1566 Tuner->CH_Ctrl[15].bit[12] = 2;
1567 Tuner->CH_Ctrl[15].val[12] = 0;
1568 Tuner->CH_Ctrl[15].addr[13] = 15;
1569 Tuner->CH_Ctrl[15].bit[13] = 3;
1570 Tuner->CH_Ctrl[15].val[13] = 0;
1571 Tuner->CH_Ctrl[15].addr[14] = 15;
1572 Tuner->CH_Ctrl[15].bit[14] = 4;
1573 Tuner->CH_Ctrl[15].val[14] = 0;
1574 Tuner->CH_Ctrl[15].addr[15] = 15;
1575 Tuner->CH_Ctrl[15].bit[15] = 5;
1576 Tuner->CH_Ctrl[15].val[15] = 0;
1577 Tuner->CH_Ctrl[15].addr[16] = 15;
1578 Tuner->CH_Ctrl[15].bit[16] = 6;
1579 Tuner->CH_Ctrl[15].val[16] = 1;
1580 Tuner->CH_Ctrl[15].addr[17] = 15;
1581 Tuner->CH_Ctrl[15].bit[17] = 7;
1582 Tuner->CH_Ctrl[15].val[17] = 1;
1583
1584 Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1585 Tuner->CH_Ctrl[16].size = 5 ;
1586 Tuner->CH_Ctrl[16].addr[0] = 112;
1587 Tuner->CH_Ctrl[16].bit[0] = 0;
1588 Tuner->CH_Ctrl[16].val[0] = 0;
1589 Tuner->CH_Ctrl[16].addr[1] = 112;
1590 Tuner->CH_Ctrl[16].bit[1] = 1;
1591 Tuner->CH_Ctrl[16].val[1] = 0;
1592 Tuner->CH_Ctrl[16].addr[2] = 112;
1593 Tuner->CH_Ctrl[16].bit[2] = 2;
1594 Tuner->CH_Ctrl[16].val[2] = 0;
1595 Tuner->CH_Ctrl[16].addr[3] = 112;
1596 Tuner->CH_Ctrl[16].bit[3] = 3;
1597 Tuner->CH_Ctrl[16].val[3] = 0;
1598 Tuner->CH_Ctrl[16].addr[4] = 112;
1599 Tuner->CH_Ctrl[16].bit[4] = 4;
1600 Tuner->CH_Ctrl[16].val[4] = 1;
1601
1602 Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1603 Tuner->CH_Ctrl[17].size = 1 ;
1604 Tuner->CH_Ctrl[17].addr[0] = 14;
1605 Tuner->CH_Ctrl[17].bit[0] = 7;
1606 Tuner->CH_Ctrl[17].val[0] = 0;
1607
1608 Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1609 Tuner->CH_Ctrl[18].size = 4 ;
1610 Tuner->CH_Ctrl[18].addr[0] = 107;
1611 Tuner->CH_Ctrl[18].bit[0] = 3;
1612 Tuner->CH_Ctrl[18].val[0] = 0;
1613 Tuner->CH_Ctrl[18].addr[1] = 107;
1614 Tuner->CH_Ctrl[18].bit[1] = 4;
1615 Tuner->CH_Ctrl[18].val[1] = 0;
1616 Tuner->CH_Ctrl[18].addr[2] = 107;
1617 Tuner->CH_Ctrl[18].bit[2] = 5;
1618 Tuner->CH_Ctrl[18].val[2] = 0;
1619 Tuner->CH_Ctrl[18].addr[3] = 107;
1620 Tuner->CH_Ctrl[18].bit[3] = 6;
1621 Tuner->CH_Ctrl[18].val[3] = 0;
1622
1623 Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1624 Tuner->CH_Ctrl[19].size = 3 ;
1625 Tuner->CH_Ctrl[19].addr[0] = 107;
1626 Tuner->CH_Ctrl[19].bit[0] = 7;
1627 Tuner->CH_Ctrl[19].val[0] = 1;
1628 Tuner->CH_Ctrl[19].addr[1] = 106;
1629 Tuner->CH_Ctrl[19].bit[1] = 0;
1630 Tuner->CH_Ctrl[19].val[1] = 1;
1631 Tuner->CH_Ctrl[19].addr[2] = 106;
1632 Tuner->CH_Ctrl[19].bit[2] = 1;
1633 Tuner->CH_Ctrl[19].val[2] = 1;
1634
1635 Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1636 Tuner->CH_Ctrl[20].size = 11 ;
1637 Tuner->CH_Ctrl[20].addr[0] = 109;
1638 Tuner->CH_Ctrl[20].bit[0] = 2;
1639 Tuner->CH_Ctrl[20].val[0] = 0;
1640 Tuner->CH_Ctrl[20].addr[1] = 109;
1641 Tuner->CH_Ctrl[20].bit[1] = 3;
1642 Tuner->CH_Ctrl[20].val[1] = 0;
1643 Tuner->CH_Ctrl[20].addr[2] = 109;
1644 Tuner->CH_Ctrl[20].bit[2] = 4;
1645 Tuner->CH_Ctrl[20].val[2] = 0;
1646 Tuner->CH_Ctrl[20].addr[3] = 109;
1647 Tuner->CH_Ctrl[20].bit[3] = 5;
1648 Tuner->CH_Ctrl[20].val[3] = 0;
1649 Tuner->CH_Ctrl[20].addr[4] = 109;
1650 Tuner->CH_Ctrl[20].bit[4] = 6;
1651 Tuner->CH_Ctrl[20].val[4] = 0;
1652 Tuner->CH_Ctrl[20].addr[5] = 109;
1653 Tuner->CH_Ctrl[20].bit[5] = 7;
1654 Tuner->CH_Ctrl[20].val[5] = 0;
1655 Tuner->CH_Ctrl[20].addr[6] = 108;
1656 Tuner->CH_Ctrl[20].bit[6] = 0;
1657 Tuner->CH_Ctrl[20].val[6] = 0;
1658 Tuner->CH_Ctrl[20].addr[7] = 108;
1659 Tuner->CH_Ctrl[20].bit[7] = 1;
1660 Tuner->CH_Ctrl[20].val[7] = 0;
1661 Tuner->CH_Ctrl[20].addr[8] = 108;
1662 Tuner->CH_Ctrl[20].bit[8] = 2;
1663 Tuner->CH_Ctrl[20].val[8] = 1;
1664 Tuner->CH_Ctrl[20].addr[9] = 108;
1665 Tuner->CH_Ctrl[20].bit[9] = 3;
1666 Tuner->CH_Ctrl[20].val[9] = 1;
1667 Tuner->CH_Ctrl[20].addr[10] = 108;
1668 Tuner->CH_Ctrl[20].bit[10] = 4;
1669 Tuner->CH_Ctrl[20].val[10] = 1;
1670
1671 Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1672 Tuner->CH_Ctrl[21].size = 6 ;
1673 Tuner->CH_Ctrl[21].addr[0] = 106;
1674 Tuner->CH_Ctrl[21].bit[0] = 2;
1675 Tuner->CH_Ctrl[21].val[0] = 0;
1676 Tuner->CH_Ctrl[21].addr[1] = 106;
1677 Tuner->CH_Ctrl[21].bit[1] = 3;
1678 Tuner->CH_Ctrl[21].val[1] = 0;
1679 Tuner->CH_Ctrl[21].addr[2] = 106;
1680 Tuner->CH_Ctrl[21].bit[2] = 4;
1681 Tuner->CH_Ctrl[21].val[2] = 0;
1682 Tuner->CH_Ctrl[21].addr[3] = 106;
1683 Tuner->CH_Ctrl[21].bit[3] = 5;
1684 Tuner->CH_Ctrl[21].val[3] = 0;
1685 Tuner->CH_Ctrl[21].addr[4] = 106;
1686 Tuner->CH_Ctrl[21].bit[4] = 6;
1687 Tuner->CH_Ctrl[21].val[4] = 0;
1688 Tuner->CH_Ctrl[21].addr[5] = 106;
1689 Tuner->CH_Ctrl[21].bit[5] = 7;
1690 Tuner->CH_Ctrl[21].val[5] = 1;
1691
1692 Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1693 Tuner->CH_Ctrl[22].size = 1 ;
1694 Tuner->CH_Ctrl[22].addr[0] = 138;
1695 Tuner->CH_Ctrl[22].bit[0] = 4;
1696 Tuner->CH_Ctrl[22].val[0] = 1;
1697
1698 Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1699 Tuner->CH_Ctrl[23].size = 1 ;
1700 Tuner->CH_Ctrl[23].addr[0] = 17;
1701 Tuner->CH_Ctrl[23].bit[0] = 5;
1702 Tuner->CH_Ctrl[23].val[0] = 0;
1703
1704 Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1705 Tuner->CH_Ctrl[24].size = 1 ;
1706 Tuner->CH_Ctrl[24].addr[0] = 111;
1707 Tuner->CH_Ctrl[24].bit[0] = 3;
1708 Tuner->CH_Ctrl[24].val[0] = 0;
1709
1710 Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1711 Tuner->CH_Ctrl[25].size = 1 ;
1712 Tuner->CH_Ctrl[25].addr[0] = 112;
1713 Tuner->CH_Ctrl[25].bit[0] = 7;
1714 Tuner->CH_Ctrl[25].val[0] = 0;
1715
1716 Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1717 Tuner->CH_Ctrl[26].size = 1 ;
1718 Tuner->CH_Ctrl[26].addr[0] = 136;
1719 Tuner->CH_Ctrl[26].bit[0] = 7;
1720 Tuner->CH_Ctrl[26].val[0] = 0;
1721
1722 Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1723 Tuner->CH_Ctrl[27].size = 1 ;
1724 Tuner->CH_Ctrl[27].addr[0] = 149;
1725 Tuner->CH_Ctrl[27].bit[0] = 7;
1726 Tuner->CH_Ctrl[27].val[0] = 0;
1727
1728 Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1729 Tuner->CH_Ctrl[28].size = 1 ;
1730 Tuner->CH_Ctrl[28].addr[0] = 149;
1731 Tuner->CH_Ctrl[28].bit[0] = 6;
1732 Tuner->CH_Ctrl[28].val[0] = 0;
1733
1734 Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1735 Tuner->CH_Ctrl[29].size = 1 ;
1736 Tuner->CH_Ctrl[29].addr[0] = 149;
1737 Tuner->CH_Ctrl[29].bit[0] = 5;
1738 Tuner->CH_Ctrl[29].val[0] = 1;
1739
1740 Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1741 Tuner->CH_Ctrl[30].size = 1 ;
1742 Tuner->CH_Ctrl[30].addr[0] = 149;
1743 Tuner->CH_Ctrl[30].bit[0] = 4;
1744 Tuner->CH_Ctrl[30].val[0] = 1;
1745
1746 Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1747 Tuner->CH_Ctrl[31].size = 1 ;
1748 Tuner->CH_Ctrl[31].addr[0] = 149;
1749 Tuner->CH_Ctrl[31].bit[0] = 3;
1750 Tuner->CH_Ctrl[31].val[0] = 0;
1751
1752 Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1753 Tuner->CH_Ctrl[32].size = 1 ;
1754 Tuner->CH_Ctrl[32].addr[0] = 93;
1755 Tuner->CH_Ctrl[32].bit[0] = 1;
1756 Tuner->CH_Ctrl[32].val[0] = 0;
1757
1758 Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1759 Tuner->CH_Ctrl[33].size = 1 ;
1760 Tuner->CH_Ctrl[33].addr[0] = 93;
1761 Tuner->CH_Ctrl[33].bit[0] = 0;
1762 Tuner->CH_Ctrl[33].val[0] = 0;
1763
1764 Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1765 Tuner->CH_Ctrl[34].size = 6 ;
1766 Tuner->CH_Ctrl[34].addr[0] = 92;
1767 Tuner->CH_Ctrl[34].bit[0] = 2;
1768 Tuner->CH_Ctrl[34].val[0] = 0;
1769 Tuner->CH_Ctrl[34].addr[1] = 92;
1770 Tuner->CH_Ctrl[34].bit[1] = 3;
1771 Tuner->CH_Ctrl[34].val[1] = 0;
1772 Tuner->CH_Ctrl[34].addr[2] = 92;
1773 Tuner->CH_Ctrl[34].bit[2] = 4;
1774 Tuner->CH_Ctrl[34].val[2] = 0;
1775 Tuner->CH_Ctrl[34].addr[3] = 92;
1776 Tuner->CH_Ctrl[34].bit[3] = 5;
1777 Tuner->CH_Ctrl[34].val[3] = 0;
1778 Tuner->CH_Ctrl[34].addr[4] = 92;
1779 Tuner->CH_Ctrl[34].bit[4] = 6;
1780 Tuner->CH_Ctrl[34].val[4] = 0;
1781 Tuner->CH_Ctrl[34].addr[5] = 92;
1782 Tuner->CH_Ctrl[34].bit[5] = 7;
1783 Tuner->CH_Ctrl[34].val[5] = 0;
1784
1785 Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1786 Tuner->CH_Ctrl[35].size = 6 ;
1787 Tuner->CH_Ctrl[35].addr[0] = 93;
1788 Tuner->CH_Ctrl[35].bit[0] = 2;
1789 Tuner->CH_Ctrl[35].val[0] = 0;
1790 Tuner->CH_Ctrl[35].addr[1] = 93;
1791 Tuner->CH_Ctrl[35].bit[1] = 3;
1792 Tuner->CH_Ctrl[35].val[1] = 0;
1793 Tuner->CH_Ctrl[35].addr[2] = 93;
1794 Tuner->CH_Ctrl[35].bit[2] = 4;
1795 Tuner->CH_Ctrl[35].val[2] = 0;
1796 Tuner->CH_Ctrl[35].addr[3] = 93;
1797 Tuner->CH_Ctrl[35].bit[3] = 5;
1798 Tuner->CH_Ctrl[35].val[3] = 0;
1799 Tuner->CH_Ctrl[35].addr[4] = 93;
1800 Tuner->CH_Ctrl[35].bit[4] = 6;
1801 Tuner->CH_Ctrl[35].val[4] = 0;
1802 Tuner->CH_Ctrl[35].addr[5] = 93;
1803 Tuner->CH_Ctrl[35].bit[5] = 7;
1804 Tuner->CH_Ctrl[35].val[5] = 0;
1805
1806#ifdef _MXL_PRODUCTION
1807 Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1808 Tuner->CH_Ctrl[36].size = 1 ;
1809 Tuner->CH_Ctrl[36].addr[0] = 109;
1810 Tuner->CH_Ctrl[36].bit[0] = 1;
1811 Tuner->CH_Ctrl[36].val[0] = 1;
1812
1813 Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1814 Tuner->CH_Ctrl[37].size = 2 ;
1815 Tuner->CH_Ctrl[37].addr[0] = 112;
1816 Tuner->CH_Ctrl[37].bit[0] = 5;
1817 Tuner->CH_Ctrl[37].val[0] = 0;
1818 Tuner->CH_Ctrl[37].addr[1] = 112;
1819 Tuner->CH_Ctrl[37].bit[1] = 6;
1820 Tuner->CH_Ctrl[37].val[1] = 0;
1821
1822 Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1823 Tuner->CH_Ctrl[38].size = 1 ;
1824 Tuner->CH_Ctrl[38].addr[0] = 65;
1825 Tuner->CH_Ctrl[38].bit[0] = 1;
1826 Tuner->CH_Ctrl[38].val[0] = 0;
1827#endif
1828
1829 return 0 ;
1830}
1831
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1832// MaxLinear source code - MXL5005_c.cpp
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1833// MXL5005.cpp : Defines the initialization routines for the DLL.
1834// 2.6.12
1835
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1836void InitTunerControls(Tuner_struct *Tuner)
1837{
1838 MXL5005_RegisterInit(Tuner) ;
1839 MXL5005_ControlInit(Tuner) ;
1840#ifdef _MXL_INTERNAL
1841 MXL5005_MXLControlInit(Tuner) ;
1842#endif
1843}
1844
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1845///////////////////////////////////////////////////////////////////////////////
1846// //
1847// Function: MXL_ConfigTuner //
1848// //
1849// Description: Configure MXL5005Tuner structure for desired //
1850// Channel Bandwidth/Channel Frequency //
1851// //
1852// //
1853// Functions used: //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1854// MXL_SynthIFLO_Calc //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1855// //
1856// Inputs: //
1857// Tuner_struct: structure defined at higher level //
1858// Mode: Tuner Mode (Analog/Digital) //
1859// IF_Mode: IF Mode ( Zero/Low ) //
1860// Bandwidth: Filter Channel Bandwidth (in Hz) //
1861// IF_out: Desired IF out Frequency (in Hz) //
1862// Fxtal: Crystal Frerquency (in Hz) //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1863// TOP: 0: Dual AGC; Value: take over point //
1864// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
1865// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
1866// DIV_OUT: 0: Div-1; 1: Div-4 //
1867// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
1868// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1869// //
1870// Outputs: //
1871// Tuner //
1872// //
1873// Return: //
1874// 0 : Successful //
1875// > 0 : Failed //
1876// //
1877///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1878u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
1879 u8 Mode, // 0: Analog Mode ; 1: Digital Mode
1880 u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF
1881 u32 Bandwidth, // filter channel bandwidth (6, 7, 8)
1882 u32 IF_out, // Desired IF Out Frequency
1883 u32 Fxtal, // XTAL Frequency
1884 u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1
1885 u16 TOP, // 0: Dual AGC; Value: take over point
1886 u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms)
1887 u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out
1888 u8 DIV_OUT, // 0: Div-1; 1: Div-4
1889 u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable
1890 u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI
1891 u8 Mod_Type, // Modulation Type;
1892 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable
1893 u8 TF_Type // Tracking Filter
1894 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1895 )
1896{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1897 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1898
1899 Tuner->Mode = Mode ;
1900 Tuner->IF_Mode = IF_mode ;
1901 Tuner->Chan_Bandwidth = Bandwidth ;
1902 Tuner->IF_OUT = IF_out ;
1903 Tuner->Fxtal = Fxtal ;
1904 Tuner->AGC_Mode = AGC_Mode ;
1905 Tuner->TOP = TOP ;
1906 Tuner->IF_OUT_LOAD = IF_OUT_LOAD ;
1907 Tuner->CLOCK_OUT = CLOCK_OUT ;
1908 Tuner->DIV_OUT = DIV_OUT ;
1909 Tuner->CAPSELECT = CAPSELECT ;
1910 Tuner->EN_RSSI = EN_RSSI ;
1911 Tuner->Mod_Type = Mod_Type ;
1912 Tuner->TF_Type = TF_Type ;
1913
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1914 /* Initialize all the controls and registers */
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1915 InitTunerControls (Tuner) ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]1916
1917 /* Synthesizer LO frequency calculation */
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1918 MXL_SynthIFLO_Calc( Tuner ) ;
1919
1920 return status ;
1921}
1922
1923///////////////////////////////////////////////////////////////////////////////
1924// //
1925// Function: MXL_SynthIFLO_Calc //
1926// //
1927// Description: Calculate Internal IF-LO Frequency //
1928// //
1929// Globals: //
1930// NONE //
1931// //
1932// Functions used: //
1933// NONE //
1934// //
1935// Inputs: //
1936// Tuner_struct: structure defined at higher level //
1937// //
1938// Outputs: //
1939// Tuner //
1940// //
1941// Return: //
1942// 0 : Successful //
1943// > 0 : Failed //
1944// //
1945///////////////////////////////////////////////////////////////////////////////
1946void MXL_SynthIFLO_Calc(Tuner_struct *Tuner)
1947{
1948 if (Tuner->Mode == 1) // Digital Mode
1949 {
1950 Tuner->IF_LO = Tuner->IF_OUT ;
1951 }
1952 else // Analog Mode
1953 {
1954 if(Tuner->IF_Mode == 0) // Analog Zero IF mode
1955 {
1956 Tuner->IF_LO = Tuner->IF_OUT + 400000 ;
1957 }
1958 else // Analog Low IF mode
1959 {
1960 Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ;
1961 }
1962 }
1963}
1964
1965///////////////////////////////////////////////////////////////////////////////
1966// //
1967// Function: MXL_SynthRFTGLO_Calc //
1968// //
1969// Description: Calculate Internal RF-LO frequency and //
1970// internal Tone-Gen(TG)-LO frequency //
1971// //
1972// Globals: //
1973// NONE //
1974// //
1975// Functions used: //
1976// NONE //
1977// //
1978// Inputs: //
1979// Tuner_struct: structure defined at higher level //
1980// //
1981// Outputs: //
1982// Tuner //
1983// //
1984// Return: //
1985// 0 : Successful //
1986// > 0 : Failed //
1987// //
1988///////////////////////////////////////////////////////////////////////////////
1989void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner)
1990{
1991 if (Tuner->Mode == 1) // Digital Mode
1992 {
1993 //remove 20.48MHz setting for 2.6.10
1994 Tuner->RF_LO = Tuner->RF_IN ;
1995 Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6
1996 }
1997 else // Analog Mode
1998 {
1999 if(Tuner->IF_Mode == 0) // Analog Zero IF mode
2000 {
2001 Tuner->RF_LO = Tuner->RF_IN - 400000 ;
2002 Tuner->TG_LO = Tuner->RF_IN - 1750000 ;
2003 }
2004 else // Analog Low IF mode
2005 {
2006 Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ;
2007 Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ;
2008 }
2009 }
2010}
2011
2012///////////////////////////////////////////////////////////////////////////////
2013// //
2014// Function: MXL_OverwriteICDefault //
2015// //
2016// Description: Overwrite the Default Register Setting //
2017// //
2018// //
2019// Functions used: //
2020// //
2021// Inputs: //
2022// Tuner_struct: structure defined at higher level //
2023// Outputs: //
2024// Tuner //
2025// //
2026// Return: //
2027// 0 : Successful //
2028// > 0 : Failed //
2029// //
2030///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2031u16 MXL_OverwriteICDefault( Tuner_struct *Tuner)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2032{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2033 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2034
2035 status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ;
2036 status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ;
2037 status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ;
2038 status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ;
2039
2040 return status ;
2041}
2042
2043///////////////////////////////////////////////////////////////////////////////
2044// //
2045// Function: MXL_BlockInit //
2046// //
2047// Description: Tuner Initialization as a function of 'User Settings' //
2048// * User settings in Tuner strcuture must be assigned //
2049// first //
2050// //
2051// Globals: //
2052// NONE //
2053// //
2054// Functions used: //
2055// Tuner_struct: structure defined at higher level //
2056// //
2057// Inputs: //
2058// Tuner : Tuner structure defined at higher level //
2059// //
2060// Outputs: //
2061// Tuner //
2062// //
2063// Return: //
2064// 0 : Successful //
2065// > 0 : Failed //
2066// //
2067///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2068u16 MXL_BlockInit( Tuner_struct *Tuner )
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2069{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2070 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2071
2072 status += MXL_OverwriteICDefault(Tuner) ;
2073
2074 //
2075 // Downconverter Control
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2076 // Dig Ana
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2077 status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ;
2078
2079 //
2080 // Filter Control
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2081 // Dig Ana
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2082 status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ;
2083 status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ;
2084 status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ;
2085
2086 status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ;
2087 status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ;
2088
2089 // Initialize Low-Pass Filter
2090 if (Tuner->Mode) { // Digital Mode
2091 switch (Tuner->Chan_Bandwidth) {
2092 case 8000000:
2093 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ;
2094 break ;
2095 case 7000000:
2096 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ;
2097 break ;
2098 case 6000000:
2099 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ;
2100 break ;
2101 }
2102 } else { // Analog Mode
2103 switch (Tuner->Chan_Bandwidth) {
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2104 case 8000000: // Low Zero
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2105 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ;
2106 break ;
2107 case 7000000:
2108 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ;
2109 break ;
2110 case 6000000:
2111 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ;
2112 break ;
2113 }
2114 }
2115
2116 //
2117 // Charge Pump Control
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2118 // Dig Ana
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2119 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ;
2120 status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ;
2121 status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ;
2122
2123 //
2124 // AGC TOP Control
2125 //
2126 if (Tuner->AGC_Mode == 0) // Dual AGC
2127 {
2128 status += MXL_ControlWrite(Tuner, AGC_IF, 15) ;
2129 status += MXL_ControlWrite(Tuner, AGC_RF, 15) ;
2130 }
2131 else // Single AGC Mode Dig Ana
2132 status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ;
2133
2134
2135 if (Tuner->TOP == 55) // TOP == 5.5
2136 status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ;
2137
2138 if (Tuner->TOP == 72) // TOP == 7.2
2139 status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ;
2140
2141 if (Tuner->TOP == 92) // TOP == 9.2
2142 status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ;
2143
2144 if (Tuner->TOP == 110) // TOP == 11.0
2145 status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ;
2146
2147 if (Tuner->TOP == 129) // TOP == 12.9
2148 status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ;
2149
2150 if (Tuner->TOP == 147) // TOP == 14.7
2151 status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ;
2152
2153 if (Tuner->TOP == 168) // TOP == 16.8
2154 status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ;
2155
2156 if (Tuner->TOP == 194) // TOP == 19.4
2157 status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ;
2158
2159 if (Tuner->TOP == 212) // TOP == 21.2
2160 status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ;
2161
2162 if (Tuner->TOP == 232) // TOP == 23.2
2163 status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ;
2164
2165 if (Tuner->TOP == 252) // TOP == 25.2
2166 status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ;
2167
2168 if (Tuner->TOP == 271) // TOP == 27.1
2169 status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ;
2170
2171 if (Tuner->TOP == 292) // TOP == 29.2
2172 status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ;
2173
2174 if (Tuner->TOP == 317) // TOP == 31.7
2175 status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ;
2176
2177 if (Tuner->TOP == 349) // TOP == 34.9
2178 status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ;
2179
2180 //
2181 // IF Synthesizer Control
2182 //
2183 status += MXL_IFSynthInit( Tuner ) ;
2184
2185 //
2186 // IF UpConverter Control
2187 if (Tuner->IF_OUT_LOAD == 200)
2188 {
2189 status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ;
2190 status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ;
2191 }
2192 if (Tuner->IF_OUT_LOAD == 300)
2193 {
2194 status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ;
2195 status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ;
2196 }
2197
2198 //
2199 // Anti-Alias Filtering Control
2200 //
2201 // initialise Anti-Aliasing Filter
2202 if (Tuner->Mode) {// Digital Mode
2203 if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) {
2204 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2205 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2206 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2207 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2208 }
2209 if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) {
2210 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2211 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2212 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2213 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ;
2214 }
2215 if (Tuner->IF_OUT > 36150000UL) {
2216 status += MXL_ControlWrite(Tuner, EN_AAF, 0) ;
2217 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2218 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2219 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ;
2220 }
2221 } else { // Analog Mode
2222 if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL)
2223 {
2224 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2225 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2226 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2227 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2228 }
2229 if (Tuner->IF_OUT > 5000000UL)
2230 {
2231 status += MXL_ControlWrite(Tuner, EN_AAF, 0) ;
2232 status += MXL_ControlWrite(Tuner, EN_3P, 0) ;
2233 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ;
2234 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2235 }
2236 }
2237
2238 //
2239 // Demod Clock Out
2240 //
2241 if (Tuner->CLOCK_OUT)
2242 status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ;
2243 else
2244 status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ;
2245
2246 if (Tuner->DIV_OUT == 1)
2247 status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ;
2248 if (Tuner->DIV_OUT == 0)
2249 status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ;
2250
2251 //
2252 // Crystal Control
2253 //
2254 if (Tuner->CAPSELECT)
2255 status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ;
2256 else
2257 status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ;
2258
2259 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL)
2260 status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ;
2261 if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL)
2262 status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ;
2263
2264 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL)
2265 status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ;
2266 if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL)
2267 status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ;
2268
2269 //
2270 // Misc Controls
2271 //
2272 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode
2273 status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0);
2274 else
2275 status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1);
2276
2277// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ;
2278
2279 // Set TG_R_DIV
2280 status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ;
2281
2282 //
2283 // Apply Default value to BB_INITSTATE_DLPF_TUNE
2284 //
2285
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2286 //
2287 // RSSI Control
2288 //
2289 if(Tuner->EN_RSSI)
2290 {
2291 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2292 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2293 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2294 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2295 // RSSI reference point
2296 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ;
2297 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ;
2298 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2299 // TOP point
2300 status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ;
2301 status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ;
2302 }
2303
2304 //
2305 // Modulation type bit settings
2306 // Override the control values preset
2307 //
2308 if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode
2309 {
2310 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2311
2312 // Enable RSSI
2313 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2314 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2315 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2316 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2317 // RSSI reference point
2318 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2319 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2320 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2321 // TOP point
2322 status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ;
2323 status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ;
2324 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2325 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2326 else // High IF
2327 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2328
2329 }
2330 if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode
2331 {
2332 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2333
2334 // Enable RSSI
2335 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2336 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2337 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2338 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2339 // RSSI reference point
2340 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ;
2341 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ;
2342 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2343 // TOP point
2344 status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ;
2345 status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ;
2346
2347 status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ;
2348 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero
2349 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2350 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2351 else // High IF
2352 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2353 }
2354 if (Tuner->Mod_Type == MXL_QAM) // QAM Mode
2355 {
2356 Tuner->Mode = MXL_DIGITAL_MODE;
2357
2358 //Tuner->AGC_Mode = 1 ; // Single AGC Mode
2359
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2360 // Disable RSSI //change here for v2.6.5
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2361 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2362 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2363 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2364 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2365
2366 // RSSI reference point
2367 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2368 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2369 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
2370
2371 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5
2372
2373 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2374 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2375 else // High IF
2376 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2377 }
2378 if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode
2379 {
2380 //Tuner->Mode = MXL_DIGITAL_MODE ;
2381 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2382
2383 // Disable RSSI
2384 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2385 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2386 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2387 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2388
2389 status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3
2390 status += MXL_ControlWrite(Tuner, AGC_RF, 15) ;
2391
2392 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2393 }
2394
2395 if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7
2396 {
2397 //Tuner->Mode = MXL_ANALOG_MODE;
2398
2399 // Enable RSSI
2400 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2401 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2402 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2403 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2404
2405 // RSSI reference point
2406 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2407 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2408 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
2409
2410 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
2411
2412 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2413 }
2414
2415 // RSSI disable
2416 if(Tuner->EN_RSSI==0)
2417 {
2418 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2419 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2420 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2421 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2422 }
2423
2424 return status ;
2425}
2426
2427///////////////////////////////////////////////////////////////////////////////
2428// //
2429// Function: MXL_IFSynthInit //
2430// //
2431// Description: Tuner IF Synthesizer related register initialization //
2432// //
2433// Globals: //
2434// NONE //
2435// //
2436// Functions used: //
2437// Tuner_struct: structure defined at higher level //
2438// //
2439// Inputs: //
2440// Tuner : Tuner structure defined at higher level //
2441// //
2442// Outputs: //
2443// Tuner //
2444// //
2445// Return: //
2446// 0 : Successful //
2447// > 0 : Failed //
2448// //
2449///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2450u16 MXL_IFSynthInit(Tuner_struct * Tuner)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2451{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2452 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2453 // Declare Local Variables
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2454 u32 Fref = 0 ;
2455 u32 Kdbl, intModVal ;
2456 u32 fracModVal ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2457 Kdbl = 2 ;
2458
2459 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL)
2460 Kdbl = 2 ;
2461 if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL)
2462 Kdbl = 1 ;
2463
2464 //
2465 // IF Synthesizer Control
2466 //
2467 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode
2468 {
2469 if (Tuner->IF_LO == 41000000UL) {
2470 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2471 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2472 Fref = 328000000UL ;
2473 }
2474 if (Tuner->IF_LO == 47000000UL) {
2475 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2476 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2477 Fref = 376000000UL ;
2478 }
2479 if (Tuner->IF_LO == 54000000UL) {
2480 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2481 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2482 Fref = 324000000UL ;
2483 }
2484 if (Tuner->IF_LO == 60000000UL) {
2485 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2486 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2487 Fref = 360000000UL ;
2488 }
2489 if (Tuner->IF_LO == 39250000UL) {
2490 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2491 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2492 Fref = 314000000UL ;
2493 }
2494 if (Tuner->IF_LO == 39650000UL) {
2495 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2496 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2497 Fref = 317200000UL ;
2498 }
2499 if (Tuner->IF_LO == 40150000UL) {
2500 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2501 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2502 Fref = 321200000UL ;
2503 }
2504 if (Tuner->IF_LO == 40650000UL) {
2505 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2506 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2507 Fref = 325200000UL ;
2508 }
2509 }
2510
2511 if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0))
2512 {
2513 if (Tuner->IF_LO == 57000000UL) {
2514 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2515 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2516 Fref = 342000000UL ;
2517 }
2518 if (Tuner->IF_LO == 44000000UL) {
2519 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2520 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2521 Fref = 352000000UL ;
2522 }
2523 if (Tuner->IF_LO == 43750000UL) {
2524 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2525 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2526 Fref = 350000000UL ;
2527 }
2528 if (Tuner->IF_LO == 36650000UL) {
2529 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2530 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2531 Fref = 366500000UL ;
2532 }
2533 if (Tuner->IF_LO == 36150000UL) {
2534 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2535 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2536 Fref = 361500000UL ;
2537 }
2538 if (Tuner->IF_LO == 36000000UL) {
2539 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2540 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2541 Fref = 360000000UL ;
2542 }
2543 if (Tuner->IF_LO == 35250000UL) {
2544 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2545 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2546 Fref = 352500000UL ;
2547 }
2548 if (Tuner->IF_LO == 34750000UL) {
2549 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2550 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2551 Fref = 347500000UL ;
2552 }
2553 if (Tuner->IF_LO == 6280000UL) {
2554 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2555 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2556 Fref = 376800000UL ;
2557 }
2558 if (Tuner->IF_LO == 5000000UL) {
2559 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2560 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2561 Fref = 360000000UL ;
2562 }
2563 if (Tuner->IF_LO == 4500000UL) {
2564 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2565 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2566 Fref = 360000000UL ;
2567 }
2568 if (Tuner->IF_LO == 4570000UL) {
2569 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2570 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2571 Fref = 365600000UL ;
2572 }
2573 if (Tuner->IF_LO == 4000000UL) {
2574 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ;
2575 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2576 Fref = 360000000UL ;
2577 }
2578 if (Tuner->IF_LO == 57400000UL)
2579 {
2580 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2581 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2582 Fref = 344400000UL ;
2583 }
2584 if (Tuner->IF_LO == 44400000UL)
2585 {
2586 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2587 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2588 Fref = 355200000UL ;
2589 }
2590 if (Tuner->IF_LO == 44150000UL)
2591 {
2592 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2593 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2594 Fref = 353200000UL ;
2595 }
2596 if (Tuner->IF_LO == 37050000UL)
2597 {
2598 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2599 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2600 Fref = 370500000UL ;
2601 }
2602 if (Tuner->IF_LO == 36550000UL)
2603 {
2604 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2605 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2606 Fref = 365500000UL ;
2607 }
2608 if (Tuner->IF_LO == 36125000UL) {
2609 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2610 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2611 Fref = 361250000UL ;
2612 }
2613 if (Tuner->IF_LO == 6000000UL) {
2614 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2615 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2616 Fref = 360000000UL ;
2617 }
2618 if (Tuner->IF_LO == 5400000UL)
2619 {
2620 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2621 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2622 Fref = 324000000UL ;
2623 }
2624 if (Tuner->IF_LO == 5380000UL) {
2625 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2626 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2627 Fref = 322800000UL ;
2628 }
2629 if (Tuner->IF_LO == 5200000UL) {
2630 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2631 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2632 Fref = 374400000UL ;
2633 }
2634 if (Tuner->IF_LO == 4900000UL)
2635 {
2636 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2637 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2638 Fref = 352800000UL ;
2639 }
2640 if (Tuner->IF_LO == 4400000UL)
2641 {
2642 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2643 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2644 Fref = 352000000UL ;
2645 }
2646 if (Tuner->IF_LO == 4063000UL) //add for 2.6.8
2647 {
2648 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ;
2649 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2650 Fref = 365670000UL ;
2651 }
2652 }
2653 // CHCAL_INT_MOD_IF
2654 // CHCAL_FRAC_MOD_IF
2655 intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ;
2656 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ;
2657
2658 fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal);
2659 fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ;
2660 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ;
2661
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2662 return status ;
2663}
2664
2665///////////////////////////////////////////////////////////////////////////////
2666// //
2667// Function: MXL_GetXtalInt //
2668// //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2669// Description: return the Crystal Integration Value for //
2670// TG_VCO_BIAS calculation //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2671// //
2672// Globals: //
2673// NONE //
2674// //
2675// Functions used: //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2676// NONE //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2677// //
2678// Inputs: //
2679// Crystal Frequency Value in Hz //
2680// //
2681// Outputs: //
2682// Calculated Crystal Frequency Integration Value //
2683// //
2684// Return: //
2685// 0 : Successful //
2686// > 0 : Failed //
2687// //
2688///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2689u32 MXL_GetXtalInt(u32 Xtal_Freq)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2690{
2691 if ((Xtal_Freq % 1000000) == 0)
2692 return (Xtal_Freq / 10000) ;
2693 else
2694 return (((Xtal_Freq / 1000000) + 1)*100) ;
2695}
2696
2697///////////////////////////////////////////////////////////////////////////////
2698// //
2699// Function: MXL5005_TuneRF //
2700// //
2701// Description: Set control names to tune to requested RF_IN frequency //
2702// //
2703// Globals: //
2704// None //
2705// //
2706// Functions used: //
2707// MXL_SynthRFTGLO_Calc //
2708// MXL5005_ControlWrite //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2709// MXL_GetXtalInt //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2710// //
2711// Inputs: //
2712// Tuner : Tuner structure defined at higher level //
2713// //
2714// Outputs: //
2715// Tuner //
2716// //
2717// Return: //
2718// 0 : Successful //
2719// 1 : Unsuccessful //
2720///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2721u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2722{
2723 // Declare Local Variables
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2724 u16 status = 0 ;
2725 u32 divider_val, E3, E4, E5, E5A ;
2726 u32 Fmax, Fmin, FmaxBin, FminBin ;
2727 u32 Kdbl_RF = 2;
2728 u32 tg_divval ;
2729 u32 tg_lo ;
2730 u32 Xtal_Int ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2731
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]2732 u32 Fref_TG;
2733 u32 Fvco;
2734// u32 temp;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]2735
2736
2737 Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ;
2738
2739 Tuner->RF_IN = RF_Freq ;
2740
2741 MXL_SynthRFTGLO_Calc( Tuner ) ;
2742
2743 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL)
2744 Kdbl_RF = 2 ;
2745 if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000)
2746 Kdbl_RF = 1 ;
2747
2748 //
2749 // Downconverter Controls
2750 //
2751 // Look-Up Table Implementation for:
2752 // DN_POLY
2753 // DN_RFGAIN
2754 // DN_CAP_RFLPF
2755 // DN_EN_VHFUHFBAR
2756 // DN_GAIN_ADJUST
2757 // Change the boundary reference from RF_IN to RF_LO
2758 if (Tuner->RF_LO < 40000000UL) {
2759 return -1;
2760 }
2761 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
2762 // Look-Up Table implementation
2763 status += MXL_ControlWrite(Tuner, DN_POLY, 2) ;
2764 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
2765 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ;
2766 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
2767 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
2768 }
2769 if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
2770 // Look-Up Table implementation
2771 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2772 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
2773 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ;
2774 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
2775 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
2776 }
2777 if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
2778 // Look-Up Table implementation
2779 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2780 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
2781 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ;
2782 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
2783 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
2784 }
2785 if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
2786 // Look-Up Table implementation
2787 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2788 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
2789 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ;
2790 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
2791 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
2792 }
2793 if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
2794 // Look-Up Table implementation
2795 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2796 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
2797 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
2798 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
2799 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
2800 }
2801 if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) {
2802 // Look-Up Table implementation
2803 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2804 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ;
2805 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
2806 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
2807 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
2808 }
2809 if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) {
2810 // Look-Up Table implementation
2811 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
2812 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ;
2813 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
2814 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
2815 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
2816 }
2817 if (Tuner->RF_LO > 900000000UL) {
2818 return -1;
2819 }
2820 // DN_IQTNBUF_AMP
2821 // DN_IQTNGNBFBIAS_BST
2822 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
2823 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2824 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2825 }
2826 if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
2827 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2828 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2829 }
2830 if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
2831 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2832 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2833 }
2834 if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
2835 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2836 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2837 }
2838 if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
2839 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2840 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2841 }
2842 if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) {
2843 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2844 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2845 }
2846 if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) {
2847 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2848 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2849 }
2850 if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) {
2851 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2852 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2853 }
2854 if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) {
2855 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2856 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2857 }
2858 if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) {
2859 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2860 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2861 }
2862 if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) {
2863 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2864 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2865 }
2866 if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) {
2867 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2868 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2869 }
2870 if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) {
2871 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2872 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2873 }
2874 if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) {
2875 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
2876 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
2877 }
2878 if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) {
2879 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
2880 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
2881 }
2882 if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) {
2883 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
2884 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
2885 }
2886
2887 //
2888 // Set RF Synth and LO Path Control
2889 //
2890 // Look-Up table implementation for:
2891 // RFSYN_EN_OUTMUX
2892 // RFSYN_SEL_VCO_OUT
2893 // RFSYN_SEL_VCO_HI
2894 // RFSYN_SEL_DIVM
2895 // RFSYN_RF_DIV_BIAS
2896 // DN_SEL_FREQ
2897 //
2898 // Set divider_val, Fmax, Fmix to use in Equations
2899 FminBin = 28000000UL ;
2900 FmaxBin = 42500000UL ;
2901 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) {
2902 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
2903 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
2904 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
2905 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2906 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2907 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
2908 divider_val = 64 ;
2909 Fmax = FmaxBin ;
2910 Fmin = FminBin ;
2911 }
2912 FminBin = 42500000UL ;
2913 FmaxBin = 56000000UL ;
2914 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2915 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
2916 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
2917 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
2918 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2919 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2920 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
2921 divider_val = 64 ;
2922 Fmax = FmaxBin ;
2923 Fmin = FminBin ;
2924 }
2925 FminBin = 56000000UL ;
2926 FmaxBin = 85000000UL ;
2927 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2928 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
2929 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
2930 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
2931 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2932 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2933 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
2934 divider_val = 32 ;
2935 Fmax = FmaxBin ;
2936 Fmin = FminBin ;
2937 }
2938 FminBin = 85000000UL ;
2939 FmaxBin = 112000000UL ;
2940 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2941 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
2942 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
2943 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
2944 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2945 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2946 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
2947 divider_val = 32 ;
2948 Fmax = FmaxBin ;
2949 Fmin = FminBin ;
2950 }
2951 FminBin = 112000000UL ;
2952 FmaxBin = 170000000UL ;
2953 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2954 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
2955 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
2956 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
2957 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2958 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2959 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
2960 divider_val = 16 ;
2961 Fmax = FmaxBin ;
2962 Fmin = FminBin ;
2963 }
2964 FminBin = 170000000UL ;
2965 FmaxBin = 225000000UL ;
2966 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2967 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
2968 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
2969 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
2970 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2971 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2972 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
2973 divider_val = 16 ;
2974 Fmax = FmaxBin ;
2975 Fmin = FminBin ;
2976 }
2977 FminBin = 225000000UL ;
2978 FmaxBin = 300000000UL ;
2979 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2980 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
2981 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
2982 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
2983 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2984 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2985 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ;
2986 divider_val = 8 ;
2987 Fmax = 340000000UL ;
2988 Fmin = FminBin ;
2989 }
2990 FminBin = 300000000UL ;
2991 FmaxBin = 340000000UL ;
2992 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
2993 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
2994 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
2995 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
2996 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
2997 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
2998 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
2999 divider_val = 8 ;
3000 Fmax = FmaxBin ;
3001 Fmin = 225000000UL ;
3002 }
3003 FminBin = 340000000UL ;
3004 FmaxBin = 450000000UL ;
3005 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3006 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
3007 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
3008 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3009 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3010 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ;
3011 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3012 divider_val = 8 ;
3013 Fmax = FmaxBin ;
3014 Fmin = FminBin ;
3015 }
3016 FminBin = 450000000UL ;
3017 FmaxBin = 680000000UL ;
3018 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3019 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3020 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3021 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3022 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
3023 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3024 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3025 divider_val = 4 ;
3026 Fmax = FmaxBin ;
3027 Fmin = FminBin ;
3028 }
3029 FminBin = 680000000UL ;
3030 FmaxBin = 900000000UL ;
3031 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3032 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3033 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3034 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3035 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
3036 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3037 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3038 divider_val = 4 ;
3039 Fmax = FmaxBin ;
3040 Fmin = FminBin ;
3041 }
3042
3043 // CHCAL_INT_MOD_RF
3044 // CHCAL_FRAC_MOD_RF
3045 // RFSYN_LPF_R
3046 // CHCAL_EN_INT_RF
3047
3048 // Equation E3
3049 // RFSYN_VCO_BIAS
3050 E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
3051 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ;
3052
3053 // Equation E4
3054 // CHCAL_INT_MOD_RF
3055 E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ;
3056 MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ;
3057
3058 // Equation E5
3059 // CHCAL_FRAC_MOD_RF
3060 // CHCAL_EN_INT_RF
3061 E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ;
3062 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
3063
3064 // Equation E5A
3065 // RFSYN_LPF_R
3066 E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
3067 status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ;
3068
3069 // Euqation E5B
3070 // CHCAL_EN_INIT_RF
3071 status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
3072 //if (E5 == 0)
3073 // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1);
3074 //else
3075 // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
3076
3077 //
3078 // Set TG Synth
3079 //
3080 // Look-Up table implementation for:
3081 // TG_LO_DIVVAL
3082 // TG_LO_SELVAL
3083 //
3084 // Set divider_val, Fmax, Fmix to use in Equations
3085 if (Tuner->TG_LO < 33000000UL) {
3086 return -1;
3087 }
3088 FminBin = 33000000UL ;
3089 FmaxBin = 50000000UL ;
3090 if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) {
3091 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ;
3092 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
3093 divider_val = 36 ;
3094 Fmax = FmaxBin ;
3095 Fmin = FminBin ;
3096 }
3097 FminBin = 50000000UL ;
3098 FmaxBin = 67000000UL ;
3099 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3100 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ;
3101 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
3102 divider_val = 24 ;
3103 Fmax = FmaxBin ;
3104 Fmin = FminBin ;
3105 }
3106 FminBin = 67000000UL ;
3107 FmaxBin = 100000000UL ;
3108 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3109 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ;
3110 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3111 divider_val = 18 ;
3112 Fmax = FmaxBin ;
3113 Fmin = FminBin ;
3114 }
3115 FminBin = 100000000UL ;
3116 FmaxBin = 150000000UL ;
3117 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3118 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3119 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3120 divider_val = 12 ;
3121 Fmax = FmaxBin ;
3122 Fmin = FminBin ;
3123 }
3124 FminBin = 150000000UL ;
3125 FmaxBin = 200000000UL ;
3126 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3127 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3128 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3129 divider_val = 8 ;
3130 Fmax = FmaxBin ;
3131 Fmin = FminBin ;
3132 }
3133 FminBin = 200000000UL ;
3134 FmaxBin = 300000000UL ;
3135 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3136 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3137 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
3138 divider_val = 6 ;
3139 Fmax = FmaxBin ;
3140 Fmin = FminBin ;
3141 }
3142 FminBin = 300000000UL ;
3143 FmaxBin = 400000000UL ;
3144 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3145 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3146 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
3147 divider_val = 4 ;
3148 Fmax = FmaxBin ;
3149 Fmin = FminBin ;
3150 }
3151 FminBin = 400000000UL ;
3152 FmaxBin = 600000000UL ;
3153 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3154 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3155 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
3156 divider_val = 3 ;
3157 Fmax = FmaxBin ;
3158 Fmin = FminBin ;
3159 }
3160 FminBin = 600000000UL ;
3161 FmaxBin = 900000000UL ;
3162 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3163 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3164 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
3165 divider_val = 2 ;
3166 Fmax = FmaxBin ;
3167 Fmin = FminBin ;
3168 }
3169
3170 // TG_DIV_VAL
3171 tg_divval = (Tuner->TG_LO*divider_val/100000)
3172 *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ;
3173 status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ;
3174
3175 if (Tuner->TG_LO > 600000000UL)
3176 status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ;
3177
3178 Fmax = 1800000000UL ;
3179 Fmin = 1200000000UL ;
3180
3181
3182
3183 // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
3184 Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
3185
3186 Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
3187
3188 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
3189
3190 //below equation is same as above but much harder to debug.
3191 //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
3192
3193
3194 status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ;
3195
3196
3197
3198 //add for 2.6.5
3199 //Special setting for QAM
3200 if(Tuner ->Mod_Type == MXL_QAM)
3201 {
3202 if(Tuner->RF_IN < 680000000)
3203 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
3204 else
3205 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ;
3206 }
3207
3208
3209 //remove 20.48MHz setting for 2.6.10
3210
3211 //
3212 // Off Chip Tracking Filter Control
3213 //
3214 if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
3215 {
3216 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ;
3217 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ;
3218
3219 status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1
3220 status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2
3221 status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3
3222 }
3223
3224 if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C
3225 {
3226 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ;
3227 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3228
3229 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
3230 {
3231
3232 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3233 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3234 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On
3235 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3236 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3237 }
3238 if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
3239 {
3240 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3241 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3242 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3243 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3244 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3245 }
3246 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
3247 {
3248 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3249 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3250 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3251 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3252 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3253 }
3254 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
3255 {
3256 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3257 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3258 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3259 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3260 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3261 }
3262 if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
3263 {
3264 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3265 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ;
3266 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3267 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3268 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3269 }
3270 if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
3271 {
3272 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3273 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3274 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3275 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3276 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3277 }
3278 if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
3279 {
3280 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3281 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ;
3282 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3283 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3284 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3285 }
3286 if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
3287 {
3288 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3289 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ;
3290 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3291 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3292 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3293 }
3294 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3295 {
3296 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3297 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3298 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3299 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3300 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3301 }
3302 }
3303
3304 if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
3305 {
3306 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3307
3308 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
3309 {
3310
3311 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3312 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3313 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3314 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3315 }
3316 if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
3317 {
3318 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3319 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3320 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
3321 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3322 }
3323 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
3324 {
3325 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3326 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3327 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
3328 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3329 }
3330 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
3331 {
3332 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3333 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3334 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3335 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3336 }
3337 if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
3338 {
3339 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3340 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3341 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3342 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3343 }
3344 if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
3345 {
3346 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3347 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3348 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3349 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3350 }
3351 if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
3352 {
3353 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3354 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3355 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3356 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3357 }
3358 if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
3359 {
3360 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3361 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3362 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3363 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3364 }
3365 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3366 {
3367 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3368 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3369 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3370 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3371 }
3372 }
3373
3374 if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D
3375 {
3376 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3377
3378 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3379 {
3380
3381 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3382 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3383 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3384 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3385 }
3386 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3387 {
3388 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3389 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3390 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3391 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3392 }
3393 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000)
3394 {
3395 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3396 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3397 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3398 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3399 }
3400 if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000)
3401 {
3402 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3403 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3404 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3405 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3406 }
3407 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000)
3408 {
3409 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3410 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3411 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3412 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3413 }
3414 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
3415 {
3416 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3417 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3418 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3419 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3420 }
3421 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000)
3422 {
3423 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3424 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3425 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3426 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3427 }
3428 }
3429
3430
3431 if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3
3432 {
3433 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3434
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3435 // if UHF and terrestrial => Turn off Tracking Filter
3436 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3437 {
3438 // Turn off all the banks
3439 status += MXL_SetGPIO(Tuner, 3, 1) ;
3440 status += MXL_SetGPIO(Tuner, 1, 1) ;
3441 status += MXL_SetGPIO(Tuner, 4, 1) ;
3442 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ;
3443
3444 status += MXL_ControlWrite(Tuner, AGC_IF, 10) ;
3445 }
3446
3447 else // if VHF or cable => Turn on Tracking Filter
3448 {
3449 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000)
3450 {
3451
3452 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3453 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
3454 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3455 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3456 }
3457 if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000)
3458 {
3459 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3460 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
3461 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3462 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3463 }
3464 if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000)
3465 {
3466 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3467 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3468 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On
3469 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3470 }
3471 if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000)
3472 {
3473 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3474 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3475 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3476 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3477 }
3478 if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000)
3479 {
3480 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off
3481 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3482 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
3483 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3484 }
3485 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000)
3486 {
3487 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3488 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3489 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
3490 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3491 }
3492 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000)
3493 {
3494 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On
3495 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3496 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3497 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq
3498 }
3499 if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000)
3500 {
3501 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3502 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3503 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3504 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3505 }
3506 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3507 {
3508 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3509 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3510 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3511 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3512 }
3513 }
3514 }
3515
3516 if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E
3517 {
3518 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3519
3520 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3521 {
3522
3523 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3524 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3525 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3526 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3527 }
3528 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3529 {
3530 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3531 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3532 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3533 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3534 }
3535 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000)
3536 {
3537 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3538 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3539 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3540 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3541 }
3542 if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000)
3543 {
3544 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3545 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3546 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3547 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3548 }
3549 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000)
3550 {
3551 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3552 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3553 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3554 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3555 }
3556 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
3557 {
3558 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3559 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3560 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3561 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3562 }
3563 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000)
3564 {
3565 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3566 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3567 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3568 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3569 }
3570 }
3571
3572 if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F
3573 {
3574 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3575
3576 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000)
3577 {
3578
3579 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3580 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3581 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3582 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3583 }
3584 if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000)
3585 {
3586 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3587 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3588 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3589 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3590 }
3591 if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000)
3592 {
3593 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3594 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3595 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3596 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3597 }
3598 if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000)
3599 {
3600 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3601 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3602 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3603 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3604 }
3605 if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000)
3606 {
3607 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3608 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3609 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3610 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3611 }
3612 if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000)
3613 {
3614 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3615 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3616 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3617 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3618 }
3619 if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000)
3620 {
3621 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3622 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3623 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3624 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3625 }
3626 }
3627
3628 if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
3629 {
3630 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3631
3632 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3633 {
3634
3635 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3636 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3637 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3638 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3639 }
3640 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3641 {
3642 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3643 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3644 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3645 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3646 }
3647 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000)
3648 {
3649 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3650 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3651 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3652 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3653 }
3654 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
3655 {
3656 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3657 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3658 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3659 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3660 }
3661 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000)
3662 {
3663 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3664 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3665 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3666 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3667 }
3668 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000)
3669 {
3670 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3671 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3672 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3673 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3674 }
3675 if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000)
3676 {
3677 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3678 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3679 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3680 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3681 }
3682 }
3683
3684 if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
3685 {
3686 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3687
3688 if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000)
3689 {
3690
3691 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3692 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3693 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3694 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3695 }
3696 if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000)
3697 {
3698 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3699 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3700 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3701 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3702 }
3703 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000)
3704 {
3705 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3706 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3707 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3708 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3709 }
3710 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
3711 {
3712 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3713 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3714 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3715 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3716 }
3717 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11
3718 {
3719 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3720 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
3721 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
3722 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3723 }
3724 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
3725 {
3726 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3727 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3728 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3729 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3730 }
3731 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000)
3732 {
3733 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3734 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3735 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3736 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3737 }
3738 if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000)
3739 {
3740 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3741 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3742 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3743 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3744 }
3745 }
3746
3747 if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8
3748 {
3749 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3750
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3751 // if UHF and terrestrial=> Turn off Tracking Filter
3752 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3753 {
3754 // Turn off all the banks
3755 status += MXL_SetGPIO(Tuner, 3, 1) ;
3756 status += MXL_SetGPIO(Tuner, 1, 1) ;
3757 status += MXL_SetGPIO(Tuner, 4, 1) ;
3758 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ;
3759
3760 //2.6.12
3761 //Turn on RSSI
3762 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
3763 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
3764 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
3765 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
3766
3767 // RSSI reference point
3768 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
3769 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
3770 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
3771
3772
3773 //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on
3774
3775 //following parameter is from analog OTA mode, can be change to seek better performance
3776 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
3777 }
3778
3779 else //if VHF or Cable => Turn on Tracking Filter
3780 {
3781 //2.6.12
3782 //Turn off RSSI
3783 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
3784
3785 //change back from above condition
3786 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ;
3787
3788
3789 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3790 {
3791
3792 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3793 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3794 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3795 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3796 }
3797 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3798 {
3799 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3800 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3801 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3802 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3803 }
3804 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000)
3805 {
3806 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3807 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3808 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3809 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3810 }
3811 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
3812 {
3813 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3814 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3815 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3816 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3817 }
3818 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000)
3819 {
3820 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3821 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3822 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3823 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3824 }
3825 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000)
3826 {
3827 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3828 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3829 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3830 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3831 }
3832 if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000)
3833 {
3834 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3835 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3836 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3837 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3838 }
3839 }
3840 }
3841 return status ;
3842}
3843
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3844u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3845{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3846 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3847
3848 if (GPIO_Num == 1)
3849 status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ;
3850 // GPIO2 is not available
3851 if (GPIO_Num == 3)
3852 {
3853 if (GPIO_Val == 1) {
3854 status += MXL_ControlWrite(Tuner, GPIO_3, 0) ;
3855 status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ;
3856 }
3857 if (GPIO_Val == 0) {
3858 status += MXL_ControlWrite(Tuner, GPIO_3, 1) ;
3859 status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ;
3860 }
3861 if (GPIO_Val == 3) { // tri-state
3862 status += MXL_ControlWrite(Tuner, GPIO_3, 0) ;
3863 status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ;
3864 }
3865 }
3866 if (GPIO_Num == 4)
3867 {
3868 if (GPIO_Val == 1) {
3869 status += MXL_ControlWrite(Tuner, GPIO_4, 0) ;
3870 status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ;
3871 }
3872 if (GPIO_Val == 0) {
3873 status += MXL_ControlWrite(Tuner, GPIO_4, 1) ;
3874 status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ;
3875 }
3876 if (GPIO_Val == 3) { // tri-state
3877 status += MXL_ControlWrite(Tuner, GPIO_4, 0) ;
3878 status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ;
3879 }
3880 }
3881
3882 return status ;
3883}
3884
3885///////////////////////////////////////////////////////////////////////////////
3886// //
3887// Function: MXL_ControlWrite //
3888// //
3889// Description: Update control name value //
3890// //
3891// Globals: //
3892// NONE //
3893// //
3894// Functions used: //
3895// MXL_ControlWrite( Tuner, controlName, value, Group ) //
3896// //
3897// Inputs: //
3898// Tuner : Tuner structure //
3899// ControlName : Control name to be updated //
3900// value : Value to be written //
3901// //
3902// Outputs: //
3903// Tuner : Tuner structure defined at higher level //
3904// //
3905// Return: //
3906// 0 : Successful write //
3907// >0 : Value exceed maximum allowed for control number //
3908// //
3909///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3910u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3911{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3912 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3913 // Will write ALL Matching Control Name
3914 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control
3915 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control
3916#ifdef _MXL_INTERNAL
3917 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control
3918#endif
3919
3920 return status ;
3921}
3922
3923///////////////////////////////////////////////////////////////////////////////
3924// //
3925// Function: MXL_ControlWrite //
3926// //
3927// Description: Update control name value //
3928// //
3929// Globals: //
3930// NONE //
3931// //
3932// Functions used: //
3933// strcmp //
3934// //
3935// Inputs: //
3936// Tuner_struct: structure defined at higher level //
3937// ControlName : Control Name //
3938// value : Value Assigned to Control Name //
3939// controlGroup : Control Register Group //
3940// //
3941// Outputs: //
3942// NONE //
3943// //
3944// Return: //
3945// 0 : Successful write //
3946// 1 : Value exceed maximum allowed for control name //
3947// 2 : Control name not found //
3948// //
3949///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3950u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3951{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3952 u16 i, j, k ;
3953 u32 highLimit ;
3954 u32 ctrlVal ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3955
3956 if( controlGroup == 1) // Initial Control
3957 {
3958 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
3959 {
3960 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
3961 { // find the control Name
3962 highLimit = 1 << Tuner->Init_Ctrl[i].size ;
3963 if ( value < highLimit)
3964 {
3965 for( j=0; j<Tuner->Init_Ctrl[i].size; j++)
3966 {
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3967 Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3968 // change the register map accordingly
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3969 MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]),
3970 (u8)(Tuner->Init_Ctrl[i].bit[j]),
3971 (u8)((value>>j) & 0x01) ) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3972 }
3973 ctrlVal = 0 ;
3974 for(k=0; k<Tuner->Init_Ctrl[i].size; k++)
3975 {
3976 ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ;
3977 }
3978 }
3979 else
3980 {
3981 return -1 ;
3982 }
3983 }
3984 }
3985 }
3986 if ( controlGroup == 2) // Chan change Control
3987 {
3988 for (i=0; i<Tuner->CH_Ctrl_Num; i++)
3989 {
3990 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
3991 { // find the control Name
3992 highLimit = 1 << Tuner->CH_Ctrl[i].size ;
3993 if ( value < highLimit)
3994 {
3995 for( j=0; j<Tuner->CH_Ctrl[i].size; j++)
3996 {
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3997 Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]3998 // change the register map accordingly
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]3999 MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]),
4000 (u8)(Tuner->CH_Ctrl[i].bit[j]),
4001 (u8)((value>>j) & 0x01) ) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4002 }
4003 ctrlVal = 0 ;
4004 for(k=0; k<Tuner->CH_Ctrl[i].size; k++)
4005 {
4006 ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ;
4007 }
4008 }
4009 else
4010 {
4011 return -1 ;
4012 }
4013 }
4014 }
4015 }
4016#ifdef _MXL_INTERNAL
4017 if ( controlGroup == 3) // Maxlinear Control
4018 {
4019 for (i=0; i<Tuner->MXL_Ctrl_Num; i++)
4020 {
4021 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4022 { // find the control Name
4023 highLimit = (1 << Tuner->MXL_Ctrl[i].size) ;
4024 if ( value < highLimit)
4025 {
4026 for( j=0; j<Tuner->MXL_Ctrl[i].size; j++)
4027 {
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4028 Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4029 // change the register map accordingly
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4030 MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]),
4031 (u8)(Tuner->MXL_Ctrl[i].bit[j]),
4032 (u8)((value>>j) & 0x01) ) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4033 }
4034 ctrlVal = 0 ;
4035 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++)
4036 {
4037 ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ;
4038 }
4039 }
4040 else
4041 {
4042 return -1 ;
4043 }
4044 }
4045 }
4046 }
4047#endif
4048 return 0 ; // successful return
4049}
4050
4051///////////////////////////////////////////////////////////////////////////////
4052// //
4053// Function: MXL_RegWrite //
4054// //
4055// Description: Update tuner register value //
4056// //
4057// Globals: //
4058// NONE //
4059// //
4060// Functions used: //
4061// NONE //
4062// //
4063// Inputs: //
4064// Tuner_struct: structure defined at higher level //
4065// RegNum : Register address to be assigned a value //
4066// RegVal : Register value to write //
4067// //
4068// Outputs: //
4069// NONE //
4070// //
4071// Return: //
4072// 0 : Successful write //
4073// -1 : Invalid Register Address //
4074// //
4075///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4076u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4077{
4078 int i ;
4079
4080 for (i=0; i<104; i++)
4081 {
4082 if (RegNum == Tuner->TunerRegs[i].Reg_Num )
4083 {
4084 Tuner->TunerRegs[i].Reg_Val = RegVal ;
4085 return 0 ;
4086 }
4087 }
4088
4089 return 1 ;
4090}
4091
4092///////////////////////////////////////////////////////////////////////////////
4093// //
4094// Function: MXL_RegRead //
4095// //
4096// Description: Retrieve tuner register value //
4097// //
4098// Globals: //
4099// NONE //
4100// //
4101// Functions used: //
4102// NONE //
4103// //
4104// Inputs: //
4105// Tuner_struct: structure defined at higher level //
4106// RegNum : Register address to be assigned a value //
4107// //
4108// Outputs: //
4109// RegVal : Retrieved register value //
4110// //
4111// Return: //
4112// 0 : Successful read //
4113// -1 : Invalid Register Address //
4114// //
4115///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4116u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4117{
4118 int i ;
4119
4120 for (i=0; i<104; i++)
4121 {
4122 if (RegNum == Tuner->TunerRegs[i].Reg_Num )
4123 {
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4124 *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4125 return 0 ;
4126 }
4127 }
4128
4129 return 1 ;
4130}
4131
4132///////////////////////////////////////////////////////////////////////////////
4133// //
4134// Function: MXL_ControlRead //
4135// //
4136// Description: Retrieve the control value based on the control name //
4137// //
4138// Globals: //
4139// NONE //
4140// //
4141// Inputs: //
4142// Tuner_struct : structure defined at higher level //
4143// ControlName : Control Name //
4144// //
4145// Outputs: //
4146// value : returned control value //
4147// //
4148// Return: //
4149// 0 : Successful read //
4150// -1 : Invalid control name //
4151// //
4152///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4153u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4154{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4155 u32 ctrlVal ;
4156 u16 i, k ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4157
4158 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4159 {
4160 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4161 {
4162 ctrlVal = 0 ;
4163 for(k=0; k<Tuner->Init_Ctrl[i].size; k++)
4164 ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ;
4165 *value = ctrlVal ;
4166 return 0 ;
4167 }
4168 }
4169 for (i=0; i<Tuner->CH_Ctrl_Num ; i++)
4170 {
4171 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4172 {
4173 ctrlVal = 0 ;
4174 for(k=0; k<Tuner->CH_Ctrl[i].size; k++)
4175 ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ;
4176 *value = ctrlVal ;
4177 return 0 ;
4178 }
4179 }
4180
4181#ifdef _MXL_INTERNAL
4182 for (i=0; i<Tuner->MXL_Ctrl_Num ; i++)
4183 {
4184 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4185 {
4186 ctrlVal = 0 ;
4187 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++)
4188 ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<<k) ;
4189 *value = ctrlVal ;
4190 return 0 ;
4191 }
4192 }
4193#endif
4194 return 1 ;
4195}
4196
4197///////////////////////////////////////////////////////////////////////////////
4198// //
4199// Function: MXL_ControlRegRead //
4200// //
4201// Description: Retrieve the register addresses and count related to a //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4202// a specific control name //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4203// //
4204// Globals: //
4205// NONE //
4206// //
4207// Inputs: //
4208// Tuner_struct : structure defined at higher level //
4209// ControlName : Control Name //
4210// //
4211// Outputs: //
4212// RegNum : returned register address array //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4213// count : returned register count related to a control //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4214// //
4215// Return: //
4216// 0 : Successful read //
4217// -1 : Invalid control name //
4218// //
4219///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4220u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4221{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4222 u16 i, j, k ;
4223 u16 Count ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4224
4225 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4226 {
4227 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4228 {
4229 Count = 1 ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4230 RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4231
4232 for(k=1; k<Tuner->Init_Ctrl[i].size; k++)
4233 {
4234 for (j= 0; j<Count; j++)
4235 {
4236 if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j])
4237 {
4238 Count ++ ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4239 RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4240 }
4241 }
4242
4243 }
4244 *count = Count ;
4245 return 0 ;
4246 }
4247 }
4248 for (i=0; i<Tuner->CH_Ctrl_Num ; i++)
4249 {
4250 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4251 {
4252 Count = 1 ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4253 RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4254
4255 for(k=1; k<Tuner->CH_Ctrl[i].size; k++)
4256 {
4257 for (j= 0; j<Count; j++)
4258 {
4259 if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j])
4260 {
4261 Count ++ ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4262 RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4263 }
4264 }
4265 }
4266 *count = Count ;
4267 return 0 ;
4268 }
4269 }
4270#ifdef _MXL_INTERNAL
4271 for (i=0; i<Tuner->MXL_Ctrl_Num ; i++)
4272 {
4273 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4274 {
4275 Count = 1 ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4276 RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4277
4278 for(k=1; k<Tuner->MXL_Ctrl[i].size; k++)
4279 {
4280 for (j= 0; j<Count; j++)
4281 {
4282 if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j])
4283 {
4284 Count ++ ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4285 RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4286 }
4287 }
4288 }
4289 *count = Count ;
4290 return 0 ;
4291 }
4292 }
4293#endif
4294 *count = 0 ;
4295 return 1 ;
4296}
4297
4298///////////////////////////////////////////////////////////////////////////////
4299// //
4300// Function: MXL_RegWriteBit //
4301// //
4302// Description: Write a register for specified register address, //
4303// register bit and register bit value //
4304// //
4305// Globals: //
4306// NONE //
4307// //
4308// Inputs: //
4309// Tuner_struct : structure defined at higher level //
4310// address : register address //
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4311// bit : register bit number //
4312// bitVal : register bit value //
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4313// //
4314// Outputs: //
4315// NONE //
4316// //
4317// Return: //
4318// NONE //
4319// //
4320///////////////////////////////////////////////////////////////////////////////
4321
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4322void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4323{
4324 int i ;
4325
4326 // Declare Local Constants
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4327 const u8 AND_MAP[8] = {
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4328 0xFE, 0xFD, 0xFB, 0xF7,
4329 0xEF, 0xDF, 0xBF, 0x7F } ;
4330
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4331 const u8 OR_MAP[8] = {
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4332 0x01, 0x02, 0x04, 0x08,
4333 0x10, 0x20, 0x40, 0x80 } ;
4334
4335 for(i=0; i<Tuner->TunerRegs_Num; i++) {
4336 if ( Tuner->TunerRegs[i].Reg_Num == address ) {
4337 if (bitVal)
4338 Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ;
4339 else
4340 Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ;
4341 break ;
4342 }
4343 }
4344} ;
4345
4346
4347///////////////////////////////////////////////////////////////////////////////
4348// //
4349// Function: MXL_Ceiling //
4350// //
4351// Description: Complete to closest increment of resolution //
4352// //
4353// Globals: //
4354// NONE //
4355// //
4356// Functions used: //
4357// NONE //
4358// //
4359// Inputs: //
4360// value : Input number to compute //
4361// resolution : Increment step //
4362// //
4363// Outputs: //
4364// NONE //
4365// //
4366// Return: //
4367// Computed value //
4368// //
4369///////////////////////////////////////////////////////////////////////////////
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4370u32 MXL_Ceiling( u32 value, u32 resolution )
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4371{
4372 return (value/resolution + (value%resolution > 0 ? 1 : 0)) ;
4373};
4374
4375//
4376// Retrieve the Initialzation Registers
4377//
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4378u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4379{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4380 u16 status = 0;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4381 int i ;
4382
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4383 u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4384 76, 77, 91, 134, 135, 137, 147,
4385 156, 166, 167, 168, 25 } ;
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4386 *count = sizeof(RegAddr) / sizeof(u8) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4387
4388 status += MXL_BlockInit(Tuner) ;
4389
4390 for (i=0 ; i< *count; i++)
4391 {
4392 RegNum[i] = RegAddr[i] ;
4393 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4394 }
4395
4396 return status ;
4397}
4398
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4399u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4400{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4401 u16 status = 0;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4402 int i ;
4403
4404//add 77, 166, 167, 168 register for 2.6.12
4405#ifdef _MXL_PRODUCTION
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4406 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4407 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4408#else
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4409 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4410 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4411 //u8 RegAddr[171];
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4412 //for (i=0; i<=170; i++)
4413 // RegAddr[i] = i;
4414#endif
4415
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4416 *count = sizeof(RegAddr) / sizeof(u8) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4417
4418 for (i=0 ; i< *count; i++)
4419 {
4420 RegNum[i] = RegAddr[i] ;
4421 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4422 }
4423
4424 return status ;
4425
4426}
4427
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4428u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4429{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4430 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4431 int i ;
4432
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4433 u8 RegAddr[] = {43, 136} ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4434
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4435 *count = sizeof(RegAddr) / sizeof(u8) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4436
4437 for (i=0; i<*count; i++)
4438 {
4439 RegNum[i] = RegAddr[i] ;
4440 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4441 }
4442 return status ;
4443
4444}
4445
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4446u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4447{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4448 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4449 int i ;
4450
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4451 u8 RegAddr[] = {138} ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4452
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4453 *count = sizeof(RegAddr) / sizeof(u8) ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4454
4455 for (i=0; i<*count; i++)
4456 {
4457 RegNum[i] = RegAddr[i] ;
4458 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4459 }
4460 return status ;
4461
4462}
4463
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4464u16 MXL_GetMasterControl(u8 *MasterReg, int state)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4465{
4466 if (state == 1) // Load_Start
4467 *MasterReg = 0xF3 ;
4468 if (state == 2) // Power_Down
4469 *MasterReg = 0x41 ;
4470 if (state == 3) // Synth_Reset
4471 *MasterReg = 0xB1 ;
4472 if (state == 4) // Seq_Off
4473 *MasterReg = 0xF1 ;
4474
4475 return 0 ;
4476}
4477
4478#ifdef _MXL_PRODUCTION
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4479u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4480{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4481 u16 status = 0 ;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4482
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4483 if (VCO_Range == 1) {
4484 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4485 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4486 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4487 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4488 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4489 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4490 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4491 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4492 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4493 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4494 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56);
4495 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224);
4496 }
4497 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4498 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4499 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4500 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4501 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ;
4502 }
4503 if (Tuner->Mode == 1) // Digital Mode {
4504 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4505 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4506 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4507 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ;
4508 }
4509 }
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4510
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4511 if (VCO_Range == 2) {
4512 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4513 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4514 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4515 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4516 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4517 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4518 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4519 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4520 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4521 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41);
4522 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4523 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4524 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4525 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4526 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4527 }
4528 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4529 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4530 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4531 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4532 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4533 }
4534 if (Tuner->Mode == 1) // Digital Mode {
4535 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4536 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4537 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41);
4538 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384);
4539 }
4540 }
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4541
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4542 if (VCO_Range == 3) {
4543 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4544 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4545 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4546 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4547 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4548 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4549 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4550 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4551 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4552 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4553 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4554 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4555 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4556 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44);
4557 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670);
4558 }
4559 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4560 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4561 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4562 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44);
4563 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670);
4564 }
4565 if (Tuner->Mode == 1) // Digital Mode {
4566 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4567 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4568 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4569 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760);
4570 }
4571 }
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4572
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4573 if (VCO_Range == 4) {
4574 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4575 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4576 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4577 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4578 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4579 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4580 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4581 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4582 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4583 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4584 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4585 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4586 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4587 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4588 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4589 }
4590 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4591 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4592 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4593 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4594 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4595 }
4596 if (Tuner->Mode == 1) // Digital Mode {
4597 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4598 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4599 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4600 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992);
4601 }
4602 }
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4603
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4604 return status;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4605}
4606
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4607u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis)
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4608{
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4609 u16 status = 0;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4610
4611 if (Hystersis == 1)
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4612 status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1);
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4613
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4614 return status;
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4615}
Steven Totha8214d42008-05-01 05:02:58 -0300[diff] [blame^]4616
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]4617#endif
4618