| Jay Cliburn | f3cc28c | 2007-02-08 10:42:37 -0500 | [diff] [blame] | 1 | /* | 
|  | 2 | * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. | 
|  | 3 | * Copyright(c) 2006 Chris Snook <csnook@redhat.com> | 
|  | 4 | * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> | 
|  | 5 | * | 
|  | 6 | * Derived from Intel e1000 driver | 
|  | 7 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | 
|  | 8 | * | 
|  | 9 | * This program is free software; you can redistribute it and/or modify it | 
|  | 10 | * under the terms of the GNU General Public License as published by the Free | 
|  | 11 | * Software Foundation; either version 2 of the License, or (at your option) | 
|  | 12 | * any later version. | 
|  | 13 | * | 
|  | 14 | * This program is distributed in the hope that it will be useful, but WITHOUT | 
|  | 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 
|  | 16 | * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for | 
|  | 17 | * more details. | 
|  | 18 | * | 
|  | 19 | * You should have received a copy of the GNU General Public License along with | 
|  | 20 | * this program; if not, write to the Free Software Foundation, Inc., 59 | 
|  | 21 | * Temple Place - Suite 330, Boston, MA  02111-1307, USA. | 
|  | 22 | */ | 
|  | 23 |  | 
|  | 24 | #ifndef _ATL1_H_ | 
|  | 25 | #define _ATL1_H_ | 
|  | 26 |  | 
|  | 27 | #include <linux/types.h> | 
|  | 28 | #include <linux/if_vlan.h> | 
|  | 29 |  | 
|  | 30 | #include "atl1_hw.h" | 
|  | 31 |  | 
|  | 32 | /* function prototypes needed by multiple files */ | 
|  | 33 | s32 atl1_up(struct atl1_adapter *adapter); | 
|  | 34 | void atl1_down(struct atl1_adapter *adapter); | 
|  | 35 | int atl1_reset(struct atl1_adapter *adapter); | 
|  | 36 | s32 atl1_setup_ring_resources(struct atl1_adapter *adapter); | 
|  | 37 | void atl1_free_ring_resources(struct atl1_adapter *adapter); | 
|  | 38 |  | 
|  | 39 | extern char atl1_driver_name[]; | 
|  | 40 | extern char atl1_driver_version[]; | 
|  | 41 | extern const struct ethtool_ops atl1_ethtool_ops; | 
|  | 42 |  | 
|  | 43 | struct atl1_adapter; | 
|  | 44 |  | 
|  | 45 | #define ATL1_MAX_INTR		3 | 
|  | 46 |  | 
|  | 47 | #define ATL1_DEFAULT_TPD	256 | 
|  | 48 | #define ATL1_MAX_TPD		1024 | 
|  | 49 | #define ATL1_MIN_TPD		64 | 
|  | 50 | #define ATL1_DEFAULT_RFD	512 | 
|  | 51 | #define ATL1_MIN_RFD		128 | 
|  | 52 | #define ATL1_MAX_RFD		2048 | 
|  | 53 |  | 
|  | 54 | #define ATL1_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[i])) | 
|  | 55 | #define ATL1_RFD_DESC(R, i)	ATL1_GET_DESC(R, i, struct rx_free_desc) | 
|  | 56 | #define ATL1_TPD_DESC(R, i)	ATL1_GET_DESC(R, i, struct tx_packet_desc) | 
|  | 57 | #define ATL1_RRD_DESC(R, i)	ATL1_GET_DESC(R, i, struct rx_return_desc) | 
|  | 58 |  | 
|  | 59 | /* | 
|  | 60 | * Some workarounds require millisecond delays and are run during interrupt | 
|  | 61 | * context.  Most notably, when establishing link, the phy may need tweaking | 
|  | 62 | * but cannot process phy register reads/writes faster than millisecond | 
|  | 63 | * intervals...and we establish link due to a "link status change" interrupt. | 
|  | 64 | */ | 
|  | 65 |  | 
|  | 66 | /* | 
|  | 67 | * wrapper around a pointer to a socket buffer, | 
|  | 68 | * so a DMA handle can be stored along with the buffer | 
|  | 69 | */ | 
|  | 70 | struct atl1_buffer { | 
|  | 71 | struct sk_buff *skb; | 
|  | 72 | u16 length; | 
|  | 73 | u16 alloced; | 
|  | 74 | dma_addr_t dma; | 
|  | 75 | }; | 
|  | 76 |  | 
|  | 77 | #define MAX_TX_BUF_LEN		0x3000	/* 12KB */ | 
|  | 78 |  | 
|  | 79 | struct atl1_tpd_ring { | 
|  | 80 | void *desc;		/* pointer to the descriptor ring memory */ | 
|  | 81 | dma_addr_t dma;		/* physical adress of the descriptor ring */ | 
|  | 82 | u16 size;		/* length of descriptor ring in bytes */ | 
|  | 83 | u16 count;		/* number of descriptors in the ring */ | 
|  | 84 | u16 hw_idx;		/* hardware index */ | 
|  | 85 | atomic_t next_to_clean; | 
|  | 86 | atomic_t next_to_use; | 
|  | 87 | struct atl1_buffer *buffer_info; | 
|  | 88 | }; | 
|  | 89 |  | 
|  | 90 | struct atl1_rfd_ring { | 
|  | 91 | void *desc; | 
|  | 92 | dma_addr_t dma; | 
|  | 93 | u16 size; | 
|  | 94 | u16 count; | 
|  | 95 | atomic_t next_to_use; | 
|  | 96 | u16 next_to_clean; | 
|  | 97 | struct atl1_buffer *buffer_info; | 
|  | 98 | }; | 
|  | 99 |  | 
|  | 100 | struct atl1_rrd_ring { | 
|  | 101 | void *desc; | 
|  | 102 | dma_addr_t dma; | 
|  | 103 | unsigned int size; | 
|  | 104 | u16 count; | 
|  | 105 | u16 next_to_use; | 
|  | 106 | atomic_t next_to_clean; | 
|  | 107 | }; | 
|  | 108 |  | 
|  | 109 | struct atl1_ring_header { | 
|  | 110 | void *desc;		/* pointer to the descriptor ring memory */ | 
|  | 111 | dma_addr_t dma;		/* physical adress of the descriptor ring */ | 
|  | 112 | unsigned int size;	/* length of descriptor ring in bytes */ | 
|  | 113 | }; | 
|  | 114 |  | 
|  | 115 | struct atl1_cmb { | 
|  | 116 | struct coals_msg_block *cmb; | 
|  | 117 | dma_addr_t dma; | 
|  | 118 | }; | 
|  | 119 |  | 
|  | 120 | struct atl1_smb { | 
|  | 121 | struct stats_msg_block *smb; | 
|  | 122 | dma_addr_t dma; | 
|  | 123 | }; | 
|  | 124 |  | 
|  | 125 | /* Statistics counters */ | 
|  | 126 | struct atl1_sft_stats { | 
|  | 127 | u64 rx_packets; | 
|  | 128 | u64 tx_packets; | 
|  | 129 | u64 rx_bytes; | 
|  | 130 | u64 tx_bytes; | 
|  | 131 | u64 multicast; | 
|  | 132 | u64 collisions; | 
|  | 133 | u64 rx_errors; | 
|  | 134 | u64 rx_length_errors; | 
|  | 135 | u64 rx_crc_errors; | 
|  | 136 | u64 rx_frame_errors; | 
|  | 137 | u64 rx_fifo_errors; | 
|  | 138 | u64 rx_missed_errors; | 
|  | 139 | u64 tx_errors; | 
|  | 140 | u64 tx_fifo_errors; | 
|  | 141 | u64 tx_aborted_errors; | 
|  | 142 | u64 tx_window_errors; | 
|  | 143 | u64 tx_carrier_errors; | 
|  | 144 |  | 
|  | 145 | u64 tx_pause;		/* num Pause packet transmitted. */ | 
|  | 146 | u64 excecol;		/* num tx packets aborted due to excessive collisions. */ | 
|  | 147 | u64 deffer;		/* num deferred tx packets */ | 
|  | 148 | u64 scc;		/* num packets subsequently transmitted successfully w/ single prior collision. */ | 
|  | 149 | u64 mcc;		/* num packets subsequently transmitted successfully w/ multiple prior collisions. */ | 
|  | 150 | u64 latecol;		/* num tx packets  w/ late collisions. */ | 
|  | 151 | u64 tx_underun;		/* num tx packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ | 
|  | 152 | u64 tx_trunc;		/* num tx packets truncated due to size exceeding MTU, regardless whether truncated by Selene or not. (The name doesn't really reflect the meaning in this case.) */ | 
|  | 153 | u64 rx_pause;		/* num Pause packets received. */ | 
|  | 154 | u64 rx_rrd_ov; | 
|  | 155 | u64 rx_trunc; | 
|  | 156 | }; | 
|  | 157 |  | 
|  | 158 | /* board specific private data structure */ | 
|  | 159 | #define ATL1_REGS_LEN	8 | 
|  | 160 |  | 
|  | 161 | /* Structure containing variables used by the shared code */ | 
|  | 162 | struct atl1_hw { | 
|  | 163 | u8 __iomem *hw_addr; | 
|  | 164 | struct atl1_adapter *back; | 
|  | 165 | enum atl1_dma_order dma_ord; | 
|  | 166 | enum atl1_dma_rcb rcb_value; | 
|  | 167 | enum atl1_dma_req_block dmar_block; | 
|  | 168 | enum atl1_dma_req_block dmaw_block; | 
|  | 169 | u8 preamble_len; | 
|  | 170 | u8 max_retry;		/* Retransmission maximum, after which the packet will be discarded */ | 
|  | 171 | u8 jam_ipg;		/* IPG to start JAM for collision based flow control in half-duplex mode. In units of 8-bit time */ | 
|  | 172 | u8 ipgt;		/* Desired back to back inter-packet gap. The default is 96-bit time */ | 
|  | 173 | u8 min_ifg;		/* Minimum number of IFG to enforce in between RX frames. Frame gap below such IFP is dropped */ | 
|  | 174 | u8 ipgr1;		/* 64bit Carrier-Sense window */ | 
|  | 175 | u8 ipgr2;		/* 96-bit IPG window */ | 
|  | 176 | u8 tpd_burst;		/* Number of TPD to prefetch in cache-aligned burst. Each TPD is 16 bytes long */ | 
|  | 177 | u8 rfd_burst;		/* Number of RFD to prefetch in cache-aligned burst. Each RFD is 12 bytes long */ | 
|  | 178 | u8 rfd_fetch_gap; | 
|  | 179 | u8 rrd_burst;		/* Threshold number of RRDs that can be retired in a burst. Each RRD is 16 bytes long */ | 
|  | 180 | u8 tpd_fetch_th; | 
|  | 181 | u8 tpd_fetch_gap; | 
|  | 182 | u16 tx_jumbo_task_th; | 
|  | 183 | u16 txf_burst;		/* Number of data bytes to read in a cache-aligned burst. Each SRAM entry is | 
|  | 184 | 8 bytes long */ | 
|  | 185 | u16 rx_jumbo_th;	/* Jumbo packet size for non-VLAN packet. VLAN packets should add 4 bytes */ | 
|  | 186 | u16 rx_jumbo_lkah; | 
|  | 187 | u16 rrd_ret_timer;	/* RRD retirement timer. Decrement by 1 after every 512ns passes. */ | 
|  | 188 | u16 lcol;		/* Collision Window */ | 
|  | 189 |  | 
|  | 190 | u16 cmb_tpd; | 
|  | 191 | u16 cmb_rrd; | 
|  | 192 | u16 cmb_rx_timer; | 
|  | 193 | u16 cmb_tx_timer; | 
|  | 194 | u32 smb_timer; | 
|  | 195 | u16 media_type; | 
|  | 196 | u16 autoneg_advertised; | 
|  | 197 | u16 pci_cmd_word; | 
|  | 198 |  | 
|  | 199 | u16 mii_autoneg_adv_reg; | 
|  | 200 | u16 mii_1000t_ctrl_reg; | 
|  | 201 |  | 
|  | 202 | u32 mem_rang; | 
|  | 203 | u32 txcw; | 
|  | 204 | u32 max_frame_size; | 
|  | 205 | u32 min_frame_size; | 
|  | 206 | u32 mc_filter_type; | 
|  | 207 | u32 num_mc_addrs; | 
|  | 208 | u32 collision_delta; | 
|  | 209 | u32 tx_packet_delta; | 
|  | 210 | u16 phy_spd_default; | 
|  | 211 |  | 
|  | 212 | u16 dev_rev; | 
|  | 213 | u8 revision_id; | 
|  | 214 |  | 
|  | 215 | /* spi flash */ | 
|  | 216 | u8 flash_vendor; | 
|  | 217 |  | 
|  | 218 | u8 dma_fairness; | 
|  | 219 | u8 mac_addr[ETH_ALEN]; | 
|  | 220 | u8 perm_mac_addr[ETH_ALEN]; | 
|  | 221 |  | 
|  | 222 | /* bool phy_preamble_sup; */ | 
|  | 223 | bool phy_configured; | 
|  | 224 | }; | 
|  | 225 |  | 
|  | 226 | struct atl1_adapter { | 
|  | 227 | /* OS defined structs */ | 
|  | 228 | struct net_device *netdev; | 
|  | 229 | struct pci_dev *pdev; | 
|  | 230 | struct net_device_stats net_stats; | 
|  | 231 | struct atl1_sft_stats soft_stats; | 
|  | 232 |  | 
|  | 233 | struct vlan_group *vlgrp; | 
|  | 234 | u32 rx_buffer_len; | 
|  | 235 | u32 wol; | 
|  | 236 | u16 link_speed; | 
|  | 237 | u16 link_duplex; | 
|  | 238 | spinlock_t lock; | 
|  | 239 | atomic_t irq_sem; | 
|  | 240 | struct work_struct tx_timeout_task; | 
|  | 241 | struct work_struct link_chg_task; | 
|  | 242 | struct work_struct pcie_dma_to_rst_task; | 
|  | 243 | struct timer_list watchdog_timer; | 
|  | 244 | struct timer_list phy_config_timer; | 
|  | 245 | bool phy_timer_pending; | 
|  | 246 |  | 
|  | 247 | bool mac_disabled; | 
|  | 248 |  | 
|  | 249 | /* All descriptor rings' memory */ | 
|  | 250 | struct atl1_ring_header ring_header; | 
|  | 251 |  | 
|  | 252 | /* TX */ | 
|  | 253 | struct atl1_tpd_ring tpd_ring; | 
|  | 254 | spinlock_t mb_lock; | 
|  | 255 |  | 
|  | 256 | /* RX */ | 
|  | 257 | struct atl1_rfd_ring rfd_ring; | 
|  | 258 | struct atl1_rrd_ring rrd_ring; | 
|  | 259 | u64 hw_csum_err; | 
|  | 260 | u64 hw_csum_good; | 
|  | 261 |  | 
|  | 262 | u32 gorcl; | 
|  | 263 | u64 gorcl_old; | 
|  | 264 |  | 
|  | 265 | /* Interrupt Moderator timer ( 2us resolution) */ | 
|  | 266 | u16 imt; | 
|  | 267 | /* Interrupt Clear timer (2us resolution) */ | 
|  | 268 | u16 ict; | 
|  | 269 |  | 
|  | 270 | /* MII interface info */ | 
|  | 271 | struct mii_if_info mii; | 
|  | 272 |  | 
|  | 273 | /* structs defined in atl1_hw.h */ | 
|  | 274 | u32 bd_number;		/* board number */ | 
|  | 275 | bool pci_using_64; | 
|  | 276 | struct atl1_hw hw; | 
|  | 277 | struct atl1_smb smb; | 
|  | 278 | struct atl1_cmb cmb; | 
|  | 279 |  | 
|  | 280 | u32 pci_state[16]; | 
|  | 281 | }; | 
|  | 282 |  | 
|  | 283 | #endif	/* _ATL1_H_ */ |