| Liam Girdwood | aaf9346 | 2011-02-03 15:02:46 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * omap-mcpdm.h |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments |
| 5 | * |
| 6 | * Contact: Misael Lopez Cruz <x0052729@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 20 | * 02110-1301 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #ifndef __OMAP_MCPDM_H__ |
| 25 | #define __OMAP_MCPDM_H__ |
| 26 | |
| 27 | #include <linux/platform_device.h> |
| 28 | |
| 29 | #define MCPDM_REVISION 0x00 |
| 30 | #define MCPDM_SYSCONFIG 0x10 |
| 31 | #define MCPDM_IRQSTATUS_RAW 0x24 |
| 32 | #define MCPDM_IRQSTATUS 0x28 |
| 33 | #define MCPDM_IRQENABLE_SET 0x2C |
| 34 | #define MCPDM_IRQENABLE_CLR 0x30 |
| 35 | #define MCPDM_IRQWAKE_EN 0x34 |
| 36 | #define MCPDM_DMAENABLE_SET 0x38 |
| 37 | #define MCPDM_DMAENABLE_CLR 0x3C |
| 38 | #define MCPDM_DMAWAKEEN 0x40 |
| 39 | #define MCPDM_CTRL 0x44 |
| 40 | #define MCPDM_DN_DATA 0x48 |
| 41 | #define MCPDM_UP_DATA 0x4C |
| 42 | #define MCPDM_FIFO_CTRL_DN 0x50 |
| 43 | #define MCPDM_FIFO_CTRL_UP 0x54 |
| 44 | #define MCPDM_DN_OFFSET 0x58 |
| 45 | |
| 46 | /* |
| 47 | * MCPDM_IRQ bit fields |
| 48 | * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR |
| 49 | */ |
| 50 | |
| 51 | #define MCPDM_DN_IRQ (1 << 0) |
| 52 | #define MCPDM_DN_IRQ_EMPTY (1 << 1) |
| 53 | #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) |
| 54 | #define MCPDM_DN_IRQ_FULL (1 << 3) |
| 55 | |
| 56 | #define MCPDM_UP_IRQ (1 << 8) |
| 57 | #define MCPDM_UP_IRQ_EMPTY (1 << 9) |
| 58 | #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) |
| 59 | #define MCPDM_UP_IRQ_FULL (1 << 11) |
| 60 | |
| 61 | #define MCPDM_DOWNLINK_IRQ_MASK 0x00F |
| 62 | #define MCPDM_UPLINK_IRQ_MASK 0xF00 |
| 63 | |
| 64 | /* |
| 65 | * MCPDM_DMAENABLE bit fields |
| 66 | */ |
| 67 | |
| 68 | #define DMA_DN_ENABLE 0x1 |
| 69 | #define DMA_UP_ENABLE 0x2 |
| 70 | |
| 71 | /* |
| 72 | * MCPDM_CTRL bit fields |
| 73 | */ |
| 74 | |
| 75 | #define PDM_UP1_EN 0x0001 |
| 76 | #define PDM_UP2_EN 0x0002 |
| 77 | #define PDM_UP3_EN 0x0004 |
| 78 | #define PDM_DN1_EN 0x0008 |
| 79 | #define PDM_DN2_EN 0x0010 |
| 80 | #define PDM_DN3_EN 0x0020 |
| 81 | #define PDM_DN4_EN 0x0040 |
| 82 | #define PDM_DN5_EN 0x0080 |
| 83 | #define PDMOUTFORMAT 0x0100 |
| 84 | #define CMD_INT 0x0200 |
| 85 | #define STATUS_INT 0x0400 |
| 86 | #define SW_UP_RST 0x0800 |
| 87 | #define SW_DN_RST 0x1000 |
| 88 | #define WD_EN 0x4000 |
| 89 | #define PDM_UP_MASK 0x007 |
| 90 | #define PDM_DN_MASK 0x0F8 |
| 91 | #define PDM_CMD_MASK 0x200 |
| 92 | #define PDM_STATUS_MASK 0x400 |
| 93 | |
| 94 | |
| 95 | #define PDMOUTFORMAT_LJUST (0 << 8) |
| 96 | #define PDMOUTFORMAT_RJUST (1 << 8) |
| 97 | |
| 98 | /* |
| 99 | * MCPDM_FIFO_CTRL bit fields |
| 100 | */ |
| 101 | |
| 102 | #define UP_THRES_MAX 0xF |
| 103 | #define DN_THRES_MAX 0xF |
| 104 | |
| 105 | /* |
| 106 | * MCPDM_DN_OFFSET bit fields |
| 107 | */ |
| 108 | |
| 109 | #define DN_OFST_RX1_EN 0x0001 |
| 110 | #define DN_OFST_RX2_EN 0x0100 |
| 111 | |
| 112 | #define DN_OFST_RX1 1 |
| 113 | #define DN_OFST_RX2 9 |
| 114 | #define DN_OFST_MAX 0x1F |
| 115 | |
| 116 | #define MCPDM_UPLINK 1 |
| 117 | #define MCPDM_DOWNLINK 2 |
| 118 | |
| 119 | #endif /* End of __OMAP_MCPDM_H__ */ |