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review.evervolv.com / android_kernel_htc_msm8960 / ab1363a8929f32cc163cd3f50ca72f20d901b00c / . / arch / sh / drivers / pci / fixups-lboxre2.c
blob: a82011d03cb0a01e1787ea00345178422570acc3 [file] [log] [blame]
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]1/*
2 * arch/sh/drivers/pci/fixups-lboxre2.c
3 *
4 * L-BOX RE2 PCI fixups
5 *
6 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]12#include <linux/pci.h>
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]13#include "pci-sh4.h"
14
15#define PCIMCR_MRSET_OFF 0xBFFFFFFF
16#define PCIMCR_RFSH_OFF 0xFFFFFFFB
17
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]18int pci_fixup_pcic(struct pci_channel *chan)
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]19{
20 unsigned long bcr1, mcr;
21
Magnus Damme036eaa2008-02-14 13:52:43 +0900[diff] [blame]22 bcr1 = ctrl_inl(SH7751_BCR1);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]24 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]25
26 /* Enable all interrupts, so we known what to fix */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]27 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
28 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
29 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
30 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]31
Magnus Damme036eaa2008-02-14 13:52:43 +0900[diff] [blame]32 mcr = ctrl_inl(SH7751_MCR);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]33 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]34 pci_write_reg(chan, mcr, SH4_PCIMCR);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]35
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame]36 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
37 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
38 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
39 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
Nobuhiro Iwamatsuc86c5a92007-03-26 14:27:43 +0900[diff] [blame]40
41 return 0;
42}