blob: e45bb62bf8ce08aa539e79b135ee61e95f9f1588 [file] [log] [blame]
Jamie Lenehana09749d2006-09-27 15:05:39 +09001/*
2 * arch/sh/drivers/pci/ops-titan.c
3 *
4 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
5 *
6 * Modified from ops-snapgear.c written by David McCullough
7 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
8 *
9 * May be copied or modified under the terms of the GNU General Public
10 * License. See linux/COPYING for more information.
11 *
12 * PCI initialization for the Titan boards
13 */
Jamie Lenehana09749d2006-09-27 15:05:39 +090014#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
Paul Mundt0f08f332006-09-27 17:03:56 +090017#include <linux/pci.h>
Jamie Lenehanea0f8fe2006-12-06 12:05:02 +090018#include <linux/io.h>
Paul Mundt7639a452008-10-20 13:02:48 +090019#include <mach/titan.h>
Paul Mundt959f85f2006-09-27 16:43:28 +090020#include "pci-sh4.h"
Jamie Lenehana09749d2006-09-27 15:05:39 +090021
Jamie Lenehanea0f8fe2006-12-06 12:05:02 +090022static char titan_irq_tab[] __initdata = {
23 TITAN_IRQ_WAN,
24 TITAN_IRQ_LAN,
25 TITAN_IRQ_MPCIA,
26 TITAN_IRQ_MPCIB,
27 TITAN_IRQ_USB,
28};
29
Paul Mundt959f85f2006-09-27 16:43:28 +090030int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
Jamie Lenehana09749d2006-09-27 15:05:39 +090031{
Jamie Lenehanea0f8fe2006-12-06 12:05:02 +090032 int irq = titan_irq_tab[slot];
Jamie Lenehana09749d2006-09-27 15:05:39 +090033
34 printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n",
35 slot, pin - 1 + 'A', irq);
36
37 return irq;
38}
39
40static struct resource sh7751_io_resource = {
41 .name = "SH7751_IO",
42 .start = SH7751_PCI_IO_BASE,
43 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
44 .flags = IORESOURCE_IO
45};
46
47static struct resource sh7751_mem_resource = {
48 .name = "SH7751_mem",
49 .start = SH7751_PCI_MEMORY_BASE,
50 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
51 .flags = IORESOURCE_MEM
52};
53
Jamie Lenehana09749d2006-09-27 15:05:39 +090054struct pci_channel board_pci_channels[] = {
Magnus Dammd0e3db42009-03-11 15:46:14 +090055 { sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
Jamie Lenehana09749d2006-09-27 15:05:39 +090056 { NULL, NULL, NULL, 0, 0 },
57};
Jamie Lenehana09749d2006-09-27 15:05:39 +090058
Paul Mundt959f85f2006-09-27 16:43:28 +090059static struct sh4_pci_address_map sh7751_pci_map = {
Jamie Lenehana09749d2006-09-27 15:05:39 +090060 .window0 = {
61 .base = SH7751_CS2_BASE_ADDR,
62 .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
63 },
64
65 .window1 = {
66 .base = SH7751_CS2_BASE_ADDR,
67 .size = SH7751_MEM_REGION_SIZE*2,
68 },
Jamie Lenehana09749d2006-09-27 15:05:39 +090069};
70
71int __init pcibios_init_platform(void)
72{
Magnus Dammb8b47bf2009-03-11 15:41:51 +090073 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
Jamie Lenehana09749d2006-09-27 15:05:39 +090074}