| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | *	Registers for the ESS PCI cards | 
|  | 3 | */ | 
|  | 4 |  | 
|  | 5 | /* | 
|  | 6 | *	Memory access | 
|  | 7 | */ | 
|  | 8 |  | 
|  | 9 | #define ESS_MEM_DATA		0x00 | 
|  | 10 | #define	ESS_MEM_INDEX		0x02 | 
|  | 11 |  | 
|  | 12 | /* | 
|  | 13 | *	AC-97 Codec port. Delay 1uS after each write. This is used to | 
|  | 14 | *	talk AC-97 (see intel.com). Write data then register. | 
|  | 15 | */ | 
|  | 16 |  | 
|  | 17 | #define ESS_AC97_INDEX		0x30		/* byte wide */ | 
|  | 18 | #define ESS_AC97_DATA		0x32 | 
|  | 19 |  | 
|  | 20 | /* | 
|  | 21 | *	Reading is a bit different. You write register|0x80 to ubdex | 
|  | 22 | *	delay 1uS poll the low bit of index, when it clears read the | 
|  | 23 | *	data value. | 
|  | 24 | */ | 
|  | 25 |  | 
|  | 26 | /* | 
|  | 27 | *	Control port. Not yet fully understood | 
|  | 28 | *	The value 0xC090 gets loaded to it then 0x0000 and 0x2800 | 
|  | 29 | *	to the data port. Then after 4uS the value 0x300 is written | 
|  | 30 | */ | 
|  | 31 |  | 
|  | 32 | #define RING_BUS_CTRL_L		0x34 | 
|  | 33 | #define RING_BUS_CTRL_H		0x36 | 
|  | 34 |  | 
|  | 35 | /* | 
|  | 36 | *	This is also used during setup. The value 0x17 is written to it | 
|  | 37 | */ | 
|  | 38 |  | 
|  | 39 | #define ESS_SETUP_18		0x18 | 
|  | 40 |  | 
|  | 41 | /* | 
|  | 42 | *	And this one gets 0x000b | 
|  | 43 | */ | 
|  | 44 |  | 
|  | 45 | #define ESS_SETUP_A2		0xA2 | 
|  | 46 |  | 
|  | 47 | /* | 
|  | 48 | *	And this 0x0000 | 
|  | 49 | */ | 
|  | 50 |  | 
|  | 51 | #define ESS_SETUP_A4		0xA4 | 
|  | 52 | #define ESS_SETUP_A6		0xA6 | 
|  | 53 |  | 
|  | 54 | /* | 
|  | 55 | *	Stuff to do with Harpo - the wave stuff | 
|  | 56 | */ | 
|  | 57 |  | 
|  | 58 | #define ESS_WAVETABLE_SIZE	0x14 | 
|  | 59 | #define 	ESS_WAVETABLE_2M	0xA180 | 
|  | 60 |  |