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review.evervolv.com / android_kernel_htc_msm8960 / ae5536d6f7f9b51f7a0451421eade1988cfd7126 / . / drivers / video / imsttfb.c
blob: 7fbe24206b190458b8b9aeb89e123cb47b8b6aa2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
3 *
4 * This file is derived from the powermac console "imstt" driver:
5 * Copyright (C) 1997 Sigurdur Asgeirsson
6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7 * Modified by Danilo Beuche 1998
8 * Some register values added by Damien Doligez, INRIA Rocquencourt
9 * Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
10 *
11 * This file was written by Ryan Nielsen (ran@krazynet.com)
12 * Most of the frame buffer device stuff was copied from atyfb.c
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file COPYING in the main directory of this archive for
16 * more details.
17 */
18
19#include <linux/config.h>
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/tty.h>
26#include <linux/slab.h>
27#include <linux/vmalloc.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/fb.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <asm/io.h>
34#include <asm/uaccess.h>
35
36#if defined(CONFIG_PPC)
37#include <linux/nvram.h>
38#include <asm/prom.h>
39#include <asm/pci-bridge.h>
40#include "macmodes.h"
41#endif
42
43#ifndef __powerpc__
44#define eieio() /* Enforce In-order Execution of I/O */
45#endif
46
47/* TwinTurbo (Cosmo) registers */
48enum {
49 S1SA = 0, /* 0x00 */
50 S2SA = 1, /* 0x04 */
51 SP = 2, /* 0x08 */
52 DSA = 3, /* 0x0C */
53 CNT = 4, /* 0x10 */
54 DP_OCTL = 5, /* 0x14 */
55 CLR = 6, /* 0x18 */
56 BI = 8, /* 0x20 */
57 MBC = 9, /* 0x24 */
58 BLTCTL = 10, /* 0x28 */
59
60 /* Scan Timing Generator Registers */
61 HES = 12, /* 0x30 */
62 HEB = 13, /* 0x34 */
63 HSB = 14, /* 0x38 */
64 HT = 15, /* 0x3C */
65 VES = 16, /* 0x40 */
66 VEB = 17, /* 0x44 */
67 VSB = 18, /* 0x48 */
68 VT = 19, /* 0x4C */
69 HCIV = 20, /* 0x50 */
70 VCIV = 21, /* 0x54 */
71 TCDR = 22, /* 0x58 */
72 VIL = 23, /* 0x5C */
73 STGCTL = 24, /* 0x60 */
74
75 /* Screen Refresh Generator Registers */
76 SSR = 25, /* 0x64 */
77 HRIR = 26, /* 0x68 */
78 SPR = 27, /* 0x6C */
79 CMR = 28, /* 0x70 */
80 SRGCTL = 29, /* 0x74 */
81
82 /* RAM Refresh Generator Registers */
83 RRCIV = 30, /* 0x78 */
84 RRSC = 31, /* 0x7C */
85 RRCR = 34, /* 0x88 */
86
87 /* System Registers */
88 GIOE = 32, /* 0x80 */
89 GIO = 33, /* 0x84 */
90 SCR = 35, /* 0x8C */
91 SSTATUS = 36, /* 0x90 */
92 PRC = 37, /* 0x94 */
93
94#if 0
95 /* PCI Registers */
96 DVID = 0x00000000L,
97 SC = 0x00000004L,
98 CCR = 0x00000008L,
99 OG = 0x0000000CL,
100 BARM = 0x00000010L,
101 BARER = 0x00000030L,
102#endif
103};
104
105/* IBM 624 RAMDAC Direct Registers */
106enum {
107 PADDRW = 0x00,
108 PDATA = 0x04,
109 PPMASK = 0x08,
110 PADDRR = 0x0c,
111 PIDXLO = 0x10,
112 PIDXHI = 0x14,
113 PIDXDATA= 0x18,
114 PIDXCTL = 0x1c
115};
116
117/* IBM 624 RAMDAC Indirect Registers */
118enum {
119 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
120 SYNCCTL = 0x03, /* (0x00) Sync Control */
121 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
122 PWRMNGMT = 0x05, /* (0x00) Power Management */
123 DACOP = 0x06, /* (0x02) DAC Operation */
124 PALETCTL = 0x07, /* (0x00) Palette Control */
125 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
126 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
127 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
128 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
129 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
130 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
131 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
132 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
133 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
134 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
135 SYSCLKP = 0x17, /* () System Clock P */
136 SYSCLKC = 0x18, /* () System Clock C */
137 /*
138 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
139 * c is charge pump bias which depends on the VCO frequency
140 */
141 PIXM0 = 0x20, /* () Pixel M 0 */
142 PIXN0 = 0x21, /* () Pixel N 0 */
143 PIXP0 = 0x22, /* () Pixel P 0 */
144 PIXC0 = 0x23, /* () Pixel C 0 */
145 CURSCTL = 0x30, /* (0x00) Cursor Control */
146 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
147 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
148 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
149 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
150 CURSHOTX = 0x35, /* () Cursor Hot Spot X */
151 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
152 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
153 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
154 CURS1R = 0x40, /* () Cursor 1 Red */
155 CURS1G = 0x41, /* () Cursor 1 Green */
156 CURS1B = 0x42, /* () Cursor 1 Blue */
157 CURS2R = 0x43, /* () Cursor 2 Red */
158 CURS2G = 0x44, /* () Cursor 2 Green */
159 CURS2B = 0x45, /* () Cursor 2 Blue */
160 CURS3R = 0x46, /* () Cursor 3 Red */
161 CURS3G = 0x47, /* () Cursor 3 Green */
162 CURS3B = 0x48, /* () Cursor 3 Blue */
163 BORDR = 0x60, /* () Border Color Red */
164 BORDG = 0x61, /* () Border Color Green */
165 BORDB = 0x62, /* () Border Color Blue */
166 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
167 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
168 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
169 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
170};
171
172/* TI TVP 3030 RAMDAC Direct Registers */
173enum {
174 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */
175 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
176 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
177 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */
178 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
179 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
180 /* 6 reserved */
181 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
182 /* 8 reserved */
183 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
184 TVPIDATA = 0x28, /* 10 Index Data */
185 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
186 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
187 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
188 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
189 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
190};
191
192/* TI TVP 3030 RAMDAC Indirect Registers */
193enum {
194 TVPIRREV = 0x01, /* Silicon Revision [RO] */
195 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
196 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
197 TVPIRLAC = 0x0f, /* Latch Control (0x06) */
198 TVPIRTCC = 0x18, /* True Color Control (0x80) */
199 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
200 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
201 TVPIRPPG = 0x1c, /* Palette Page (0x00) */
202 TVPIRGEC = 0x1d, /* General Control (0x00) */
203 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
204 TVPIRPLA = 0x2c, /* PLL Address */
205 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
206 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
207 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
208 TVPIRCKL = 0x30, /* Color-Key Overlay Low */
209 TVPIRCKH = 0x31, /* Color-Key Overlay High */
210 TVPIRCRL = 0x32, /* Color-Key Red Low */
211 TVPIRCRH = 0x33, /* Color-Key Red High */
212 TVPIRCGL = 0x34, /* Color-Key Green Low */
213 TVPIRCGH = 0x35, /* Color-Key Green High */
214 TVPIRCBL = 0x36, /* Color-Key Blue Low */
215 TVPIRCBH = 0x37, /* Color-Key Blue High */
216 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
217 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
218 TVPIRSEN = 0x3a, /* Sense Test (0x00) */
219 TVPIRTMD = 0x3b, /* Test Mode Data */
220 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
221 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
222 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
223 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
224 TVPIRRES = 0xff /* Software Reset [WO] */
225};
226
227struct initvalues {
228 __u8 addr, value;
229};
230
231static struct initvalues ibm_initregs[] __devinitdata = {
232 { CLKCTL, 0x21 },
233 { SYNCCTL, 0x00 },
234 { HSYNCPOS, 0x00 },
235 { PWRMNGMT, 0x00 },
236 { DACOP, 0x02 },
237 { PALETCTL, 0x00 },
238 { SYSCLKCTL, 0x01 },
239
240 /*
241 * Note that colors in X are correct only if all video data is
242 * passed through the palette in the DAC. That is, "indirect
243 * color" must be configured. This is the case for the IBM DAC
244 * used in the 2MB and 4MB cards, at least.
245 */
246 { BPP8, 0x00 },
247 { BPP16, 0x01 },
248 { BPP24, 0x00 },
249 { BPP32, 0x00 },
250
251 { PIXCTL1, 0x05 },
252 { PIXCTL2, 0x00 },
253 { SYSCLKN, 0x08 },
254 { SYSCLKM, 0x4f },
255 { SYSCLKP, 0x00 },
256 { SYSCLKC, 0x00 },
257 { CURSCTL, 0x00 },
258 { CURSACCTL, 0x01 },
259 { CURSACATTR, 0xa8 },
260 { CURS1R, 0xff },
261 { CURS1G, 0xff },
262 { CURS1B, 0xff },
263 { CURS2R, 0xff },
264 { CURS2G, 0xff },
265 { CURS2B, 0xff },
266 { CURS3R, 0xff },
267 { CURS3G, 0xff },
268 { CURS3B, 0xff },
269 { BORDR, 0xff },
270 { BORDG, 0xff },
271 { BORDB, 0xff },
272 { MISCTL1, 0x01 },
273 { MISCTL2, 0x45 },
274 { MISCTL3, 0x00 },
275 { KEYCTL, 0x00 }
276};
277
278static struct initvalues tvp_initregs[] __devinitdata = {
279 { TVPIRICC, 0x00 },
280 { TVPIRBRC, 0xe4 },
281 { TVPIRLAC, 0x06 },
282 { TVPIRTCC, 0x80 },
283 { TVPIRMXC, 0x4d },
284 { TVPIRCLS, 0x05 },
285 { TVPIRPPG, 0x00 },
286 { TVPIRGEC, 0x00 },
287 { TVPIRMIC, 0x08 },
288 { TVPIRCKL, 0xff },
289 { TVPIRCKH, 0xff },
290 { TVPIRCRL, 0xff },
291 { TVPIRCRH, 0xff },
292 { TVPIRCGL, 0xff },
293 { TVPIRCGH, 0xff },
294 { TVPIRCBL, 0xff },
295 { TVPIRCBH, 0xff },
296 { TVPIRCKC, 0x00 },
297 { TVPIRPLA, 0x00 },
298 { TVPIRPPD, 0xc0 },
299 { TVPIRPPD, 0xd5 },
300 { TVPIRPPD, 0xea },
301 { TVPIRPLA, 0x00 },
302 { TVPIRMPD, 0xb9 },
303 { TVPIRMPD, 0x3a },
304 { TVPIRMPD, 0xb1 },
305 { TVPIRPLA, 0x00 },
306 { TVPIRLPD, 0xc1 },
307 { TVPIRLPD, 0x3d },
308 { TVPIRLPD, 0xf3 },
309};
310
311struct imstt_regvals {
312 __u32 pitch;
313 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
314 __u8 pclk_m, pclk_n, pclk_p;
315 /* Values of the tvp which change depending on colormode x resolution */
316 __u8 mlc[3]; /* Memory Loop Config 0x39 */
317 __u8 lckl_p[3]; /* P value of LCKL PLL */
318};
319
320struct imstt_par {
321 struct imstt_regvals init;
322 __u32 __iomem *dc_regs;
323 unsigned long cmap_regs_phys;
324 __u8 *cmap_regs;
325 __u32 ramdac;
326};
327
328enum {
329 IBM = 0,
330 TVP = 1
331};
332
333#define USE_NV_MODES 1
334#define INIT_BPP 8
335#define INIT_XRES 640
336#define INIT_YRES 480
337
338static int inverse = 0;
339static char fontname[40] __initdata = { 0 };
340#if defined(CONFIG_PPC)
341static signed char init_vmode __devinitdata = -1, init_cmode __devinitdata = -1;
342#endif
343
344static struct imstt_regvals tvp_reg_init_2 = {
345 512,
346 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
347 0xec, 0x2a, 0xf3,
348 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
349};
350
351static struct imstt_regvals tvp_reg_init_6 = {
352 640,
353 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
354 0xef, 0x2e, 0xb2,
355 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
356};
357
358static struct imstt_regvals tvp_reg_init_12 = {
359 800,
360 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
361 0xf6, 0x2e, 0xf2,
362 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
363};
364
365static struct imstt_regvals tvp_reg_init_13 = {
366 832,
367 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
368 0xfe, 0x3e, 0xf1,
369 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
370};
371
372static struct imstt_regvals tvp_reg_init_17 = {
373 1024,
374 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
375 0xfc, 0x3a, 0xf1,
376 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
377};
378
379static struct imstt_regvals tvp_reg_init_18 = {
380 1152,
381 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
382 0xfd, 0x3a, 0xf1,
383 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
384};
385
386static struct imstt_regvals tvp_reg_init_19 = {
387 1280,
388 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
389 0xf7, 0x36, 0xf0,
390 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
391};
392
393static struct imstt_regvals tvp_reg_init_20 = {
394 1280,
395 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
396 0xf0, 0x2d, 0xf0,
397 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
398};
399
400/*
401 * PCI driver prototypes
402 */
403static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
404static void imsttfb_remove(struct pci_dev *pdev);
405
406/*
407 * Register access
408 */
409static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
410{
411#ifdef __powerpc__
412 return in_le32(base + regindex);
413#else
414 return readl(base + regindex);
415#endif
416}
417
418static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
419{
420#ifdef __powerpc__
421 out_le32(base + regindex, val);
422#else
423 writel(val, base + regindex);
424#endif
425}
426
427static __u32
428getclkMHz(struct imstt_par *par)
429{
430 __u32 clk_m, clk_n, clk_p;
431
432 clk_m = par->init.pclk_m;
433 clk_n = par->init.pclk_n;
434 clk_p = par->init.pclk_p;
435
436 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
437}
438
439static void
440setclkMHz(struct imstt_par *par, __u32 MHz)
441{
442 __u32 clk_m, clk_n, clk_p, x, stage, spilled;
443
444 clk_m = clk_n = clk_p = 0;
445 stage = spilled = 0;
446 for (;;) {
447 switch (stage) {
448 case 0:
449 clk_m++;
450 break;
451 case 1:
452 clk_n++;
453 break;
454 }
455 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
456 if (x == MHz)
457 break;
458 if (x > MHz) {
459 spilled = 1;
460 stage = 1;
461 } else if (spilled && x < MHz) {
462 stage = 0;
463 }
464 }
465
466 par->init.pclk_m = clk_m;
467 par->init.pclk_n = clk_n;
468 par->init.pclk_p = clk_p;
469}
470
471static struct imstt_regvals *
472compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
473{
474 struct imstt_regvals *init = &par->init;
475 __u32 MHz, hes, heb, veb, htp, vtp;
476
477 switch (xres) {
478 case 640:
479 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
480 MHz = 30 /* .25 */ ;
481 break;
482 case 832:
483 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
484 MHz = 57 /* .27_ */ ;
485 break;
486 case 1024:
487 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
488 MHz = 80;
489 break;
490 case 1152:
491 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
492 MHz = 101 /* .6_ */ ;
493 break;
494 case 1280:
495 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
496 MHz = yres == 960 ? 126 : 135;
497 break;
498 case 1600:
499 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
500 MHz = 200;
501 break;
502 default:
503 return NULL;
504 }
505
506 setclkMHz(par, MHz);
507
508 init->hes = hes;
509 init->heb = heb;
510 init->hsb = init->heb + (xres >> 3);
511 init->ht = init->hsb + htp;
512 init->ves = 0x0003;
513 init->veb = veb;
514 init->vsb = init->veb + yres;
515 init->vt = init->vsb + vtp;
516 init->vil = init->vsb;
517
518 init->pitch = xres;
519 return init;
520}
521
522static struct imstt_regvals *
523compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
524{
525 struct imstt_regvals *init;
526
527 switch (xres) {
528 case 512:
529 init = &tvp_reg_init_2;
530 break;
531 case 640:
532 init = &tvp_reg_init_6;
533 break;
534 case 800:
535 init = &tvp_reg_init_12;
536 break;
537 case 832:
538 init = &tvp_reg_init_13;
539 break;
540 case 1024:
541 init = &tvp_reg_init_17;
542 break;
543 case 1152:
544 init = &tvp_reg_init_18;
545 break;
546 case 1280:
547 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
548 break;
549 default:
550 return NULL;
551 }
552 par->init = *init;
553 return init;
554}
555
556static struct imstt_regvals *
557compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
558{
559 if (par->ramdac == IBM)
560 return compute_imstt_regvals_ibm(par, xres, yres);
561 else
562 return compute_imstt_regvals_tvp(par, xres, yres);
563}
564
565static void
566set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
567{
568 struct imstt_regvals *init = &par->init;
569 __u8 pformat = (bpp >> 3) + 2;
570
571 par->cmap_regs[PIDXHI] = 0; eieio();
572 par->cmap_regs[PIDXLO] = PIXM0; eieio();
573 par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
574 par->cmap_regs[PIDXLO] = PIXN0; eieio();
575 par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
576 par->cmap_regs[PIDXLO] = PIXP0; eieio();
577 par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
578 par->cmap_regs[PIDXLO] = PIXC0; eieio();
579 par->cmap_regs[PIDXDATA] = 0x02; eieio();
580
581 par->cmap_regs[PIDXLO] = PIXFMT; eieio();
582 par->cmap_regs[PIDXDATA] = pformat; eieio();
583}
584
585static void
586set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
587{
588 struct imstt_regvals *init = &par->init;
589 __u8 tcc, mxc, lckl_n, mic;
590 __u8 mlc, lckl_p;
591
592 switch (bpp) {
593 default:
594 case 8:
595 tcc = 0x80;
596 mxc = 0x4d;
597 lckl_n = 0xc1;
598 mlc = init->mlc[0];
599 lckl_p = init->lckl_p[0];
600 break;
601 case 16:
602 tcc = 0x44;
603 mxc = 0x55;
604 lckl_n = 0xe1;
605 mlc = init->mlc[1];
606 lckl_p = init->lckl_p[1];
607 break;
608 case 24:
609 tcc = 0x5e;
610 mxc = 0x5d;
611 lckl_n = 0xf1;
612 mlc = init->mlc[2];
613 lckl_p = init->lckl_p[2];
614 break;
615 case 32:
616 tcc = 0x46;
617 mxc = 0x5d;
618 lckl_n = 0xf1;
619 mlc = init->mlc[2];
620 lckl_p = init->lckl_p[2];
621 break;
622 }
623 mic = 0x08;
624
625 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
626 par->cmap_regs[TVPIDATA] = 0x00; eieio();
627 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
628 par->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
629 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
630 par->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
631 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
632 par->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
633
634 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
635 par->cmap_regs[TVPIDATA] = tcc; eieio();
636 par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
637 par->cmap_regs[TVPIDATA] = mxc; eieio();
638 par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
639 par->cmap_regs[TVPIDATA] = mic; eieio();
640
641 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
642 par->cmap_regs[TVPIDATA] = 0x00; eieio();
643 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
644 par->cmap_regs[TVPIDATA] = lckl_n; eieio();
645
646 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
647 par->cmap_regs[TVPIDATA] = 0x15; eieio();
648 par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
649 par->cmap_regs[TVPIDATA] = mlc; eieio();
650
651 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
652 par->cmap_regs[TVPIDATA] = 0x2a; eieio();
653 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
654 par->cmap_regs[TVPIDATA] = lckl_p; eieio();
655}
656
657static void
658set_imstt_regvals (struct fb_info *info, u_int bpp)
659{
660 struct imstt_par *par = (struct imstt_par *) info->par;
661 struct imstt_regvals *init = &par->init;
662 __u32 ctl, pitch, byteswap, scr;
663
664 if (par->ramdac == IBM)
665 set_imstt_regvals_ibm(par, bpp);
666 else
667 set_imstt_regvals_tvp(par, bpp);
668
669 /*
670 * From what I (jsk) can gather poking around with MacsBug,
671 * bits 8 and 9 in the SCR register control endianness
672 * correction (byte swapping). These bits must be set according
673 * to the color depth as follows:
674 * Color depth Bit 9 Bit 8
675 * ========== ===== =====
676 * 8bpp 0 0
677 * 16bpp 0 1
678 * 32bpp 1 1
679 */
680 switch (bpp) {
681 default:
682 case 8:
683 ctl = 0x17b1;
684 pitch = init->pitch >> 2;
685 byteswap = 0x000;
686 break;
687 case 16:
688 ctl = 0x17b3;
689 pitch = init->pitch >> 1;
690 byteswap = 0x100;
691 break;
692 case 24:
693 ctl = 0x17b9;
694 pitch = init->pitch - (init->pitch >> 2);
695 byteswap = 0x200;
696 break;
697 case 32:
698 ctl = 0x17b5;
699 pitch = init->pitch;
700 byteswap = 0x300;
701 break;
702 }
703 if (par->ramdac == TVP)
704 ctl -= 0x30;
705
706 write_reg_le32(par->dc_regs, HES, init->hes);
707 write_reg_le32(par->dc_regs, HEB, init->heb);
708 write_reg_le32(par->dc_regs, HSB, init->hsb);
709 write_reg_le32(par->dc_regs, HT, init->ht);
710 write_reg_le32(par->dc_regs, VES, init->ves);
711 write_reg_le32(par->dc_regs, VEB, init->veb);
712 write_reg_le32(par->dc_regs, VSB, init->vsb);
713 write_reg_le32(par->dc_regs, VT, init->vt);
714 write_reg_le32(par->dc_regs, VIL, init->vil);
715 write_reg_le32(par->dc_regs, HCIV, 1);
716 write_reg_le32(par->dc_regs, VCIV, 1);
717 write_reg_le32(par->dc_regs, TCDR, 4);
718 write_reg_le32(par->dc_regs, RRCIV, 1);
719 write_reg_le32(par->dc_regs, RRSC, 0x980);
720 write_reg_le32(par->dc_regs, RRCR, 0x11);
721
722 if (par->ramdac == IBM) {
723 write_reg_le32(par->dc_regs, HRIR, 0x0100);
724 write_reg_le32(par->dc_regs, CMR, 0x00ff);
725 write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
726 } else {
727 write_reg_le32(par->dc_regs, HRIR, 0x0200);
728 write_reg_le32(par->dc_regs, CMR, 0x01ff);
729 write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
730 }
731
732 switch (info->fix.smem_len) {
733 case 0x200000:
734 scr = 0x059d | byteswap;
735 break;
736 /* case 0x400000:
737 case 0x800000: */
738 default:
739 pitch >>= 1;
740 scr = 0x150dd | byteswap;
741 break;
742 }
743
744 write_reg_le32(par->dc_regs, SCR, scr);
745 write_reg_le32(par->dc_regs, SPR, pitch);
746 write_reg_le32(par->dc_regs, STGCTL, ctl);
747}
748
749static inline void
750set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
751{
752 struct imstt_par *par = (struct imstt_par *) info->par;
753 __u32 off = var->yoffset * (info->fix.line_length >> 3)
754 + ((var->xoffset * (var->bits_per_pixel >> 3)) >> 3);
755 write_reg_le32(par->dc_regs, SSR, off);
756}
757
758static inline void
759set_555 (struct imstt_par *par)
760{
761 if (par->ramdac == IBM) {
762 par->cmap_regs[PIDXHI] = 0; eieio();
763 par->cmap_regs[PIDXLO] = BPP16; eieio();
764 par->cmap_regs[PIDXDATA] = 0x01; eieio();
765 } else {
766 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
767 par->cmap_regs[TVPIDATA] = 0x44; eieio();
768 }
769}
770
771static inline void
772set_565 (struct imstt_par *par)
773{
774 if (par->ramdac == IBM) {
775 par->cmap_regs[PIDXHI] = 0; eieio();
776 par->cmap_regs[PIDXLO] = BPP16; eieio();
777 par->cmap_regs[PIDXDATA] = 0x03; eieio();
778 } else {
779 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
780 par->cmap_regs[TVPIDATA] = 0x45; eieio();
781 }
782}
783
784static int
785imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
786{
787 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
788 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
789 || var->xres_virtual < var->xres || var->yres_virtual < var->yres
790 || var->nonstd
791 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
792 return -EINVAL;
793
794 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
795 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
796 return -EINVAL;
797
798 switch (var->bits_per_pixel) {
799 case 8:
800 var->red.offset = 0;
801 var->red.length = 8;
802 var->green.offset = 0;
803 var->green.length = 8;
804 var->blue.offset = 0;
805 var->blue.length = 8;
806 var->transp.offset = 0;
807 var->transp.length = 0;
808 break;
809 case 16: /* RGB 555 or 565 */
810 if (var->green.length != 6)
811 var->red.offset = 10;
812 var->red.length = 5;
813 var->green.offset = 5;
814 if (var->green.length != 6)
815 var->green.length = 5;
816 var->blue.offset = 0;
817 var->blue.length = 5;
818 var->transp.offset = 0;
819 var->transp.length = 0;
820 break;
821 case 24: /* RGB 888 */
822 var->red.offset = 16;
823 var->red.length = 8;
824 var->green.offset = 8;
825 var->green.length = 8;
826 var->blue.offset = 0;
827 var->blue.length = 8;
828 var->transp.offset = 0;
829 var->transp.length = 0;
830 break;
831 case 32: /* RGBA 8888 */
832 var->red.offset = 16;
833 var->red.length = 8;
834 var->green.offset = 8;
835 var->green.length = 8;
836 var->blue.offset = 0;
837 var->blue.length = 8;
838 var->transp.offset = 24;
839 var->transp.length = 8;
840 break;
841 }
842
843 if (var->yres == var->yres_virtual) {
844 __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
845 var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
846 if (var->yres_virtual < var->yres)
847 var->yres_virtual = var->yres;
848 }
849
850 var->red.msb_right = 0;
851 var->green.msb_right = 0;
852 var->blue.msb_right = 0;
853 var->transp.msb_right = 0;
854 var->height = -1;
855 var->width = -1;
856 var->vmode = FB_VMODE_NONINTERLACED;
857 var->left_margin = var->right_margin = 16;
858 var->upper_margin = var->lower_margin = 16;
859 var->hsync_len = var->vsync_len = 8;
860 return 0;
861}
862
863static int
864imsttfb_set_par(struct fb_info *info)
865{
866 struct imstt_par *par = (struct imstt_par *) info->par;
867
868 if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
869 return -EINVAL;
870
871 if (info->var.green.length == 6)
872 set_565(par);
873 else
874 set_555(par);
875 set_imstt_regvals(info, info->var.bits_per_pixel);
876 info->var.pixclock = 1000000 / getclkMHz(par);
877 return 0;
878}
879
880static int
881imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
882 u_int transp, struct fb_info *info)
883{
884 struct imstt_par *par = (struct imstt_par *) info->par;
885 u_int bpp = info->var.bits_per_pixel;
886
887 if (regno > 255)
888 return 1;
889
890 red >>= 8;
891 green >>= 8;
892 blue >>= 8;
893
894 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
895 if (0 && bpp == 16) /* screws up X */
896 par->cmap_regs[PADDRW] = regno << 3;
897 else
898 par->cmap_regs[PADDRW] = regno;
899 eieio();
900
901 par->cmap_regs[PDATA] = red; eieio();
902 par->cmap_regs[PDATA] = green; eieio();
903 par->cmap_regs[PDATA] = blue; eieio();
904
905 if (regno < 16)
906 switch (bpp) {
907 case 16:
908 ((u16 *)info->pseudo_palette)[regno] = (regno << (info->var.green.length == 5 ? 10 : 11)) | (regno << 5) | regno;
909 break;
910 case 24:
911 ((u32 *)info->pseudo_palette)[regno] = (regno << 16) | (regno << 8) | regno;
912 break;
913 case 32: {
914 int i = (regno << 8) | regno;
915 ((u32 *)info->pseudo_palette)[regno] = (i << 16) | i;
916 break;
917 }
918 }
919 return 0;
920}
921
922static int
923imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
924{
925 if (var->xoffset + info->var.xres > info->var.xres_virtual
926 || var->yoffset + info->var.yres > info->var.yres_virtual)
927 return -EINVAL;
928
929 info->var.xoffset = var->xoffset;
930 info->var.yoffset = var->yoffset;
931 set_offset(var, info);
932 return 0;
933}
934
935static int
936imsttfb_blank(int blank, struct fb_info *info)
937{
938 struct imstt_par *par = (struct imstt_par *) info->par;
939 __u32 ctrl;
940
941 ctrl = read_reg_le32(par->dc_regs, STGCTL);
942 if (blank > 0) {
943 switch (blank) {
944 case FB_BLANK_NORMAL:
945 case FB_BLANK_POWERDOWN:
946 ctrl &= ~0x00000380;
947 if (par->ramdac == IBM) {
948 par->cmap_regs[PIDXHI] = 0; eieio();
949 par->cmap_regs[PIDXLO] = MISCTL2; eieio();
950 par->cmap_regs[PIDXDATA] = 0x55; eieio();
951 par->cmap_regs[PIDXLO] = MISCTL1; eieio();
952 par->cmap_regs[PIDXDATA] = 0x11; eieio();
953 par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
954 par->cmap_regs[PIDXDATA] = 0x0f; eieio();
955 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
956 par->cmap_regs[PIDXDATA] = 0x1f; eieio();
957 par->cmap_regs[PIDXLO] = CLKCTL; eieio();
958 par->cmap_regs[PIDXDATA] = 0xc0;
959 }
960 break;
961 case FB_BLANK_VSYNC_SUSPEND:
962 ctrl &= ~0x00000020;
963 break;
964 case FB_BLANK_HSYNC_SUSPEND:
965 ctrl &= ~0x00000010;
966 break;
967 }
968 } else {
969 if (par->ramdac == IBM) {
970 ctrl |= 0x000017b0;
971 par->cmap_regs[PIDXHI] = 0; eieio();
972 par->cmap_regs[PIDXLO] = CLKCTL; eieio();
973 par->cmap_regs[PIDXDATA] = 0x01; eieio();
974 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
975 par->cmap_regs[PIDXDATA] = 0x00; eieio();
976 par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
977 par->cmap_regs[PIDXDATA] = 0x00; eieio();
978 par->cmap_regs[PIDXLO] = MISCTL1; eieio();
979 par->cmap_regs[PIDXDATA] = 0x01; eieio();
980 par->cmap_regs[PIDXLO] = MISCTL2; eieio();
981 par->cmap_regs[PIDXDATA] = 0x45; eieio();
982 } else
983 ctrl |= 0x00001780;
984 }
985 write_reg_le32(par->dc_regs, STGCTL, ctrl);
986 return 0;
987}
988
989static void
990imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
991{
992 struct imstt_par *par = (struct imstt_par *) info->par;
993 __u32 Bpp, line_pitch, bgc, dx, dy, width, height;
994
995 bgc = rect->color;
996 bgc |= (bgc << 8);
997 bgc |= (bgc << 16);
998
999 Bpp = info->var.bits_per_pixel >> 3,
1000 line_pitch = info->fix.line_length;
1001
1002 dy = rect->dy * line_pitch;
1003 dx = rect->dx * Bpp;
1004 height = rect->height;
1005 height--;
1006 width = rect->width * Bpp;
1007 width--;
1008
1009 if (rect->rop == ROP_COPY) {
1010 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1011 write_reg_le32(par->dc_regs, DSA, dy + dx);
1012 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1013 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1014 write_reg_le32(par->dc_regs, BI, 0xffffffff);
1015 write_reg_le32(par->dc_regs, MBC, 0xffffffff);
1016 write_reg_le32(par->dc_regs, CLR, bgc);
1017 write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
1018 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1019 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1020 } else {
1021 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1022 write_reg_le32(par->dc_regs, DSA, dy + dx);
1023 write_reg_le32(par->dc_regs, S1SA, dy + dx);
1024 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1025 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1026 write_reg_le32(par->dc_regs, SP, line_pitch);
1027 write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
1028 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1029 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1030 }
1031}
1032
1033static void
1034imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1035{
1036 struct imstt_par *par = (struct imstt_par *) info->par;
1037 __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
1038 __u32 cnt, bltctl, sx, sy, dx, dy, height, width;
1039
1040 Bpp = info->var.bits_per_pixel >> 3,
1041
1042 sx = area->sx * Bpp;
1043 sy = area->sy;
1044 dx = area->dx * Bpp;
1045 dy = area->dy;
1046 height = area->height;
1047 height--;
1048 width = area->width * Bpp;
1049 width--;
1050
1051 line_pitch = info->fix.line_length;
1052 bltctl = 0x05;
1053 sp = line_pitch << 16;
1054 cnt = height << 16;
1055
1056 if (sy < dy) {
1057 sy += height;
1058 dy += height;
1059 sp |= -(line_pitch) & 0xffff;
1060 dp_octl = -(line_pitch) & 0xffff;
1061 } else {
1062 sp |= line_pitch;
1063 dp_octl = line_pitch;
1064 }
1065 if (sx < dx) {
1066 sx += width;
1067 dx += width;
1068 bltctl |= 0x80;
1069 cnt |= -(width) & 0xffff;
1070 } else {
1071 cnt |= width;
1072 }
1073 fb_offset_old = sy * line_pitch + sx;
1074 fb_offset_new = dy * line_pitch + dx;
1075
1076 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1077 write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
1078 write_reg_le32(par->dc_regs, SP, sp);
1079 write_reg_le32(par->dc_regs, DSA, fb_offset_new);
1080 write_reg_le32(par->dc_regs, CNT, cnt);
1081 write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
1082 write_reg_le32(par->dc_regs, BLTCTL, bltctl);
1083 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1084 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1085}
1086
1087#if 0
1088static int
1089imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
1090{
1091 u_int x, y;
1092
1093 if (width > 32 || height > 32)
1094 return -EINVAL;
1095
1096 if (par->ramdac == IBM) {
1097 par->cmap_regs[PIDXHI] = 1; eieio();
1098 for (x = 0; x < 0x100; x++) {
1099 par->cmap_regs[PIDXLO] = x; eieio();
1100 par->cmap_regs[PIDXDATA] = 0x00; eieio();
1101 }
1102 par->cmap_regs[PIDXHI] = 1; eieio();
1103 for (y = 0; y < height; y++)
1104 for (x = 0; x < width >> 2; x++) {
1105 par->cmap_regs[PIDXLO] = x + y * 8; eieio();
1106 par->cmap_regs[PIDXDATA] = 0xff; eieio();
1107 }
1108 par->cmap_regs[PIDXHI] = 0; eieio();
1109 par->cmap_regs[PIDXLO] = CURS1R; eieio();
1110 par->cmap_regs[PIDXDATA] = fgc; eieio();
1111 par->cmap_regs[PIDXLO] = CURS1G; eieio();
1112 par->cmap_regs[PIDXDATA] = fgc; eieio();
1113 par->cmap_regs[PIDXLO] = CURS1B; eieio();
1114 par->cmap_regs[PIDXDATA] = fgc; eieio();
1115 par->cmap_regs[PIDXLO] = CURS2R; eieio();
1116 par->cmap_regs[PIDXDATA] = fgc; eieio();
1117 par->cmap_regs[PIDXLO] = CURS2G; eieio();
1118 par->cmap_regs[PIDXDATA] = fgc; eieio();
1119 par->cmap_regs[PIDXLO] = CURS2B; eieio();
1120 par->cmap_regs[PIDXDATA] = fgc; eieio();
1121 par->cmap_regs[PIDXLO] = CURS3R; eieio();
1122 par->cmap_regs[PIDXDATA] = fgc; eieio();
1123 par->cmap_regs[PIDXLO] = CURS3G; eieio();
1124 par->cmap_regs[PIDXDATA] = fgc; eieio();
1125 par->cmap_regs[PIDXLO] = CURS3B; eieio();
1126 par->cmap_regs[PIDXDATA] = fgc; eieio();
1127 } else {
1128 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1129 par->cmap_regs[TVPIDATA] &= 0x03; eieio();
1130 par->cmap_regs[TVPADDRW] = 0; eieio();
1131 for (x = 0; x < 0x200; x++) {
1132 par->cmap_regs[TVPCRDAT] = 0x00; eieio();
1133 }
1134 for (x = 0; x < 0x200; x++) {
1135 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1136 }
1137 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1138 par->cmap_regs[TVPIDATA] &= 0x03; eieio();
1139 for (y = 0; y < height; y++)
1140 for (x = 0; x < width >> 3; x++) {
1141 par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
1142 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1143 }
1144 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1145 par->cmap_regs[TVPIDATA] |= 0x08; eieio();
1146 for (y = 0; y < height; y++)
1147 for (x = 0; x < width >> 3; x++) {
1148 par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
1149 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1150 }
1151 par->cmap_regs[TVPCADRW] = 0x00; eieio();
1152 for (x = 0; x < 12; x++)
1153 par->cmap_regs[TVPCDATA] = fgc; eieio();
1154 }
1155 return 1;
1156}
1157
1158static void
1159imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
1160{
1161 if (par->ramdac == IBM) {
1162 par->cmap_regs[PIDXHI] = 0; eieio();
1163 if (!on) {
1164 par->cmap_regs[PIDXLO] = CURSCTL; eieio();
1165 par->cmap_regs[PIDXDATA] = 0x00; eieio();
1166 } else {
1167 par->cmap_regs[PIDXLO] = CURSXHI; eieio();
1168 par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio();
1169 par->cmap_regs[PIDXLO] = CURSXLO; eieio();
1170 par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
1171 par->cmap_regs[PIDXLO] = CURSYHI; eieio();
1172 par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio();
1173 par->cmap_regs[PIDXLO] = CURSYLO; eieio();
1174 par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
1175 par->cmap_regs[PIDXLO] = CURSCTL; eieio();
1176 par->cmap_regs[PIDXDATA] = 0x02; eieio();
1177 }
1178 } else {
1179 if (!on) {
1180 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1181 par->cmap_regs[TVPIDATA] = 0x00; eieio();
1182 } else {
1183 __u16 x = d->dx + 0x40, y = d->dy + 0x40;
1184
1185 par->cmap_regs[TVPCXPOH] = x >> 8; eieio();
1186 par->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
1187 par->cmap_regs[TVPCYPOH] = y >> 8; eieio();
1188 par->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
1189 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1190 par->cmap_regs[TVPIDATA] = 0x02; eieio();
1191 }
1192 }
1193}
1194
1195static int
1196imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1197{
1198 struct imstt_par *par = (struct imstt_par *) info->par;
1199 u32 flags = cursor->set, fg, bg, xx, yy;
1200
1201 if (cursor->dest == NULL && cursor->rop == ROP_XOR)
1202 return 1;
1203
1204 imstt_set_cursor(info, cursor, 0);
1205
1206 if (flags & FB_CUR_SETPOS) {
1207 xx = cursor->image.dx - info->var.xoffset;
1208 yy = cursor->image.dy - info->var.yoffset;
1209 }
1210
1211 if (flags & FB_CUR_SETSIZE) {
1212 }
1213
1214 if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
1215 int fg_idx = cursor->image.fg_color;
1216 int width = (cursor->image.width+7)/8;
1217 u8 *dat = (u8 *) cursor->image.data;
1218 u8 *dst = (u8 *) cursor->dest;
1219 u8 *msk = (u8 *) cursor->mask;
1220
1221 switch (cursor->rop) {
1222 case ROP_XOR:
1223 for (i = 0; i < cursor->image.height; i++) {
1224 for (j = 0; j < width; j++) {
1225 d_idx = i * MAX_CURS/8 + j;
1226 data[d_idx] = byte_rev[dat[s_idx] ^
1227 dst[s_idx]];
1228 mask[d_idx] = byte_rev[msk[s_idx]];
1229 s_idx++;
1230 }
1231 }
1232 break;
1233 case ROP_COPY:
1234 default:
1235 for (i = 0; i < cursor->image.height; i++) {
1236 for (j = 0; j < width; j++) {
1237 d_idx = i * MAX_CURS/8 + j;
1238 data[d_idx] = byte_rev[dat[s_idx]];
1239 mask[d_idx] = byte_rev[msk[s_idx]];
1240 s_idx++;
1241 }
1242 }
1243 break;
1244 }
1245
1246 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1247 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1248 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1249
1250 imsttfb_load_cursor_image(par, xx, yy, fgc);
1251 }
1252 if (cursor->enable)
1253 imstt_set_cursor(info, cursor, 1);
1254 return 0;
1255}
1256#endif
1257
1258#define FBIMSTT_SETREG 0x545401
1259#define FBIMSTT_GETREG 0x545402
1260#define FBIMSTT_SETCMAPREG 0x545403
1261#define FBIMSTT_GETCMAPREG 0x545404
1262#define FBIMSTT_SETIDXREG 0x545405
1263#define FBIMSTT_GETIDXREG 0x545406
1264
1265static int
1266imsttfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1267 u_long arg, struct fb_info *info)
1268{
1269 struct imstt_par *par = (struct imstt_par *) info->par;
1270 void __user *argp = (void __user *)arg;
1271 __u32 reg[2];
1272 __u8 idx[2];
1273
1274 switch (cmd) {
1275 case FBIMSTT_SETREG:
1276 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1277 return -EFAULT;
1278 write_reg_le32(par->dc_regs, reg[0], reg[1]);
1279 return 0;
1280 case FBIMSTT_GETREG:
1281 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1282 return -EFAULT;
1283 reg[1] = read_reg_le32(par->dc_regs, reg[0]);
1284 if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1285 return -EFAULT;
1286 return 0;
1287 case FBIMSTT_SETCMAPREG:
1288 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1289 return -EFAULT;
Al Virof815e812005-04-26 07:43:42 -0700[diff] [blame]1290 write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1291 return 0;
1292 case FBIMSTT_GETCMAPREG:
1293 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1294 return -EFAULT;
Al Virof815e812005-04-26 07:43:42 -0700[diff] [blame]1295 reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1296 if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1297 return -EFAULT;
1298 return 0;
1299 case FBIMSTT_SETIDXREG:
1300 if (copy_from_user(idx, argp, 2))
1301 return -EFAULT;
1302 par->cmap_regs[PIDXHI] = 0; eieio();
1303 par->cmap_regs[PIDXLO] = idx[0]; eieio();
1304 par->cmap_regs[PIDXDATA] = idx[1]; eieio();
1305 return 0;
1306 case FBIMSTT_GETIDXREG:
1307 if (copy_from_user(idx, argp, 1))
1308 return -EFAULT;
1309 par->cmap_regs[PIDXHI] = 0; eieio();
1310 par->cmap_regs[PIDXLO] = idx[0]; eieio();
1311 idx[1] = par->cmap_regs[PIDXDATA];
1312 if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
1313 return -EFAULT;
1314 return 0;
1315 default:
1316 return -ENOIOCTLCMD;
1317 }
1318}
1319
1320static struct pci_device_id imsttfb_pci_tbl[] = {
1321 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
1322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
1323 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
1324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
1325 { 0, }
1326};
1327
1328MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
1329
1330static struct pci_driver imsttfb_pci_driver = {
1331 .name = "imsttfb",
1332 .id_table = imsttfb_pci_tbl,
1333 .probe = imsttfb_probe,
1334 .remove = __devexit_p(imsttfb_remove),
1335};
1336
1337static struct fb_ops imsttfb_ops = {
1338 .owner = THIS_MODULE,
1339 .fb_check_var = imsttfb_check_var,
1340 .fb_set_par = imsttfb_set_par,
1341 .fb_setcolreg = imsttfb_setcolreg,
1342 .fb_pan_display = imsttfb_pan_display,
1343 .fb_blank = imsttfb_blank,
1344 .fb_fillrect = imsttfb_fillrect,
1345 .fb_copyarea = imsttfb_copyarea,
1346 .fb_imageblit = cfb_imageblit,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1347 .fb_ioctl = imsttfb_ioctl,
1348};
1349
1350static void __devinit
1351init_imstt(struct fb_info *info)
1352{
1353 struct imstt_par *par = (struct imstt_par *) info->par;
1354 __u32 i, tmp, *ip, *end;
1355
1356 tmp = read_reg_le32(par->dc_regs, PRC);
1357 if (par->ramdac == IBM)
1358 info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
1359 else
1360 info->fix.smem_len = 0x800000;
1361
1362 ip = (__u32 *)info->screen_base;
1363 end = (__u32 *)(info->screen_base + info->fix.smem_len);
1364 while (ip < end)
1365 *ip++ = 0;
1366
1367 /* initialize the card */
1368 tmp = read_reg_le32(par->dc_regs, STGCTL);
1369 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
1370 write_reg_le32(par->dc_regs, SSR, 0);
1371
1372 /* set default values for DAC registers */
1373 if (par->ramdac == IBM) {
1374 par->cmap_regs[PPMASK] = 0xff; eieio();
1375 par->cmap_regs[PIDXHI] = 0; eieio();
1376 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
1377 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio();
1378 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio();
1379 }
1380 } else {
1381 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
1382 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio();
1383 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio();
1384 }
1385 }
1386
1387#if USE_NV_MODES && defined(CONFIG_PPC)
1388 {
1389 int vmode = init_vmode, cmode = init_cmode;
1390
1391 if (vmode == -1) {
1392 vmode = nvram_read_byte(NV_VMODE);
1393 if (vmode <= 0 || vmode > VMODE_MAX)
1394 vmode = VMODE_640_480_67;
1395 }
1396 if (cmode == -1) {
1397 cmode = nvram_read_byte(NV_CMODE);
1398 if (cmode < CMODE_8 || cmode > CMODE_32)
1399 cmode = CMODE_8;
1400 }
1401 if (mac_vmode_to_var(vmode, cmode, &info->var)) {
1402 info->var.xres = info->var.xres_virtual = INIT_XRES;
1403 info->var.yres = info->var.yres_virtual = INIT_YRES;
1404 info->var.bits_per_pixel = INIT_BPP;
1405 }
1406 }
1407#else
1408 info->var.xres = info->var.xres_virtual = INIT_XRES;
1409 info->var.yres = info->var.yres_virtual = INIT_YRES;
1410 info->var.bits_per_pixel = INIT_BPP;
1411#endif
1412
1413 if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
1414 || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
1415 printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
1416 kfree(info);
1417 return;
1418 }
1419
1420 sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
1421 info->fix.mmio_len = 0x1000;
1422 info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1423 info->fix.type = FB_TYPE_PACKED_PIXELS;
1424 info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1425 : FB_VISUAL_DIRECTCOLOR;
1426 info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
1427 info->fix.xpanstep = 8;
1428 info->fix.ypanstep = 1;
1429 info->fix.ywrapstep = 0;
1430
1431 info->var.accel_flags = FB_ACCELF_TEXT;
1432
1433// if (par->ramdac == IBM)
1434// imstt_cursor_init(info);
1435 if (info->var.green.length == 6)
1436 set_565(par);
1437 else
1438 set_555(par);
1439 set_imstt_regvals(info, info->var.bits_per_pixel);
1440
1441 info->var.pixclock = 1000000 / getclkMHz(par);
1442
1443 info->fbops = &imsttfb_ops;
1444 info->flags = FBINFO_DEFAULT |
1445 FBINFO_HWACCEL_COPYAREA |
1446 FBINFO_HWACCEL_FILLRECT |
1447 FBINFO_HWACCEL_YPAN;
1448
1449 fb_alloc_cmap(&info->cmap, 0, 0);
1450
1451 if (register_framebuffer(info) < 0) {
1452 kfree(info);
1453 return;
1454 }
1455
1456 tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
1457 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1458 info->node, info->fix.id, info->fix.smem_len >> 20, tmp);
1459}
1460
1461static int __devinit
1462imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1463{
1464 unsigned long addr, size;
1465 struct imstt_par *par;
1466 struct fb_info *info;
1467#ifdef CONFIG_PPC_OF
1468 struct device_node *dp;
1469
1470 dp = pci_device_to_OF_node(pdev);
1471 if(dp)
1472 printk(KERN_INFO "%s: OF name %s\n",__FUNCTION__, dp->name);
1473 else
1474 printk(KERN_ERR "imsttfb: no OF node for pci device\n");
1475#endif /* CONFIG_PPC_OF */
1476
1477 size = sizeof(struct fb_info) + sizeof(struct imstt_par) +
1478 sizeof(u32) * 16;
1479
1480 info = kmalloc(size, GFP_KERNEL);
1481
1482 if (!info) {
1483 printk(KERN_ERR "imsttfb: Can't allocate memory\n");
1484 return -ENOMEM;
1485 }
1486
1487 memset(info, 0, size);
1488
1489 par = (struct imstt_par *) (info + 1);
1490
1491 addr = pci_resource_start (pdev, 0);
1492 size = pci_resource_len (pdev, 0);
1493
1494 if (!request_mem_region(addr, size, "imsttfb")) {
1495 printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
1496 kfree(info);
1497 return -ENODEV;
1498 }
1499
1500 switch (pdev->device) {
1501 case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
1502 par->ramdac = IBM;
1503#ifdef CONFIG_PPC_OF
1504 if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) ||
1505 (strcmp(dp->name, "IMS,tt128mb8A") == 0)))
1506 par->ramdac = TVP;
1507#endif /* CONFIG_PPC_OF */
1508 break;
1509 case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */
1510 par->ramdac = TVP;
1511 break;
1512 default:
1513 printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
1514 "contact maintainer.\n", pdev->device);
1515 return -ENODEV;
1516 }
1517
1518 info->fix.smem_start = addr;
1519 info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 0x400000 : 0x800000);
1520 info->fix.mmio_start = addr + 0x800000;
1521 par->dc_regs = ioremap(addr + 0x800000, 0x1000);
1522 par->cmap_regs_phys = addr + 0x840000;
1523 par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1524 info->par = par;
1525 info->pseudo_palette = (void *) (par + 1);
1526 info->device = &pdev->dev;
1527 init_imstt(info);
1528
1529 pci_set_drvdata(pdev, info);
1530 return 0;
1531}
1532
1533static void __devexit
1534imsttfb_remove(struct pci_dev *pdev)
1535{
1536 struct fb_info *info = pci_get_drvdata(pdev);
1537 struct imstt_par *par = (struct imstt_par *) info->par;
1538 int size = pci_resource_len(pdev, 0);
1539
1540 unregister_framebuffer(info);
1541 iounmap(par->cmap_regs);
1542 iounmap(par->dc_regs);
1543 iounmap(info->screen_base);
1544 release_mem_region(info->fix.smem_start, size);
1545 kfree(info);
1546}
1547
1548#ifndef MODULE
1549static int __init
1550imsttfb_setup(char *options)
1551{
1552 char *this_opt;
1553
1554 if (!options || !*options)
1555 return 0;
1556
1557 while ((this_opt = strsep(&options, ",")) != NULL) {
1558 if (!strncmp(this_opt, "font:", 5)) {
1559 char *p;
1560 int i;
1561
1562 p = this_opt + 5;
1563 for (i = 0; i < sizeof(fontname) - 1; i++)
1564 if (!*p || *p == ' ' || *p == ',')
1565 break;
1566 memcpy(fontname, this_opt + 5, i);
1567 fontname[i] = 0;
1568 } else if (!strncmp(this_opt, "inverse", 7)) {
1569 inverse = 1;
1570 fb_invert_cmaps();
1571 }
1572#if defined(CONFIG_PPC)
1573 else if (!strncmp(this_opt, "vmode:", 6)) {
1574 int vmode = simple_strtoul(this_opt+6, NULL, 0);
1575 if (vmode > 0 && vmode <= VMODE_MAX)
1576 init_vmode = vmode;
1577 } else if (!strncmp(this_opt, "cmode:", 6)) {
1578 int cmode = simple_strtoul(this_opt+6, NULL, 0);
1579 switch (cmode) {
1580 case CMODE_8:
1581 case 8:
1582 init_cmode = CMODE_8;
1583 break;
1584 case CMODE_16:
1585 case 15:
1586 case 16:
1587 init_cmode = CMODE_16;
1588 break;
1589 case CMODE_32:
1590 case 24:
1591 case 32:
1592 init_cmode = CMODE_32;
1593 break;
1594 }
1595 }
1596#endif
1597 }
1598 return 0;
1599}
1600
1601#endif /* MODULE */
1602
1603static int __init imsttfb_init(void)
1604{
1605#ifndef MODULE
1606 char *option = NULL;
1607
1608 if (fb_get_options("imsttfb", &option))
1609 return -ENODEV;
1610
1611 imsttfb_setup(option);
1612#endif
1613 return pci_register_driver(&imsttfb_pci_driver);
1614}
1615
1616static void __exit imsttfb_exit(void)
1617{
1618 pci_unregister_driver(&imsttfb_pci_driver);
1619}
1620
1621MODULE_LICENSE("GPL");
1622
1623module_init(imsttfb_init);
1624module_exit(imsttfb_exit);
1625