| Vitaly Bordug | a6dbba7 | 2005-05-28 15:52:09 -0700 | [diff] [blame] | 1 | |
| 2 | #ifndef _PPC_KERNEL_M82XX_PCI_H |
| 3 | #define _PPC_KERNEL_M82XX_PCI_H |
| 4 | |
| 5 | #include <asm/m8260_pci.h> |
| 6 | /* |
| 7 | * Local->PCI map (from CPU) controlled by |
| 8 | * MPC826x master window |
| 9 | * |
| 10 | * 0xF6000000 - 0xF7FFFFFF IO space |
| 11 | * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0 |
| 12 | * |
| 13 | * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1) |
| 14 | * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2) |
| 15 | * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3) |
| 16 | * |
| 17 | * PCI->Local map (from PCI) |
| 18 | * MPC826x slave window controlled by |
| 19 | * |
| 20 | * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1) |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Slave window that allows PCI masters to access MPC826x local memory. |
| 25 | * This window is set up using the first set of Inbound ATU registers |
| 26 | */ |
| 27 | |
| 28 | #ifndef M82xx_PCI_SLAVE_MEM_LOCAL |
| 29 | #define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart) |
| 30 | #define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart) |
| 31 | #define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize) |
| 32 | #endif |
| 33 | |
| 34 | /* |
| 35 | * This is the window that allows the CPU to access PCI address space. |
| 36 | * It will be setup with the SIU PCIBR0 register. All three PCI master |
| 37 | * windows, which allow the CPU to access PCI prefetch, non prefetch, |
| 38 | * and IO space (see below), must all fit within this window. |
| 39 | */ |
| 40 | |
| 41 | #ifndef M82xx_PCI_LOWER_MEM |
| 42 | #define M82xx_PCI_LOWER_MEM 0x80000000 |
| 43 | #define M82xx_PCI_UPPER_MEM 0x9fffffff |
| 44 | #define M82xx_PCI_MEM_OFFSET 0x00000000 |
| 45 | #define M82xx_PCI_MEM_SIZE 0x20000000 |
| 46 | #endif |
| 47 | |
| 48 | #ifndef M82xx_PCI_LOWER_MMIO |
| 49 | #define M82xx_PCI_LOWER_MMIO 0xa0000000 |
| 50 | #define M82xx_PCI_UPPER_MMIO 0xafffffff |
| 51 | #define M82xx_PCI_MMIO_OFFSET 0x00000000 |
| 52 | #define M82xx_PCI_MMIO_SIZE 0x20000000 |
| 53 | #endif |
| 54 | |
| 55 | #ifndef M82xx_PCI_LOWER_IO |
| 56 | #define M82xx_PCI_LOWER_IO 0x00000000 |
| 57 | #define M82xx_PCI_UPPER_IO 0x01ffffff |
| 58 | #define M82xx_PCI_IO_BASE 0xf6000000 |
| 59 | #define M82xx_PCI_IO_SIZE 0x02000000 |
| 60 | #endif |
| 61 | |
| 62 | #ifndef M82xx_PCI_PRIM_WND_SIZE |
| 63 | #define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U) |
| 64 | #define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE) |
| 65 | #endif |
| 66 | |
| 67 | #ifndef M82xx_PCI_SEC_WND_SIZE |
| 68 | #define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U) |
| 69 | #define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM) |
| 70 | #endif |
| 71 | |
| 72 | #ifndef POTA_ADDR_SHIFT |
| 73 | #define POTA_ADDR_SHIFT 12 |
| 74 | #endif |
| 75 | |
| 76 | #ifndef PITA_ADDR_SHIFT |
| 77 | #define PITA_ADDR_SHIFT 12 |
| 78 | #endif |
| 79 | |
| 80 | #ifndef _IO_BASE |
| 81 | #define _IO_BASE isa_io_base |
| 82 | #endif |
| 83 | |
| 84 | #ifdef CONFIG_8260_PCI9 |
| 85 | struct pci_controller; |
| 86 | extern void setup_m8260_indirect_pci(struct pci_controller* hose, |
| 87 | u32 cfg_addr, u32 cfg_data); |
| 88 | #else |
| 89 | #define setup_m8260_indirect_pci setup_indirect_pci |
| 90 | #endif |
| 91 | |
| 92 | #endif /* _PPC_KERNEL_M8260_PCI_H */ |