Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / afbf7c2c7ca528b55f36724e901b815d1c245d61 / . / arch / arm / mach-msm / acpuclock-copper.c
blob: 1a02c069e88b5fcdbb31b7a71bef49cebac1216f [file] [log] [blame]
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]1/*
2 * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <mach/rpm-regulator.h>
17#include <mach/msm_bus_board.h>
18#include <mach/msm_bus.h>
19#include <mach/socinfo.h>
20
21#include "acpuclock.h"
22#include "acpuclock-krait.h"
23
24/* Corner type vreg VDD values */
25#define LVL_NONE RPM_VREG_CORNER_NONE
26#define LVL_LOW RPM_VREG_CORNER_LOW
27#define LVL_NOM RPM_VREG_CORNER_NOMINAL
28#define LVL_HIGH RPM_VREG_CORNER_HIGH
29
30static struct hfpll_data hfpll_data_cpu = {
31 .mode_offset = 0x00,
32 .l_offset = 0x04,
33 .m_offset = 0x08,
34 .n_offset = 0x0C,
35 .config_offset = 0x14,
36 /* TODO: Verify magic number for copper when available. */
37 .config_val = 0x7845C665,
38 .low_vdd_l_max = 52,
39 .vdd[HFPLL_VDD_NONE] = 0,
40 .vdd[HFPLL_VDD_LOW] = 810000,
41 .vdd[HFPLL_VDD_NOM] = 900000,
42};
43
44static struct hfpll_data hfpll_data_l2 = {
45 .mode_offset = 0x00,
46 .l_offset = 0x04,
47 .m_offset = 0x08,
48 .n_offset = 0x0C,
49 .config_offset = 0x14,
50 /* TODO: Verify magic number for copper when available. */
51 .config_val = 0x7845C665,
52 .low_vdd_l_max = 52,
53 .vdd[HFPLL_VDD_NONE] = LVL_NONE,
54 .vdd[HFPLL_VDD_LOW] = LVL_LOW,
55 .vdd[HFPLL_VDD_NOM] = LVL_NOM,
56};
57
58static struct scalable scalable[] = {
59 [CPU0] = {
60 .hfpll_phys_base = 0xF908A000,
61 .hfpll_data = &hfpll_data_cpu,
62 .l2cpmr_iaddr = 0x4501,
63 .vreg[VREG_CORE] = { "krait0", 1050000, 3200000 },
64 .vreg[VREG_MEM] = { "krait0_mem", 1050000, 0,
65 RPM_VREG_VOTER1,
66 RPM_VREG_ID_PM8941_S1 },
67 .vreg[VREG_DIG] = { "krait0_dig", 1050000, 0,
68 RPM_VREG_VOTER1,
69 RPM_VREG_ID_PM8941_S2 },
70 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
71 RPM_VREG_VOTER1,
72 RPM_VREG_ID_PM8941_L12 },
73 },
74 [CPU1] = {
75 .hfpll_phys_base = 0xF909A000,
76 .hfpll_data = &hfpll_data_cpu,
77 .l2cpmr_iaddr = 0x5501,
78 .vreg[VREG_CORE] = { "krait1", 1050000, 3200000 },
79 .vreg[VREG_MEM] = { "krait1_mem", 1050000, 0,
80 RPM_VREG_VOTER2,
81 RPM_VREG_ID_PM8941_S1 },
82 .vreg[VREG_DIG] = { "krait1_dig", 1050000, 0,
83 RPM_VREG_VOTER2,
84 RPM_VREG_ID_PM8941_S2 },
85 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
86 RPM_VREG_VOTER2,
87 RPM_VREG_ID_PM8941_L12 },
88 },
89 [CPU2] = {
90 .hfpll_phys_base = 0xF90AA000,
91 .hfpll_data = &hfpll_data_cpu,
92 .l2cpmr_iaddr = 0x6501,
93 .vreg[VREG_CORE] = { "krait2", 1050000, 3200000 },
94 .vreg[VREG_MEM] = { "krait2_mem", 1050000, 0,
95 RPM_VREG_VOTER4,
96 RPM_VREG_ID_PM8921_S1 },
97 .vreg[VREG_DIG] = { "krait2_dig", 1050000, 0,
98 RPM_VREG_VOTER4,
99 RPM_VREG_ID_PM8921_S2 },
100 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
101 RPM_VREG_VOTER4,
102 RPM_VREG_ID_PM8941_L12 },
103 },
104 [CPU3] = {
105 .hfpll_phys_base = 0xF90BA000,
106 .hfpll_data = &hfpll_data_cpu,
107 .l2cpmr_iaddr = 0x7501,
108 .vreg[VREG_CORE] = { "krait3", 1050000, 3200000 },
109 .vreg[VREG_MEM] = { "krait3_mem", 1050000, 0,
110 RPM_VREG_VOTER5,
111 RPM_VREG_ID_PM8941_S1 },
112 .vreg[VREG_DIG] = { "krait3_dig", 1050000, 0,
113 RPM_VREG_VOTER5,
114 RPM_VREG_ID_PM8941_S2 },
115 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
116 RPM_VREG_VOTER5,
117 RPM_VREG_ID_PM8941_L12 },
118 },
119 [L2] = {
120 .hfpll_phys_base = 0xF9016000,
121 .hfpll_data = &hfpll_data_l2,
122 .l2cpmr_iaddr = 0x0500,
123 .vreg[VREG_HFPLL_A] = { "hfpll", 1800000, 0,
124 RPM_VREG_VOTER6,
125 RPM_VREG_ID_PM8941_L12 },
126 },
127};
128
129static struct msm_bus_paths bw_level_tbl[] = {
130 [0] = BW_MBPS(400), /* At least 50 MHz on bus. */
131 [1] = BW_MBPS(800), /* At least 100 MHz on bus. */
132 [2] = BW_MBPS(1334), /* At least 167 MHz on bus. */
133 [3] = BW_MBPS(2666), /* At least 200 MHz on bus. */
134 [4] = BW_MBPS(3200), /* At least 333 MHz on bus. */
135};
136
137static struct msm_bus_scale_pdata bus_scale_data = {
138 .usecase = bw_level_tbl,
139 .num_usecases = ARRAY_SIZE(bw_level_tbl),
140 .active_only = 1,
141 .name = "acpuclk-copper",
142};
143
144#define L2(x) (&l2_freq_tbl[(x)])
145static struct l2_level l2_freq_tbl[] = {
146 [0] = { {STBY_KHZ, QSB, 0, 0, 0 }, LVL_NOM, 1050000, 0 },
147 [1] = { { 300000, PLL_0, 0, 2, 0 }, LVL_NOM, 1050000, 2 },
148 [2] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 1050000, 2 },
149 [3] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 1050000, 2 },
150 [4] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 1050000, 2 },
151 [5] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 1050000, 3 },
152 [6] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 1050000, 3 },
153 [7] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 1050000, 3 },
154 [8] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 1050000, 3 },
155 [9] = { { 883200, HFPLL, 1, 0, 46 }, LVL_NOM, 1050000, 4 },
156 [10] = { { 960000, HFPLL, 1, 0, 50 }, LVL_NOM, 1050000, 4 },
157 [11] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_NOM, 1050000, 4 },
158};
159
160static struct acpu_level acpu_freq_tbl[] = {
161 { 0, {STBY_KHZ, QSB, 0, 0, 0 }, L2(0), 1050000 },
162 { 1, { 300000, PLL_0, 0, 2, 0 }, L2(1), 1050000 },
163 { 1, { 384000, HFPLL, 2, 0, 40 }, L2(2), 1050000 },
164 { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 1050000 },
165 { 1, { 537600, HFPLL, 1, 0, 28 }, L2(4), 1050000 },
166 { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 1050000 },
167 { 1, { 652800, HFPLL, 1, 0, 34 }, L2(6), 1050000 },
168 { 1, { 729600, HFPLL, 1, 0, 38 }, L2(7), 1050000 },
169 { 1, { 806400, HFPLL, 1, 0, 42 }, L2(8), 1050000 },
170 { 1, { 883200, HFPLL, 1, 0, 46 }, L2(9), 1050000 },
171 { 1, { 960000, HFPLL, 1, 0, 50 }, L2(10), 1050000 },
172 { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(11), 1050000 },
173 { 0, { 0 } }
174};
175
176static struct acpuclk_krait_params acpuclk_copper_params = {
177 .scalable = scalable,
178 .pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,
179 .pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,
180 .pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,
181 .l2_freq_tbl = l2_freq_tbl,
182 .l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),
183 .bus_scale_data = &bus_scale_data,
184 .qfprom_phys_base = 0xFC4A8000,
185};
186
187static int __init acpuclk_copper_probe(struct platform_device *pdev)
188{
189 return acpuclk_krait_init(&pdev->dev, &acpuclk_copper_params);
190}
191
192static struct of_device_id acpuclk_copper_match_table[] = {
193 { .compatible = "qcom,acpuclk-copper" },
194 {}
195};
196
197static struct platform_driver acpuclk_copper_driver = {
198 .driver = {
199 .name = "acpuclk-copper",
200 .of_match_table = acpuclk_copper_match_table,
201 .owner = THIS_MODULE,
202 },
203};
204
205static int __init acpuclk_8960_init(void)
206{
207 return platform_driver_probe(&acpuclk_copper_driver,
208 acpuclk_copper_probe);
209}
210device_initcall(acpuclk_8960_init);