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review.evervolv.com / android_kernel_htc_msm8960 / b1cc493ae3745e18c025cddc51775c4ae8763751 / . / arch / arm / boot / dts / msm8974.dtsi
blob: 446f3100416e377bb49a08191af55094c815d3a1 [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Kevin Chan350b6932012-08-01 02:21:00 -0700[diff] [blame]16/include/ "msm8974-camera.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Olav Haugan49173442012-08-01 13:23:18 -0700[diff] [blame]18/include/ "msm8974-ion.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]19/include/ "msm8974-gpu.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]20
21/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]22 model = "Qualcomm MSM 8974";
23 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]24 interrupt-parent = <&intc>;
25
26 intc: interrupt-controller@F9000000 {
27 compatible = "qcom,msm-qgic2";
28 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]29 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]30 reg = <0xF9000000 0x1000>,
31 <0xF9002000 0x1000>;
32 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]33
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]34 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]35 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -0700[diff] [blame^]36 gpio-controller;
37 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]38 interrupt-controller;
39 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]40 reg = <0xfd510000 0x4000>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]41 };
42
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]43 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]44 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]45 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]46 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]47 };
48
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]49 qcom,vidc@fdc00000 {
50 compatible = "qcom,msm-vidc";
51 reg = <0xfdc00000 0xff000>;
52 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]53 vidc-cp-map = <0x1000000 0x40000000>;
54 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -0700[diff] [blame]55 load-freq-tbl = <979200 410000000>,
56 <560145 266670000>,
57 <421161 200000000>,
58 <243000 133330000>,
59 <108000 100000000>,
60 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]61 };
62
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]63 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]64 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]65 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]66 interrupts = <0 109 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]67 status = "disabled";
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]68 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]69
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]70 serial@f995e000 {
71 compatible = "qcom,msm-lsuart-v14";
72 reg = <0xf995e000 0x1000>;
73 interrupts = <0 114 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]74 status = "disabled";
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]75 };
76
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]77 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]78 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]79 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]80 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]81 HSUSB_VDDCX-supply = <&pm8841_s2>;
82 HSUSB_1p8-supply = <&pm8941_l6>;
83 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]84
85 qcom,hsusb-otg-phy-type = <2>;
86 qcom,hsusb-otg-mode = <1>;
87 qcom,hsusb-otg-otg-control = <1>;
Manu Gautambd53fba2012-07-31 16:13:06 +0530[diff] [blame]88 qcom,hsusb-otg-disable-reset;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]89 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]90
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]91 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]92 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]93 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]94 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]95 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]96 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]97 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]98 vdd-supply = <&pm8941_l20>;
99 vdd-io-supply = <&pm8941_s3>;
100
101 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
102 qcom,sdcc-vdd-current_level = <800 500000>;
103
104 qcom,sdcc-vdd-io-always_on;
105 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
106 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]107
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]108 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
109 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
110 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
111 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
112
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]113 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
114 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]115 qcom,sdcc-bus-width = <8>;
116 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]117 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]118 };
119
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]120 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]121 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]122 compatible = "qcom,msm-sdcc";
123 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]124 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]125 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]126 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]127 vdd-supply = <&pm8941_l21>;
128 vdd-io-supply = <&pm8941_l13>;
129
130 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
131 qcom,sdcc-vdd-current_level = <9000 800000>;
132
133 qcom,sdcc-vdd-io-always_on;
134 qcom,sdcc-vdd-io-lpm_sup;
135 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
136 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]137
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]138 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
139 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
140 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
141 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
142
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]143 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
144 qcom,sdcc-sup-voltages = <2950 2950>;
145 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]146 qcom,sdcc-xpc;
147 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
148 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]149 };
150
151 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]152 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]153 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]154 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]155 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]156 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]157 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]158
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]159 gpios = <&msmgpio 40 0>, /* CLK */
160 <&msmgpio 39 0>, /* CMD */
161 <&msmgpio 38 0>, /* DATA0 */
162 <&msmgpio 37 0>, /* DATA1 */
163 <&msmgpio 36 0>, /* DATA2 */
164 <&msmgpio 35 0>; /* DATA3 */
165 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
166
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]167 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
168 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]169 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]170 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]171 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]172 };
173
174 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]175 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]176 compatible = "qcom,msm-sdcc";
177 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]178 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]179 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]180 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]181
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]182 gpios = <&msmgpio 93 0>, /* CLK */
183 <&msmgpio 91 0>, /* CMD */
184 <&msmgpio 96 0>, /* DATA0 */
185 <&msmgpio 95 0>, /* DATA1 */
186 <&msmgpio 94 0>, /* DATA2 */
187 <&msmgpio 92 0>; /* DATA3 */
188 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
189
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]190 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
191 qcom,sdcc-sup-voltages = <1800 1800>;
192 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]193 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]194 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]195 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]196
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]197 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]198 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]199 reg = <0xf9984000 0x15000>,
200 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]201 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]202
203 qcom,bam-dma-res-pipes = <6>;
204 };
205
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]206
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]207 spi@f9924000 {
208 compatible = "qcom,spi-qup-v2";
209 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]210 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]211 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]212 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]213
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]214 slim@fe12f000 {
215 cell-index = <1>;
216 compatible = "qcom,slim-msm";
217 reg = <0xfe12f000 0x35000>,
218 <0xfe104000 0x20000>;
219 reg-names = "slimbus_physical", "slimbus_bam_physical";
220 interrupts = <0 163 0 0 164 0>;
221 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
222 qcom,min-clk-gear = <10>;
Sagar Dhariac0d6cf52012-07-31 19:17:26 -0600[diff] [blame]223 qcom,rxreg-access;
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]224 };
225
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]226 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]227 cell-index = <0>;
228 compatible = "qcom,spmi-pmic-arb";
229 reg = <0xfc4cf000 0x1000>,
230 <0Xfc4cb000 0x1000>;
231 /* 190,ee0_krait_hlos_spmi_periph_irq */
232 /* 187,channel_0_krait_hlos_trans_done_irq */
233 interrupts = <0 190 0 0 187 0>;
234 qcom,pmic-arb-ee = <0>;
235 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]236 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
237 <0x13100001>, /* PM8941_LDO2 */
238 <0x13200002>, /* PM8941_LDO3 */
239 <0x13300003>, /* PM8941_LDO4 */
240 <0x13400004>, /* PM8941_LDO5 */
241 <0x13500005>, /* PM8941_LDO6 */
242 <0x13600006>, /* PM8941_LDO7 */
243 <0x13700007>, /* PM8941_LDO8 */
244 <0x13800008>, /* PM8941_LDO9 */
245 <0x13900009>, /* PM8941_LDO10 */
246 <0x13a0000a>, /* PM8941_LDO11 */
247 <0x13b0000b>, /* PM8941_LDO12 */
248 <0x13c0000c>, /* PM8941_LDO13 */
249 <0x13d0000d>, /* PM8941_LDO14 */
250 <0x13e0000e>, /* PM8941_LDO15 */
251 <0x13f0000f>, /* PM8941_LDO16 */
252 <0x14000010>, /* PM8941_LDO17 */
253 <0x14100011>, /* PM8941_LDO18 */
254 <0x14200012>, /* PM8941_LDO19 */
255 <0x14300013>, /* PM8941_LDO20 */
256 <0x14400014>, /* PM8941_LDO21 */
257 <0x14500015>, /* PM8941_LDO22 */
258 <0x14600016>, /* PM8941_LDO23 */
259 <0x14700017>, /* PM8941_LDO24 */
260 <0x14800018>, /* PM8941_LDO25 */
261 <0x14900019>, /* PM8941_LDO26 */
262 <0x0c00001a>, /* PM8941_GPIO1 */
263 <0x0c10001b>, /* PM8941_GPIO2 */
264 <0x0c20001c>, /* PM8941_GPIO3 */
265 <0x0c30001d>, /* PM8941_GPIO4 */
266 <0x0c40001e>, /* PM8941_GPIO5 */
267 <0x0c50001f>, /* PM8941_GPIO6 */
268 <0x0c600020>, /* PM8941_GPIO7 */
269 <0x0c700021>, /* PM8941_GPIO8 */
270 <0x0c800022>, /* PM8941_GPIO9 */
271 <0x0c900023>, /* PM8941_GPIO10 */
272 <0x0ca00024>, /* PM8941_GPIO11 */
273 <0x0cb00025>, /* PM8941_GPIO12 */
274 <0x0cc00026>, /* PM8941_GPIO13 */
275 <0x0cd00027>, /* PM8941_GPIO14 */
276 <0x0ce00028>, /* PM8941_GPIO15 */
277 <0x0cf00029>, /* PM8941_GPIO16 */
278 <0x0d00002a>, /* PM8941_GPIO17 */
279 <0x0d10002b>, /* PM8941_GPIO18 */
280 <0x0d20002c>, /* PM8941_GPIO19 */
281 <0x0d30002d>, /* PM8941_GPIO20 */
282 <0x0d40002e>, /* PM8941_GPIO21 */
283 <0x0d50002f>, /* PM8941_GPIO22 */
284 <0x0d600030>, /* PM8941_GPIO23 */
285 <0x0d700031>, /* PM8941_GPIO24 */
286 <0x0d800032>, /* PM8941_GPIO25 */
287 <0x0d900033>, /* PM8941_GPIO26 */
288 <0x0da00034>, /* PM8941_GPIO27 */
289 <0x0db00035>, /* PM8941_GPIO28 */
290 <0x0dc00036>, /* PM8941_GPIO29 */
291 <0x0dd00037>, /* PM8941_GPIO30 */
292 <0x0de00038>, /* PM8941_GPIO31 */
293 <0x0df00039>, /* PM8941_GPIO32 */
294 <0x0e00003a>, /* PM8941_GPIO33 */
295 <0x0e10003b>, /* PM8941_GPIO34 */
296 <0x0e20003c>, /* PM8941_GPIO35 */
297 <0x0e30003d>, /* PM8941_GPIO36 */
298 <0x0280003e>, /* COINCELL */
299 <0x0100003f>, /* SMBC_OVP */
300 <0x01100040>, /* SMBC_CHG */
301 <0x01200041>, /* SMBC_BIF */
302 <0x00500042>, /* INTERRUPT */
303 <0x00100043>, /* PM8941_0 */
304 <0x20100044>, /* PM8841_0 */
305 <0x10100045>, /* PM8941_1 */
306 <0x30100046>, /* PM8841_1 */
307 <0x00800047>, /* PON0 */
308 <0x20800048>, /* PON1 */
309 <0x11000049>, /* PM8941_SMPS1 */
310 <0x1110004a>, /* PM8941_SMPS2 */
311 <0x1120004b>, /* PM8941_SMPS3 */
312 <0x3100004c>, /* PM8841_SMPS1 */
313 <0x3110004d>, /* PM8841_SMPS2 */
314 <0x3120004e>, /* PM8841_SMPS3 */
315 <0x3130004f>, /* PM8841_SMPS4 */
316 <0x31400050>, /* PM8841_SMPS5 */
317 <0x31500051>, /* PM8841_SMPS6 */
318 <0x31600052>, /* PM8841_SMPS7 */
319 <0x31700053>, /* PM8841_SMPS8 */
320 <0x05000054>, /* SHARED_XO */
321 <0x05100055>, /* BB_CLK1 */
322 <0x05200056>, /* BB_CLK2 */
323 <0x05900057>, /* SLEEP_CLK */
324 <0x07000058>, /* PBS_CORE */
325 <0x07100059>, /* PBS_CLIENT1 */
326 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]327 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]328
329 i2c@f9966000 {
330 cell-index = <0>;
331 compatible = "qcom,i2c-qup";
332 reg = <0Xf9966000 0x1000>;
333 reg-names = "qup_phys_addr";
334 interrupts = <0 104 0>;
335 interrupt-names = "qup_err_intr";
336 qcom,i2c-bus-freq = <100000>;
337 qcom,i2c-src-freq = <24000000>;
338 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]339
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]340 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]341 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]342 krait0-supply = <&krait0_vreg>;
343 krait1-supply = <&krait1_vreg>;
344 krait2-supply = <&krait2_vreg>;
345 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]346 krait0_mem-supply = <&pm8841_s1_ao>;
347 krait1_mem-supply = <&pm8841_s1_ao>;
348 krait2_mem-supply = <&pm8841_s1_ao>;
349 krait3_mem-supply = <&pm8841_s1_ao>;
350 krait0_dig-supply = <&pm8841_s2_corner_ao>;
351 krait1_dig-supply = <&pm8841_s2_corner_ao>;
352 krait2_dig-supply = <&pm8841_s2_corner_ao>;
353 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]354 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
355 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
356 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
357 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
358 l2_hfpll_a-supply = <&pm8941_s2_ao>;
359 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
360 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
361 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
362 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
363 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]364 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]365
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]366 qcom,ssusb@f9200000 {
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]367 compatible = "qcom,dwc-usb3-msm";
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]368 reg = <0xf9200000 0xfc000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]369 interrupts = <0 131 0 0 179 0>;
370 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]371 SSUSB_VDDCX-supply = <&pm8841_s2>;
372 SSUSB_1p8-supply = <&pm8941_l6>;
373 HSUSB_VDDCX-supply = <&pm8841_s2>;
374 HSUSB_1p8-supply = <&pm8941_l6>;
375 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]376 qcom,dwc-usb3-msm-dbm-eps = <4>;
377 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]378
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]379 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
380 parent-supply = <&pm8841_s4>;
381 };
382
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]383 qcom,lpass@fe200000 {
384 compatible = "qcom,pil-q6v5-lpass";
385 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]386 <0xfd485100 0x00010>;
387
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]388 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]389 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]390
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]391 qcom,msm-pcm {
392 compatible = "qcom,msm-pcm-dsp";
393 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]394
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]395 qcom,msm-pcm-routing {
396 compatible = "qcom,msm-pcm-routing";
397 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]398
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]399 qcom,msm-pcm-lpa {
400 compatible = "qcom,msm-pcm-lpa";
401 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]402
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]403 qcom,msm-compr-dsp {
404 compatible = "qcom,msm-compr-dsp";
405 };
406
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]407 qcom,msm-voip-dsp {
408 compatible = "qcom,msm-voip-dsp";
409 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]410
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]411 qcom,msm-stub-codec {
412 compatible = "qcom,msm-stub-codec";
413 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]414
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]415 qcom,msm-dai-fe {
416 compatible = "qcom,msm-dai-fe";
417 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]418
Joonwoo Park6572ac52012-07-10 17:17:00 -0700[diff] [blame]419 qcom,msm-dai-q6 {
420 compatible = "qcom,msm-dai-q6";
421 qcom,msm-dai-q6-sb-0-rx {
422 compatible = "qcom,msm-dai-q6-dev";
423 qcom,msm-dai-q6-dev-id = <16384>;
424 };
425
426 qcom,msm-dai-q6-sb-0-tx {
427 compatible = "qcom,msm-dai-q6-dev";
428 qcom,msm-dai-q6-dev-id = <16385>;
429 };
430 };
431
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]432 qcom,msm-auxpcm {
433 compatible = "qcom,msm-auxpcm-resource";
434 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
435 qcom,msm-cpudai-auxpcm-mode = <0>;
436 qcom,msm-cpudai-auxpcm-sync = <1>;
437 qcom,msm-cpudai-auxpcm-frame = <5>;
438 qcom,msm-cpudai-auxpcm-quant = <2>;
439 qcom,msm-cpudai-auxpcm-slot = <1>;
440 qcom,msm-cpudai-auxpcm-data = <0>;
441 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]442
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]443 qcom,msm-auxpcm-rx {
444 qcom,msm-auxpcm-dev-id = <4106>;
445 compatible = "qcom,msm-auxpcm-dev";
446 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]447
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]448 qcom,msm-auxpcm-tx {
449 qcom,msm-auxpcm-dev-id = <4107>;
450 compatible = "qcom,msm-auxpcm-dev";
451 };
452 };
453
454 qcom,msm-pcm-hostless {
455 compatible = "qcom,msm-pcm-hostless";
456 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]457
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700[diff] [blame]458 qcom,msm-ocmem-audio {
459 compatible = "qcom,msm-ocmem-audio";
460 qcom,msm-ocmem-audio-src-id = <11>;
461 qcom,msm-ocmem-audio-dst-id = <604>;
462 qcom,msm-ocmem-audio-ab = <32505856>;
463 qcom,msm-ocmem-audio-ib = <32505856>;
464 };
465
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]466 qcom,mss@fc880000 {
467 compatible = "qcom,pil-q6v5-mss";
468 reg = <0xfc880000 0x100>,
469 <0xfd485000 0x400>,
470 <0xfc820000 0x020>,
471 <0xfc401680 0x004>;
472 vdd_mss-supply = <&pm8841_s3>;
473
474 qcom,firmware-name = "mba";
475 qcom,pil-self-auth = <1>;
476 };
477
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]478 qcom,mba@fc820000 {
479 compatible = "qcom,pil-mba";
480 reg = <0xfc820000 0x0020>,
481 <0x0d1fc000 0x4000>;
482
483 qcom,firmware-name = "modem";
484 qcom,depends-on = "mba";
485 };
486
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]487 qcom,pronto@fb21b000 {
488 compatible = "qcom,pil-pronto";
489 reg = <0xfb21b000 0x3000>,
490 <0xfc401700 0x4>,
491 <0xfd485300 0xc>;
492 vdd_pronto_pll-supply = <&pm8941_l12>;
493
494 qcom,firmware-name = "wcnss";
495 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]496
497 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]498 compatible = "qcom,msm-ocmem";
499 reg = <0xfdd00000 0x2000>,
500 <0xfdd02000 0x2000>,
501 <0xfe039000 0x400>,
502 <0xfec00000 0x180000>;
503 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
504 interrupts = <0 76 0 0 77 0>;
505 interrupt-names = "ocmem_irq", "dm_irq";
506 qcom,ocmem-num-regions = <0x3>;
Naveen Ramarajba3a6262012-08-02 17:14:27 -0700[diff] [blame]507 qcom,resource-type = <0x706d636f>;
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]508 #address-cells = <1>;
509 #size-cells = <1>;
510 ranges = <0x0 0xfec00000 0x180000>;
511
512 partition@0 {
513 reg = <0x0 0x100000>;
514 qcom,ocmem-part-name = "graphics";
515 qcom,ocmem-part-min = <0x80000>;
516 };
517
518 partition@80000 {
519 reg = <0x80000 0xA0000>;
520 qcom,ocmem-part-name = "lp_audio";
521 qcom,ocmem-part-min = <0xA0000>;
522 };
523
524 partition@E0000 {
525 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame]526 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]527 qcom,ocmem-part-min = <0x20000>;
528 };
529
530 partition@100000 {
531 reg = <0x100000 0x80000>;
532 qcom,ocmem-part-name = "video";
533 qcom,ocmem-part-min = <0x55000>;
534 };
535
536 partition@140000 {
537 reg = <0x140000 0x40000>;
538 qcom,ocmem-part-name = "sensors";
539 qcom,ocmem-part-min = <0x40000>;
540 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]541 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]542
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]543 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]544 compatible = "qcom,rpm-smd";
545 rpm-channel-name = "rpm_requests";
546 rpm-channel-type = <15>; /* SMD_APPS_RPM */
547 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]548
549 qcom,msm-rng@f9bff000 {
550 compatible = "qcom,msm-rng";
551 reg = <0xf9bff000 0x200>;
552 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]553
554 qcom,qseecom@fe806000 {
555 compatible = "qcom,qseecom";
556 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]557
558 qcom,mdss_mdp@fd900000 {
559 cell-index = <0>;
560 compatible = "qcom,mdss_mdp";
561 reg = <0xfd900000 0x22100>;
562 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]563 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]564 };
565
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]566 mdss_dsi: qcom,mdss_dsi@fd922800 {
567 cell-index = <1>;
568 compatible = "qcom,msm-mdss-dsi";
569 reg = <0xfd922800 0x5ac>,
570 <0xfd8c0000 0x01000>;
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]571 };
572
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]573 qcom,mdss_wb_panel {
574 cell-index = <1>;
575 compatible = "qcom,mdss_wb";
576 qcom,mdss_pan_res = <640 480>;
577 qcom,mdss_pan_bpp = <24>;
578 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]579
580 qcom,wdt@f9017000 {
581 compatible = "qcom,msm-watchdog";
582 reg = <0xf9017000 0x1000>;
583 interrupts = <0 3 0 0 4 0>;
584 qcom,bark-time = <11000>;
585 qcom,pet-time = <10000>;
586 qcom,ipi-ping = <1>;
587 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]588
589 qcom,tz-log@fe805720 {
590 compatible = "qcom,tz-log";
591 reg = <0xfe805720 0x1000>;
592 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]593
594 qcom,venus@fdce0000 {
595 compatible = "qcom,pil-venus";
596 reg = <0xfdce0000 0x4000>,
597 <0xfdc80208 0x8>;
598 vdd-supply = <&gdsc_venus>;
599
600 qcom,firmware-name = "venus";
601 qcom,firmware-min-paddr = <0xF500000>;
602 qcom,firmware-max-paddr = <0xFA00000>;
603 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]604
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700[diff] [blame]605 qcom,cache_erp {
606 compatible = "qcom,cache_erp";
607 interrupts = <1 9 0>, <0 2 0>;
608 interrupt-names = "l1_irq", "l2_irq";
609 };
610
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]611 tsens@fc4a8000 {
612 compatible = "qcom,msm-tsens";
613 reg = <0xfc4a8000 0x2000>,
614 <0xfc4b80d0 0x5>;
615 reg-names = "tsens_physical", "tsens_eeprom_physical";
616 interrupts = <0 184 0>;
617 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700[diff] [blame]618 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
619 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]620 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700[diff] [blame]621
622 qcom,msm-rtb {
623 compatible = "qcom,msm-rtb";
624 qcom,memory-reservation-type = "EBI1";
625 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
626 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]627
628 qcom,qcedev@fd440000 {
629 compatible = "qcom,qcedev";
630 reg = <0xfd440000 0x20000>,
631 <0xfd444000 0x8000>;
632 interrupts = <0 235 0>;
633 qcom,bam-pipes = <0>;
634 };
635
636 qcom,qcrypto@fd444000 {
637 compatible = "qcom,qcrypto";
638 reg = <0xfd440000 0x20000>,
639 <0xfd444000 0x8000>;
640 interrupts = <0 235 0>;
641 qcom,bam-pipes = <1>;
642 };
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]643
644 qcom,usbbam@f9304000 {
645 compatible = "qcom,usb-bam-msm";
646 reg = <0xf9304000 0x9000>;
647 interrupts = <0 132 0>;
648 qcom,usb-active-bam = <0>;
649 qcom,usb-total-bam-num = <1>;
650 qcom,usb-bam-num-pipes = <16>;
651 qcom,usb-base-address = <0xf9200000>;
652
653 qcom,pipe1 {
654 label = "usb-to-peri-qdss-dwc3";
655 qcom,usb-bam-type = <0>;
656 qcom,src-bam-physical-address = <0>;
657 qcom,src-bam-pipe-index = <0>;
658 qcom,dst-bam-physical-address = <0>;
659 qcom,dst-bam-pipe-index = <0>;
660 qcom,data-fifo-offset = <0>;
661 qcom,data-fifo-size = <0>;
662 qcom,descriptor-fifo-offset = <0>;
663 qcom,descriptor-fifo-size = <0>;
664 };
665
666 qcom,pipe2 {
667 label = "peri-to-usb-qdss-dwc3";
668 qcom,usb-bam-type = <0>;
669 qcom,src-bam-physical-address = <0xfc37C000>;
670 qcom,src-bam-pipe-index = <0>;
671 qcom,dst-bam-physical-address = <0xf9304000>;
672 qcom,dst-bam-pipe-index = <2>;
673 qcom,data-fifo-offset = <0xf0000>;
674 qcom,data-fifo-size = <0x4000>;
675 qcom,descriptor-fifo-offset = <0xf4000>;
676 qcom,descriptor-fifo-size = <0x1400>;
677 };
678 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]679};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]680
681/include/ "msm-pm8x41-rpm-regulator.dtsi"
682/include/ "msm-pm8841.dtsi"
683/include/ "msm-pm8941.dtsi"
684/include/ "msm8974-regulator.dtsi"
685/include/ "msm8974-gpio.dtsi"