| Bryan Wu | 0c6a881 | 2008-12-02 21:33:44 +0200 | [diff] [blame] | 1 | /* | 
|  | 2 | * Copyright (C) 2007 by Analog Devices, Inc. | 
|  | 3 | * | 
|  | 4 | * The Inventra Controller Driver for Linux is free software; you | 
|  | 5 | * can redistribute it and/or modify it under the terms of the GNU | 
|  | 6 | * General Public License version 2 as published by the Free Software | 
|  | 7 | * Foundation. | 
|  | 8 | */ | 
|  | 9 |  | 
|  | 10 | #ifndef __MUSB_BLACKFIN_H__ | 
|  | 11 | #define __MUSB_BLACKFIN_H__ | 
|  | 12 |  | 
|  | 13 | /* | 
|  | 14 | * Blackfin specific definitions | 
|  | 15 | */ | 
|  | 16 |  | 
| Sonic Zhang | daf5822 | 2009-11-16 19:13:08 +0530 | [diff] [blame] | 17 | /* Anomalies notes: | 
|  | 18 | * | 
|  | 19 | *  05000450 - USB DMA Mode 1 Short Packet Data Corruption: | 
|  | 20 | *             MUSB driver is designed to transfer buffer of N * maxpacket size | 
|  | 21 | *             in DMA mode 1 and leave the rest of the data to the next | 
|  | 22 | *             transfer in DMA mode 0, so we never transmit a short packet in | 
|  | 23 | *             DMA mode 1. | 
|  | 24 | * | 
|  | 25 | *  05000463 - This anomaly doesn't affect this driver since it | 
|  | 26 | *             never uses L1 or L2 memory as data destination. | 
|  | 27 | * | 
|  | 28 | *  05000464 - This anomaly doesn't affect this driver since it | 
|  | 29 | *             never uses L1 or L2 memory as data source. | 
|  | 30 | * | 
|  | 31 | *  05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is | 
|  | 32 | *             no way to workaround for bulk endpoints.  Since the wMaxPackSize | 
|  | 33 | *             of bulk is less than or equal to 512, while the fifo size of | 
|  | 34 | *             endpoint 5, 6, 7 is 1024, the double buffer mode is enabled | 
|  | 35 | *             automatically when these endpoints are used for bulk OUT. | 
|  | 36 | * | 
|  | 37 | *  05000466 - This anomaly doesn't affect this driver since it never mixes | 
|  | 38 | *             concurrent DMA and core accesses to the TX endpoint FIFOs. | 
|  | 39 | * | 
|  | 40 | *  05000467 - The workaround for this anomaly will introduce another | 
|  | 41 | *             anomaly - 05000465. | 
|  | 42 | */ | 
|  | 43 |  | 
| Sonic Zhang | 0702794 | 2009-11-16 16:19:27 +0530 | [diff] [blame] | 44 | /* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be | 
|  | 45 | * unstable in host mode.  This may be caused by Anomaly 05000380.  After | 
|  | 46 | * digging out the root cause, we will change this number accordingly. | 
|  | 47 | * So, need to either use silicon v0.2+ or disable DMA mode in MUSB. | 
|  | 48 | */ | 
|  | 49 | #if ANOMALY_05000380 && defined(CONFIG_BF52x) && \ | 
| Felipe Balbi | 6228596 | 2011-06-22 17:28:09 +0300 | [diff] [blame] | 50 | !defined(CONFIG_MUSB_PIO_ONLY) | 
| Sonic Zhang | 0702794 | 2009-11-16 16:19:27 +0530 | [diff] [blame] | 51 | # error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1" | 
|  | 52 | #endif | 
|  | 53 |  | 
| Bryan Wu | 0c6a881 | 2008-12-02 21:33:44 +0200 | [diff] [blame] | 54 | #undef DUMP_FIFO_DATA | 
|  | 55 | #ifdef DUMP_FIFO_DATA | 
|  | 56 | static void dump_fifo_data(u8 *buf, u16 len) | 
|  | 57 | { | 
|  | 58 | u8 *tmp = buf; | 
|  | 59 | int i; | 
|  | 60 |  | 
|  | 61 | for (i = 0; i < len; i++) { | 
|  | 62 | if (!(i % 16) && i) | 
|  | 63 | pr_debug("\n"); | 
|  | 64 | pr_debug("%02x ", *tmp++); | 
|  | 65 | } | 
|  | 66 | pr_debug("\n"); | 
|  | 67 | } | 
|  | 68 | #else | 
|  | 69 | #define dump_fifo_data(buf, len)	do {} while (0) | 
|  | 70 | #endif | 
|  | 71 |  | 
| Bryan Wu | 0c6a881 | 2008-12-02 21:33:44 +0200 | [diff] [blame] | 72 |  | 
|  | 73 | #define USB_DMA_BASE		USB_DMA_INTERRUPT | 
|  | 74 | #define USB_DMAx_CTRL		0x04 | 
|  | 75 | #define USB_DMAx_ADDR_LOW	0x08 | 
|  | 76 | #define USB_DMAx_ADDR_HIGH	0x0C | 
|  | 77 | #define USB_DMAx_COUNT_LOW	0x10 | 
|  | 78 | #define USB_DMAx_COUNT_HIGH	0x14 | 
|  | 79 |  | 
|  | 80 | #define USB_DMA_REG(ep, reg)	(USB_DMA_BASE + 0x20 * ep + reg) | 
| Bryan Wu | 0c6a881 | 2008-12-02 21:33:44 +0200 | [diff] [blame] | 81 |  | 
|  | 82 | /* Almost 1 second */ | 
|  | 83 | #define TIMER_DELAY	(1 * HZ) | 
|  | 84 |  | 
|  | 85 | static struct timer_list musb_conn_timer; | 
|  | 86 |  | 
|  | 87 | #endif	/* __MUSB_BLACKFIN_H__ */ |