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review.evervolv.com / android_kernel_htc_msm8960 / b31a1d8b41513b96e9c7ec2f68c5734cef0b26a4 / . / arch / powerpc / boot / dts / mpc8572ds.dts
blob: 05f67253b49fcf54e18d2a848c8bdf2ee71e6e7c [file] [log] [blame]
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]1/*
2 * MPC8572 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]16 #address-cells = <2>;
17 #size-cells = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]45 next-level-cache = <&L2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]46 };
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]47
48 PowerPC,8572@1 {
49 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]58 next-level-cache = <&L2>;
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]59 };
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]60 };
61
62 memory {
63 device_type = "memory";
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]64 };
65
66 soc8572@ffe00000 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 device_type = "soc";
Kim Phillipscf0d19f2008-07-29 15:29:24 -0500[diff] [blame]70 compatible = "simple-bus";
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]71 ranges = <0x0 0 0xffe00000 0x100000>;
72 reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]73 bus-frequency = <0>; // Filled out by uboot.
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]77 reg = <0x2000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]78 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]79 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]80 };
81
82 memory-controller@6000 {
83 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]84 reg = <0x6000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]85 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]86 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]87 };
88
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]89 L2: l2-cache-controller@20000 {
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]90 compatible = "fsl,mpc8572-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]91 reg = <0x20000 0x1000>;
92 cache-line-size = <32>; // 32 bytes
Trent Piephof464ff52008-11-19 10:40:55 -0800[diff] [blame]93 cache-size = <0x100000>; // L2, 1M
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]94 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]95 interrupts = <16 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]96 };
97
98 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]99 #address-cells = <1>;
100 #size-cells = <0>;
101 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]102 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]103 reg = <0x3000 0x100>;
104 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]105 interrupt-parent = <&mpic>;
106 dfsrr;
107 };
108
109 i2c@3100 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]110 #address-cells = <1>;
111 #size-cells = <0>;
112 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]113 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]114 reg = <0x3100 0x100>;
115 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]116 interrupt-parent = <&mpic>;
117 dfsrr;
118 };
119
Kumar Galadee80552008-06-27 13:45:19 -0500[diff] [blame]120 dma@c300 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
124 reg = <0xc300 0x4>;
125 ranges = <0x0 0xc100 0x200>;
126 cell-index = <1>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8572-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x0 0x80>;
131 cell-index = <0>;
132 interrupt-parent = <&mpic>;
133 interrupts = <76 2>;
134 };
135 dma-channel@80 {
136 compatible = "fsl,mpc8572-dma-channel",
137 "fsl,eloplus-dma-channel";
138 reg = <0x80 0x80>;
139 cell-index = <1>;
140 interrupt-parent = <&mpic>;
141 interrupts = <77 2>;
142 };
143 dma-channel@100 {
144 compatible = "fsl,mpc8572-dma-channel",
145 "fsl,eloplus-dma-channel";
146 reg = <0x100 0x80>;
147 cell-index = <2>;
148 interrupt-parent = <&mpic>;
149 interrupts = <78 2>;
150 };
151 dma-channel@180 {
152 compatible = "fsl,mpc8572-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x180 0x80>;
155 cell-index = <3>;
156 interrupt-parent = <&mpic>;
157 interrupts = <79 2>;
158 };
159 };
160
161 dma@21300 {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
165 reg = <0x21300 0x4>;
166 ranges = <0x0 0x21100 0x200>;
167 cell-index = <0>;
168 dma-channel@0 {
169 compatible = "fsl,mpc8572-dma-channel",
170 "fsl,eloplus-dma-channel";
171 reg = <0x0 0x80>;
172 cell-index = <0>;
173 interrupt-parent = <&mpic>;
174 interrupts = <20 2>;
175 };
176 dma-channel@80 {
177 compatible = "fsl,mpc8572-dma-channel",
178 "fsl,eloplus-dma-channel";
179 reg = <0x80 0x80>;
180 cell-index = <1>;
181 interrupt-parent = <&mpic>;
182 interrupts = <21 2>;
183 };
184 dma-channel@100 {
185 compatible = "fsl,mpc8572-dma-channel",
186 "fsl,eloplus-dma-channel";
187 reg = <0x100 0x80>;
188 cell-index = <2>;
189 interrupt-parent = <&mpic>;
190 interrupts = <22 2>;
191 };
192 dma-channel@180 {
193 compatible = "fsl,mpc8572-dma-channel",
194 "fsl,eloplus-dma-channel";
195 reg = <0x180 0x80>;
196 cell-index = <3>;
197 interrupt-parent = <&mpic>;
198 interrupts = <23 2>;
199 };
200 };
201
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]202 mdio@24520 {
203 #address-cells = <1>;
204 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]205 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]206 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]207
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]208 phy0: ethernet-phy@0 {
209 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]210 interrupts = <10 1>;
211 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]212 };
213 phy1: ethernet-phy@1 {
214 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]215 interrupts = <10 1>;
216 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]217 };
218 phy2: ethernet-phy@2 {
219 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]220 interrupts = <10 1>;
221 reg = <0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]222 };
223 phy3: ethernet-phy@3 {
224 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]225 interrupts = <10 1>;
226 reg = <0x3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]227 };
Andy Flemingb31a1d82008-12-16 15:29:15 -0800[diff] [blame^]228
229 tbi0: tbi-phy@11 {
230 reg = <0x11>;
231 device_type = "tbi-phy";
232 };
233 };
234
235 mdio@25520 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "fsl,gianfar-tbi";
239 reg = <0x25520 0x20>;
240
241 tbi1: tbi-phy@11 {
242 reg = <0x11>;
243 device_type = "tbi-phy";
244 };
245 };
246
247 mdio@26520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-tbi";
251 reg = <0x26520 0x20>;
252
253 tbi2: tbi-phy@11 {
254 reg = <0x11>;
255 device_type = "tbi-phy";
256 };
257 };
258
259 mdio@27520 {
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "fsl,gianfar-tbi";
263 reg = <0x27520 0x20>;
264
265 tbi3: tbi-phy@11 {
266 reg = <0x11>;
267 device_type = "tbi-phy";
268 };
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]269 };
270
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]271 enet0: ethernet@24000 {
272 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]273 device_type = "network";
274 model = "eTSEC";
275 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]276 reg = <0x24000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]277 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]278 interrupts = <29 2 30 2 34 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]279 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800[diff] [blame^]280 tbi-handle = <&tbi0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]281 phy-handle = <&phy0>;
282 phy-connection-type = "rgmii-id";
283 };
284
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]285 enet1: ethernet@25000 {
286 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]287 device_type = "network";
288 model = "eTSEC";
289 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]290 reg = <0x25000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]291 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]292 interrupts = <35 2 36 2 40 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]293 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800[diff] [blame^]294 tbi-handle = <&tbi1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]295 phy-handle = <&phy1>;
296 phy-connection-type = "rgmii-id";
297 };
298
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]299 enet2: ethernet@26000 {
300 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]301 device_type = "network";
302 model = "eTSEC";
303 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]304 reg = <0x26000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]305 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]306 interrupts = <31 2 32 2 33 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]307 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800[diff] [blame^]308 tbi-handle = <&tbi2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]309 phy-handle = <&phy2>;
310 phy-connection-type = "rgmii-id";
311 };
312
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]313 enet3: ethernet@27000 {
314 cell-index = <3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]315 device_type = "network";
316 model = "eTSEC";
317 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]318 reg = <0x27000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]319 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]320 interrupts = <37 2 38 2 39 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]321 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800[diff] [blame^]322 tbi-handle = <&tbi3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]323 phy-handle = <&phy3>;
324 phy-connection-type = "rgmii-id";
325 };
326
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]327 serial0: serial@4500 {
328 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]329 device_type = "serial";
330 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]331 reg = <0x4500 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]332 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]333 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]334 interrupt-parent = <&mpic>;
335 };
336
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]337 serial1: serial@4600 {
338 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]339 device_type = "serial";
340 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]341 reg = <0x4600 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]342 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]343 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]344 interrupt-parent = <&mpic>;
345 };
346
347 global-utilities@e0000 { //global utilities block
348 compatible = "fsl,mpc8572-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]349 reg = <0xe0000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]350 fsl,has-rstcr;
351 };
352
Jason Jin741edc42008-05-23 16:32:48 +0800[diff] [blame]353 msi@41600 {
354 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
355 reg = <0x41600 0x80>;
356 msi-available-ranges = <0 0x100>;
357 interrupts = <
358 0xe0 0
359 0xe1 0
360 0xe2 0
361 0xe3 0
362 0xe4 0
363 0xe5 0
364 0xe6 0
365 0xe7 0>;
366 interrupt-parent = <&mpic>;
367 };
368
Kim Phillips3fd44732008-07-08 19:13:33 -0500[diff] [blame]369 crypto@30000 {
370 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
371 "fsl,sec2.1", "fsl,sec2.0";
372 reg = <0x30000 0x10000>;
373 interrupts = <45 2 58 2>;
374 interrupt-parent = <&mpic>;
375 fsl,num-channels = <4>;
376 fsl,channel-fifo-len = <24>;
377 fsl,exec-units-mask = <0x9fe>;
378 fsl,descriptor-types-mask = <0x3ab0ebf>;
379 };
380
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]381 mpic: pic@40000 {
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]382 interrupt-controller;
383 #address-cells = <0>;
384 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]385 reg = <0x40000 0x40000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]386 compatible = "chrp,open-pic";
387 device_type = "open-pic";
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]388 };
389 };
390
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]391 pci0: pcie@ffe08000 {
392 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]393 compatible = "fsl,mpc8548-pcie";
394 device_type = "pci";
395 #interrupt-cells = <1>;
396 #size-cells = <2>;
397 #address-cells = <3>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]398 reg = <0 0xffe08000 0 0x1000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]399 bus-range = <0 255>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]400 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
401 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]402 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]403 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]404 interrupts = <24 2>;
405 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]406 interrupt-map = <
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]407 /* IDSEL 0x11 func 0 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]408 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
409 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
410 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
411 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]412
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]413 /* IDSEL 0x11 func 1 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]414 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
415 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
416 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
417 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]418
419 /* IDSEL 0x11 func 2 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]420 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
421 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
422 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
423 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]424
425 /* IDSEL 0x11 func 3 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]426 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
427 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
428 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
429 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]430
431 /* IDSEL 0x11 func 4 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]432 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
433 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
434 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
435 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]436
437 /* IDSEL 0x11 func 5 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]438 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
439 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
440 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
441 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]442
443 /* IDSEL 0x11 func 6 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]444 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
445 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
446 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
447 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]448
449 /* IDSEL 0x11 func 7 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]450 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
451 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
452 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
453 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]454
455 /* IDSEL 0x12 func 0 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]456 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
457 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
458 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
459 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]460
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]461 /* IDSEL 0x12 func 1 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]462 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
463 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
464 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
465 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]466
467 /* IDSEL 0x12 func 2 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]468 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
469 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
470 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
471 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]472
473 /* IDSEL 0x12 func 3 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]474 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
475 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
476 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
477 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]478
479 /* IDSEL 0x12 func 4 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]480 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
481 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
482 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
483 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]484
485 /* IDSEL 0x12 func 5 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]486 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
487 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
488 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
489 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]490
491 /* IDSEL 0x12 func 6 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]492 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
493 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
494 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
495 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]496
497 /* IDSEL 0x12 func 7 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]498 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
499 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
500 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
501 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]502
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]503 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]504 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
505 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
506 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
507 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]508
509 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]510 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]511
512 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]513 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
514 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]515
516 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]517 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
518 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]519
520 >;
521
522 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]523 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]524 #size-cells = <2>;
525 #address-cells = <3>;
526 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]527 ranges = <0x2000000 0x0 0x80000000
528 0x2000000 0x0 0x80000000
529 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]530
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]531 0x1000000 0x0 0x0
532 0x1000000 0x0 0x0
533 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]534 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]535 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]536 #size-cells = <2>;
537 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]538 ranges = <0x2000000 0x0 0x80000000
539 0x2000000 0x0 0x80000000
540 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]541
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]542 0x1000000 0x0 0x0
543 0x1000000 0x0 0x0
544 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]545 isa@1e {
546 device_type = "isa";
547 #interrupt-cells = <2>;
548 #size-cells = <1>;
549 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]550 reg = <0xf000 0x0 0x0 0x0 0x0>;
551 ranges = <0x1 0x0 0x1000000 0x0 0x0
552 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]553 interrupt-parent = <&i8259>;
554
555 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]556 reg = <0x1 0x20 0x2
557 0x1 0xa0 0x2
558 0x1 0x4d0 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]559 interrupt-controller;
560 device_type = "interrupt-controller";
561 #address-cells = <0>;
562 #interrupt-cells = <2>;
563 compatible = "chrp,iic";
564 interrupts = <9 2>;
565 interrupt-parent = <&mpic>;
566 };
567
568 i8042@60 {
569 #size-cells = <0>;
570 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]571 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
572 interrupts = <1 3 12 3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]573 interrupt-parent =
574 <&i8259>;
575
576 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]577 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]578 compatible = "pnpPNP,303";
579 };
580
581 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]582 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]583 compatible = "pnpPNP,f03";
584 };
585 };
586
587 rtc@70 {
588 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]589 reg = <0x1 0x70 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]590 };
591
592 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]593 reg = <0x1 0x400 0x80>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]594 };
595 };
596 };
597 };
598
599 };
600
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]601 pci1: pcie@ffe09000 {
602 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]603 compatible = "fsl,mpc8548-pcie";
604 device_type = "pci";
605 #interrupt-cells = <1>;
606 #size-cells = <2>;
607 #address-cells = <3>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]608 reg = <0 0xffe09000 0 0x1000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]609 bus-range = <0 255>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]610 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
611 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]612 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]613 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]614 interrupts = <26 2>;
615 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]616 interrupt-map = <
617 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]618 0000 0x0 0x0 0x1 &mpic 0x4 0x1
619 0000 0x0 0x0 0x2 &mpic 0x5 0x1
620 0000 0x0 0x0 0x3 &mpic 0x6 0x1
621 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]622 >;
623 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]624 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]625 #size-cells = <2>;
626 #address-cells = <3>;
627 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]628 ranges = <0x2000000 0x0 0xa0000000
629 0x2000000 0x0 0xa0000000
630 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]631
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]632 0x1000000 0x0 0x0
633 0x1000000 0x0 0x0
634 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]635 };
636 };
637
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]638 pci2: pcie@ffe0a000 {
639 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]640 compatible = "fsl,mpc8548-pcie";
641 device_type = "pci";
642 #interrupt-cells = <1>;
643 #size-cells = <2>;
644 #address-cells = <3>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]645 reg = <0 0xffe0a000 0 0x1000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]646 bus-range = <0 255>;
Kumar Gala66eb9882008-10-20 23:02:26 -0500[diff] [blame]647 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
648 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]649 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]650 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]651 interrupts = <27 2>;
652 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]653 interrupt-map = <
654 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]655 0000 0x0 0x0 0x1 &mpic 0x0 0x1
656 0000 0x0 0x0 0x2 &mpic 0x1 0x1
657 0000 0x0 0x0 0x3 &mpic 0x2 0x1
658 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]659 >;
660 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]661 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]662 #size-cells = <2>;
663 #address-cells = <3>;
664 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]665 ranges = <0x2000000 0x0 0xc0000000
666 0x2000000 0x0 0xc0000000
667 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]668
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]669 0x1000000 0x0 0x0
670 0x1000000 0x0 0x0
671 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]672 };
673 };
674};