| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  * linux/kernel/irq/chip.c | 
 | 3 |  * | 
 | 4 |  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | 
 | 5 |  * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | 
 | 6 |  * | 
 | 7 |  * This file contains the core interrupt handling code, for irq-chip | 
 | 8 |  * based architectures. | 
 | 9 |  * | 
 | 10 |  * Detailed information is available in Documentation/DocBook/genericirq | 
 | 11 |  */ | 
 | 12 |  | 
 | 13 | #include <linux/irq.h> | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> | 
 | 16 | #include <linux/interrupt.h> | 
 | 17 | #include <linux/kernel_stat.h> | 
 | 18 |  | 
 | 19 | #include "internals.h" | 
 | 20 |  | 
| Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 22 |  *	irq_set_chip - set the irq chip for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 23 |  *	@irq:	irq number | 
 | 24 |  *	@chip:	pointer to irq chip description structure | 
 | 25 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 27 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 28 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 29 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 31 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 |  | 
 | 34 | 	if (!chip) | 
 | 35 | 		chip = &no_irq_chip; | 
 | 36 |  | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 37 | 	desc->irq_data.chip = chip; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 38 | 	irq_put_desc_unlock(desc, flags); | 
| David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 39 | 	/* | 
 | 40 | 	 * For !CONFIG_SPARSE_IRQ make the irq show up in | 
 | 41 | 	 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | 
 | 42 | 	 * already marked, and this call is harmless. | 
 | 43 | 	 */ | 
 | 44 | 	irq_reserve_irq(irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 45 | 	return 0; | 
 | 46 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 47 | EXPORT_SYMBOL(irq_set_chip); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 48 |  | 
 | 49 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 50 |  *	irq_set_type - set the irq trigger type for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 51 |  *	@irq:	irq number | 
| David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 52 |  *	@type:	IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 53 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 54 | int irq_set_irq_type(unsigned int irq, unsigned int type) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 55 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 56 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 57 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 58 | 	int ret = 0; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 59 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 60 | 	if (!desc) | 
 | 61 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 62 |  | 
| David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 63 | 	type &= IRQ_TYPE_SENSE_MASK; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 64 | 	if (type != IRQ_TYPE_NONE) | 
 | 65 | 		ret = __irq_set_trigger(desc, irq, type); | 
 | 66 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 67 | 	return ret; | 
 | 68 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 69 | EXPORT_SYMBOL(irq_set_irq_type); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 70 |  | 
 | 71 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 72 |  *	irq_set_handler_data - set irq handler data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 73 |  *	@irq:	Interrupt number | 
 | 74 |  *	@data:	Pointer to interrupt specific data | 
 | 75 |  * | 
 | 76 |  *	Set the hardware irq controller data for an irq | 
 | 77 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 78 | int irq_set_handler_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 79 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 80 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 81 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 82 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 83 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 84 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 85 | 	desc->irq_data.handler_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 86 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 87 | 	return 0; | 
 | 88 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 89 | EXPORT_SYMBOL(irq_set_handler_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 90 |  | 
 | 91 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 92 |  *	irq_set_msi_desc - set MSI descriptor data for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 93 |  *	@irq:	Interrupt number | 
| Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 94 |  *	@entry:	Pointer to MSI descriptor data | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 95 |  * | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 96 |  *	Set the MSI descriptor entry for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 97 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 98 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 99 | { | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 100 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 101 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 102 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 103 | 	if (!desc) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 104 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 105 | 	desc->irq_data.msi_desc = entry; | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 106 | 	if (entry) | 
 | 107 | 		entry->irq = irq; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 108 | 	irq_put_desc_unlock(desc, flags); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 109 | 	return 0; | 
 | 110 | } | 
 | 111 |  | 
 | 112 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 113 |  *	irq_set_chip_data - set irq chip data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 114 |  *	@irq:	Interrupt number | 
 | 115 |  *	@data:	Pointer to chip specific data | 
 | 116 |  * | 
 | 117 |  *	Set the hardware irq chip data for an irq | 
 | 118 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 119 | int irq_set_chip_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 120 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 121 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 122 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 123 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 124 | 	if (!desc) | 
| Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 125 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 126 | 	desc->irq_data.chip_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 127 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 128 | 	return 0; | 
 | 129 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 130 | EXPORT_SYMBOL(irq_set_chip_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 131 |  | 
| Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 132 | struct irq_data *irq_get_irq_data(unsigned int irq) | 
 | 133 | { | 
 | 134 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 135 |  | 
 | 136 | 	return desc ? &desc->irq_data : NULL; | 
 | 137 | } | 
 | 138 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | 
 | 139 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 140 | static void irq_state_clr_disabled(struct irq_desc *desc) | 
 | 141 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 142 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 143 | } | 
 | 144 |  | 
 | 145 | static void irq_state_set_disabled(struct irq_desc *desc) | 
 | 146 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 147 | 	irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 148 | } | 
 | 149 |  | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 150 | static void irq_state_clr_masked(struct irq_desc *desc) | 
 | 151 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 152 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 153 | } | 
 | 154 |  | 
 | 155 | static void irq_state_set_masked(struct irq_desc *desc) | 
 | 156 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 157 | 	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 158 | } | 
 | 159 |  | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 160 | int irq_startup(struct irq_desc *desc) | 
 | 161 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 162 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 163 | 	desc->depth = 0; | 
 | 164 |  | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 165 | 	if (desc->irq_data.chip->irq_startup) { | 
 | 166 | 		int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 167 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 168 | 		return ret; | 
 | 169 | 	} | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 170 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 171 | 	irq_enable(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 172 | 	return 0; | 
 | 173 | } | 
 | 174 |  | 
 | 175 | void irq_shutdown(struct irq_desc *desc) | 
 | 176 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 177 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 178 | 	desc->depth = 1; | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 179 | 	if (desc->irq_data.chip->irq_shutdown) | 
 | 180 | 		desc->irq_data.chip->irq_shutdown(&desc->irq_data); | 
| Geert Uytterhoeven | ed585a6 | 2011-09-11 13:59:27 +0200 | [diff] [blame] | 181 | 	else if (desc->irq_data.chip->irq_disable) | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 182 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
 | 183 | 	else | 
 | 184 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 185 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 186 | } | 
 | 187 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 188 | void irq_enable(struct irq_desc *desc) | 
 | 189 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 190 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 191 | 	if (desc->irq_data.chip->irq_enable) | 
 | 192 | 		desc->irq_data.chip->irq_enable(&desc->irq_data); | 
 | 193 | 	else | 
 | 194 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 195 | 	irq_state_clr_masked(desc); | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 196 | } | 
 | 197 |  | 
 | 198 | void irq_disable(struct irq_desc *desc) | 
 | 199 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 200 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 201 | 	if (desc->irq_data.chip->irq_disable) { | 
 | 202 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
| Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 203 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 204 | 	} | 
| Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 205 | } | 
 | 206 |  | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 207 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) | 
 | 208 | { | 
 | 209 | 	if (desc->irq_data.chip->irq_enable) | 
 | 210 | 		desc->irq_data.chip->irq_enable(&desc->irq_data); | 
 | 211 | 	else | 
 | 212 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
 | 213 | 	cpumask_set_cpu(cpu, desc->percpu_enabled); | 
 | 214 | } | 
 | 215 |  | 
 | 216 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | 
 | 217 | { | 
 | 218 | 	if (desc->irq_data.chip->irq_disable) | 
 | 219 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
 | 220 | 	else | 
 | 221 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
 | 222 | 	cpumask_clear_cpu(cpu, desc->percpu_enabled); | 
 | 223 | } | 
 | 224 |  | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 225 | static inline void mask_ack_irq(struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 226 | { | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 227 | 	if (desc->irq_data.chip->irq_mask_ack) | 
 | 228 | 		desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 229 | 	else { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 230 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 231 | 		if (desc->irq_data.chip->irq_ack) | 
 | 232 | 			desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 233 | 	} | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 234 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 235 | } | 
 | 236 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 237 | void mask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 238 | { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 239 | 	if (desc->irq_data.chip->irq_mask) { | 
 | 240 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 241 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 242 | 	} | 
 | 243 | } | 
 | 244 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 245 | void unmask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 246 | { | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 247 | 	if (desc->irq_data.chip->irq_unmask) { | 
 | 248 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 249 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 250 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 251 | } | 
 | 252 |  | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 253 | /* | 
 | 254 |  *	handle_nested_irq - Handle a nested irq from a irq thread | 
 | 255 |  *	@irq:	the interrupt number | 
 | 256 |  * | 
 | 257 |  *	Handle interrupts which are nested into a threaded interrupt | 
 | 258 |  *	handler. The handler function is called inside the calling | 
 | 259 |  *	threads context. | 
 | 260 |  */ | 
 | 261 | void handle_nested_irq(unsigned int irq) | 
 | 262 | { | 
 | 263 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 264 | 	struct irqaction *action; | 
 | 265 | 	irqreturn_t action_ret; | 
 | 266 |  | 
 | 267 | 	might_sleep(); | 
 | 268 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 269 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 270 |  | 
 | 271 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 272 |  | 
 | 273 | 	action = desc->action; | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 274 | 	if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 275 | 		goto out_unlock; | 
 | 276 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 277 | 	irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 278 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 279 |  | 
 | 280 | 	action_ret = action->thread_fn(action->irq, action->dev_id); | 
 | 281 | 	if (!noirqdebug) | 
 | 282 | 		note_interrupt(irq, desc, action_ret); | 
 | 283 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 284 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 285 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 286 |  | 
 | 287 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 288 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 289 | } | 
 | 290 | EXPORT_SYMBOL_GPL(handle_nested_irq); | 
 | 291 |  | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 292 | static bool irq_check_poll(struct irq_desc *desc) | 
 | 293 | { | 
| Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 294 | 	if (!(desc->istate & IRQS_POLL_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 295 | 		return false; | 
 | 296 | 	return irq_wait_for_poll(desc); | 
 | 297 | } | 
 | 298 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 299 | /** | 
 | 300 |  *	handle_simple_irq - Simple and software-decoded IRQs. | 
 | 301 |  *	@irq:	the interrupt number | 
 | 302 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 303 |  * | 
 | 304 |  *	Simple interrupts are either sent from a demultiplexing interrupt | 
 | 305 |  *	handler or come from hardware, where no interrupt hardware control | 
 | 306 |  *	is necessary. | 
 | 307 |  * | 
 | 308 |  *	Note: The caller is expected to handle the ack, clear, mask and | 
 | 309 |  *	unmask issues if necessary. | 
 | 310 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 311 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 312 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 313 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 314 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 315 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 316 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 317 | 		if (!irq_check_poll(desc)) | 
 | 318 | 			goto out_unlock; | 
 | 319 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 320 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 321 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 322 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 323 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 324 | 		goto out_unlock; | 
 | 325 |  | 
| Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 326 | 	handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 327 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 328 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 329 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 330 | } | 
| Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 331 | EXPORT_SYMBOL_GPL(handle_simple_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 332 |  | 
 | 333 | /** | 
 | 334 |  *	handle_level_irq - Level type irq handler | 
 | 335 |  *	@irq:	the interrupt number | 
 | 336 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 337 |  * | 
 | 338 |  *	Level type interrupts are active as long as the hardware line has | 
 | 339 |  *	the active level. This may require to mask the interrupt and unmask | 
 | 340 |  *	it after the associated handler has acknowledged the device, so the | 
 | 341 |  *	interrupt line is back to inactive. | 
 | 342 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 343 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 344 | handle_level_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 345 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 346 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 347 | 	mask_ack_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 348 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 349 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 350 | 		if (!irq_check_poll(desc)) | 
 | 351 | 			goto out_unlock; | 
 | 352 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 353 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 354 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 355 |  | 
 | 356 | 	/* | 
 | 357 | 	 * If its disabled or no action available | 
 | 358 | 	 * keep it masked and get out of here | 
 | 359 | 	 */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 360 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 361 | 		goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 362 |  | 
| Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 363 | 	handle_irq_event(desc); | 
| Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 364 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 365 | 	if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT)) | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 366 | 		unmask_irq(desc); | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 367 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 368 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 369 | } | 
| Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 370 | EXPORT_SYMBOL_GPL(handle_level_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 371 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 372 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI | 
 | 373 | static inline void preflow_handler(struct irq_desc *desc) | 
 | 374 | { | 
 | 375 | 	if (desc->preflow_handler) | 
 | 376 | 		desc->preflow_handler(&desc->irq_data); | 
 | 377 | } | 
 | 378 | #else | 
 | 379 | static inline void preflow_handler(struct irq_desc *desc) { } | 
 | 380 | #endif | 
 | 381 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 382 | /** | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 383 |  *	handle_fasteoi_irq - irq handler for transparent controllers | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 384 |  *	@irq:	the interrupt number | 
 | 385 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 386 |  * | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 387 |  *	Only a single callback will be issued to the chip: an ->eoi() | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 388 |  *	call when the interrupt has been serviced. This enables support | 
 | 389 |  *	for modern forms of interrupt handlers, which handle the flow | 
 | 390 |  *	details in hardware, transparently. | 
 | 391 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 392 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 393 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 394 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 395 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 396 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 397 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 398 | 		if (!irq_check_poll(desc)) | 
 | 399 | 			goto out; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 400 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 401 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 402 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 403 |  | 
 | 404 | 	/* | 
 | 405 | 	 * If its disabled or no action available | 
| Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 406 | 	 * then mask it and get out of here: | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 407 | 	 */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 408 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 409 | 		desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 410 | 		mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 411 | 		goto out; | 
| Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 412 | 	} | 
| Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 413 |  | 
 | 414 | 	if (desc->istate & IRQS_ONESHOT) | 
 | 415 | 		mask_irq(desc); | 
 | 416 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 417 | 	preflow_handler(desc); | 
| Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 418 | 	handle_irq_event(desc); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 419 |  | 
 | 420 | out_eoi: | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 421 | 	desc->irq_data.chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 422 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 423 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 424 | 	return; | 
 | 425 | out: | 
 | 426 | 	if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | 
 | 427 | 		goto out_eoi; | 
 | 428 | 	goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 429 | } | 
 | 430 |  | 
 | 431 | /** | 
 | 432 |  *	handle_edge_irq - edge type IRQ handler | 
 | 433 |  *	@irq:	the interrupt number | 
 | 434 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 435 |  * | 
 | 436 |  *	Interrupt occures on the falling and/or rising edge of a hardware | 
| Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 437 |  *	signal. The occurrence is latched into the irq controller hardware | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 438 |  *	and must be acked in order to be reenabled. After the ack another | 
 | 439 |  *	interrupt can happen on the same source even before the first one | 
| Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 440 |  *	is handled by the associated event handler. If this happens it | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 441 |  *	might be necessary to disable (mask) the interrupt depending on the | 
 | 442 |  *	controller hardware. This requires to reenable the interrupt inside | 
 | 443 |  *	of the loop which handles the interrupts which have arrived while | 
 | 444 |  *	the handler was running. If all pending interrupts are handled, the | 
 | 445 |  *	loop is left. | 
 | 446 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 447 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 448 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 449 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 450 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 451 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 452 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 453 | 	/* | 
 | 454 | 	 * If we're currently running this IRQ, or its disabled, | 
 | 455 | 	 * we shouldn't process the IRQ. Mark it pending, handle | 
 | 456 | 	 * the necessary masking and go out | 
 | 457 | 	 */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 458 | 	if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
 | 459 | 		     irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 460 | 		if (!irq_check_poll(desc)) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 461 | 			desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 462 | 			mask_ack_irq(desc); | 
 | 463 | 			goto out_unlock; | 
 | 464 | 		} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 465 | 	} | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 466 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 467 |  | 
 | 468 | 	/* Start handling the irq */ | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 469 | 	desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 470 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 471 | 	do { | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 472 | 		if (unlikely(!desc->action)) { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 473 | 			mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 474 | 			goto out_unlock; | 
 | 475 | 		} | 
 | 476 |  | 
 | 477 | 		/* | 
 | 478 | 		 * When another irq arrived while we were handling | 
 | 479 | 		 * one, we could have masked the irq. | 
 | 480 | 		 * Renable it, if it was not disabled in meantime. | 
 | 481 | 		 */ | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 482 | 		if (unlikely(desc->istate & IRQS_PENDING)) { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 483 | 			if (!irqd_irq_disabled(&desc->irq_data) && | 
 | 484 | 			    irqd_irq_masked(&desc->irq_data)) | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 485 | 				unmask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 486 | 		} | 
 | 487 |  | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 488 | 		handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 489 |  | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 490 | 	} while ((desc->istate & IRQS_PENDING) && | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 491 | 		 !irqd_irq_disabled(&desc->irq_data)); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 492 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 493 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 494 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 495 | } | 
 | 496 |  | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 497 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER | 
 | 498 | /** | 
 | 499 |  *	handle_edge_eoi_irq - edge eoi type IRQ handler | 
 | 500 |  *	@irq:	the interrupt number | 
 | 501 |  *	@desc:	the interrupt description structure for this irq | 
 | 502 |  * | 
 | 503 |  * Similar as the above handle_edge_irq, but using eoi and w/o the | 
 | 504 |  * mask/unmask logic. | 
 | 505 |  */ | 
 | 506 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | 
 | 507 | { | 
 | 508 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
 | 509 |  | 
 | 510 | 	raw_spin_lock(&desc->lock); | 
 | 511 |  | 
 | 512 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
 | 513 | 	/* | 
 | 514 | 	 * If we're currently running this IRQ, or its disabled, | 
 | 515 | 	 * we shouldn't process the IRQ. Mark it pending, handle | 
 | 516 | 	 * the necessary masking and go out | 
 | 517 | 	 */ | 
 | 518 | 	if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
 | 519 | 		     irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
 | 520 | 		if (!irq_check_poll(desc)) { | 
 | 521 | 			desc->istate |= IRQS_PENDING; | 
 | 522 | 			goto out_eoi; | 
 | 523 | 		} | 
 | 524 | 	} | 
 | 525 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 526 |  | 
 | 527 | 	do { | 
 | 528 | 		if (unlikely(!desc->action)) | 
 | 529 | 			goto out_eoi; | 
 | 530 |  | 
 | 531 | 		handle_irq_event(desc); | 
 | 532 |  | 
 | 533 | 	} while ((desc->istate & IRQS_PENDING) && | 
 | 534 | 		 !irqd_irq_disabled(&desc->irq_data)); | 
 | 535 |  | 
| Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 536 | out_eoi: | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 537 | 	chip->irq_eoi(&desc->irq_data); | 
 | 538 | 	raw_spin_unlock(&desc->lock); | 
 | 539 | } | 
 | 540 | #endif | 
 | 541 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 542 | /** | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 543 |  *	handle_percpu_irq - Per CPU local irq handler | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 |  *	@irq:	the interrupt number | 
 | 545 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 546 |  * | 
 | 547 |  *	Per CPU interrupts on SMP machines without locking requirements | 
 | 548 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 549 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 550 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 551 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 552 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 553 |  | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 554 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 555 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 556 | 	if (chip->irq_ack) | 
 | 557 | 		chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 558 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 559 | 	handle_irq_event_percpu(desc, desc->action); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 560 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 561 | 	if (chip->irq_eoi) | 
 | 562 | 		chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 563 | } | 
 | 564 |  | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 565 | /** | 
 | 566 |  * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | 
 | 567 |  * @irq:	the interrupt number | 
 | 568 |  * @desc:	the interrupt description structure for this irq | 
 | 569 |  * | 
 | 570 |  * Per CPU interrupts on SMP machines without locking requirements. Same as | 
 | 571 |  * handle_percpu_irq() above but with the following extras: | 
 | 572 |  * | 
 | 573 |  * action->percpu_dev_id is a pointer to percpu variables which | 
 | 574 |  * contain the real device id for the cpu on which this handler is | 
 | 575 |  * called | 
 | 576 |  */ | 
 | 577 | void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) | 
 | 578 | { | 
 | 579 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
 | 580 | 	struct irqaction *action = desc->action; | 
 | 581 | 	void *dev_id = __this_cpu_ptr(action->percpu_dev_id); | 
 | 582 | 	irqreturn_t res; | 
 | 583 |  | 
 | 584 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 585 |  | 
 | 586 | 	if (chip->irq_ack) | 
 | 587 | 		chip->irq_ack(&desc->irq_data); | 
 | 588 |  | 
 | 589 | 	trace_irq_handler_entry(irq, action); | 
 | 590 | 	res = action->handler(irq, dev_id); | 
 | 591 | 	trace_irq_handler_exit(irq, action, res); | 
 | 592 |  | 
 | 593 | 	if (chip->irq_eoi) | 
 | 594 | 		chip->irq_eoi(&desc->irq_data); | 
 | 595 | } | 
 | 596 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 597 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 598 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 599 | 		  const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 600 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 601 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 602 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 604 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 605 | 		return; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 606 |  | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 607 | 	if (!handle) { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 608 | 		handle = handle_bad_irq; | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 609 | 	} else { | 
 | 610 | 		if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 611 | 			goto out; | 
| Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 612 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 613 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 614 | 	/* Uninstall? */ | 
 | 615 | 	if (handle == handle_bad_irq) { | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 616 | 		if (desc->irq_data.chip != &no_irq_chip) | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 617 | 			mask_ack_irq(desc); | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 618 | 		irq_state_set_disabled(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 619 | 		desc->depth = 1; | 
 | 620 | 	} | 
 | 621 | 	desc->handle_irq = handle; | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 622 | 	desc->name = name; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 623 |  | 
 | 624 | 	if (handle != handle_bad_irq && is_chained) { | 
| Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 625 | 		irq_settings_set_noprobe(desc); | 
 | 626 | 		irq_settings_set_norequest(desc); | 
| Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 627 | 		irq_settings_set_nothread(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 628 | 		irq_startup(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 629 | 	} | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 630 | out: | 
 | 631 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 632 | } | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 633 | EXPORT_SYMBOL_GPL(__irq_set_handler); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 634 |  | 
 | 635 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 636 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 637 | 			      irq_flow_handler_t handle, const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 638 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 639 | 	irq_set_chip(irq, chip); | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 640 | 	__irq_set_handler(irq, handle, 0, name); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 641 | } | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 642 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 643 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 644 | { | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 645 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 646 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 647 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 648 | 	if (!desc) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 649 | 		return; | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 650 | 	irq_settings_clr_and_set(desc, clr, set); | 
 | 651 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 652 | 	irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 653 | 		   IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 654 | 	if (irq_settings_has_no_balance_set(desc)) | 
 | 655 | 		irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | 
 | 656 | 	if (irq_settings_is_per_cpu(desc)) | 
 | 657 | 		irqd_set(&desc->irq_data, IRQD_PER_CPU); | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 658 | 	if (irq_settings_can_move_pcntxt(desc)) | 
 | 659 | 		irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 660 | 	if (irq_settings_is_level(desc)) | 
 | 661 | 		irqd_set(&desc->irq_data, IRQD_LEVEL); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 662 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 663 | 	irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); | 
 | 664 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 665 | 	irq_put_desc_unlock(desc, flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 666 | } | 
| Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 667 | EXPORT_SYMBOL_GPL(irq_modify_status); | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 668 |  | 
 | 669 | /** | 
 | 670 |  *	irq_cpu_online - Invoke all irq_cpu_online functions. | 
 | 671 |  * | 
 | 672 |  *	Iterate through all irqs and invoke the chip.irq_cpu_online() | 
 | 673 |  *	for each. | 
 | 674 |  */ | 
 | 675 | void irq_cpu_online(void) | 
 | 676 | { | 
 | 677 | 	struct irq_desc *desc; | 
 | 678 | 	struct irq_chip *chip; | 
 | 679 | 	unsigned long flags; | 
 | 680 | 	unsigned int irq; | 
 | 681 |  | 
 | 682 | 	for_each_active_irq(irq) { | 
 | 683 | 		desc = irq_to_desc(irq); | 
 | 684 | 		if (!desc) | 
 | 685 | 			continue; | 
 | 686 |  | 
 | 687 | 		raw_spin_lock_irqsave(&desc->lock, flags); | 
 | 688 |  | 
 | 689 | 		chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 690 | 		if (chip && chip->irq_cpu_online && | 
 | 691 | 		    (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 692 | 		     !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 693 | 			chip->irq_cpu_online(&desc->irq_data); | 
 | 694 |  | 
 | 695 | 		raw_spin_unlock_irqrestore(&desc->lock, flags); | 
 | 696 | 	} | 
 | 697 | } | 
 | 698 |  | 
 | 699 | /** | 
 | 700 |  *	irq_cpu_offline - Invoke all irq_cpu_offline functions. | 
 | 701 |  * | 
 | 702 |  *	Iterate through all irqs and invoke the chip.irq_cpu_offline() | 
 | 703 |  *	for each. | 
 | 704 |  */ | 
 | 705 | void irq_cpu_offline(void) | 
 | 706 | { | 
 | 707 | 	struct irq_desc *desc; | 
 | 708 | 	struct irq_chip *chip; | 
 | 709 | 	unsigned long flags; | 
 | 710 | 	unsigned int irq; | 
 | 711 |  | 
 | 712 | 	for_each_active_irq(irq) { | 
 | 713 | 		desc = irq_to_desc(irq); | 
 | 714 | 		if (!desc) | 
 | 715 | 			continue; | 
 | 716 |  | 
 | 717 | 		raw_spin_lock_irqsave(&desc->lock, flags); | 
 | 718 |  | 
 | 719 | 		chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 720 | 		if (chip && chip->irq_cpu_offline && | 
 | 721 | 		    (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 722 | 		     !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 723 | 			chip->irq_cpu_offline(&desc->irq_data); | 
 | 724 |  | 
 | 725 | 		raw_spin_unlock_irqrestore(&desc->lock, flags); | 
 | 726 | 	} | 
 | 727 | } |