blob: 10bd65b7c567d9de43c3563ef51126720ce2b5db [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
19#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080020
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#include <linux/input/pmic8058-keypad.h>
22#include <linux/pmic8058-batt-alarm.h>
23#include <linux/pmic8058-pwrkey.h>
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +053024#include <linux/rtc/rtc-pm8058.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <linux/pmic8058-vibrator.h>
26#include <linux/leds.h>
27#include <linux/pmic8058-othc.h>
28#include <linux/mfd/pmic8901.h>
29#include <linux/regulator/pmic8058-regulator.h>
30#include <linux/regulator/pmic8901-regulator.h>
31#include <linux/bootmem.h>
32#include <linux/pwm.h>
33#include <linux/pmic8058-pwm.h>
34#include <linux/leds-pmic8058.h>
35#include <linux/pmic8058-xoadc.h>
36#include <linux/msm_adc.h>
37#include <linux/m_adcproc.h>
38#include <linux/mfd/marimba.h>
39#include <linux/msm-charger.h>
40#include <linux/i2c.h>
41#include <linux/i2c/sx150x.h>
42#include <linux/smsc911x.h>
43#include <linux/spi/spi.h>
44#include <linux/input/tdisc_shinetsu.h>
45#include <linux/input/cy8c_ts.h>
46#include <linux/cyttsp.h>
47#include <linux/i2c/isa1200.h>
48#include <linux/dma-mapping.h>
49#include <linux/i2c/bq27520.h>
50
51#ifdef CONFIG_ANDROID_PMEM
52#include <linux/android_pmem.h>
53#endif
54
55#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
56#include <linux/i2c/smb137b.h>
57#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080058#include <asm/mach-types.h>
59#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080061
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070062#include <mach/dma.h>
63#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080064#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070065#include <mach/irqs.h>
66#include <mach/msm_spi.h>
67#include <mach/msm_serial_hs.h>
68#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080069#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#include <mach/msm_memtypes.h>
71#include <asm/mach/mmc.h>
72#include <mach/msm_battery.h>
73#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070074#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070075#ifdef CONFIG_MSM_DSPS
76#include <mach/msm_dsps.h>
77#endif
78#include <mach/msm_xo.h>
79#include <mach/msm_bus_board.h>
80#include <mach/socinfo.h>
81#include <linux/i2c/isl9519.h>
82#ifdef CONFIG_USB_G_ANDROID
83#include <linux/usb/android.h>
84#include <mach/usbdiag.h>
85#endif
86#include <linux/regulator/consumer.h>
87#include <linux/regulator/machine.h>
88#include <mach/sdio_al.h>
89#include <mach/rpm.h>
90#include <mach/rpm-regulator.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080091
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070092#include "devices.h"
93#include "devices-msm8x60.h"
94#include "cpuidle.h"
95#include "pm.h"
96#include "mpm.h"
97#include "spm.h"
98#include "rpm_log.h"
99#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100#include "gpiomux-8x60.h"
101#include "rpm_stats.h"
102#include "peripheral-loader.h"
103#include <linux/platform_data/qcom_crypto_device.h>
104#include "rpm_resources.h"
Steve Mucklea55df6e2010-01-07 12:43:24 -0800105
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700106#define MSM_SHARED_RAM_PHYS 0x40000000
107
108/* Macros assume PMIC GPIOs start at 0 */
109#define PM8058_GPIO_BASE NR_MSM_GPIOS
110#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
111#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
112#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
113#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
114#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
115#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
116
117#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
118 PM8058_GPIOS + PM8058_MPPS)
119#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
120#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
121#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
122 NR_PMIC8058_IRQS)
123
124#define MDM2AP_SYNC 129
125
Terence Hampson1c73fef2011-07-19 17:10:49 -0400126#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700127#define LCDC_SPI_GPIO_CLK 73
128#define LCDC_SPI_GPIO_CS 72
129#define LCDC_SPI_GPIO_MOSI 70
130#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
131#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
132#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
133#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
134#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400135#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700136
137#define DSPS_PIL_GENERIC_NAME "dsps"
138#define DSPS_PIL_FLUID_NAME "dsps_fluid"
139
140enum {
141 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
142 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
143 /* CORE expander */
144 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
145 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
146 GPIO_WLAN_DEEP_SLEEP_N,
147 GPIO_LVDS_SHUTDOWN_N,
148 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
149 GPIO_MS_SYS_RESET_N,
150 GPIO_CAP_TS_RESOUT_N,
151 GPIO_CAP_GAUGE_BI_TOUT,
152 GPIO_ETHERNET_PME,
153 GPIO_EXT_GPS_LNA_EN,
154 GPIO_MSM_WAKES_BT,
155 GPIO_ETHERNET_RESET_N,
156 GPIO_HEADSET_DET_N,
157 GPIO_USB_UICC_EN,
158 GPIO_BACKLIGHT_EN,
159 GPIO_EXT_CAMIF_PWR_EN,
160 GPIO_BATT_GAUGE_INT_N,
161 GPIO_BATT_GAUGE_EN,
162 /* DOCKING expander */
163 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
164 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
165 GPIO_AUX_JTAG_DET_N,
166 GPIO_DONGLE_DET_N,
167 GPIO_SVIDEO_LOAD_DET,
168 GPIO_SVID_AMP_SHUTDOWN1_N,
169 GPIO_SVID_AMP_SHUTDOWN0_N,
170 GPIO_SDC_WP,
171 GPIO_IRDA_PWDN,
172 GPIO_IRDA_RESET_N,
173 GPIO_DONGLE_GPIO0,
174 GPIO_DONGLE_GPIO1,
175 GPIO_DONGLE_GPIO2,
176 GPIO_DONGLE_GPIO3,
177 GPIO_DONGLE_PWR_EN,
178 GPIO_EMMC_RESET_N,
179 GPIO_TP_EXP2_IO15,
180 /* SURF expander */
181 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
182 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
183 GPIO_SD_CARD_DET_2,
184 GPIO_SD_CARD_DET_4,
185 GPIO_SD_CARD_DET_5,
186 GPIO_UIM3_RST,
187 GPIO_SURF_EXPANDER_IO5,
188 GPIO_SURF_EXPANDER_IO6,
189 GPIO_ADC_I2C_EN,
190 GPIO_SURF_EXPANDER_IO8,
191 GPIO_SURF_EXPANDER_IO9,
192 GPIO_SURF_EXPANDER_IO10,
193 GPIO_SURF_EXPANDER_IO11,
194 GPIO_SURF_EXPANDER_IO12,
195 GPIO_SURF_EXPANDER_IO13,
196 GPIO_SURF_EXPANDER_IO14,
197 GPIO_SURF_EXPANDER_IO15,
198 /* LEFT KB IO expander */
199 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
200 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
201 GPIO_LEFT_LED_2,
202 GPIO_LEFT_LED_3,
203 GPIO_LEFT_LED_WLAN,
204 GPIO_JOYSTICK_EN,
205 GPIO_CAP_TS_SLEEP,
206 GPIO_LEFT_KB_IO6,
207 GPIO_LEFT_LED_5,
208 /* RIGHT KB IO expander */
209 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
210 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
211 GPIO_RIGHT_LED_2,
212 GPIO_RIGHT_LED_3,
213 GPIO_RIGHT_LED_BT,
214 GPIO_WEB_CAMIF_STANDBY,
215 GPIO_COMPASS_RST_N,
216 GPIO_WEB_CAMIF_RESET_N,
217 GPIO_RIGHT_LED_5,
218 GPIO_R_ALTIMETER_RESET_N,
219 /* FLUID S IO expander */
220 GPIO_SOUTH_EXPANDER_BASE,
221 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
222 GPIO_MIC1_ANCL_SEL,
223 GPIO_HS_MIC4_SEL,
224 GPIO_FML_MIC3_SEL,
225 GPIO_FMR_MIC5_SEL,
226 GPIO_TS_SLEEP,
227 GPIO_HAP_SHIFT_LVL_OE,
228 GPIO_HS_SW_DIR,
229 /* FLUID N IO expander */
230 GPIO_NORTH_EXPANDER_BASE,
231 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
232 GPIO_EPM_5V_BOOST_EN,
233 GPIO_AUX_CAM_2P7_EN,
234 GPIO_LED_FLASH_EN,
235 GPIO_LED1_GREEN_N,
236 GPIO_LED2_RED_N,
237 GPIO_FRONT_CAM_RESET_N,
238 GPIO_EPM_LVLSFT_EN,
239 GPIO_N_ALTIMETER_RESET_N,
240 /* EPM expander */
241 GPIO_EPM_EXPANDER_BASE,
242 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
243 GPIO_PWR_MON_RESET_N,
244 GPIO_ADC1_PWDN_N,
245 GPIO_ADC2_PWDN_N,
246 GPIO_EPM_EXPANDER_IO4,
247 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
248 GPIO_ADC2_MUX_SPI_INT_N,
249 GPIO_EPM_EXPANDER_IO7,
250 GPIO_PWR_MON_ENABLE,
251 GPIO_EPM_SPI_ADC1_CS_N,
252 GPIO_EPM_SPI_ADC2_CS_N,
253 GPIO_EPM_EXPANDER_IO11,
254 GPIO_EPM_EXPANDER_IO12,
255 GPIO_EPM_EXPANDER_IO13,
256 GPIO_EPM_EXPANDER_IO14,
257 GPIO_EPM_EXPANDER_IO15,
258};
259
260/*
261 * The UI_INTx_N lines are pmic gpio lines which connect i2c
262 * gpio expanders to the pm8058.
263 */
264#define UI_INT1_N 25
265#define UI_INT2_N 34
266#define UI_INT3_N 14
267/*
268FM GPIO is GPIO 18 on PMIC 8058.
269As the index starts from 0 in the PMIC driver, and hence 17
270corresponds to GPIO 18 on PMIC 8058.
271*/
272#define FM_GPIO 17
273
274#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
275static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
276static void *sdc2_status_notify_cb_devid;
277#endif
278
279#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
280static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
281static void *sdc5_status_notify_cb_devid;
282#endif
283
284static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
285 [0] = {
286 .reg_base_addr = MSM_SAW0_BASE,
287
288#ifdef CONFIG_MSM_AVS_HW
289 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
290#endif
291 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
292 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
293 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
294 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
295
296 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
297 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
298 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
299
300 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
301 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
302 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
303
304 .awake_vlevel = 0x94,
305 .retention_vlevel = 0x81,
306 .collapse_vlevel = 0x20,
307 .retention_mid_vlevel = 0x94,
308 .collapse_mid_vlevel = 0x8C,
309
310 .vctl_timeout_us = 50,
311 },
312
313 [1] = {
314 .reg_base_addr = MSM_SAW1_BASE,
315
316#ifdef CONFIG_MSM_AVS_HW
317 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
318#endif
319 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
320 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
321 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
322 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
323
324 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
325 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
326 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
327
328 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
329 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
330 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
331
332 .awake_vlevel = 0x94,
333 .retention_vlevel = 0x81,
334 .collapse_vlevel = 0x20,
335 .retention_mid_vlevel = 0x94,
336 .collapse_mid_vlevel = 0x8C,
337
338 .vctl_timeout_us = 50,
339 },
340};
341
342static struct msm_spm_platform_data msm_spm_data[] __initdata = {
343 [0] = {
344 .reg_base_addr = MSM_SAW0_BASE,
345
346#ifdef CONFIG_MSM_AVS_HW
347 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
348#endif
349 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
350 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
351 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
352 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
353
354 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
355 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
356 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
357
358 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
359 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
360 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
361
362 .awake_vlevel = 0xA0,
363 .retention_vlevel = 0x89,
364 .collapse_vlevel = 0x20,
365 .retention_mid_vlevel = 0x89,
366 .collapse_mid_vlevel = 0x89,
367
368 .vctl_timeout_us = 50,
369 },
370
371 [1] = {
372 .reg_base_addr = MSM_SAW1_BASE,
373
374#ifdef CONFIG_MSM_AVS_HW
375 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
376#endif
377 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
378 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
379 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
380 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
381
382 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
383 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
384 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
385
386 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
387 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
388 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
389
390 .awake_vlevel = 0xA0,
391 .retention_vlevel = 0x89,
392 .collapse_vlevel = 0x20,
393 .retention_mid_vlevel = 0x89,
394 .collapse_mid_vlevel = 0x89,
395
396 .vctl_timeout_us = 50,
397 },
398};
399
400static struct msm_acpu_clock_platform_data msm8x60_acpu_clock_data = {
401};
402
403/*
404 * Consumer specific regulator names:
405 * regulator name consumer dev_name
406 */
407static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
408 REGULATOR_SUPPLY("8901_s0", NULL),
409};
410static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
411 REGULATOR_SUPPLY("8901_s1", NULL),
412};
413
414static struct regulator_init_data saw_s0_init_data = {
415 .constraints = {
416 .name = "8901_s0",
417 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
418 .min_uV = 840000,
419 .max_uV = 1250000,
420 },
421 .consumer_supplies = vreg_consumers_8901_S0,
422 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
423};
424
425static struct regulator_init_data saw_s1_init_data = {
426 .constraints = {
427 .name = "8901_s1",
428 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
429 .min_uV = 840000,
430 .max_uV = 1250000,
431 },
432 .consumer_supplies = vreg_consumers_8901_S1,
433 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
434};
435
436static struct platform_device msm_device_saw_s0 = {
437 .name = "saw-regulator",
438 .id = 0,
439 .dev = {
440 .platform_data = &saw_s0_init_data,
441 },
442};
443
444static struct platform_device msm_device_saw_s1 = {
445 .name = "saw-regulator",
446 .id = 1,
447 .dev = {
448 .platform_data = &saw_s1_init_data,
449 },
450};
451
452/*
453 * The smc91x configuration varies depending on platform.
454 * The resources data structure is filled in at runtime.
455 */
456static struct resource smc91x_resources[] = {
457 [0] = {
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .flags = IORESOURCE_IRQ,
462 },
463};
464
465static struct platform_device smc91x_device = {
466 .name = "smc91x",
467 .id = 0,
468 .num_resources = ARRAY_SIZE(smc91x_resources),
469 .resource = smc91x_resources,
470};
471
472static struct resource smsc911x_resources[] = {
473 [0] = {
474 .flags = IORESOURCE_MEM,
475 .start = 0x1b800000,
476 .end = 0x1b8000ff
477 },
478 [1] = {
479 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
480 },
481};
482
483static struct smsc911x_platform_config smsc911x_config = {
484 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
485 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
486 .flags = SMSC911X_USE_16BIT,
487 .has_reset_gpio = 1,
488 .reset_gpio = GPIO_ETHERNET_RESET_N
489};
490
491static struct platform_device smsc911x_device = {
492 .name = "smsc911x",
493 .id = 0,
494 .num_resources = ARRAY_SIZE(smsc911x_resources),
495 .resource = smsc911x_resources,
496 .dev = {
497 .platform_data = &smsc911x_config
498 }
499};
500
501#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
502 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
503 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
504 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
505
506#define QCE_SIZE 0x10000
507#define QCE_0_BASE 0x18500000
508
509#define QCE_HW_KEY_SUPPORT 0
510#define QCE_SHA_HMAC_SUPPORT 0
511#define QCE_SHARE_CE_RESOURCE 2
512#define QCE_CE_SHARED 1
513
514static struct resource qcrypto_resources[] = {
515 [0] = {
516 .start = QCE_0_BASE,
517 .end = QCE_0_BASE + QCE_SIZE - 1,
518 .flags = IORESOURCE_MEM,
519 },
520 [1] = {
521 .name = "crypto_channels",
522 .start = DMOV_CE_IN_CHAN,
523 .end = DMOV_CE_OUT_CHAN,
524 .flags = IORESOURCE_DMA,
525 },
526 [2] = {
527 .name = "crypto_crci_in",
528 .start = DMOV_CE_IN_CRCI,
529 .end = DMOV_CE_IN_CRCI,
530 .flags = IORESOURCE_DMA,
531 },
532 [3] = {
533 .name = "crypto_crci_out",
534 .start = DMOV_CE_OUT_CRCI,
535 .end = DMOV_CE_OUT_CRCI,
536 .flags = IORESOURCE_DMA,
537 },
538 [4] = {
539 .name = "crypto_crci_hash",
540 .start = DMOV_CE_HASH_CRCI,
541 .end = DMOV_CE_HASH_CRCI,
542 .flags = IORESOURCE_DMA,
543 },
544};
545
546static struct resource qcedev_resources[] = {
547 [0] = {
548 .start = QCE_0_BASE,
549 .end = QCE_0_BASE + QCE_SIZE - 1,
550 .flags = IORESOURCE_MEM,
551 },
552 [1] = {
553 .name = "crypto_channels",
554 .start = DMOV_CE_IN_CHAN,
555 .end = DMOV_CE_OUT_CHAN,
556 .flags = IORESOURCE_DMA,
557 },
558 [2] = {
559 .name = "crypto_crci_in",
560 .start = DMOV_CE_IN_CRCI,
561 .end = DMOV_CE_IN_CRCI,
562 .flags = IORESOURCE_DMA,
563 },
564 [3] = {
565 .name = "crypto_crci_out",
566 .start = DMOV_CE_OUT_CRCI,
567 .end = DMOV_CE_OUT_CRCI,
568 .flags = IORESOURCE_DMA,
569 },
570 [4] = {
571 .name = "crypto_crci_hash",
572 .start = DMOV_CE_HASH_CRCI,
573 .end = DMOV_CE_HASH_CRCI,
574 .flags = IORESOURCE_DMA,
575 },
576};
577
578#endif
579
580#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
581 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
582
583static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
584 .ce_shared = QCE_CE_SHARED,
585 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
586 .hw_key_support = QCE_HW_KEY_SUPPORT,
587 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
588};
589
590static struct platform_device qcrypto_device = {
591 .name = "qcrypto",
592 .id = 0,
593 .num_resources = ARRAY_SIZE(qcrypto_resources),
594 .resource = qcrypto_resources,
595 .dev = {
596 .coherent_dma_mask = DMA_BIT_MASK(32),
597 .platform_data = &qcrypto_ce_hw_suppport,
598 },
599};
600#endif
601
602#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
603 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
604
605static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
606 .ce_shared = QCE_CE_SHARED,
607 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
608 .hw_key_support = QCE_HW_KEY_SUPPORT,
609 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
610};
611
612static struct platform_device qcedev_device = {
613 .name = "qce",
614 .id = 0,
615 .num_resources = ARRAY_SIZE(qcedev_resources),
616 .resource = qcedev_resources,
617 .dev = {
618 .coherent_dma_mask = DMA_BIT_MASK(32),
619 .platform_data = &qcedev_ce_hw_suppport,
620 },
621};
622#endif
623
624#if defined(CONFIG_HAPTIC_ISA1200) || \
625 defined(CONFIG_HAPTIC_ISA1200_MODULE)
626
627static const char *vregs_isa1200_name[] = {
628 "8058_s3",
629 "8901_l4",
630};
631
632static const int vregs_isa1200_val[] = {
633 1800000,/* uV */
634 2600000,
635};
636static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
637static struct msm_xo_voter *xo_handle_a1;
638
639static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800640{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700641 int i, rc = 0;
642
643 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
644 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
645 regulator_disable(vregs_isa1200[i]);
646 if (rc < 0) {
647 pr_err("%s: vreg %s %s failed (%d)\n",
648 __func__, vregs_isa1200_name[i],
649 vreg_on ? "enable" : "disable", rc);
650 goto vreg_fail;
651 }
652 }
653
654 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
655 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
656 if (rc < 0) {
657 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
658 __func__, vreg_on ? "" : "de-", rc);
659 goto vreg_fail;
660 }
661 return 0;
662
663vreg_fail:
664 while (i--)
665 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
666 regulator_disable(vregs_isa1200[i]);
667 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800668}
669
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700670static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800671{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700672 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800673
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700674 if (enable == true) {
675 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
676 vregs_isa1200[i] = regulator_get(NULL,
677 vregs_isa1200_name[i]);
678 if (IS_ERR(vregs_isa1200[i])) {
679 pr_err("%s: regulator get of %s failed (%ld)\n",
680 __func__, vregs_isa1200_name[i],
681 PTR_ERR(vregs_isa1200[i]));
682 rc = PTR_ERR(vregs_isa1200[i]);
683 goto vreg_get_fail;
684 }
685 rc = regulator_set_voltage(vregs_isa1200[i],
686 vregs_isa1200_val[i], vregs_isa1200_val[i]);
687 if (rc) {
688 pr_err("%s: regulator_set_voltage(%s) failed\n",
689 __func__, vregs_isa1200_name[i]);
690 goto vreg_get_fail;
691 }
692 }
Steve Muckle9161d302010-02-11 11:50:40 -0800693
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700694 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
695 if (rc) {
696 pr_err("%s: unable to request gpio %d (%d)\n",
697 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
698 goto vreg_get_fail;
699 }
Steve Muckle9161d302010-02-11 11:50:40 -0800700
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700701 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
702 if (rc) {
703 pr_err("%s: Unable to set direction\n", __func__);;
704 goto free_gpio;
705 }
706
707 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
708 if (IS_ERR(xo_handle_a1)) {
709 rc = PTR_ERR(xo_handle_a1);
710 pr_err("%s: failed to get the handle for A1(%d)\n",
711 __func__, rc);
712 goto gpio_set_dir;
713 }
714 } else {
715 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
716 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
717
718 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
719 regulator_put(vregs_isa1200[i]);
720
721 msm_xo_put(xo_handle_a1);
722 }
723
724 return 0;
725gpio_set_dir:
726 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
727free_gpio:
728 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
729vreg_get_fail:
730 while (i)
731 regulator_put(vregs_isa1200[--i]);
732 return rc;
733}
734
735#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
736static struct isa1200_platform_data isa1200_1_pdata = {
737 .name = "vibrator",
738 .power_on = isa1200_power,
739 .dev_setup = isa1200_dev_setup,
740 /*gpio to enable haptic*/
741 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
742 .max_timeout = 15000,
743 .mode_ctrl = PWM_GEN_MODE,
744 .pwm_fd = {
745 .pwm_div = 256,
746 },
747 .is_erm = false,
748 .smart_en = true,
749 .ext_clk_en = true,
750 .chip_en = 1,
751};
752
753static struct i2c_board_info msm_isa1200_board_info[] = {
754 {
755 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
756 .platform_data = &isa1200_1_pdata,
757 },
758};
759#endif
760
761#if defined(CONFIG_BATTERY_BQ27520) || \
762 defined(CONFIG_BATTERY_BQ27520_MODULE)
763static struct bq27520_platform_data bq27520_pdata = {
764 .name = "fuel-gauge",
765 .vreg_name = "8058_s3",
766 .vreg_value = 1800000,
767 .soc_int = GPIO_BATT_GAUGE_INT_N,
768 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
769 .chip_en = GPIO_BATT_GAUGE_EN,
770 .enable_dlog = 0, /* if enable coulomb counter logger */
771};
772
773static struct i2c_board_info msm_bq27520_board_info[] = {
774 {
775 I2C_BOARD_INFO("bq27520", 0xaa>>1),
776 .platform_data = &bq27520_pdata,
777 },
778};
779#endif
780
781static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
782 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
783 .idle_supported = 1,
784 .suspend_supported = 1,
785 .idle_enabled = 0,
786 .suspend_enabled = 0,
787 .latency = 4000,
788 .residency = 13000,
789 },
790
791 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
792 .idle_supported = 1,
793 .suspend_supported = 1,
794 .idle_enabled = 0,
795 .suspend_enabled = 0,
796 .latency = 500,
797 .residency = 6000,
798 },
799
800 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
801 .idle_supported = 1,
802 .suspend_supported = 1,
803 .idle_enabled = 1,
804 .suspend_enabled = 1,
805 .latency = 2,
806 .residency = 0,
807 },
808
809 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
810 .idle_supported = 1,
811 .suspend_supported = 1,
812 .idle_enabled = 0,
813 .suspend_enabled = 0,
814 .latency = 600,
815 .residency = 7200,
816 },
817
818 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
819 .idle_supported = 1,
820 .suspend_supported = 1,
821 .idle_enabled = 0,
822 .suspend_enabled = 0,
823 .latency = 500,
824 .residency = 6000,
825 },
826
827 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
828 .idle_supported = 1,
829 .suspend_supported = 1,
830 .idle_enabled = 1,
831 .suspend_enabled = 1,
832 .latency = 2,
833 .residency = 0,
834 },
835};
836
837static struct msm_cpuidle_state msm_cstates[] __initdata = {
838 {0, 0, "C0", "WFI",
839 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
840
841 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
842 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
843
844 {0, 2, "C2", "POWER_COLLAPSE",
845 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
846
847 {1, 0, "C0", "WFI",
848 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
849
850 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
851 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
852};
853
854static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
855 {
856 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
857 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
858 true,
859 1, 8000, 100000, 1,
860 },
861
862 {
863 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
864 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
865 true,
866 1500, 5000, 60100000, 3000,
867 },
868
869 {
870 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
871 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
872 false,
873 1800, 5000, 60350000, 3500,
874 },
875 {
876 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
877 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
878 false,
879 3800, 4500, 65350000, 5500,
880 },
881
882 {
883 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
884 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
885 false,
886 2800, 2500, 66850000, 4800,
887 },
888
889 {
890 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
891 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
892 false,
893 4800, 2000, 71850000, 6800,
894 },
895
896 {
897 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
898 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
899 false,
900 6800, 500, 75850000, 8800,
901 },
902
903 {
904 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
905 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
906 false,
907 7800, 0, 76350000, 9800,
908 },
909};
910
911#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
912
913#define ISP1763_INT_GPIO 117
914#define ISP1763_RST_GPIO 152
915static struct resource isp1763_resources[] = {
916 [0] = {
917 .flags = IORESOURCE_MEM,
918 .start = 0x1D000000,
919 .end = 0x1D005FFF, /* 24KB */
920 },
921 [1] = {
922 .flags = IORESOURCE_IRQ,
923 },
924};
925static void __init msm8x60_cfg_isp1763(void)
926{
927 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
928 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
929}
930
931static int isp1763_setup_gpio(int enable)
932{
933 int status = 0;
934
935 if (enable) {
936 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
937 if (status) {
938 pr_err("%s:Failed to request GPIO %d\n",
939 __func__, ISP1763_INT_GPIO);
940 return status;
941 }
942 status = gpio_direction_input(ISP1763_INT_GPIO);
943 if (status) {
944 pr_err("%s:Failed to configure GPIO %d\n",
945 __func__, ISP1763_INT_GPIO);
946 goto gpio_free_int;
947 }
948 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
949 if (status) {
950 pr_err("%s:Failed to request GPIO %d\n",
951 __func__, ISP1763_RST_GPIO);
952 goto gpio_free_int;
953 }
954 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
955 if (status) {
956 pr_err("%s:Failed to configure GPIO %d\n",
957 __func__, ISP1763_RST_GPIO);
958 goto gpio_free_rst;
959 }
960 pr_debug("\nISP GPIO configuration done\n");
961 return status;
962 }
963
964gpio_free_rst:
965 gpio_free(ISP1763_RST_GPIO);
966gpio_free_int:
967 gpio_free(ISP1763_INT_GPIO);
968
969 return status;
970}
971static struct isp1763_platform_data isp1763_pdata = {
972 .reset_gpio = ISP1763_RST_GPIO,
973 .setup_gpio = isp1763_setup_gpio
974};
975
976static struct platform_device isp1763_device = {
977 .name = "isp1763_usb",
978 .num_resources = ARRAY_SIZE(isp1763_resources),
979 .resource = isp1763_resources,
980 .dev = {
981 .platform_data = &isp1763_pdata
982 }
983};
984#endif
985
986#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
987static struct regulator *ldo6_3p3;
988static struct regulator *ldo7_1p8;
989static struct regulator *vdd_cx;
990#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
991notify_vbus_state notify_vbus_state_func_ptr;
992static int usb_phy_susp_dig_vol = 750000;
993static int pmic_id_notif_supported;
994
995#ifdef CONFIG_USB_EHCI_MSM_72K
996#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
997struct delayed_work pmic_id_det;
998
999static int __init usb_id_pin_rework_setup(char *support)
1000{
1001 if (strncmp(support, "true", 4) == 0)
1002 pmic_id_notif_supported = 1;
1003
1004 return 1;
1005}
1006__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1007
1008static void pmic_id_detect(struct work_struct *w)
1009{
1010 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1011 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1012
1013 if (notify_vbus_state_func_ptr)
1014 (*notify_vbus_state_func_ptr) (val);
1015}
1016
1017static irqreturn_t pmic_id_on_irq(int irq, void *data)
1018{
1019 /*
1020 * Spurious interrupts are observed on pmic gpio line
1021 * even though there is no state change on USB ID. Schedule the
1022 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001023 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001024 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001025
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001026 return IRQ_HANDLED;
1027}
1028
1029static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1030{
1031 unsigned ret = -ENODEV;
1032
1033 if (!callback)
1034 return -EINVAL;
1035
1036 if (machine_is_msm8x60_fluid())
1037 return -ENOTSUPP;
1038
1039 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1040 pr_debug("%s: USB_ID pin is not routed to PMIC"
1041 "on V1 surf/ffa\n", __func__);
1042 return -ENOTSUPP;
1043 }
1044
1045 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1046 !pmic_id_notif_supported) {
1047 pr_debug("%s: USB_ID is not routed to PMIC"
1048 "on V2 ffa\n", __func__);
1049 return -ENOTSUPP;
1050 }
1051
1052 usb_phy_susp_dig_vol = 500000;
1053
1054 if (init) {
1055 notify_vbus_state_func_ptr = callback;
1056 ret = pm8901_mpp_config_digital_out(1,
1057 PM8901_MPP_DIG_LEVEL_L5, 1);
1058 if (ret) {
1059 pr_err("%s: MPP2 configuration failed\n", __func__);
1060 return -ENODEV;
1061 }
1062 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
1063 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1064 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1065 "msm_otg_id", NULL);
1066 if (ret) {
1067 pm8901_mpp_config_digital_out(1,
1068 PM8901_MPP_DIG_LEVEL_L5, 0);
1069 pr_err("%s:pmic_usb_id interrupt registration failed",
1070 __func__);
1071 return ret;
1072 }
1073 /* Notify the initial Id status */
1074 pmic_id_detect(&pmic_id_det.work);
1075 } else {
1076 free_irq(PMICID_INT, 0);
1077 cancel_delayed_work_sync(&pmic_id_det);
1078 notify_vbus_state_func_ptr = NULL;
1079 ret = pm8901_mpp_config_digital_out(1,
1080 PM8901_MPP_DIG_LEVEL_L5, 0);
1081 if (ret) {
1082 pr_err("%s:MPP2 configuration failed\n", __func__);
1083 return -ENODEV;
1084 }
1085 }
1086 return 0;
1087}
1088#endif
1089
1090#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1091#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1092static int msm_hsusb_init_vddcx(int init)
1093{
1094 int ret = 0;
1095
1096 if (init) {
1097 vdd_cx = regulator_get(NULL, "8058_s1");
1098 if (IS_ERR(vdd_cx)) {
1099 return PTR_ERR(vdd_cx);
1100 }
1101
1102 ret = regulator_set_voltage(vdd_cx,
1103 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1104 USB_PHY_MAX_VDD_DIG_VOL);
1105 if (ret) {
1106 pr_err("%s: unable to set the voltage for regulator"
1107 "vdd_cx\n", __func__);
1108 regulator_put(vdd_cx);
1109 return ret;
1110 }
1111
1112 ret = regulator_enable(vdd_cx);
1113 if (ret) {
1114 pr_err("%s: unable to enable regulator"
1115 "vdd_cx\n", __func__);
1116 regulator_put(vdd_cx);
1117 }
1118 } else {
1119 ret = regulator_disable(vdd_cx);
1120 if (ret) {
1121 pr_err("%s: Unable to disable the regulator:"
1122 "vdd_cx\n", __func__);
1123 return ret;
1124 }
1125
1126 regulator_put(vdd_cx);
1127 }
1128
1129 return ret;
1130}
1131
1132static int msm_hsusb_config_vddcx(int high)
1133{
1134 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1135 int min_vol;
1136 int ret;
1137
1138 if (high)
1139 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1140 else
1141 min_vol = usb_phy_susp_dig_vol;
1142
1143 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1144 if (ret) {
1145 pr_err("%s: unable to set the voltage for regulator"
1146 "vdd_cx\n", __func__);
1147 return ret;
1148 }
1149
1150 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1151
1152 return ret;
1153}
1154
1155#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1156#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1157#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1158#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1159
1160#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1161#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1162#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1163#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1164static int msm_hsusb_ldo_init(int init)
1165{
1166 int rc = 0;
1167
1168 if (init) {
1169 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1170 if (IS_ERR(ldo6_3p3))
1171 return PTR_ERR(ldo6_3p3);
1172
1173 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1174 if (IS_ERR(ldo7_1p8)) {
1175 rc = PTR_ERR(ldo7_1p8);
1176 goto put_3p3;
1177 }
1178
1179 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1180 USB_PHY_3P3_VOL_MAX);
1181 if (rc) {
1182 pr_err("%s: Unable to set voltage level for"
1183 "ldo6_3p3 regulator\n", __func__);
1184 goto put_1p8;
1185 }
1186 rc = regulator_enable(ldo6_3p3);
1187 if (rc) {
1188 pr_err("%s: Unable to enable the regulator:"
1189 "ldo6_3p3\n", __func__);
1190 goto put_1p8;
1191 }
1192 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1193 USB_PHY_1P8_VOL_MAX);
1194 if (rc) {
1195 pr_err("%s: Unable to set voltage level for"
1196 "ldo7_1p8 regulator\n", __func__);
1197 goto disable_3p3;
1198 }
1199 rc = regulator_enable(ldo7_1p8);
1200 if (rc) {
1201 pr_err("%s: Unable to enable the regulator:"
1202 "ldo7_1p8\n", __func__);
1203 goto disable_3p3;
1204 }
1205
1206 return 0;
1207 }
1208
1209 regulator_disable(ldo7_1p8);
1210disable_3p3:
1211 regulator_disable(ldo6_3p3);
1212put_1p8:
1213 regulator_put(ldo7_1p8);
1214put_3p3:
1215 regulator_put(ldo6_3p3);
1216 return rc;
1217}
1218
1219static int msm_hsusb_ldo_enable(int on)
1220{
1221 int ret = 0;
1222
1223 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1224 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1225 return -ENODEV;
1226 }
1227
1228 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1229 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1230 return -ENODEV;
1231 }
1232
1233 if (on) {
1234 ret = regulator_set_optimum_mode(ldo7_1p8,
1235 USB_PHY_1P8_HPM_LOAD);
1236 if (ret < 0) {
1237 pr_err("%s: Unable to set HPM of the regulator:"
1238 "ldo7_1p8\n", __func__);
1239 return ret;
1240 }
1241 ret = regulator_set_optimum_mode(ldo6_3p3,
1242 USB_PHY_3P3_HPM_LOAD);
1243 if (ret < 0) {
1244 pr_err("%s: Unable to set HPM of the regulator:"
1245 "ldo6_3p3\n", __func__);
1246 regulator_set_optimum_mode(ldo7_1p8,
1247 USB_PHY_1P8_LPM_LOAD);
1248 return ret;
1249 }
1250 } else {
1251 ret = regulator_set_optimum_mode(ldo7_1p8,
1252 USB_PHY_1P8_LPM_LOAD);
1253 if (ret < 0)
1254 pr_err("%s: Unable to set LPM of the regulator:"
1255 "ldo7_1p8\n", __func__);
1256 ret = regulator_set_optimum_mode(ldo6_3p3,
1257 USB_PHY_3P3_LPM_LOAD);
1258 if (ret < 0)
1259 pr_err("%s: Unable to set LPM of the regulator:"
1260 "ldo6_3p3\n", __func__);
1261 }
1262
1263 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1264 return ret < 0 ? ret : 0;
1265 }
1266#endif
1267#ifdef CONFIG_USB_EHCI_MSM_72K
1268#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1269static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1270{
1271 static int vbus_is_on;
1272
1273 /* If VBUS is already on (or off), do nothing. */
1274 if (on == vbus_is_on)
1275 return;
1276 smb137b_otg_power(on);
1277 vbus_is_on = on;
1278}
1279#endif
1280static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1281{
1282 static struct regulator *votg_5v_switch;
1283 static struct regulator *ext_5v_reg;
1284 static int vbus_is_on;
1285
1286 /* If VBUS is already on (or off), do nothing. */
1287 if (on == vbus_is_on)
1288 return;
1289
1290 if (!votg_5v_switch) {
1291 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1292 if (IS_ERR(votg_5v_switch)) {
1293 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1294 return;
1295 }
1296 }
1297 if (!ext_5v_reg) {
1298 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1299 if (IS_ERR(ext_5v_reg)) {
1300 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1301 return;
1302 }
1303 }
1304 if (on) {
1305 if (regulator_enable(ext_5v_reg)) {
1306 pr_err("%s: Unable to enable the regulator:"
1307 " ext_5v_reg\n", __func__);
1308 return;
1309 }
1310 if (regulator_enable(votg_5v_switch)) {
1311 pr_err("%s: Unable to enable the regulator:"
1312 " votg_5v_switch\n", __func__);
1313 return;
1314 }
1315 } else {
1316 if (regulator_disable(votg_5v_switch))
1317 pr_err("%s: Unable to enable the regulator:"
1318 " votg_5v_switch\n", __func__);
1319 if (regulator_disable(ext_5v_reg))
1320 pr_err("%s: Unable to enable the regulator:"
1321 " ext_5v_reg\n", __func__);
1322 }
1323
1324 vbus_is_on = on;
1325}
1326
1327static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1328 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1329 .power_budget = 390,
1330};
1331#endif
1332
1333#ifdef CONFIG_BATTERY_MSM8X60
1334static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1335 int init)
1336{
1337 int ret = -ENOTSUPP;
1338
1339#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1340 if (machine_is_msm8x60_fluid()) {
1341 if (init)
1342 msm_charger_register_vbus_sn(callback);
1343 else
1344 msm_charger_unregister_vbus_sn(callback);
1345 return 0;
1346 }
1347#endif
1348 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1349 * hence, irrespective of either peripheral only mode or
1350 * OTG (host and peripheral) modes, can depend on pmic for
1351 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001352 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001353 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1354 && (machine_is_msm8x60_surf() ||
1355 pmic_id_notif_supported)) {
1356 if (init)
1357 ret = msm_charger_register_vbus_sn(callback);
1358 else {
1359 msm_charger_unregister_vbus_sn(callback);
1360 ret = 0;
1361 }
1362 } else {
1363#if !defined(CONFIG_USB_EHCI_MSM_72K)
1364 if (init)
1365 ret = msm_charger_register_vbus_sn(callback);
1366 else {
1367 msm_charger_unregister_vbus_sn(callback);
1368 ret = 0;
1369 }
1370#endif
1371 }
1372 return ret;
1373}
1374#endif
1375
1376#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1377static struct msm_otg_platform_data msm_otg_pdata = {
1378 /* if usb link is in sps there is no need for
1379 * usb pclk as dayatona fabric clock will be
1380 * used instead
1381 */
1382 .pclk_src_name = "dfab_usb_hs_clk",
1383 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1384 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1385 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301386 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001387#ifdef CONFIG_USB_EHCI_MSM_72K
1388 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
1389#endif
1390#ifdef CONFIG_USB_EHCI_MSM_72K
1391 .vbus_power = msm_hsusb_vbus_power,
1392#endif
1393#ifdef CONFIG_BATTERY_MSM8X60
1394 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1395#endif
1396 .ldo_init = msm_hsusb_ldo_init,
1397 .ldo_enable = msm_hsusb_ldo_enable,
1398 .config_vddcx = msm_hsusb_config_vddcx,
1399 .init_vddcx = msm_hsusb_init_vddcx,
1400#ifdef CONFIG_BATTERY_MSM8X60
1401 .chg_vbus_draw = msm_charger_vbus_draw,
1402#endif
1403};
1404#endif
1405
1406#ifdef CONFIG_USB_GADGET_MSM_72K
1407static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1408 .is_phy_status_timer_on = 1,
1409};
1410#endif
1411
1412#ifdef CONFIG_USB_G_ANDROID
1413
1414#define PID_MAGIC_ID 0x71432909
1415#define SERIAL_NUM_MAGIC_ID 0x61945374
1416#define SERIAL_NUMBER_LENGTH 127
1417#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1418
1419struct magic_num_struct {
1420 uint32_t pid;
1421 uint32_t serial_num;
1422};
1423
1424struct dload_struct {
1425 uint32_t reserved1;
1426 uint32_t reserved2;
1427 uint32_t reserved3;
1428 uint16_t reserved4;
1429 uint16_t pid;
1430 char serial_number[SERIAL_NUMBER_LENGTH];
1431 uint16_t reserved5;
1432 struct magic_num_struct
1433 magic_struct;
1434};
1435
1436static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1437{
1438 struct dload_struct __iomem *dload = 0;
1439
1440 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1441 if (!dload) {
1442 pr_err("%s: cannot remap I/O memory region: %08x\n",
1443 __func__, DLOAD_USB_BASE_ADD);
1444 return -ENXIO;
1445 }
1446
1447 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1448 __func__, dload, pid, snum);
1449 /* update pid */
1450 dload->magic_struct.pid = PID_MAGIC_ID;
1451 dload->pid = pid;
1452
1453 /* update serial number */
1454 dload->magic_struct.serial_num = 0;
1455 if (!snum)
1456 return 0;
1457
1458 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1459 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1460 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1461
1462 iounmap(dload);
1463
1464 return 0;
1465}
1466
1467static struct android_usb_platform_data android_usb_pdata = {
1468 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1469};
1470
1471static struct platform_device android_usb_device = {
1472 .name = "android_usb",
1473 .id = -1,
1474 .dev = {
1475 .platform_data = &android_usb_pdata,
1476 },
1477};
1478
1479
1480#endif
1481
1482#ifdef CONFIG_MSM_VPE
1483static struct resource msm_vpe_resources[] = {
1484 {
1485 .start = 0x05300000,
1486 .end = 0x05300000 + SZ_1M - 1,
1487 .flags = IORESOURCE_MEM,
1488 },
1489 {
1490 .start = INT_VPE,
1491 .end = INT_VPE,
1492 .flags = IORESOURCE_IRQ,
1493 },
1494};
1495
1496static struct platform_device msm_vpe_device = {
1497 .name = "msm_vpe",
1498 .id = 0,
1499 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1500 .resource = msm_vpe_resources,
1501};
1502#endif
1503
1504#ifdef CONFIG_MSM_CAMERA
1505#ifdef CONFIG_MSM_CAMERA_FLASH
1506#define VFE_CAMIF_TIMER1_GPIO 29
1507#define VFE_CAMIF_TIMER2_GPIO 30
1508#define VFE_CAMIF_TIMER3_GPIO_INT 31
1509#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1510static struct msm_camera_sensor_flash_src msm_flash_src = {
1511 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1512 ._fsrc.pmic_src.num_of_src = 2,
1513 ._fsrc.pmic_src.low_current = 100,
1514 ._fsrc.pmic_src.high_current = 300,
1515 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1516 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1517 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1518};
1519#ifdef CONFIG_IMX074
1520static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1521 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1522 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1523 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1524 .flash_recharge_duration = 50000,
1525 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1526};
1527#endif
1528#endif
1529
1530int msm_cam_gpio_tbl[] = {
1531 32,/*CAMIF_MCLK*/
1532 47,/*CAMIF_I2C_DATA*/
1533 48,/*CAMIF_I2C_CLK*/
1534 105,/*STANDBY*/
1535};
1536
1537enum msm_cam_stat{
1538 MSM_CAM_OFF,
1539 MSM_CAM_ON,
1540};
1541
1542static int config_gpio_table(enum msm_cam_stat stat)
1543{
1544 int rc = 0, i = 0;
1545 if (stat == MSM_CAM_ON) {
1546 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1547 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1548 if (unlikely(rc < 0)) {
1549 pr_err("%s not able to get gpio\n", __func__);
1550 for (i--; i >= 0; i--)
1551 gpio_free(msm_cam_gpio_tbl[i]);
1552 break;
1553 }
1554 }
1555 } else {
1556 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1557 gpio_free(msm_cam_gpio_tbl[i]);
1558 }
1559 return rc;
1560}
1561
1562static struct msm_camera_sensor_platform_info sensor_board_info = {
1563 .mount_angle = 0
1564};
1565
1566/*external regulator VREG_5V*/
1567static struct regulator *reg_flash_5V;
1568
1569static int config_camera_on_gpios_fluid(void)
1570{
1571 int rc = 0;
1572
1573 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1574 if (IS_ERR(reg_flash_5V)) {
1575 pr_err("'%s' regulator not found, rc=%ld\n",
1576 "8901_mpp0", IS_ERR(reg_flash_5V));
1577 return -ENODEV;
1578 }
1579
1580 rc = regulator_enable(reg_flash_5V);
1581 if (rc) {
1582 pr_err("'%s' regulator enable failed, rc=%d\n",
1583 "8901_mpp0", rc);
1584 regulator_put(reg_flash_5V);
1585 return rc;
1586 }
1587
1588#ifdef CONFIG_IMX074
1589 sensor_board_info.mount_angle = 90;
1590#endif
1591 rc = config_gpio_table(MSM_CAM_ON);
1592 if (rc < 0) {
1593 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1594 "failed\n", __func__);
1595 return rc;
1596 }
1597
1598 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1599 if (rc < 0) {
1600 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1601 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1602 regulator_disable(reg_flash_5V);
1603 regulator_put(reg_flash_5V);
1604 return rc;
1605 }
1606 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1607 msleep(20);
1608 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1609
1610
1611 /*Enable LED_FLASH_EN*/
1612 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1613 if (rc < 0) {
1614 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1615 "failed\n", __func__, GPIO_LED_FLASH_EN);
1616
1617 regulator_disable(reg_flash_5V);
1618 regulator_put(reg_flash_5V);
1619 config_gpio_table(MSM_CAM_OFF);
1620 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1621 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1622 return rc;
1623 }
1624 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1625 msleep(20);
1626 return rc;
1627}
1628
1629
1630static void config_camera_off_gpios_fluid(void)
1631{
1632 regulator_disable(reg_flash_5V);
1633 regulator_put(reg_flash_5V);
1634
1635 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1636 gpio_free(GPIO_LED_FLASH_EN);
1637
1638 config_gpio_table(MSM_CAM_OFF);
1639
1640 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1641 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1642}
1643static int config_camera_on_gpios(void)
1644{
1645 int rc = 0;
1646
1647 if (machine_is_msm8x60_fluid())
1648 return config_camera_on_gpios_fluid();
1649
1650 rc = config_gpio_table(MSM_CAM_ON);
1651 if (rc < 0) {
1652 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1653 "failed\n", __func__);
1654 return rc;
1655 }
1656
Jilai Wang971f97f2011-07-13 14:25:25 -04001657 if (!machine_is_msm8x60_dragon()) {
1658 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1659 if (rc < 0) {
1660 config_gpio_table(MSM_CAM_OFF);
1661 pr_err("%s: CAMSENSOR gpio %d request"
1662 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1663 return rc;
1664 }
1665 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1666 msleep(20);
1667 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001668 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001669
1670#ifdef CONFIG_MSM_CAMERA_FLASH
1671#ifdef CONFIG_IMX074
1672 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1673 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1674#endif
1675#endif
1676 return rc;
1677}
1678
1679static void config_camera_off_gpios(void)
1680{
1681 if (machine_is_msm8x60_fluid())
1682 return config_camera_off_gpios_fluid();
1683
1684
1685 config_gpio_table(MSM_CAM_OFF);
1686
Jilai Wang971f97f2011-07-13 14:25:25 -04001687 if (!machine_is_msm8x60_dragon()) {
1688 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1689 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1690 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001691}
1692
1693#ifdef CONFIG_QS_S5K4E1
1694
1695#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1696
1697static int config_camera_on_gpios_qs_cam_fluid(void)
1698{
1699 int rc = 0;
1700
1701 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1702 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1703 if (rc < 0) {
1704 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1705 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1706 return rc;
1707 }
1708 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1709 msleep(20);
1710 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1711 msleep(20);
1712
1713 /*
1714 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1715 * to enable 2.7V power to Camera
1716 */
1717 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1718 if (rc < 0) {
1719 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1720 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1721 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1722 gpio_free(QS_CAM_HC37_CAM_PD);
1723 return rc;
1724 }
1725 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1726 msleep(20);
1727 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1728 msleep(20);
1729
1730 rc = config_camera_on_gpios_fluid();
1731 if (rc < 0) {
1732 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1733 " failed\n", __func__);
1734 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1735 gpio_free(QS_CAM_HC37_CAM_PD);
1736 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1737 gpio_free(GPIO_AUX_CAM_2P7_EN);
1738 return rc;
1739 }
1740 return rc;
1741}
1742
1743static void config_camera_off_gpios_qs_cam_fluid(void)
1744{
1745 /*
1746 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1747 * to disable 2.7V power to Camera
1748 */
1749 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1750 gpio_free(GPIO_AUX_CAM_2P7_EN);
1751
1752 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1753 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1754 gpio_free(QS_CAM_HC37_CAM_PD);
1755
1756 config_camera_off_gpios_fluid();
1757 return;
1758}
1759
1760static int config_camera_on_gpios_qs_cam(void)
1761{
1762 int rc = 0;
1763
1764 if (machine_is_msm8x60_fluid())
1765 return config_camera_on_gpios_qs_cam_fluid();
1766
1767 rc = config_camera_on_gpios();
1768 return rc;
1769}
1770
1771static void config_camera_off_gpios_qs_cam(void)
1772{
1773 if (machine_is_msm8x60_fluid())
1774 return config_camera_off_gpios_qs_cam_fluid();
1775
1776 config_camera_off_gpios();
1777 return;
1778}
1779#endif
1780
1781static int config_camera_on_gpios_web_cam(void)
1782{
1783 int rc = 0;
1784 rc = config_gpio_table(MSM_CAM_ON);
1785 if (rc < 0) {
1786 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1787 "failed\n", __func__);
1788 return rc;
1789 }
1790
Jilai Wang53d27a82011-07-13 14:32:58 -04001791 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001792 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1793 if (rc < 0) {
1794 config_gpio_table(MSM_CAM_OFF);
1795 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1796 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1797 return rc;
1798 }
1799 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1800 }
1801 return rc;
1802}
1803
1804static void config_camera_off_gpios_web_cam(void)
1805{
1806 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001807 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001808 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1809 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1810 }
1811 return;
1812}
1813
1814#ifdef CONFIG_MSM_BUS_SCALING
1815static struct msm_bus_vectors cam_init_vectors[] = {
1816 {
1817 .src = MSM_BUS_MASTER_VFE,
1818 .dst = MSM_BUS_SLAVE_SMI,
1819 .ab = 0,
1820 .ib = 0,
1821 },
1822 {
1823 .src = MSM_BUS_MASTER_VFE,
1824 .dst = MSM_BUS_SLAVE_EBI_CH0,
1825 .ab = 0,
1826 .ib = 0,
1827 },
1828 {
1829 .src = MSM_BUS_MASTER_VPE,
1830 .dst = MSM_BUS_SLAVE_SMI,
1831 .ab = 0,
1832 .ib = 0,
1833 },
1834 {
1835 .src = MSM_BUS_MASTER_VPE,
1836 .dst = MSM_BUS_SLAVE_EBI_CH0,
1837 .ab = 0,
1838 .ib = 0,
1839 },
1840 {
1841 .src = MSM_BUS_MASTER_JPEG_ENC,
1842 .dst = MSM_BUS_SLAVE_SMI,
1843 .ab = 0,
1844 .ib = 0,
1845 },
1846 {
1847 .src = MSM_BUS_MASTER_JPEG_ENC,
1848 .dst = MSM_BUS_SLAVE_EBI_CH0,
1849 .ab = 0,
1850 .ib = 0,
1851 },
1852};
1853
1854static struct msm_bus_vectors cam_preview_vectors[] = {
1855 {
1856 .src = MSM_BUS_MASTER_VFE,
1857 .dst = MSM_BUS_SLAVE_SMI,
1858 .ab = 0,
1859 .ib = 0,
1860 },
1861 {
1862 .src = MSM_BUS_MASTER_VFE,
1863 .dst = MSM_BUS_SLAVE_EBI_CH0,
1864 .ab = 283115520,
1865 .ib = 452984832,
1866 },
1867 {
1868 .src = MSM_BUS_MASTER_VPE,
1869 .dst = MSM_BUS_SLAVE_SMI,
1870 .ab = 0,
1871 .ib = 0,
1872 },
1873 {
1874 .src = MSM_BUS_MASTER_VPE,
1875 .dst = MSM_BUS_SLAVE_EBI_CH0,
1876 .ab = 0,
1877 .ib = 0,
1878 },
1879 {
1880 .src = MSM_BUS_MASTER_JPEG_ENC,
1881 .dst = MSM_BUS_SLAVE_SMI,
1882 .ab = 0,
1883 .ib = 0,
1884 },
1885 {
1886 .src = MSM_BUS_MASTER_JPEG_ENC,
1887 .dst = MSM_BUS_SLAVE_EBI_CH0,
1888 .ab = 0,
1889 .ib = 0,
1890 },
1891};
1892
1893static struct msm_bus_vectors cam_video_vectors[] = {
1894 {
1895 .src = MSM_BUS_MASTER_VFE,
1896 .dst = MSM_BUS_SLAVE_SMI,
1897 .ab = 283115520,
1898 .ib = 452984832,
1899 },
1900 {
1901 .src = MSM_BUS_MASTER_VFE,
1902 .dst = MSM_BUS_SLAVE_EBI_CH0,
1903 .ab = 283115520,
1904 .ib = 452984832,
1905 },
1906 {
1907 .src = MSM_BUS_MASTER_VPE,
1908 .dst = MSM_BUS_SLAVE_SMI,
1909 .ab = 319610880,
1910 .ib = 511377408,
1911 },
1912 {
1913 .src = MSM_BUS_MASTER_VPE,
1914 .dst = MSM_BUS_SLAVE_EBI_CH0,
1915 .ab = 0,
1916 .ib = 0,
1917 },
1918 {
1919 .src = MSM_BUS_MASTER_JPEG_ENC,
1920 .dst = MSM_BUS_SLAVE_SMI,
1921 .ab = 0,
1922 .ib = 0,
1923 },
1924 {
1925 .src = MSM_BUS_MASTER_JPEG_ENC,
1926 .dst = MSM_BUS_SLAVE_EBI_CH0,
1927 .ab = 0,
1928 .ib = 0,
1929 },
1930};
1931
1932static struct msm_bus_vectors cam_snapshot_vectors[] = {
1933 {
1934 .src = MSM_BUS_MASTER_VFE,
1935 .dst = MSM_BUS_SLAVE_SMI,
1936 .ab = 566231040,
1937 .ib = 905969664,
1938 },
1939 {
1940 .src = MSM_BUS_MASTER_VFE,
1941 .dst = MSM_BUS_SLAVE_EBI_CH0,
1942 .ab = 69984000,
1943 .ib = 111974400,
1944 },
1945 {
1946 .src = MSM_BUS_MASTER_VPE,
1947 .dst = MSM_BUS_SLAVE_SMI,
1948 .ab = 0,
1949 .ib = 0,
1950 },
1951 {
1952 .src = MSM_BUS_MASTER_VPE,
1953 .dst = MSM_BUS_SLAVE_EBI_CH0,
1954 .ab = 0,
1955 .ib = 0,
1956 },
1957 {
1958 .src = MSM_BUS_MASTER_JPEG_ENC,
1959 .dst = MSM_BUS_SLAVE_SMI,
1960 .ab = 320864256,
1961 .ib = 513382810,
1962 },
1963 {
1964 .src = MSM_BUS_MASTER_JPEG_ENC,
1965 .dst = MSM_BUS_SLAVE_EBI_CH0,
1966 .ab = 320864256,
1967 .ib = 513382810,
1968 },
1969};
1970
1971static struct msm_bus_vectors cam_zsl_vectors[] = {
1972 {
1973 .src = MSM_BUS_MASTER_VFE,
1974 .dst = MSM_BUS_SLAVE_SMI,
1975 .ab = 566231040,
1976 .ib = 905969664,
1977 },
1978 {
1979 .src = MSM_BUS_MASTER_VFE,
1980 .dst = MSM_BUS_SLAVE_EBI_CH0,
1981 .ab = 706199040,
1982 .ib = 1129918464,
1983 },
1984 {
1985 .src = MSM_BUS_MASTER_VPE,
1986 .dst = MSM_BUS_SLAVE_SMI,
1987 .ab = 0,
1988 .ib = 0,
1989 },
1990 {
1991 .src = MSM_BUS_MASTER_VPE,
1992 .dst = MSM_BUS_SLAVE_EBI_CH0,
1993 .ab = 0,
1994 .ib = 0,
1995 },
1996 {
1997 .src = MSM_BUS_MASTER_JPEG_ENC,
1998 .dst = MSM_BUS_SLAVE_SMI,
1999 .ab = 320864256,
2000 .ib = 513382810,
2001 },
2002 {
2003 .src = MSM_BUS_MASTER_JPEG_ENC,
2004 .dst = MSM_BUS_SLAVE_EBI_CH0,
2005 .ab = 320864256,
2006 .ib = 513382810,
2007 },
2008};
2009
2010static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2011 {
2012 .src = MSM_BUS_MASTER_VFE,
2013 .dst = MSM_BUS_SLAVE_SMI,
2014 .ab = 212336640,
2015 .ib = 339738624,
2016 },
2017 {
2018 .src = MSM_BUS_MASTER_VFE,
2019 .dst = MSM_BUS_SLAVE_EBI_CH0,
2020 .ab = 25090560,
2021 .ib = 40144896,
2022 },
2023 {
2024 .src = MSM_BUS_MASTER_VPE,
2025 .dst = MSM_BUS_SLAVE_SMI,
2026 .ab = 239708160,
2027 .ib = 383533056,
2028 },
2029 {
2030 .src = MSM_BUS_MASTER_VPE,
2031 .dst = MSM_BUS_SLAVE_EBI_CH0,
2032 .ab = 79902720,
2033 .ib = 127844352,
2034 },
2035 {
2036 .src = MSM_BUS_MASTER_JPEG_ENC,
2037 .dst = MSM_BUS_SLAVE_SMI,
2038 .ab = 0,
2039 .ib = 0,
2040 },
2041 {
2042 .src = MSM_BUS_MASTER_JPEG_ENC,
2043 .dst = MSM_BUS_SLAVE_EBI_CH0,
2044 .ab = 0,
2045 .ib = 0,
2046 },
2047};
2048
2049static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2050 {
2051 .src = MSM_BUS_MASTER_VFE,
2052 .dst = MSM_BUS_SLAVE_SMI,
2053 .ab = 0,
2054 .ib = 0,
2055 },
2056 {
2057 .src = MSM_BUS_MASTER_VFE,
2058 .dst = MSM_BUS_SLAVE_EBI_CH0,
2059 .ab = 300902400,
2060 .ib = 481443840,
2061 },
2062 {
2063 .src = MSM_BUS_MASTER_VPE,
2064 .dst = MSM_BUS_SLAVE_SMI,
2065 .ab = 230307840,
2066 .ib = 368492544,
2067 },
2068 {
2069 .src = MSM_BUS_MASTER_VPE,
2070 .dst = MSM_BUS_SLAVE_EBI_CH0,
2071 .ab = 245113344,
2072 .ib = 392181351,
2073 },
2074 {
2075 .src = MSM_BUS_MASTER_JPEG_ENC,
2076 .dst = MSM_BUS_SLAVE_SMI,
2077 .ab = 106536960,
2078 .ib = 170459136,
2079 },
2080 {
2081 .src = MSM_BUS_MASTER_JPEG_ENC,
2082 .dst = MSM_BUS_SLAVE_EBI_CH0,
2083 .ab = 106536960,
2084 .ib = 170459136,
2085 },
2086};
2087
2088static struct msm_bus_paths cam_bus_client_config[] = {
2089 {
2090 ARRAY_SIZE(cam_init_vectors),
2091 cam_init_vectors,
2092 },
2093 {
2094 ARRAY_SIZE(cam_preview_vectors),
2095 cam_preview_vectors,
2096 },
2097 {
2098 ARRAY_SIZE(cam_video_vectors),
2099 cam_video_vectors,
2100 },
2101 {
2102 ARRAY_SIZE(cam_snapshot_vectors),
2103 cam_snapshot_vectors,
2104 },
2105 {
2106 ARRAY_SIZE(cam_zsl_vectors),
2107 cam_zsl_vectors,
2108 },
2109 {
2110 ARRAY_SIZE(cam_stereo_video_vectors),
2111 cam_stereo_video_vectors,
2112 },
2113 {
2114 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2115 cam_stereo_snapshot_vectors,
2116 },
2117};
2118
2119static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2120 cam_bus_client_config,
2121 ARRAY_SIZE(cam_bus_client_config),
2122 .name = "msm_camera",
2123};
2124#endif
2125
2126struct msm_camera_device_platform_data msm_camera_device_data = {
2127 .camera_gpio_on = config_camera_on_gpios,
2128 .camera_gpio_off = config_camera_off_gpios,
2129 .ioext.csiphy = 0x04800000,
2130 .ioext.csisz = 0x00000400,
2131 .ioext.csiirq = CSI_0_IRQ,
2132 .ioclk.mclk_clk_rate = 24000000,
2133 .ioclk.vfe_clk_rate = 228570000,
2134#ifdef CONFIG_MSM_BUS_SCALING
2135 .cam_bus_scale_table = &cam_bus_client_pdata,
2136#endif
2137};
2138
2139#ifdef CONFIG_QS_S5K4E1
2140struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2141 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2142 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2143 .ioext.csiphy = 0x04800000,
2144 .ioext.csisz = 0x00000400,
2145 .ioext.csiirq = CSI_0_IRQ,
2146 .ioclk.mclk_clk_rate = 24000000,
2147 .ioclk.vfe_clk_rate = 228570000,
2148#ifdef CONFIG_MSM_BUS_SCALING
2149 .cam_bus_scale_table = &cam_bus_client_pdata,
2150#endif
2151};
2152#endif
2153
2154struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2155 .camera_gpio_on = config_camera_on_gpios_web_cam,
2156 .camera_gpio_off = config_camera_off_gpios_web_cam,
2157 .ioext.csiphy = 0x04900000,
2158 .ioext.csisz = 0x00000400,
2159 .ioext.csiirq = CSI_1_IRQ,
2160 .ioclk.mclk_clk_rate = 24000000,
2161 .ioclk.vfe_clk_rate = 228570000,
2162#ifdef CONFIG_MSM_BUS_SCALING
2163 .cam_bus_scale_table = &cam_bus_client_pdata,
2164#endif
2165};
2166
2167struct resource msm_camera_resources[] = {
2168 {
2169 .start = 0x04500000,
2170 .end = 0x04500000 + SZ_1M - 1,
2171 .flags = IORESOURCE_MEM,
2172 },
2173 {
2174 .start = VFE_IRQ,
2175 .end = VFE_IRQ,
2176 .flags = IORESOURCE_IRQ,
2177 },
2178};
2179#ifdef CONFIG_MT9E013
2180static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2181 .mount_angle = 0
2182};
2183
2184static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2185 .flash_type = MSM_CAMERA_FLASH_LED,
2186 .flash_src = &msm_flash_src
2187};
2188
2189static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2190 .sensor_name = "mt9e013",
2191 .sensor_reset = 106,
2192 .sensor_pwd = 85,
2193 .vcm_pwd = 1,
2194 .vcm_enable = 0,
2195 .pdata = &msm_camera_device_data,
2196 .resource = msm_camera_resources,
2197 .num_resources = ARRAY_SIZE(msm_camera_resources),
2198 .flash_data = &flash_mt9e013,
2199 .strobe_flash_data = &strobe_flash_xenon,
2200 .sensor_platform_info = &mt9e013_sensor_8660_info,
2201 .csi_if = 1
2202};
2203struct platform_device msm_camera_sensor_mt9e013 = {
2204 .name = "msm_camera_mt9e013",
2205 .dev = {
2206 .platform_data = &msm_camera_sensor_mt9e013_data,
2207 },
2208};
2209#endif
2210
2211#ifdef CONFIG_IMX074
2212static struct msm_camera_sensor_flash_data flash_imx074 = {
2213 .flash_type = MSM_CAMERA_FLASH_LED,
2214 .flash_src = &msm_flash_src
2215};
2216
2217static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2218 .sensor_name = "imx074",
2219 .sensor_reset = 106,
2220 .sensor_pwd = 85,
2221 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2222 .vcm_enable = 1,
2223 .pdata = &msm_camera_device_data,
2224 .resource = msm_camera_resources,
2225 .num_resources = ARRAY_SIZE(msm_camera_resources),
2226 .flash_data = &flash_imx074,
2227 .strobe_flash_data = &strobe_flash_xenon,
2228 .sensor_platform_info = &sensor_board_info,
2229 .csi_if = 1
2230};
2231struct platform_device msm_camera_sensor_imx074 = {
2232 .name = "msm_camera_imx074",
2233 .dev = {
2234 .platform_data = &msm_camera_sensor_imx074_data,
2235 },
2236};
2237#endif
2238#ifdef CONFIG_WEBCAM_OV9726
2239
2240static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2241 .mount_angle = 0
2242};
2243
2244static struct msm_camera_sensor_flash_data flash_ov9726 = {
2245 .flash_type = MSM_CAMERA_FLASH_LED,
2246 .flash_src = &msm_flash_src
2247};
2248static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2249 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002250 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002251 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2252 .sensor_pwd = 85,
2253 .vcm_pwd = 1,
2254 .vcm_enable = 0,
2255 .pdata = &msm_camera_device_data_web_cam,
2256 .resource = msm_camera_resources,
2257 .num_resources = ARRAY_SIZE(msm_camera_resources),
2258 .flash_data = &flash_ov9726,
2259 .sensor_platform_info = &ov9726_sensor_8660_info,
2260 .csi_if = 1
2261};
2262struct platform_device msm_camera_sensor_webcam_ov9726 = {
2263 .name = "msm_camera_ov9726",
2264 .dev = {
2265 .platform_data = &msm_camera_sensor_ov9726_data,
2266 },
2267};
2268#endif
2269#ifdef CONFIG_WEBCAM_OV7692
2270static struct msm_camera_sensor_flash_data flash_ov7692 = {
2271 .flash_type = MSM_CAMERA_FLASH_LED,
2272 .flash_src = &msm_flash_src
2273};
2274static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2275 .sensor_name = "ov7692",
2276 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2277 .sensor_pwd = 85,
2278 .vcm_pwd = 1,
2279 .vcm_enable = 0,
2280 .pdata = &msm_camera_device_data_web_cam,
2281 .resource = msm_camera_resources,
2282 .num_resources = ARRAY_SIZE(msm_camera_resources),
2283 .flash_data = &flash_ov7692,
2284 .csi_if = 1
2285};
2286
2287static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2288 .name = "msm_camera_ov7692",
2289 .dev = {
2290 .platform_data = &msm_camera_sensor_ov7692_data,
2291 },
2292};
2293#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002294#ifdef CONFIG_VX6953
2295static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2296 .mount_angle = 270
2297};
2298
2299static struct msm_camera_sensor_flash_data flash_vx6953 = {
2300 .flash_type = MSM_CAMERA_FLASH_NONE,
2301 .flash_src = &msm_flash_src
2302};
2303
2304static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2305 .sensor_name = "vx6953",
2306 .sensor_reset = 63,
2307 .sensor_pwd = 63,
2308 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2309 .vcm_enable = 1,
2310 .pdata = &msm_camera_device_data,
2311 .resource = msm_camera_resources,
2312 .num_resources = ARRAY_SIZE(msm_camera_resources),
2313 .flash_data = &flash_vx6953,
2314 .sensor_platform_info = &vx6953_sensor_8660_info,
2315 .csi_if = 1
2316};
2317struct platform_device msm_camera_sensor_vx6953 = {
2318 .name = "msm_camera_vx6953",
2319 .dev = {
2320 .platform_data = &msm_camera_sensor_vx6953_data,
2321 },
2322};
2323#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002324#ifdef CONFIG_QS_S5K4E1
2325
2326static char eeprom_data[864];
2327static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2328 .flash_type = MSM_CAMERA_FLASH_LED,
2329 .flash_src = &msm_flash_src
2330};
2331
2332static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2333 .sensor_name = "qs_s5k4e1",
2334 .sensor_reset = 106,
2335 .sensor_pwd = 85,
2336 .vcm_pwd = 1,
2337 .vcm_enable = 0,
2338 .pdata = &msm_camera_device_data_qs_cam,
2339 .resource = msm_camera_resources,
2340 .num_resources = ARRAY_SIZE(msm_camera_resources),
2341 .flash_data = &flash_qs_s5k4e1,
2342 .strobe_flash_data = &strobe_flash_xenon,
2343 .csi_if = 1,
2344 .eeprom_data = eeprom_data,
2345};
2346struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2347 .name = "msm_camera_qs_s5k4e1",
2348 .dev = {
2349 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2350 },
2351};
2352#endif
2353static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2354 #ifdef CONFIG_MT9E013
2355 {
2356 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2357 },
2358 #endif
2359 #ifdef CONFIG_IMX074
2360 {
2361 I2C_BOARD_INFO("imx074", 0x1A),
2362 },
2363 #endif
2364 #ifdef CONFIG_WEBCAM_OV7692
2365 {
2366 I2C_BOARD_INFO("ov7692", 0x78),
2367 },
2368 #endif
2369 #ifdef CONFIG_WEBCAM_OV9726
2370 {
2371 I2C_BOARD_INFO("ov9726", 0x10),
2372 },
2373 #endif
2374 #ifdef CONFIG_QS_S5K4E1
2375 {
2376 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2377 },
2378 #endif
2379};
Jilai Wang971f97f2011-07-13 14:25:25 -04002380
2381static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002382 #ifdef CONFIG_WEBCAM_OV9726
2383 {
2384 I2C_BOARD_INFO("ov9726", 0x10),
2385 },
2386 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002387 #ifdef CONFIG_VX6953
2388 {
2389 I2C_BOARD_INFO("vx6953", 0x20),
2390 },
2391 #endif
2392};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002393#endif
2394
2395#ifdef CONFIG_MSM_GEMINI
2396static struct resource msm_gemini_resources[] = {
2397 {
2398 .start = 0x04600000,
2399 .end = 0x04600000 + SZ_1M - 1,
2400 .flags = IORESOURCE_MEM,
2401 },
2402 {
2403 .start = INT_JPEG,
2404 .end = INT_JPEG,
2405 .flags = IORESOURCE_IRQ,
2406 },
2407};
2408
2409static struct platform_device msm_gemini_device = {
2410 .name = "msm_gemini",
2411 .resource = msm_gemini_resources,
2412 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2413};
2414#endif
2415
2416#ifdef CONFIG_I2C_QUP
2417static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2418{
2419}
2420
2421static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2422 .clk_freq = 384000,
2423 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002424 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2425};
2426
2427static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2428 .clk_freq = 100000,
2429 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002430 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2431};
2432
2433static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2434 .clk_freq = 100000,
2435 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002436 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2437};
2438
2439static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2440 .clk_freq = 100000,
2441 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002442 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2443};
2444
2445static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2446 .clk_freq = 100000,
2447 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002448 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2449};
2450
2451static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2452 .clk_freq = 100000,
2453 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002454 .use_gsbi_shared_mode = 1,
2455 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2456};
2457#endif
2458
2459#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2460static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2461 .max_clock_speed = 24000000,
2462};
2463
2464static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2465 .max_clock_speed = 24000000,
2466};
2467#endif
2468
2469#ifdef CONFIG_I2C_SSBI
2470/* PMIC SSBI */
2471static struct msm_i2c_ssbi_platform_data msm_ssbi1_pdata = {
2472 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2473};
2474
2475/* PMIC SSBI */
2476static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2477 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2478};
2479
2480/* CODEC/TSSC SSBI */
2481static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2482 .controller_type = MSM_SBI_CTRL_SSBI,
2483};
2484#endif
2485
2486#ifdef CONFIG_BATTERY_MSM
2487/* Use basic value for fake MSM battery */
2488static struct msm_psy_batt_pdata msm_psy_batt_data = {
2489 .avail_chg_sources = AC_CHG,
2490};
2491
2492static struct platform_device msm_batt_device = {
2493 .name = "msm-battery",
2494 .id = -1,
2495 .dev.platform_data = &msm_psy_batt_data,
2496};
2497#endif
2498
2499#ifdef CONFIG_FB_MSM_LCDC_DSUB
2500/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2501 prim = 1024 x 600 x 4(bpp) x 2(pages)
2502 This is the difference. */
2503#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2504#else
2505#define MSM_FB_DSUB_PMEM_ADDER (0)
2506#endif
2507
2508/* Sensors DSPS platform data */
2509#ifdef CONFIG_MSM_DSPS
2510
2511static struct dsps_gpio_info dsps_surf_gpios[] = {
2512 {
2513 .name = "compass_rst_n",
2514 .num = GPIO_COMPASS_RST_N,
2515 .on_val = 1, /* device not in reset */
2516 .off_val = 0, /* device in reset */
2517 },
2518 {
2519 .name = "gpio_r_altimeter_reset_n",
2520 .num = GPIO_R_ALTIMETER_RESET_N,
2521 .on_val = 1, /* device not in reset */
2522 .off_val = 0, /* device in reset */
2523 }
2524};
2525
2526static struct dsps_gpio_info dsps_fluid_gpios[] = {
2527 {
2528 .name = "gpio_n_altimeter_reset_n",
2529 .num = GPIO_N_ALTIMETER_RESET_N,
2530 .on_val = 1, /* device not in reset */
2531 .off_val = 0, /* device in reset */
2532 }
2533};
2534
2535static void __init msm8x60_init_dsps(void)
2536{
2537 struct msm_dsps_platform_data *pdata =
2538 msm_dsps_device.dev.platform_data;
2539 /*
2540 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2541 * to the power supply and not controled via GPIOs. Fluid uses a
2542 * different IO-Expender (north) than used on surf/ffa.
2543 */
2544 if (machine_is_msm8x60_fluid()) {
2545 /* fluid has different firmware, gpios */
2546 peripheral_dsps.name = DSPS_PIL_FLUID_NAME;
2547 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2548 pdata->gpios = dsps_fluid_gpios;
2549 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2550 } else {
2551 peripheral_dsps.name = DSPS_PIL_GENERIC_NAME;
2552 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2553 pdata->gpios = dsps_surf_gpios;
2554 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2555 }
2556
2557 msm_pil_add_device(&peripheral_dsps);
2558
2559 platform_device_register(&msm_dsps_device);
2560}
2561#endif /* CONFIG_MSM_DSPS */
2562
2563#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
2564/* prim = 1024 x 600 x 4(bpp) x 3(pages) */
2565#define MSM_FB_PRIM_BUF_SIZE 0x708000
2566#else
2567/* prim = 1024 x 600 x 4(bpp) x 2(pages) */
2568#define MSM_FB_PRIM_BUF_SIZE 0x4B0000
2569#endif
2570
2571
2572#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002573/* width x height x 3 bpp x 2 frame buffer */
2574#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002575#else
2576#define MSM_FB_WRITEBACK_SIZE 0
2577#endif
2578
2579#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2580/* prim = 1024 x 600 x 4(bpp) x 2(pages)
2581 * hdmi = 1920 x 1080 x 2(bpp) x 1(page)
2582 * Note: must be multiple of 4096 */
2583#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + 0x3F4800 + \
2584 MSM_FB_WRITEBACK_SIZE + MSM_FB_DSUB_PMEM_ADDER, 4096)
2585#elif defined(CONFIG_FB_MSM_TVOUT)
2586/* prim = 1024 x 600 x 4(bpp) x 2(pages)
2587 * tvout = 720 x 576 x 2(bpp) x 2(pages)
2588 * Note: must be multiple of 4096 */
2589#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + 0x195000 + \
2590 MSM_FB_WRITEBACK_SIZE + MSM_FB_DSUB_PMEM_ADDER, 4096)
2591#else /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
2592#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + \
2593 MSM_FB_WRITEBACK_SIZE + MSM_FB_DSUB_PMEM_ADDER, 4096)
2594#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
2595
2596#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
2597
2598#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2599#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002600#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002601
2602#define MSM_SMI_BASE 0x38000000
2603#define MSM_SMI_SIZE 0x4000000
2604
2605#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2606#define KERNEL_SMI_SIZE 0x300000
2607
2608#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2609#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2610#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2611
2612static unsigned fb_size;
2613static int __init fb_size_setup(char *p)
2614{
2615 fb_size = memparse(p, NULL);
2616 return 0;
2617}
2618early_param("fb_size", fb_size_setup);
2619
2620static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2621static int __init pmem_kernel_ebi1_size_setup(char *p)
2622{
2623 pmem_kernel_ebi1_size = memparse(p, NULL);
2624 return 0;
2625}
2626early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2627
2628#ifdef CONFIG_ANDROID_PMEM
2629static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2630static int __init pmem_sf_size_setup(char *p)
2631{
2632 pmem_sf_size = memparse(p, NULL);
2633 return 0;
2634}
2635early_param("pmem_sf_size", pmem_sf_size_setup);
2636
2637static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2638
2639static int __init pmem_adsp_size_setup(char *p)
2640{
2641 pmem_adsp_size = memparse(p, NULL);
2642 return 0;
2643}
2644early_param("pmem_adsp_size", pmem_adsp_size_setup);
2645
2646static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2647
2648static int __init pmem_audio_size_setup(char *p)
2649{
2650 pmem_audio_size = memparse(p, NULL);
2651 return 0;
2652}
2653early_param("pmem_audio_size", pmem_audio_size_setup);
2654#endif
2655
2656static struct resource msm_fb_resources[] = {
2657 {
2658 .flags = IORESOURCE_DMA,
2659 }
2660};
2661
2662#ifdef CONFIG_FB_MSM_LCDC_AUTO_DETECT
2663static int msm_fb_detect_panel(const char *name)
2664{
2665 if (machine_is_msm8x60_fluid()) {
2666 uint32_t soc_platform_version = socinfo_get_platform_version();
2667 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2668#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2669 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
2670 strlen(LCDC_SAMSUNG_OLED_PANEL_NAME)))
2671 return 0;
2672#endif
2673 } else { /*P3 and up use AUO panel */
2674#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2675 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
2676 strlen(LCDC_AUO_PANEL_NAME)))
2677 return 0;
2678#endif
2679 }
2680 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2681 strlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME)))
2682 return -ENODEV;
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002683#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2684 } else if machine_is_msm8x60_dragon() {
2685 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
2686 sizeof(LCDC_NT35582_PANEL_NAME) - 1))
2687 return 0;
2688#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002689 } else {
2690 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2691 strlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME)))
2692 return 0;
2693 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
2694 strlen(LCDC_SAMSUNG_OLED_PANEL_NAME)))
2695 return -ENODEV;
2696 }
2697 pr_warning("%s: not supported '%s'", __func__, name);
2698 return -ENODEV;
2699}
2700
2701static struct msm_fb_platform_data msm_fb_pdata = {
2702 .detect_client = msm_fb_detect_panel,
2703};
2704#endif /* CONFIG_FB_MSM_LCDC_AUTO_DETECT */
2705
2706static struct platform_device msm_fb_device = {
2707 .name = "msm_fb",
2708 .id = 0,
2709 .num_resources = ARRAY_SIZE(msm_fb_resources),
2710 .resource = msm_fb_resources,
2711#ifdef CONFIG_FB_MSM_LCDC_AUTO_DETECT
2712 .dev.platform_data = &msm_fb_pdata,
2713#endif /* CONFIG_FB_MSM_LCDC_AUTO_DETECT */
2714};
2715
2716#ifdef CONFIG_ANDROID_PMEM
2717static struct android_pmem_platform_data android_pmem_pdata = {
2718 .name = "pmem",
2719 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2720 .cached = 1,
2721 .memory_type = MEMTYPE_EBI1,
2722};
2723
2724static struct platform_device android_pmem_device = {
2725 .name = "android_pmem",
2726 .id = 0,
2727 .dev = {.platform_data = &android_pmem_pdata},
2728};
2729
2730static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2731 .name = "pmem_adsp",
2732 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2733 .cached = 0,
2734 .memory_type = MEMTYPE_EBI1,
2735};
2736
2737static struct platform_device android_pmem_adsp_device = {
2738 .name = "android_pmem",
2739 .id = 2,
2740 .dev = { .platform_data = &android_pmem_adsp_pdata },
2741};
2742
2743static struct android_pmem_platform_data android_pmem_audio_pdata = {
2744 .name = "pmem_audio",
2745 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2746 .cached = 0,
2747 .memory_type = MEMTYPE_EBI1,
2748};
2749
2750static struct platform_device android_pmem_audio_device = {
2751 .name = "android_pmem",
2752 .id = 4,
2753 .dev = { .platform_data = &android_pmem_audio_pdata },
2754};
2755
Laura Abbott1e36a022011-06-22 17:08:13 -07002756#define PMEM_BUS_WIDTH(_bw) \
2757 { \
2758 .vectors = &(struct msm_bus_vectors){ \
2759 .src = MSM_BUS_MASTER_AMPSS_M0, \
2760 .dst = MSM_BUS_SLAVE_SMI, \
2761 .ib = (_bw), \
2762 .ab = 0, \
2763 }, \
2764 .num_paths = 1, \
2765 }
2766static struct msm_bus_paths pmem_smi_table[] = {
2767 [0] = PMEM_BUS_WIDTH(0), /* Off */
2768 [1] = PMEM_BUS_WIDTH(1), /* On */
2769};
2770
2771static struct msm_bus_scale_pdata smi_client_pdata = {
2772 .usecase = pmem_smi_table,
2773 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2774 .name = "pmem_smi",
2775};
2776
2777void pmem_request_smi_region(void *data)
2778{
2779 int bus_id = (int) data;
2780
2781 msm_bus_scale_client_update_request(bus_id, 1);
2782}
2783
2784void pmem_release_smi_region(void *data)
2785{
2786 int bus_id = (int) data;
2787
2788 msm_bus_scale_client_update_request(bus_id, 0);
2789}
2790
2791void *pmem_setup_smi_region(void)
2792{
2793 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2794}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002795static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2796 .name = "pmem_smipool",
2797 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2798 .cached = 0,
2799 .memory_type = MEMTYPE_SMI,
Laura Abbott1e36a022011-06-22 17:08:13 -07002800 .request_region = pmem_request_smi_region,
2801 .release_region = pmem_release_smi_region,
2802 .setup_region = pmem_setup_smi_region,
2803 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002804};
2805static struct platform_device android_pmem_smipool_device = {
2806 .name = "android_pmem",
2807 .id = 7,
2808 .dev = { .platform_data = &android_pmem_smipool_pdata },
2809};
2810
2811#endif
2812
2813#define GPIO_DONGLE_PWR_EN 258
2814static void setup_display_power(void);
2815static int lcdc_vga_enabled;
2816static int vga_enable_request(int enable)
2817{
2818 if (enable)
2819 lcdc_vga_enabled = 1;
2820 else
2821 lcdc_vga_enabled = 0;
2822 setup_display_power();
2823
2824 return 0;
2825}
2826
2827#define GPIO_BACKLIGHT_PWM0 0
2828#define GPIO_BACKLIGHT_PWM1 1
2829
2830static int pmic_backlight_gpio[2]
2831 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2832static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2833 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2834 .vga_switch = vga_enable_request,
2835};
2836
2837static struct platform_device lcdc_samsung_panel_device = {
2838 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2839 .id = 0,
2840 .dev = {
2841 .platform_data = &lcdc_samsung_panel_data,
2842 }
2843};
2844#if (!defined(CONFIG_SPI_QUP)) && \
2845 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2846 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2847
2848static int lcdc_spi_gpio_array_num[] = {
2849 LCDC_SPI_GPIO_CLK,
2850 LCDC_SPI_GPIO_CS,
2851 LCDC_SPI_GPIO_MOSI,
2852};
2853
2854static uint32_t lcdc_spi_gpio_config_data[] = {
2855 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2856 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2857 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2858 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2859 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2860 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2861};
2862
2863static void lcdc_config_spi_gpios(int enable)
2864{
2865 int n;
2866 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2867 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2868}
2869#endif
2870
2871#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2872#ifdef CONFIG_SPI_QUP
2873static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2874 {
2875 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2876 .mode = SPI_MODE_3,
2877 .bus_num = 1,
2878 .chip_select = 0,
2879 .max_speed_hz = 10800000,
2880 }
2881};
2882#endif /* CONFIG_SPI_QUP */
2883
2884static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2885#ifndef CONFIG_SPI_QUP
2886 .panel_config_gpio = lcdc_config_spi_gpios,
2887 .gpio_num = lcdc_spi_gpio_array_num,
2888#endif
2889};
2890
2891static struct platform_device lcdc_samsung_oled_panel_device = {
2892 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2893 .id = 0,
2894 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2895};
2896#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2897
2898#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2899#ifdef CONFIG_SPI_QUP
2900static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2901 {
2902 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2903 .mode = SPI_MODE_3,
2904 .bus_num = 1,
2905 .chip_select = 0,
2906 .max_speed_hz = 10800000,
2907 }
2908};
2909#endif
2910
2911static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
2912#ifndef CONFIG_SPI_QUP
2913 .panel_config_gpio = lcdc_config_spi_gpios,
2914 .gpio_num = lcdc_spi_gpio_array_num,
2915#endif
2916};
2917
2918static struct platform_device lcdc_auo_wvga_panel_device = {
2919 .name = LCDC_AUO_PANEL_NAME,
2920 .id = 0,
2921 .dev.platform_data = &lcdc_auo_wvga_panel_data,
2922};
2923#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
2924
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002925#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2926
2927#define GPIO_NT35582_RESET 94
2928#define GPIO_NT35582_BL_EN_HW_PIN 24
2929#define GPIO_NT35582_BL_EN \
2930 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
2931
2932static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
2933
2934static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
2935 .gpio_num = lcdc_nt35582_pmic_gpio,
2936};
2937
2938static struct platform_device lcdc_nt35582_panel_device = {
2939 .name = LCDC_NT35582_PANEL_NAME,
2940 .id = 0,
2941 .dev = {
2942 .platform_data = &lcdc_nt35582_panel_data,
2943 }
2944};
2945
2946static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
2947 {
2948 .modalias = "lcdc_nt35582_spi",
2949 .mode = SPI_MODE_0,
2950 .bus_num = 0,
2951 .chip_select = 0,
2952 .max_speed_hz = 1100000,
2953 }
2954};
2955#endif
2956
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002957#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2958static struct resource hdmi_msm_resources[] = {
2959 {
2960 .name = "hdmi_msm_qfprom_addr",
2961 .start = 0x00700000,
2962 .end = 0x007060FF,
2963 .flags = IORESOURCE_MEM,
2964 },
2965 {
2966 .name = "hdmi_msm_hdmi_addr",
2967 .start = 0x04A00000,
2968 .end = 0x04A00FFF,
2969 .flags = IORESOURCE_MEM,
2970 },
2971 {
2972 .name = "hdmi_msm_irq",
2973 .start = HDMI_IRQ,
2974 .end = HDMI_IRQ,
2975 .flags = IORESOURCE_IRQ,
2976 },
2977};
2978
2979static int hdmi_enable_5v(int on);
2980static int hdmi_core_power(int on, int show);
2981static int hdmi_cec_power(int on);
2982
2983static struct msm_hdmi_platform_data hdmi_msm_data = {
2984 .irq = HDMI_IRQ,
2985 .enable_5v = hdmi_enable_5v,
2986 .core_power = hdmi_core_power,
2987 .cec_power = hdmi_cec_power,
2988};
2989
2990static struct platform_device hdmi_msm_device = {
2991 .name = "hdmi_msm",
2992 .id = 0,
2993 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
2994 .resource = hdmi_msm_resources,
2995 .dev.platform_data = &hdmi_msm_data,
2996};
2997#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
2998
2999#ifdef CONFIG_FB_MSM_MIPI_DSI
3000static struct platform_device mipi_dsi_toshiba_panel_device = {
3001 .name = "mipi_toshiba",
3002 .id = 0,
3003};
3004
3005#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3006
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003007static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003008 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
3009};
3010
3011static struct platform_device mipi_dsi_novatek_panel_device = {
3012 .name = "mipi_novatek",
3013 .id = 0,
3014 .dev = {
3015 .platform_data = &novatek_pdata,
3016 }
3017};
3018#endif
3019
3020static void __init msm8x60_allocate_memory_regions(void)
3021{
3022 void *addr;
3023 unsigned long size;
3024
3025 size = MSM_FB_SIZE;
3026 addr = alloc_bootmem_align(size, 0x1000);
3027 msm_fb_resources[0].start = __pa(addr);
3028 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3029 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3030 size, addr, __pa(addr));
3031
3032}
3033
3034#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3035 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3036/*virtual key support */
3037static ssize_t tma300_vkeys_show(struct kobject *kobj,
3038 struct kobj_attribute *attr, char *buf)
3039{
3040 return sprintf(buf,
3041 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3042 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3043 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3044 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3045 "\n");
3046}
3047
3048static struct kobj_attribute tma300_vkeys_attr = {
3049 .attr = {
3050 .mode = S_IRUGO,
3051 },
3052 .show = &tma300_vkeys_show,
3053};
3054
3055static struct attribute *tma300_properties_attrs[] = {
3056 &tma300_vkeys_attr.attr,
3057 NULL
3058};
3059
3060static struct attribute_group tma300_properties_attr_group = {
3061 .attrs = tma300_properties_attrs,
3062};
3063
3064static struct kobject *properties_kobj;
3065
3066
3067
3068#define CYTTSP_TS_GPIO_IRQ 61
3069static int cyttsp_platform_init(struct i2c_client *client)
3070{
3071 int rc = -EINVAL;
3072 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3073
3074 if (machine_is_msm8x60_fluid()) {
3075 pm8058_l5 = regulator_get(NULL, "8058_l5");
3076 if (IS_ERR(pm8058_l5)) {
3077 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3078 __func__, PTR_ERR(pm8058_l5));
3079 rc = PTR_ERR(pm8058_l5);
3080 return rc;
3081 }
3082 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3083 if (rc) {
3084 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3085 __func__, rc);
3086 goto reg_l5_put;
3087 }
3088
3089 rc = regulator_enable(pm8058_l5);
3090 if (rc) {
3091 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3092 __func__, rc);
3093 goto reg_l5_put;
3094 }
3095 }
3096 /* vote for s3 to enable i2c communication lines */
3097 pm8058_s3 = regulator_get(NULL, "8058_s3");
3098 if (IS_ERR(pm8058_s3)) {
3099 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3100 __func__, PTR_ERR(pm8058_s3));
3101 rc = PTR_ERR(pm8058_s3);
3102 goto reg_l5_disable;
3103 }
3104
3105 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3106 if (rc) {
3107 pr_err("%s: regulator_set_voltage() = %d\n",
3108 __func__, rc);
3109 goto reg_s3_put;
3110 }
3111
3112 rc = regulator_enable(pm8058_s3);
3113 if (rc) {
3114 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3115 __func__, rc);
3116 goto reg_s3_put;
3117 }
3118
3119 /* wait for vregs to stabilize */
3120 usleep_range(10000, 10000);
3121
3122 /* check this device active by reading first byte/register */
3123 rc = i2c_smbus_read_byte_data(client, 0x01);
3124 if (rc < 0) {
3125 pr_err("%s: i2c sanity check failed\n", __func__);
3126 goto reg_s3_disable;
3127 }
3128
3129 /* virtual keys */
3130 if (machine_is_msm8x60_fluid()) {
3131 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3132 properties_kobj = kobject_create_and_add("board_properties",
3133 NULL);
3134 if (properties_kobj)
3135 rc = sysfs_create_group(properties_kobj,
3136 &tma300_properties_attr_group);
3137 if (!properties_kobj || rc)
3138 pr_err("%s: failed to create board_properties\n",
3139 __func__);
3140 }
3141 return CY_OK;
3142
3143reg_s3_disable:
3144 regulator_disable(pm8058_s3);
3145reg_s3_put:
3146 regulator_put(pm8058_s3);
3147reg_l5_disable:
3148 if (machine_is_msm8x60_fluid())
3149 regulator_disable(pm8058_l5);
3150reg_l5_put:
3151 if (machine_is_msm8x60_fluid())
3152 regulator_put(pm8058_l5);
3153 return rc;
3154}
3155
3156static int cyttsp_platform_resume(struct i2c_client *client)
3157{
3158 /* add any special code to strobe a wakeup pin or chip reset */
3159 msleep(10);
3160
3161 return CY_OK;
3162}
3163
3164static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3165 .flags = 0x04,
3166 .gen = CY_GEN3, /* or */
3167 .use_st = CY_USE_ST,
3168 .use_mt = CY_USE_MT,
3169 .use_hndshk = CY_SEND_HNDSHK,
3170 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303171 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003172 .use_gestures = CY_USE_GESTURES,
3173 /* activate up to 4 groups
3174 * and set active distance
3175 */
3176 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3177 CY_GEST_GRP3 | CY_GEST_GRP4 |
3178 CY_ACT_DIST,
3179 /* change act_intrvl to customize the Active power state
3180 * scanning/processing refresh interval for Operating mode
3181 */
3182 .act_intrvl = CY_ACT_INTRVL_DFLT,
3183 /* change tch_tmout to customize the touch timeout for the
3184 * Active power state for Operating mode
3185 */
3186 .tch_tmout = CY_TCH_TMOUT_DFLT,
3187 /* change lp_intrvl to customize the Low Power power state
3188 * scanning/processing refresh interval for Operating mode
3189 */
3190 .lp_intrvl = CY_LP_INTRVL_DFLT,
3191 .sleep_gpio = -1,
3192 .resout_gpio = -1,
3193 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3194 .resume = cyttsp_platform_resume,
3195 .init = cyttsp_platform_init,
3196};
3197
3198static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3199 .panel_maxx = 1083,
3200 .panel_maxy = 659,
3201 .disp_minx = 30,
3202 .disp_maxx = 1053,
3203 .disp_miny = 30,
3204 .disp_maxy = 629,
3205 .correct_fw_ver = 8,
3206 .fw_fname = "cyttsp_8660_ffa.hex",
3207 .flags = 0x00,
3208 .gen = CY_GEN2, /* or */
3209 .use_st = CY_USE_ST,
3210 .use_mt = CY_USE_MT,
3211 .use_hndshk = CY_SEND_HNDSHK,
3212 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303213 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003214 .use_gestures = CY_USE_GESTURES,
3215 /* activate up to 4 groups
3216 * and set active distance
3217 */
3218 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3219 CY_GEST_GRP3 | CY_GEST_GRP4 |
3220 CY_ACT_DIST,
3221 /* change act_intrvl to customize the Active power state
3222 * scanning/processing refresh interval for Operating mode
3223 */
3224 .act_intrvl = CY_ACT_INTRVL_DFLT,
3225 /* change tch_tmout to customize the touch timeout for the
3226 * Active power state for Operating mode
3227 */
3228 .tch_tmout = CY_TCH_TMOUT_DFLT,
3229 /* change lp_intrvl to customize the Low Power power state
3230 * scanning/processing refresh interval for Operating mode
3231 */
3232 .lp_intrvl = CY_LP_INTRVL_DFLT,
3233 .sleep_gpio = -1,
3234 .resout_gpio = -1,
3235 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3236 .resume = cyttsp_platform_resume,
3237 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303238 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003239};
3240static void cyttsp_set_params(void)
3241{
3242 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3243 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3244 cyttsp_fluid_pdata.panel_maxx = 539;
3245 cyttsp_fluid_pdata.panel_maxy = 994;
3246 cyttsp_fluid_pdata.disp_minx = 30;
3247 cyttsp_fluid_pdata.disp_maxx = 509;
3248 cyttsp_fluid_pdata.disp_miny = 60;
3249 cyttsp_fluid_pdata.disp_maxy = 859;
3250 cyttsp_fluid_pdata.correct_fw_ver = 4;
3251 } else {
3252 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3253 cyttsp_fluid_pdata.panel_maxx = 550;
3254 cyttsp_fluid_pdata.panel_maxy = 1013;
3255 cyttsp_fluid_pdata.disp_minx = 35;
3256 cyttsp_fluid_pdata.disp_maxx = 515;
3257 cyttsp_fluid_pdata.disp_miny = 69;
3258 cyttsp_fluid_pdata.disp_maxy = 869;
3259 cyttsp_fluid_pdata.correct_fw_ver = 5;
3260 }
3261
3262}
3263
3264static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3265 {
3266 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3267 .platform_data = &cyttsp_fluid_pdata,
3268#ifndef CY_USE_TIMER
3269 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3270#endif /* CY_USE_TIMER */
3271 },
3272};
3273
3274static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3275 {
3276 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3277 .platform_data = &cyttsp_tmg240_pdata,
3278#ifndef CY_USE_TIMER
3279 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3280#endif /* CY_USE_TIMER */
3281 },
3282};
3283#endif
3284
3285static struct regulator *vreg_tmg200;
3286
3287#define TS_PEN_IRQ_GPIO 61
3288static int tmg200_power(int vreg_on)
3289{
3290 int rc = -EINVAL;
3291
3292 if (!vreg_tmg200) {
3293 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3294 __func__, rc);
3295 return rc;
3296 }
3297
3298 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3299 regulator_disable(vreg_tmg200);
3300 if (rc < 0)
3301 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3302 __func__, vreg_on ? "enable" : "disable", rc);
3303
3304 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003305 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003306
3307 return rc;
3308}
3309
3310static int tmg200_dev_setup(bool enable)
3311{
3312 int rc;
3313
3314 if (enable) {
3315 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3316 if (IS_ERR(vreg_tmg200)) {
3317 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3318 __func__, PTR_ERR(vreg_tmg200));
3319 rc = PTR_ERR(vreg_tmg200);
3320 return rc;
3321 }
3322
3323 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3324 if (rc) {
3325 pr_err("%s: regulator_set_voltage() = %d\n",
3326 __func__, rc);
3327 goto reg_put;
3328 }
3329 } else {
3330 /* put voltage sources */
3331 regulator_put(vreg_tmg200);
3332 }
3333 return 0;
3334reg_put:
3335 regulator_put(vreg_tmg200);
3336 return rc;
3337}
3338
3339static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3340 .ts_name = "msm_tmg200_ts",
3341 .dis_min_x = 0,
3342 .dis_max_x = 1023,
3343 .dis_min_y = 0,
3344 .dis_max_y = 599,
3345 .min_tid = 0,
3346 .max_tid = 255,
3347 .min_touch = 0,
3348 .max_touch = 255,
3349 .min_width = 0,
3350 .max_width = 255,
3351 .power_on = tmg200_power,
3352 .dev_setup = tmg200_dev_setup,
3353 .nfingers = 2,
3354 .irq_gpio = TS_PEN_IRQ_GPIO,
3355 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3356};
3357
3358static struct i2c_board_info cy8ctmg200_board_info[] = {
3359 {
3360 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3361 .platform_data = &cy8ctmg200_pdata,
3362 }
3363};
3364
Zhang Chang Ken211df572011-07-05 19:16:39 -04003365static struct regulator *vreg_tma340;
3366
3367static int tma340_power(int vreg_on)
3368{
3369 int rc = -EINVAL;
3370
3371 if (!vreg_tma340) {
3372 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3373 __func__, rc);
3374 return rc;
3375 }
3376
3377 rc = vreg_on ? regulator_enable(vreg_tma340) :
3378 regulator_disable(vreg_tma340);
3379 if (rc < 0)
3380 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3381 __func__, vreg_on ? "enable" : "disable", rc);
3382
3383 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003384 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003385
3386 return rc;
3387}
3388
3389static struct kobject *tma340_prop_kobj;
3390
3391static int tma340_dragon_dev_setup(bool enable)
3392{
3393 int rc;
3394
3395 if (enable) {
3396 vreg_tma340 = regulator_get(NULL, "8901_l2");
3397 if (IS_ERR(vreg_tma340)) {
3398 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3399 __func__, PTR_ERR(vreg_tma340));
3400 rc = PTR_ERR(vreg_tma340);
3401 return rc;
3402 }
3403
3404 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3405 if (rc) {
3406 pr_err("%s: regulator_set_voltage() = %d\n",
3407 __func__, rc);
3408 goto reg_put;
3409 }
3410 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3411 tma340_prop_kobj = kobject_create_and_add("board_properties",
3412 NULL);
3413 if (tma340_prop_kobj) {
3414 rc = sysfs_create_group(tma340_prop_kobj,
3415 &tma300_properties_attr_group);
3416 if (rc) {
3417 kobject_put(tma340_prop_kobj);
3418 pr_err("%s: failed to create board_properties\n",
3419 __func__);
3420 goto reg_put;
3421 }
3422 }
3423
3424 } else {
3425 /* put voltage sources */
3426 regulator_put(vreg_tma340);
3427 /* destroy virtual keys */
3428 if (tma340_prop_kobj) {
3429 sysfs_remove_group(tma340_prop_kobj,
3430 &tma300_properties_attr_group);
3431 kobject_put(tma340_prop_kobj);
3432 }
3433 }
3434 return 0;
3435reg_put:
3436 regulator_put(vreg_tma340);
3437 return rc;
3438}
3439
3440
3441static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3442 .ts_name = "cy8ctma340",
3443 .dis_min_x = 0,
3444 .dis_max_x = 479,
3445 .dis_min_y = 0,
3446 .dis_max_y = 799,
3447 .min_tid = 0,
3448 .max_tid = 255,
3449 .min_touch = 0,
3450 .max_touch = 255,
3451 .min_width = 0,
3452 .max_width = 255,
3453 .power_on = tma340_power,
3454 .dev_setup = tma340_dragon_dev_setup,
3455 .nfingers = 2,
3456 .irq_gpio = TS_PEN_IRQ_GPIO,
3457 .resout_gpio = -1,
3458};
3459
3460static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3461 {
3462 I2C_BOARD_INFO("cy8ctma340", 0x24),
3463 .platform_data = &cy8ctma340_dragon_pdata,
3464 }
3465};
3466
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003467#ifdef CONFIG_SERIAL_MSM_HS
3468static int configure_uart_gpios(int on)
3469{
3470 int ret = 0, i;
3471 int uart_gpios[] = {53, 54, 55, 56};
3472 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3473 if (on) {
3474 ret = msm_gpiomux_get(uart_gpios[i]);
3475 if (unlikely(ret))
3476 break;
3477 } else {
3478 ret = msm_gpiomux_put(uart_gpios[i]);
3479 if (unlikely(ret))
3480 return ret;
3481 }
3482 }
3483 if (ret)
3484 for (; i >= 0; i--)
3485 msm_gpiomux_put(uart_gpios[i]);
3486 return ret;
3487}
3488static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3489 .inject_rx_on_wakeup = 1,
3490 .rx_to_inject = 0xFD,
3491 .gpio_config = configure_uart_gpios,
3492};
3493#endif
3494
3495
3496#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3497
3498static struct gpio_led gpio_exp_leds_config[] = {
3499 {
3500 .name = "left_led1:green",
3501 .gpio = GPIO_LEFT_LED_1,
3502 .active_low = 1,
3503 .retain_state_suspended = 0,
3504 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3505 },
3506 {
3507 .name = "left_led2:red",
3508 .gpio = GPIO_LEFT_LED_2,
3509 .active_low = 1,
3510 .retain_state_suspended = 0,
3511 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3512 },
3513 {
3514 .name = "left_led3:green",
3515 .gpio = GPIO_LEFT_LED_3,
3516 .active_low = 1,
3517 .retain_state_suspended = 0,
3518 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3519 },
3520 {
3521 .name = "wlan_led:orange",
3522 .gpio = GPIO_LEFT_LED_WLAN,
3523 .active_low = 1,
3524 .retain_state_suspended = 0,
3525 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3526 },
3527 {
3528 .name = "left_led5:green",
3529 .gpio = GPIO_LEFT_LED_5,
3530 .active_low = 1,
3531 .retain_state_suspended = 0,
3532 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3533 },
3534 {
3535 .name = "right_led1:green",
3536 .gpio = GPIO_RIGHT_LED_1,
3537 .active_low = 1,
3538 .retain_state_suspended = 0,
3539 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3540 },
3541 {
3542 .name = "right_led2:red",
3543 .gpio = GPIO_RIGHT_LED_2,
3544 .active_low = 1,
3545 .retain_state_suspended = 0,
3546 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3547 },
3548 {
3549 .name = "right_led3:green",
3550 .gpio = GPIO_RIGHT_LED_3,
3551 .active_low = 1,
3552 .retain_state_suspended = 0,
3553 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3554 },
3555 {
3556 .name = "bt_led:blue",
3557 .gpio = GPIO_RIGHT_LED_BT,
3558 .active_low = 1,
3559 .retain_state_suspended = 0,
3560 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3561 },
3562 {
3563 .name = "right_led5:green",
3564 .gpio = GPIO_RIGHT_LED_5,
3565 .active_low = 1,
3566 .retain_state_suspended = 0,
3567 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3568 },
3569};
3570
3571static struct gpio_led_platform_data gpio_leds_pdata = {
3572 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3573 .leds = gpio_exp_leds_config,
3574};
3575
3576static struct platform_device gpio_leds = {
3577 .name = "leds-gpio",
3578 .id = -1,
3579 .dev = {
3580 .platform_data = &gpio_leds_pdata,
3581 },
3582};
3583
3584static struct gpio_led fluid_gpio_leds[] = {
3585 {
3586 .name = "dual_led:green",
3587 .gpio = GPIO_LED1_GREEN_N,
3588 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3589 .active_low = 1,
3590 .retain_state_suspended = 0,
3591 },
3592 {
3593 .name = "dual_led:red",
3594 .gpio = GPIO_LED2_RED_N,
3595 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3596 .active_low = 1,
3597 .retain_state_suspended = 0,
3598 },
3599};
3600
3601static struct gpio_led_platform_data gpio_led_pdata = {
3602 .leds = fluid_gpio_leds,
3603 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3604};
3605
3606static struct platform_device fluid_leds_gpio = {
3607 .name = "leds-gpio",
3608 .id = -1,
3609 .dev = {
3610 .platform_data = &gpio_led_pdata,
3611 },
3612};
3613
3614#endif
3615
3616#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3617
3618static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3619 .phys_addr_base = 0x00106000,
3620 .reg_offsets = {
3621 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3622 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3623 },
3624 .phys_size = SZ_8K,
3625 .log_len = 4096, /* log's buffer length in bytes */
3626 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3627};
3628
3629static struct platform_device msm_rpm_log_device = {
3630 .name = "msm_rpm_log",
3631 .id = -1,
3632 .dev = {
3633 .platform_data = &msm_rpm_log_pdata,
3634 },
3635};
3636#endif
3637
3638#ifdef CONFIG_BATTERY_MSM8X60
3639static struct msm_charger_platform_data msm_charger_data = {
3640 .safety_time = 180,
3641 .update_time = 1,
3642 .max_voltage = 4200,
3643 .min_voltage = 3200,
3644};
3645
3646static struct platform_device msm_charger_device = {
3647 .name = "msm-charger",
3648 .id = -1,
3649 .dev = {
3650 .platform_data = &msm_charger_data,
3651 }
3652};
3653#endif
3654
3655/*
3656 * Consumer specific regulator names:
3657 * regulator name consumer dev_name
3658 */
3659static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3660 REGULATOR_SUPPLY("8058_l0", NULL),
3661};
3662static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3663 REGULATOR_SUPPLY("8058_l1", NULL),
3664};
3665static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3666 REGULATOR_SUPPLY("8058_l2", NULL),
3667};
3668static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3669 REGULATOR_SUPPLY("8058_l3", NULL),
3670};
3671static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3672 REGULATOR_SUPPLY("8058_l4", NULL),
3673};
3674static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3675 REGULATOR_SUPPLY("8058_l5", NULL),
3676};
3677static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3678 REGULATOR_SUPPLY("8058_l6", NULL),
3679};
3680static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3681 REGULATOR_SUPPLY("8058_l7", NULL),
3682};
3683static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3684 REGULATOR_SUPPLY("8058_l8", NULL),
3685};
3686static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3687 REGULATOR_SUPPLY("8058_l9", NULL),
3688};
3689static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3690 REGULATOR_SUPPLY("8058_l10", NULL),
3691};
3692static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3693 REGULATOR_SUPPLY("8058_l11", NULL),
3694};
3695static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3696 REGULATOR_SUPPLY("8058_l12", NULL),
3697};
3698static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3699 REGULATOR_SUPPLY("8058_l13", NULL),
3700};
3701static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3702 REGULATOR_SUPPLY("8058_l14", NULL),
3703};
3704static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3705 REGULATOR_SUPPLY("8058_l15", NULL),
3706};
3707static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3708 REGULATOR_SUPPLY("8058_l16", NULL),
3709};
3710static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3711 REGULATOR_SUPPLY("8058_l17", NULL),
3712};
3713static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3714 REGULATOR_SUPPLY("8058_l18", NULL),
3715};
3716static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3717 REGULATOR_SUPPLY("8058_l19", NULL),
3718};
3719static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3720 REGULATOR_SUPPLY("8058_l20", NULL),
3721};
3722static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3723 REGULATOR_SUPPLY("8058_l21", NULL),
3724};
3725static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3726 REGULATOR_SUPPLY("8058_l22", NULL),
3727};
3728static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3729 REGULATOR_SUPPLY("8058_l23", NULL),
3730};
3731static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3732 REGULATOR_SUPPLY("8058_l24", NULL),
3733};
3734static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3735 REGULATOR_SUPPLY("8058_l25", NULL),
3736};
3737static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3738 REGULATOR_SUPPLY("8058_s0", NULL),
3739};
3740static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3741 REGULATOR_SUPPLY("8058_s1", NULL),
3742};
3743static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3744 REGULATOR_SUPPLY("8058_s2", NULL),
3745};
3746static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3747 REGULATOR_SUPPLY("8058_s3", NULL),
3748};
3749static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3750 REGULATOR_SUPPLY("8058_s4", NULL),
3751};
3752static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3753 REGULATOR_SUPPLY("8058_lvs0", NULL),
3754};
3755static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3756 REGULATOR_SUPPLY("8058_lvs1", NULL),
3757};
3758static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3759 REGULATOR_SUPPLY("8058_ncp", NULL),
3760};
3761
3762static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3763 REGULATOR_SUPPLY("8901_l0", NULL),
3764};
3765static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3766 REGULATOR_SUPPLY("8901_l1", NULL),
3767};
3768static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3769 REGULATOR_SUPPLY("8901_l2", NULL),
3770};
3771static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3772 REGULATOR_SUPPLY("8901_l3", NULL),
3773};
3774static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3775 REGULATOR_SUPPLY("8901_l4", NULL),
3776};
3777static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3778 REGULATOR_SUPPLY("8901_l5", NULL),
3779};
3780static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3781 REGULATOR_SUPPLY("8901_l6", NULL),
3782};
3783static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3784 REGULATOR_SUPPLY("8901_s2", NULL),
3785};
3786static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3787 REGULATOR_SUPPLY("8901_s3", NULL),
3788};
3789static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3790 REGULATOR_SUPPLY("8901_s4", NULL),
3791};
3792static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3793 REGULATOR_SUPPLY("8901_lvs0", NULL),
3794};
3795static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3796 REGULATOR_SUPPLY("8901_lvs1", NULL),
3797};
3798static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3799 REGULATOR_SUPPLY("8901_lvs2", NULL),
3800};
3801static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3802 REGULATOR_SUPPLY("8901_lvs3", NULL),
3803};
3804static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3805 REGULATOR_SUPPLY("8901_mvs0", NULL),
3806};
3807
3808#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3809 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
3810 _freq, _pin_fn, _rpm_mode, _state, _sleep_selectable, \
3811 _always_on) \
3812 [RPM_VREG_ID_##_id] = { \
3813 .init_data = { \
3814 .constraints = { \
3815 .valid_modes_mask = _modes, \
3816 .valid_ops_mask = _ops, \
3817 .min_uV = _min_uV, \
3818 .max_uV = _max_uV, \
3819 .input_uV = _min_uV, \
3820 .apply_uV = _apply_uV, \
3821 .always_on = _always_on, \
3822 }, \
3823 .consumer_supplies = vreg_consumers_##_id, \
3824 .num_consumer_supplies = \
3825 ARRAY_SIZE(vreg_consumers_##_id), \
3826 }, \
3827 .default_uV = _default_uV, \
3828 .peak_uA = _peak_uA, \
3829 .avg_uA = _avg_uA, \
3830 .pull_down_enable = _pull_down, \
3831 .pin_ctrl = _pin_ctrl, \
3832 .freq = _freq, \
3833 .pin_fn = _pin_fn, \
3834 .mode = _rpm_mode, \
3835 .state = _state, \
3836 .sleep_selectable = _sleep_selectable, \
3837 }
3838
3839/*
3840 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3841 * via the peak_uA value specified in the table below. If the value is less
3842 * than the high power min threshold for the regulator, then the regulator will
3843 * be set to LPM. Otherwise, it will be set to HPM.
3844 *
3845 * This value can be further overridden by specifying an initial mode via
3846 * .init_data.constraints.initial_mode.
3847 */
3848
3849#define RPM_VREG_INIT_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
3850 _max_uV, _init_peak_uA, _pin_ctrl) \
3851 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3852 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3853 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3854 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3855 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
3856 _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
3857 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
3858 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
3859
3860#define RPM_VREG_INIT_LDO_PF(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
3861 _max_uV, _init_peak_uA, _pin_ctrl, _pin_fn) \
3862 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3863 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3864 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3865 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3866 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
3867 _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
3868 _pin_fn, RPM_VREG_MODE_NONE, RPM_VREG_STATE_OFF, \
3869 _sleep_selectable, _always_on)
3870
3871#define RPM_VREG_INIT_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
3872 _max_uV, _init_peak_uA, _pin_ctrl, _freq) \
3873 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3874 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3875 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3876 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3877 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
3878 _init_peak_uA, _pd, _pin_ctrl, _freq, \
3879 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
3880 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
3881
3882#define RPM_VREG_INIT_VS(_id, _always_on, _pd, _sleep_selectable, _pin_ctrl) \
3883 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
3884 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
3885 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
3886 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
3887 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
3888
3889#define RPM_VREG_INIT_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
3890 _max_uV, _pin_ctrl) \
3891 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
3892 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
3893 _min_uV, 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
3894 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
3895 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
3896
3897#define LDO50HMIN RPM_VREG_LDO_50_HPM_MIN_LOAD
3898#define LDO150HMIN RPM_VREG_LDO_150_HPM_MIN_LOAD
3899#define LDO300HMIN RPM_VREG_LDO_300_HPM_MIN_LOAD
3900#define SMPS_HMIN RPM_VREG_SMPS_HPM_MIN_LOAD
3901#define FTS_HMIN RPM_VREG_FTSMPS_HPM_MIN_LOAD
3902
3903static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
3904 RPM_VREG_INIT_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
3905 RPM_VREG_INIT_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
3906 RPM_VREG_INIT_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN, 0),
3907 RPM_VREG_INIT_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
3908 RPM_VREG_INIT_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN, 0),
3909 RPM_VREG_INIT_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
3910 RPM_VREG_INIT_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN, 0),
3911 RPM_VREG_INIT_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN, 0),
3912 RPM_VREG_INIT_LDO_PF(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN,
3913 RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
3914 RPM_VREG_INIT_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
3915 RPM_VREG_INIT_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
3916 RPM_VREG_INIT_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN, 0),
3917 RPM_VREG_INIT_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN, 0),
3918 RPM_VREG_INIT_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN, 0),
3919 RPM_VREG_INIT_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN, 0),
3920 RPM_VREG_INIT_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
3921 RPM_VREG_INIT_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
3922 RPM_VREG_INIT_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN, 0),
3923 RPM_VREG_INIT_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN, 0),
3924 RPM_VREG_INIT_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN, 0),
3925 RPM_VREG_INIT_LDO_PF(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN,
3926 RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
3927 RPM_VREG_INIT_LDO_PF(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN,
3928 RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
David Collins3cfb9652011-07-27 14:24:36 -07003929 RPM_VREG_INIT_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003930 RPM_VREG_INIT_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
3931 RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
3932 RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
3933
3934 RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
3935 RPM_VREG_FREQ_1p60),
3936 RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
3937 RPM_VREG_FREQ_1p60),
3938 RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN,
3939 RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
3940 RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
3941 RPM_VREG_FREQ_1p60),
3942 RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
3943 RPM_VREG_FREQ_1p60),
3944
3945 RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
3946 RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
3947
3948 RPM_VREG_INIT_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000, 0),
3949
3950 RPM_VREG_INIT_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN,
3951 RPM_VREG_PIN_CTRL_A0),
3952 RPM_VREG_INIT_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
3953 RPM_VREG_INIT_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN, 0),
3954 RPM_VREG_INIT_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
3955 RPM_VREG_INIT_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
3956 RPM_VREG_INIT_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
3957 RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
3958
3959 RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
3960 RPM_VREG_FREQ_1p60),
3961 RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
3962 RPM_VREG_FREQ_1p60),
3963 RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
3964 RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
3965
3966 RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
3967 RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
3968 RPM_VREG_INIT_VS(PM8901_LVS2, 0, 1, 0, 0),
3969 RPM_VREG_INIT_VS(PM8901_LVS3, 0, 1, 0, 0),
3970 RPM_VREG_INIT_VS(PM8901_MVS0, 0, 1, 0, 0),
3971};
3972
3973#define RPM_VREG(_id) \
3974 [_id] = { \
3975 .name = "rpm-regulator", \
3976 .id = _id, \
3977 .dev = { \
3978 .platform_data = &rpm_vreg_init_pdata[_id], \
3979 }, \
3980 }
3981
3982static struct platform_device rpm_vreg_device[RPM_VREG_ID_MAX] = {
3983 RPM_VREG(RPM_VREG_ID_PM8058_L0),
3984 RPM_VREG(RPM_VREG_ID_PM8058_L1),
3985 RPM_VREG(RPM_VREG_ID_PM8058_L2),
3986 RPM_VREG(RPM_VREG_ID_PM8058_L3),
3987 RPM_VREG(RPM_VREG_ID_PM8058_L4),
3988 RPM_VREG(RPM_VREG_ID_PM8058_L5),
3989 RPM_VREG(RPM_VREG_ID_PM8058_L6),
3990 RPM_VREG(RPM_VREG_ID_PM8058_L7),
3991 RPM_VREG(RPM_VREG_ID_PM8058_L8),
3992 RPM_VREG(RPM_VREG_ID_PM8058_L9),
3993 RPM_VREG(RPM_VREG_ID_PM8058_L10),
3994 RPM_VREG(RPM_VREG_ID_PM8058_L11),
3995 RPM_VREG(RPM_VREG_ID_PM8058_L12),
3996 RPM_VREG(RPM_VREG_ID_PM8058_L13),
3997 RPM_VREG(RPM_VREG_ID_PM8058_L14),
3998 RPM_VREG(RPM_VREG_ID_PM8058_L15),
3999 RPM_VREG(RPM_VREG_ID_PM8058_L16),
4000 RPM_VREG(RPM_VREG_ID_PM8058_L17),
4001 RPM_VREG(RPM_VREG_ID_PM8058_L18),
4002 RPM_VREG(RPM_VREG_ID_PM8058_L19),
4003 RPM_VREG(RPM_VREG_ID_PM8058_L20),
4004 RPM_VREG(RPM_VREG_ID_PM8058_L21),
4005 RPM_VREG(RPM_VREG_ID_PM8058_L22),
4006 RPM_VREG(RPM_VREG_ID_PM8058_L23),
4007 RPM_VREG(RPM_VREG_ID_PM8058_L24),
4008 RPM_VREG(RPM_VREG_ID_PM8058_L25),
4009 RPM_VREG(RPM_VREG_ID_PM8058_S0),
4010 RPM_VREG(RPM_VREG_ID_PM8058_S1),
4011 RPM_VREG(RPM_VREG_ID_PM8058_S2),
4012 RPM_VREG(RPM_VREG_ID_PM8058_S3),
4013 RPM_VREG(RPM_VREG_ID_PM8058_S4),
4014 RPM_VREG(RPM_VREG_ID_PM8058_LVS0),
4015 RPM_VREG(RPM_VREG_ID_PM8058_LVS1),
4016 RPM_VREG(RPM_VREG_ID_PM8058_NCP),
4017 RPM_VREG(RPM_VREG_ID_PM8901_L0),
4018 RPM_VREG(RPM_VREG_ID_PM8901_L1),
4019 RPM_VREG(RPM_VREG_ID_PM8901_L2),
4020 RPM_VREG(RPM_VREG_ID_PM8901_L3),
4021 RPM_VREG(RPM_VREG_ID_PM8901_L4),
4022 RPM_VREG(RPM_VREG_ID_PM8901_L5),
4023 RPM_VREG(RPM_VREG_ID_PM8901_L6),
4024 RPM_VREG(RPM_VREG_ID_PM8901_S2),
4025 RPM_VREG(RPM_VREG_ID_PM8901_S3),
4026 RPM_VREG(RPM_VREG_ID_PM8901_S4),
4027 RPM_VREG(RPM_VREG_ID_PM8901_LVS0),
4028 RPM_VREG(RPM_VREG_ID_PM8901_LVS1),
4029 RPM_VREG(RPM_VREG_ID_PM8901_LVS2),
4030 RPM_VREG(RPM_VREG_ID_PM8901_LVS3),
4031 RPM_VREG(RPM_VREG_ID_PM8901_MVS0),
4032};
4033
4034static struct platform_device *early_regulators[] __initdata = {
4035 &msm_device_saw_s0,
4036 &msm_device_saw_s1,
4037#ifdef CONFIG_PMIC8058
4038 &rpm_vreg_device[RPM_VREG_ID_PM8058_S0],
4039 &rpm_vreg_device[RPM_VREG_ID_PM8058_S1],
4040#endif
4041};
4042
4043static struct platform_device *early_devices[] __initdata = {
4044#ifdef CONFIG_MSM_BUS_SCALING
4045 &msm_bus_apps_fabric,
4046 &msm_bus_sys_fabric,
4047 &msm_bus_mm_fabric,
4048 &msm_bus_sys_fpb,
4049 &msm_bus_cpss_fpb,
4050#endif
4051 &msm_device_dmov_adm0,
4052 &msm_device_dmov_adm1,
4053};
4054
4055#if (defined(CONFIG_MARIMBA_CORE)) && \
4056 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4057
4058static int bluetooth_power(int);
4059static struct platform_device msm_bt_power_device = {
4060 .name = "bt_power",
4061 .id = -1,
4062 .dev = {
4063 .platform_data = &bluetooth_power,
4064 },
4065};
4066#endif
4067
4068static struct platform_device msm_tsens_device = {
4069 .name = "tsens-tm",
4070 .id = -1,
4071};
4072
4073static struct platform_device *rumi_sim_devices[] __initdata = {
4074 &smc91x_device,
4075 &msm_device_uart_dm12,
4076#ifdef CONFIG_I2C_QUP
4077 &msm_gsbi3_qup_i2c_device,
4078 &msm_gsbi4_qup_i2c_device,
4079 &msm_gsbi7_qup_i2c_device,
4080 &msm_gsbi8_qup_i2c_device,
4081 &msm_gsbi9_qup_i2c_device,
4082 &msm_gsbi12_qup_i2c_device,
4083#endif
4084#ifdef CONFIG_I2C_SSBI
4085 &msm_device_ssbi1,
4086 &msm_device_ssbi2,
4087 &msm_device_ssbi3,
4088#endif
4089#ifdef CONFIG_ANDROID_PMEM
4090 &android_pmem_device,
4091 &android_pmem_adsp_device,
4092 &android_pmem_audio_device,
4093 &android_pmem_smipool_device,
4094#endif
4095#ifdef CONFIG_MSM_ROTATOR
4096 &msm_rotator_device,
4097#endif
4098 &msm_fb_device,
4099 &msm_kgsl_3d0,
4100 &msm_kgsl_2d0,
4101 &msm_kgsl_2d1,
4102 &lcdc_samsung_panel_device,
4103#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4104 &hdmi_msm_device,
4105#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4106#ifdef CONFIG_MSM_CAMERA
4107#ifdef CONFIG_MT9E013
4108 &msm_camera_sensor_mt9e013,
4109#endif
4110#ifdef CONFIG_IMX074
4111 &msm_camera_sensor_imx074,
4112#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004113#ifdef CONFIG_VX6953
4114 &msm_camera_sensor_vx6953,
4115#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004116#ifdef CONFIG_WEBCAM_OV7692
4117 &msm_camera_sensor_webcam_ov7692,
4118#endif
4119#ifdef CONFIG_WEBCAM_OV9726
4120 &msm_camera_sensor_webcam_ov9726,
4121#endif
4122#ifdef CONFIG_QS_S5K4E1
4123 &msm_camera_sensor_qs_s5k4e1,
4124#endif
4125#endif
4126#ifdef CONFIG_MSM_GEMINI
4127 &msm_gemini_device,
4128#endif
4129#ifdef CONFIG_MSM_VPE
4130 &msm_vpe_device,
4131#endif
4132 &msm_device_vidc,
4133};
4134
4135#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4136enum {
4137 SX150X_CORE,
4138 SX150X_DOCKING,
4139 SX150X_SURF,
4140 SX150X_LEFT_FHA,
4141 SX150X_RIGHT_FHA,
4142 SX150X_SOUTH,
4143 SX150X_NORTH,
4144 SX150X_CORE_FLUID,
4145};
4146
4147static struct sx150x_platform_data sx150x_data[] __initdata = {
4148 [SX150X_CORE] = {
4149 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4150 .oscio_is_gpo = false,
4151 .io_pullup_ena = 0x0c08,
4152 .io_pulldn_ena = 0x4060,
4153 .io_open_drain_ena = 0x000c,
4154 .io_polarity = 0,
4155 .irq_summary = -1, /* see fixup_i2c_configs() */
4156 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4157 },
4158 [SX150X_DOCKING] = {
4159 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4160 .oscio_is_gpo = false,
4161 .io_pullup_ena = 0x5e06,
4162 .io_pulldn_ena = 0x81b8,
4163 .io_open_drain_ena = 0,
4164 .io_polarity = 0,
4165 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4166 UI_INT2_N),
4167 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4168 GPIO_DOCKING_EXPANDER_BASE -
4169 GPIO_EXPANDER_GPIO_BASE,
4170 },
4171 [SX150X_SURF] = {
4172 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4173 .oscio_is_gpo = false,
4174 .io_pullup_ena = 0,
4175 .io_pulldn_ena = 0,
4176 .io_open_drain_ena = 0,
4177 .io_polarity = 0,
4178 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4179 UI_INT1_N),
4180 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4181 GPIO_SURF_EXPANDER_BASE -
4182 GPIO_EXPANDER_GPIO_BASE,
4183 },
4184 [SX150X_LEFT_FHA] = {
4185 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4186 .oscio_is_gpo = false,
4187 .io_pullup_ena = 0,
4188 .io_pulldn_ena = 0x40,
4189 .io_open_drain_ena = 0,
4190 .io_polarity = 0,
4191 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4192 UI_INT3_N),
4193 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4194 GPIO_LEFT_KB_EXPANDER_BASE -
4195 GPIO_EXPANDER_GPIO_BASE,
4196 },
4197 [SX150X_RIGHT_FHA] = {
4198 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4199 .oscio_is_gpo = true,
4200 .io_pullup_ena = 0,
4201 .io_pulldn_ena = 0,
4202 .io_open_drain_ena = 0,
4203 .io_polarity = 0,
4204 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4205 UI_INT3_N),
4206 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4207 GPIO_RIGHT_KB_EXPANDER_BASE -
4208 GPIO_EXPANDER_GPIO_BASE,
4209 },
4210 [SX150X_SOUTH] = {
4211 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4212 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4213 GPIO_SOUTH_EXPANDER_BASE -
4214 GPIO_EXPANDER_GPIO_BASE,
4215 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4216 },
4217 [SX150X_NORTH] = {
4218 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4219 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4220 GPIO_NORTH_EXPANDER_BASE -
4221 GPIO_EXPANDER_GPIO_BASE,
4222 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4223 .oscio_is_gpo = true,
4224 .io_open_drain_ena = 0x30,
4225 },
4226 [SX150X_CORE_FLUID] = {
4227 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4228 .oscio_is_gpo = false,
4229 .io_pullup_ena = 0x0408,
4230 .io_pulldn_ena = 0x4060,
4231 .io_open_drain_ena = 0x0008,
4232 .io_polarity = 0,
4233 .irq_summary = -1, /* see fixup_i2c_configs() */
4234 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4235 },
4236};
4237
4238#ifdef CONFIG_SENSORS_MSM_ADC
4239/* Configuration of EPM expander is done when client
4240 * request an adc read
4241 */
4242static struct sx150x_platform_data sx150x_epmdata = {
4243 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4244 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4245 GPIO_EPM_EXPANDER_BASE -
4246 GPIO_EXPANDER_GPIO_BASE,
4247 .irq_summary = -1,
4248};
4249#endif
4250
4251/* sx150x_low_power_cfg
4252 *
4253 * This data and init function are used to put unused gpio-expander output
4254 * lines into their low-power states at boot. The init
4255 * function must be deferred until a later init stage because the i2c
4256 * gpio expander drivers do not probe until after they are registered
4257 * (see register_i2c_devices) and the work-queues for those registrations
4258 * are processed. Because these lines are unused, there is no risk of
4259 * competing with a device driver for the gpio.
4260 *
4261 * gpio lines whose low-power states are input are naturally in their low-
4262 * power configurations once probed, see the platform data structures above.
4263 */
4264struct sx150x_low_power_cfg {
4265 unsigned gpio;
4266 unsigned val;
4267};
4268
4269static struct sx150x_low_power_cfg
4270common_sx150x_lp_cfgs[] __initdata = {
4271 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4272 {GPIO_EXT_GPS_LNA_EN, 0},
4273 {GPIO_MSM_WAKES_BT, 0},
4274 {GPIO_USB_UICC_EN, 0},
4275 {GPIO_BATT_GAUGE_EN, 0},
4276};
4277
4278static struct sx150x_low_power_cfg
4279surf_ffa_sx150x_lp_cfgs[] __initdata = {
4280 {GPIO_MIPI_DSI_RST_N, 0},
4281 {GPIO_DONGLE_PWR_EN, 0},
4282 {GPIO_CAP_TS_SLEEP, 1},
4283 {GPIO_WEB_CAMIF_RESET_N, 0},
4284};
4285
4286static void __init
4287cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4288{
4289 unsigned n;
4290 int rc;
4291
4292 for (n = 0; n < nelems; ++n) {
4293 rc = gpio_request(cfgs[n].gpio, NULL);
4294 if (!rc) {
4295 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4296 gpio_free(cfgs[n].gpio);
4297 }
4298
4299 if (rc) {
4300 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4301 __func__, cfgs[n].gpio, rc);
4302 }
Steve Muckle9161d302010-02-11 11:50:40 -08004303 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004304}
4305
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004306static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004307{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004308 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4309 ARRAY_SIZE(common_sx150x_lp_cfgs));
4310 if (!machine_is_msm8x60_fluid())
4311 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4312 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4313 return 0;
4314}
4315module_init(cfg_sx150xs_low_power);
4316
4317#ifdef CONFIG_I2C
4318static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4319 {
4320 I2C_BOARD_INFO("sx1509q", 0x3e),
4321 .platform_data = &sx150x_data[SX150X_CORE]
4322 },
4323};
4324
4325static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4326 {
4327 I2C_BOARD_INFO("sx1509q", 0x3f),
4328 .platform_data = &sx150x_data[SX150X_DOCKING]
4329 },
4330};
4331
4332static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4333 {
4334 I2C_BOARD_INFO("sx1509q", 0x70),
4335 .platform_data = &sx150x_data[SX150X_SURF]
4336 }
4337};
4338
4339static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4340 {
4341 I2C_BOARD_INFO("sx1508q", 0x21),
4342 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4343 },
4344 {
4345 I2C_BOARD_INFO("sx1508q", 0x22),
4346 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4347 }
4348};
4349
4350static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4351 {
4352 I2C_BOARD_INFO("sx1508q", 0x23),
4353 .platform_data = &sx150x_data[SX150X_SOUTH]
4354 },
4355 {
4356 I2C_BOARD_INFO("sx1508q", 0x20),
4357 .platform_data = &sx150x_data[SX150X_NORTH]
4358 }
4359};
4360
4361static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4362 {
4363 I2C_BOARD_INFO("sx1509q", 0x3e),
4364 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4365 },
4366};
4367
4368#ifdef CONFIG_SENSORS_MSM_ADC
4369static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4370 {
4371 I2C_BOARD_INFO("sx1509q", 0x3e),
4372 .platform_data = &sx150x_epmdata
4373 },
4374};
4375#endif
4376#endif
4377#endif
4378
4379#ifdef CONFIG_SENSORS_MSM_ADC
4380static struct resource resources_adc[] = {
4381 {
4382 .start = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4383 .end = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4384 .flags = IORESOURCE_IRQ,
4385 },
4386};
4387
4388static struct adc_access_fn xoadc_fn = {
4389 pm8058_xoadc_select_chan_and_start_conv,
4390 pm8058_xoadc_read_adc_code,
4391 pm8058_xoadc_get_properties,
4392 pm8058_xoadc_slot_request,
4393 pm8058_xoadc_restore_slot,
4394 pm8058_xoadc_calibrate,
4395};
4396
4397#if defined(CONFIG_I2C) && \
4398 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4399static struct regulator *vreg_adc_epm1;
4400
4401static struct i2c_client *epm_expander_i2c_register_board(void)
4402
4403{
4404 struct i2c_adapter *i2c_adap;
4405 struct i2c_client *client = NULL;
4406 i2c_adap = i2c_get_adapter(0x0);
4407
4408 if (i2c_adap == NULL)
4409 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4410
4411 if (i2c_adap != NULL)
4412 client = i2c_new_device(i2c_adap,
4413 &fluid_expanders_i2c_epm_info[0]);
4414 return client;
4415
4416}
4417
4418static unsigned int msm_adc_gpio_configure_expander_enable(void)
4419{
4420 int rc = 0;
4421 static struct i2c_client *epm_i2c_client;
4422
4423 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4424
4425 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4426
4427 if (IS_ERR(vreg_adc_epm1)) {
4428 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4429 return 0;
4430 }
4431
4432 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4433 if (rc)
4434 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4435 "regulator set voltage failed\n");
4436
4437 rc = regulator_enable(vreg_adc_epm1);
4438 if (rc) {
4439 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4440 "Error while enabling regulator for epm s3 %d\n", rc);
4441 return rc;
4442 }
4443
4444 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4445 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4446
4447 msleep(1000);
4448
4449 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4450 if (!rc) {
4451 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4452 "Configure 5v boost\n");
4453 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4454 } else {
4455 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4456 "Error for epm 5v boost en\n");
4457 goto exit_vreg_epm;
4458 }
4459
4460 msleep(500);
4461
4462 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4463 if (!rc) {
4464 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4465 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4466 "Configure epm 3.3v\n");
4467 } else {
4468 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4469 "Error for gpio 3.3ven\n");
4470 goto exit_vreg_epm;
4471 }
4472 msleep(500);
4473
4474 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4475 "Trying to request EPM LVLSFT_EN\n");
4476 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4477 if (!rc) {
4478 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4479 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4480 "Configure the lvlsft\n");
4481 } else {
4482 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4483 "Error for epm lvlsft_en\n");
4484 goto exit_vreg_epm;
4485 }
4486
4487 msleep(500);
4488
4489 if (!epm_i2c_client)
4490 epm_i2c_client = epm_expander_i2c_register_board();
4491
4492 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4493 if (!rc)
4494 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4495 if (rc) {
4496 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4497 ": GPIO PWR MON Enable issue\n");
4498 goto exit_vreg_epm;
4499 }
4500
4501 msleep(1000);
4502
4503 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4504 if (!rc) {
4505 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4506 if (rc) {
4507 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4508 ": ADC1_PWDN error direction out\n");
4509 goto exit_vreg_epm;
4510 }
4511 }
4512
4513 msleep(100);
4514
4515 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4516 if (!rc) {
4517 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4518 if (rc) {
4519 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4520 ": ADC2_PWD error direction out\n");
4521 goto exit_vreg_epm;
4522 }
4523 }
4524
4525 msleep(1000);
4526
4527 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4528 if (!rc) {
4529 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4530 if (rc) {
4531 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4532 "Gpio request problem %d\n", rc);
4533 goto exit_vreg_epm;
4534 }
4535 }
4536
4537 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4538 if (!rc) {
4539 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4540 if (rc) {
4541 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4542 ": EPM_SPI_ADC1_CS_N error\n");
4543 goto exit_vreg_epm;
4544 }
4545 }
4546
4547 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4548 if (!rc) {
4549 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4550 if (rc) {
4551 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4552 ": EPM_SPI_ADC2_Cs_N error\n");
4553 goto exit_vreg_epm;
4554 }
4555 }
4556
4557 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4558 "the power monitor reset for epm\n");
4559
4560 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4561 if (!rc) {
4562 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4563 if (rc) {
4564 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4565 ": Error in the power mon reset\n");
4566 goto exit_vreg_epm;
4567 }
4568 }
4569
4570 msleep(1000);
4571
4572 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4573
4574 msleep(500);
4575
4576 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4577
4578 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4579
4580 return rc;
4581
4582exit_vreg_epm:
4583 regulator_disable(vreg_adc_epm1);
4584
4585 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4586 " rc = %d.\n", rc);
4587 return rc;
4588};
4589
4590static unsigned int msm_adc_gpio_configure_expander_disable(void)
4591{
4592 int rc = 0;
4593
4594 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4595 gpio_free(GPIO_PWR_MON_RESET_N);
4596
4597 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4598 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4599
4600 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4601 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4602
4603 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4604 gpio_free(GPIO_PWR_MON_START);
4605
4606 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4607 gpio_free(GPIO_ADC1_PWDN_N);
4608
4609 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4610 gpio_free(GPIO_ADC2_PWDN_N);
4611
4612 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4613 gpio_free(GPIO_PWR_MON_ENABLE);
4614
4615 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4616 gpio_free(GPIO_EPM_LVLSFT_EN);
4617
4618 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4619 gpio_free(GPIO_EPM_5V_BOOST_EN);
4620
4621 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4622 gpio_free(GPIO_EPM_3_3V_EN);
4623
4624 rc = regulator_disable(vreg_adc_epm1);
4625 if (rc)
4626 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4627 "Error while enabling regulator for epm s3 %d\n", rc);
4628 regulator_put(vreg_adc_epm1);
4629
4630 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4631 return rc;
4632};
4633
4634unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4635{
4636 int rc = 0;
4637
4638 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4639 cs_enable);
4640
4641 if (cs_enable < 16) {
4642 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4643 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4644 } else {
4645 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4646 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4647 }
4648 return rc;
4649};
4650
4651unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4652{
4653 int rc = 0;
4654
4655 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4656
4657 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4658
4659 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4660
4661 return rc;
4662};
4663#endif
4664
4665static struct msm_adc_channels msm_adc_channels_data[] = {
4666 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4667 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4668 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4669 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4670 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4671 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4672 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4673 CHAN_PATH_TYPE4,
4674 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4675 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4676 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4677 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4678 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4679 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4680 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4681 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4682 CHAN_PATH_TYPE12,
4683 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4684 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4685 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4686 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4687 CHAN_PATH_TYPE_NONE,
4688 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4689 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4690 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4691 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4692 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4693 scale_xtern_chgr_cur},
4694 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4695 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4696 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4697 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4698 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4699 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4700 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4701 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4702 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4703 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4704 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4705 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4706};
4707
4708static char *msm_adc_fluid_device_names[] = {
4709 "ADS_ADC1",
4710 "ADS_ADC2",
4711};
4712
4713static struct msm_adc_platform_data msm_adc_pdata = {
4714 .channel = msm_adc_channels_data,
4715 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4716#if defined(CONFIG_I2C) && \
4717 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4718 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4719 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4720 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4721 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4722#endif
4723};
4724
4725static struct platform_device msm_adc_device = {
4726 .name = "msm_adc",
4727 .id = -1,
4728 .dev = {
4729 .platform_data = &msm_adc_pdata,
4730 },
4731};
4732
4733static void pmic8058_xoadc_mpp_config(void)
4734{
4735 int rc;
4736
4737 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4738 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4739 if (rc)
4740 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4741
4742 rc = pm8058_mpp_config_analog_input(XOADC_MPP_3,
4743 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
4744 if (rc)
4745 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
4746
4747 rc = pm8058_mpp_config_analog_input(XOADC_MPP_5,
4748 PM_MPP_AIN_AMUX_CH9, PM_MPP_AOUT_CTL_DISABLE);
4749 if (rc)
4750 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
4751
4752 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
4753 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
4754 if (rc)
4755 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
4756
4757 rc = pm8058_mpp_config_analog_input(XOADC_MPP_8,
4758 PM_MPP_AIN_AMUX_CH8, PM_MPP_AOUT_CTL_DISABLE);
4759 if (rc)
4760 pr_err("%s: Config mpp8 on pmic 8058 failed\n", __func__);
4761
4762 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
4763 PM_MPP_AIN_AMUX_CH7, PM_MPP_AOUT_CTL_DISABLE);
4764 if (rc)
4765 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
4766}
4767
4768static struct regulator *vreg_ldo18_adc;
4769
4770static int pmic8058_xoadc_vreg_config(int on)
4771{
4772 int rc;
4773
4774 if (on) {
4775 rc = regulator_enable(vreg_ldo18_adc);
4776 if (rc)
4777 pr_err("%s: Enable of regulator ldo18_adc "
4778 "failed\n", __func__);
4779 } else {
4780 rc = regulator_disable(vreg_ldo18_adc);
4781 if (rc)
4782 pr_err("%s: Disable of regulator ldo18_adc "
4783 "failed\n", __func__);
4784 }
4785
4786 return rc;
4787}
4788
4789static int pmic8058_xoadc_vreg_setup(void)
4790{
4791 int rc;
4792
4793 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4794 if (IS_ERR(vreg_ldo18_adc)) {
4795 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4796 __func__, PTR_ERR(vreg_ldo18_adc));
4797 rc = PTR_ERR(vreg_ldo18_adc);
4798 goto fail;
4799 }
4800
4801 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4802 if (rc) {
4803 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4804 goto fail;
4805 }
4806
4807 return rc;
4808fail:
4809 regulator_put(vreg_ldo18_adc);
4810 return rc;
4811}
4812
4813static void pmic8058_xoadc_vreg_shutdown(void)
4814{
4815 regulator_put(vreg_ldo18_adc);
4816}
4817
4818/* usec. For this ADC,
4819 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4820 * Each channel has different configuration, thus at the time of starting
4821 * the conversion, xoadc will return actual conversion time
4822 * */
4823static struct adc_properties pm8058_xoadc_data = {
4824 .adc_reference = 2200, /* milli-voltage for this adc */
4825 .bitresolution = 15,
4826 .bipolar = 0,
4827 .conversiontime = 54,
4828};
4829
4830static struct xoadc_platform_data xoadc_pdata = {
4831 .xoadc_prop = &pm8058_xoadc_data,
4832 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4833 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4834 .xoadc_num = XOADC_PMIC_0,
4835 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4836 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4837};
4838#endif
4839
4840#ifdef CONFIG_MSM_SDIO_AL
4841
4842static unsigned mdm2ap_status = 140;
4843
4844static int configure_mdm2ap_status(int on)
4845{
4846 int ret = 0;
4847 if (on)
4848 ret = msm_gpiomux_get(mdm2ap_status);
4849 else
4850 ret = msm_gpiomux_put(mdm2ap_status);
4851
4852 if (ret)
4853 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4854 on);
4855
4856 return ret;
4857}
4858
4859
4860static int get_mdm2ap_status(void)
4861{
4862 return gpio_get_value(mdm2ap_status);
4863}
4864
4865static struct sdio_al_platform_data sdio_al_pdata = {
4866 .config_mdm2ap_status = configure_mdm2ap_status,
4867 .get_mdm2ap_status = get_mdm2ap_status,
4868 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004869 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004870 .peer_sdioc_version_major = 0x0004,
4871 .peer_sdioc_boot_version_minor = 0x0001,
4872 .peer_sdioc_boot_version_major = 0x0003
4873};
4874
4875struct platform_device msm_device_sdio_al = {
4876 .name = "msm_sdio_al",
4877 .id = -1,
4878 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004879 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004880 .platform_data = &sdio_al_pdata,
4881 },
4882};
4883
4884#endif /* CONFIG_MSM_SDIO_AL */
4885
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06004886static struct platform_device msm_rpm_device = {
4887 .name = "msm_rpm",
4888 .id = -1,
4889};
4890
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004891static struct platform_device *charm_devices[] __initdata = {
4892 &msm_charm_modem,
4893#ifdef CONFIG_MSM_SDIO_AL
4894 &msm_device_sdio_al,
4895#endif
Maya Erez6862b142011-08-22 09:07:07 +03004896#ifdef CONFIG_MSM_SDIO_AL
4897 &msm_device_sdio_al,
4898#endif
4899
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004900};
4901
4902static struct platform_device *surf_devices[] __initdata = {
4903 &msm_device_smd,
4904 &msm_device_uart_dm12,
4905#ifdef CONFIG_I2C_QUP
4906 &msm_gsbi3_qup_i2c_device,
4907 &msm_gsbi4_qup_i2c_device,
4908 &msm_gsbi7_qup_i2c_device,
4909 &msm_gsbi8_qup_i2c_device,
4910 &msm_gsbi9_qup_i2c_device,
4911 &msm_gsbi12_qup_i2c_device,
4912#endif
4913#ifdef CONFIG_SERIAL_MSM_HS
4914 &msm_device_uart_dm1,
4915#endif
4916#ifdef CONFIG_I2C_SSBI
4917 &msm_device_ssbi1,
4918 &msm_device_ssbi2,
4919 &msm_device_ssbi3,
4920#endif
4921#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
4922 &isp1763_device,
4923#endif
4924
4925 &asoc_msm_pcm,
4926 &asoc_msm_dai0,
4927 &asoc_msm_dai1,
4928#if defined (CONFIG_MSM_8x60_VOIP)
4929 &asoc_msm_mvs,
4930 &asoc_mvs_dai0,
4931 &asoc_mvs_dai1,
4932#endif
4933#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
4934 &msm_device_otg,
4935#endif
4936#ifdef CONFIG_USB_GADGET_MSM_72K
4937 &msm_device_gadget_peripheral,
4938#endif
4939#ifdef CONFIG_USB_G_ANDROID
4940 &android_usb_device,
4941#endif
4942#ifdef CONFIG_BATTERY_MSM
4943 &msm_batt_device,
4944#endif
4945#ifdef CONFIG_ANDROID_PMEM
4946 &android_pmem_device,
4947 &android_pmem_adsp_device,
4948 &android_pmem_audio_device,
4949 &android_pmem_smipool_device,
4950#endif
4951#ifdef CONFIG_MSM_ROTATOR
4952 &msm_rotator_device,
4953#endif
4954 &msm_fb_device,
4955 &msm_kgsl_3d0,
4956 &msm_kgsl_2d0,
4957 &msm_kgsl_2d1,
4958 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04004959#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
4960 &lcdc_nt35582_panel_device,
4961#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004962#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
4963 &lcdc_samsung_oled_panel_device,
4964#endif
4965#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
4966 &lcdc_auo_wvga_panel_device,
4967#endif
4968#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4969 &hdmi_msm_device,
4970#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4971#ifdef CONFIG_FB_MSM_MIPI_DSI
4972 &mipi_dsi_toshiba_panel_device,
4973 &mipi_dsi_novatek_panel_device,
4974#endif
4975#ifdef CONFIG_MSM_CAMERA
4976#ifdef CONFIG_MT9E013
4977 &msm_camera_sensor_mt9e013,
4978#endif
4979#ifdef CONFIG_IMX074
4980 &msm_camera_sensor_imx074,
4981#endif
4982#ifdef CONFIG_WEBCAM_OV7692
4983 &msm_camera_sensor_webcam_ov7692,
4984#endif
4985#ifdef CONFIG_WEBCAM_OV9726
4986 &msm_camera_sensor_webcam_ov9726,
4987#endif
4988#ifdef CONFIG_QS_S5K4E1
4989 &msm_camera_sensor_qs_s5k4e1,
4990#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004991#ifdef CONFIG_VX6953
4992 &msm_camera_sensor_vx6953,
4993#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004994#endif
4995#ifdef CONFIG_MSM_GEMINI
4996 &msm_gemini_device,
4997#endif
4998#ifdef CONFIG_MSM_VPE
4999 &msm_vpe_device,
5000#endif
5001
5002#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5003 &msm_rpm_log_device,
5004#endif
5005#if defined(CONFIG_MSM_RPM_STATS_LOG)
5006 &msm_rpm_stat_device,
5007#endif
5008 &msm_device_vidc,
5009#if (defined(CONFIG_MARIMBA_CORE)) && \
5010 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5011 &msm_bt_power_device,
5012#endif
5013#ifdef CONFIG_SENSORS_MSM_ADC
5014 &msm_adc_device,
5015#endif
5016#ifdef CONFIG_PMIC8058
5017 &rpm_vreg_device[RPM_VREG_ID_PM8058_L0],
5018 &rpm_vreg_device[RPM_VREG_ID_PM8058_L1],
5019 &rpm_vreg_device[RPM_VREG_ID_PM8058_L2],
5020 &rpm_vreg_device[RPM_VREG_ID_PM8058_L3],
5021 &rpm_vreg_device[RPM_VREG_ID_PM8058_L4],
5022 &rpm_vreg_device[RPM_VREG_ID_PM8058_L5],
5023 &rpm_vreg_device[RPM_VREG_ID_PM8058_L6],
5024 &rpm_vreg_device[RPM_VREG_ID_PM8058_L7],
5025 &rpm_vreg_device[RPM_VREG_ID_PM8058_L8],
5026 &rpm_vreg_device[RPM_VREG_ID_PM8058_L9],
5027 &rpm_vreg_device[RPM_VREG_ID_PM8058_L10],
5028 &rpm_vreg_device[RPM_VREG_ID_PM8058_L11],
5029 &rpm_vreg_device[RPM_VREG_ID_PM8058_L12],
5030 &rpm_vreg_device[RPM_VREG_ID_PM8058_L13],
5031 &rpm_vreg_device[RPM_VREG_ID_PM8058_L14],
5032 &rpm_vreg_device[RPM_VREG_ID_PM8058_L15],
5033 &rpm_vreg_device[RPM_VREG_ID_PM8058_L16],
5034 &rpm_vreg_device[RPM_VREG_ID_PM8058_L17],
5035 &rpm_vreg_device[RPM_VREG_ID_PM8058_L18],
5036 &rpm_vreg_device[RPM_VREG_ID_PM8058_L19],
5037 &rpm_vreg_device[RPM_VREG_ID_PM8058_L20],
5038 &rpm_vreg_device[RPM_VREG_ID_PM8058_L21],
5039 &rpm_vreg_device[RPM_VREG_ID_PM8058_L22],
5040 &rpm_vreg_device[RPM_VREG_ID_PM8058_L23],
5041 &rpm_vreg_device[RPM_VREG_ID_PM8058_L24],
5042 &rpm_vreg_device[RPM_VREG_ID_PM8058_L25],
5043 &rpm_vreg_device[RPM_VREG_ID_PM8058_S2],
5044 &rpm_vreg_device[RPM_VREG_ID_PM8058_S3],
5045 &rpm_vreg_device[RPM_VREG_ID_PM8058_S4],
5046 &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS0],
5047 &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS1],
5048 &rpm_vreg_device[RPM_VREG_ID_PM8058_NCP],
5049#endif
5050#ifdef CONFIG_PMIC8901
5051 &rpm_vreg_device[RPM_VREG_ID_PM8901_L0],
5052 &rpm_vreg_device[RPM_VREG_ID_PM8901_L1],
5053 &rpm_vreg_device[RPM_VREG_ID_PM8901_L2],
5054 &rpm_vreg_device[RPM_VREG_ID_PM8901_L3],
5055 &rpm_vreg_device[RPM_VREG_ID_PM8901_L4],
5056 &rpm_vreg_device[RPM_VREG_ID_PM8901_L5],
5057 &rpm_vreg_device[RPM_VREG_ID_PM8901_L6],
5058 &rpm_vreg_device[RPM_VREG_ID_PM8901_S2],
5059 &rpm_vreg_device[RPM_VREG_ID_PM8901_S3],
5060 &rpm_vreg_device[RPM_VREG_ID_PM8901_S4],
5061 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS0],
5062 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS1],
5063 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS2],
5064 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS3],
5065 &rpm_vreg_device[RPM_VREG_ID_PM8901_MVS0],
5066#endif
5067
5068#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5069 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5070 &qcrypto_device,
5071#endif
5072
5073#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5074 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5075 &qcedev_device,
5076#endif
5077
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005078
5079#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5080#ifdef CONFIG_MSM_USE_TSIF1
5081 &msm_device_tsif[1],
5082#else
5083 &msm_device_tsif[0],
5084#endif /* CONFIG_MSM_USE_TSIF1 */
5085#endif /* CONFIG_TSIF */
5086
5087#ifdef CONFIG_HW_RANDOM_MSM
5088 &msm_device_rng,
5089#endif
5090
5091 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005092 &msm_rpm_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005093
5094};
5095
5096static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5097 /* Kernel SMI memory pool for video core, used for firmware */
5098 /* and encoder, decoder scratch buffers */
5099 /* Kernel SMI memory pool should always precede the user space */
5100 /* SMI memory pool, as the video core will use offset address */
5101 /* from the Firmware base */
5102 [MEMTYPE_SMI_KERNEL] = {
5103 .start = KERNEL_SMI_BASE,
5104 .limit = KERNEL_SMI_SIZE,
5105 .size = KERNEL_SMI_SIZE,
5106 .flags = MEMTYPE_FLAGS_FIXED,
5107 },
5108 /* User space SMI memory pool for video core */
5109 /* used for encoder, decoder input & output buffers */
5110 [MEMTYPE_SMI] = {
5111 .start = USER_SMI_BASE,
5112 .limit = USER_SMI_SIZE,
5113 .flags = MEMTYPE_FLAGS_FIXED,
5114 },
5115 [MEMTYPE_EBI0] = {
5116 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5117 },
5118 [MEMTYPE_EBI1] = {
5119 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5120 },
5121};
5122
5123static void __init size_pmem_devices(void)
5124{
5125#ifdef CONFIG_ANDROID_PMEM
5126 android_pmem_adsp_pdata.size = pmem_adsp_size;
5127 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
5128 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5129 android_pmem_pdata.size = pmem_sf_size;
5130#endif
5131}
5132
5133static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5134{
5135 msm8x60_reserve_table[p->memory_type].size += p->size;
5136}
5137
5138static void __init reserve_pmem_memory(void)
5139{
5140#ifdef CONFIG_ANDROID_PMEM
5141 reserve_memory_for(&android_pmem_adsp_pdata);
5142 reserve_memory_for(&android_pmem_smipool_pdata);
5143 reserve_memory_for(&android_pmem_audio_pdata);
5144 reserve_memory_for(&android_pmem_pdata);
5145 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5146#endif
5147}
5148
5149static void __init msm8x60_calculate_reserve_sizes(void)
5150{
5151 size_pmem_devices();
5152 reserve_pmem_memory();
5153}
5154
5155static int msm8x60_paddr_to_memtype(unsigned int paddr)
5156{
5157 if (paddr >= 0x40000000 && paddr < 0x60000000)
5158 return MEMTYPE_EBI1;
5159 if (paddr >= 0x38000000 && paddr < 0x40000000)
5160 return MEMTYPE_SMI;
5161 return MEMTYPE_NONE;
5162}
5163
5164static struct reserve_info msm8x60_reserve_info __initdata = {
5165 .memtype_reserve_table = msm8x60_reserve_table,
5166 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5167 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5168};
5169
5170static void __init msm8x60_reserve(void)
5171{
5172 reserve_info = &msm8x60_reserve_info;
5173 msm_reserve();
5174}
5175
5176#define EXT_CHG_VALID_MPP 10
5177#define EXT_CHG_VALID_MPP_2 11
5178
5179#ifdef CONFIG_ISL9519_CHARGER
5180static int isl_detection_setup(void)
5181{
5182 int ret = 0;
5183
5184 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5185 PM8058_MPP_DIG_LEVEL_S3,
5186 PM_MPP_DIN_TO_INT);
5187 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5188 PM8058_MPP_DIG_LEVEL_S3,
5189 PM_MPP_BI_PULLUP_10KOHM
5190 );
5191 return ret;
5192}
5193
5194static struct isl_platform_data isl_data __initdata = {
5195 .chgcurrent = 700,
5196 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5197 .chg_detection_config = isl_detection_setup,
5198 .max_system_voltage = 4200,
5199 .min_system_voltage = 3200,
5200 .term_current = 120,
5201 .input_current = 2048,
5202};
5203
5204static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5205 {
5206 I2C_BOARD_INFO("isl9519q", 0x9),
5207 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5208 .platform_data = &isl_data,
5209 },
5210};
5211#endif
5212
5213#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5214static int smb137b_detection_setup(void)
5215{
5216 int ret = 0;
5217
5218 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5219 PM8058_MPP_DIG_LEVEL_S3,
5220 PM_MPP_DIN_TO_INT);
5221 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5222 PM8058_MPP_DIG_LEVEL_S3,
5223 PM_MPP_BI_PULLUP_10KOHM);
5224 return ret;
5225}
5226
5227static struct smb137b_platform_data smb137b_data __initdata = {
5228 .chg_detection_config = smb137b_detection_setup,
5229 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5230 .batt_mah_rating = 950,
5231};
5232
5233static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5234 {
5235 I2C_BOARD_INFO("smb137b", 0x08),
5236 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5237 .platform_data = &smb137b_data,
5238 },
5239};
5240#endif
5241
5242#ifdef CONFIG_PMIC8058
5243#define PMIC_GPIO_SDC3_DET 22
5244
5245static int pm8058_gpios_init(void)
5246{
5247 int i;
5248 int rc;
5249 struct pm8058_gpio_cfg {
5250 int gpio;
5251 struct pm8058_gpio cfg;
5252 };
5253
5254 struct pm8058_gpio_cfg gpio_cfgs[] = {
5255 { /* FFA ethernet */
5256 6,
5257 {
5258 .direction = PM_GPIO_DIR_IN,
5259 .pull = PM_GPIO_PULL_DN,
5260 .vin_sel = 2,
5261 .function = PM_GPIO_FUNC_NORMAL,
5262 .inv_int_pol = 0,
5263 },
5264 },
5265#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5266 {
5267 PMIC_GPIO_SDC3_DET - 1,
5268 {
5269 .direction = PM_GPIO_DIR_IN,
5270 .pull = PM_GPIO_PULL_UP_30,
5271 .vin_sel = 2,
5272 .function = PM_GPIO_FUNC_NORMAL,
5273 .inv_int_pol = 0,
5274 },
5275 },
5276#endif
5277 { /* core&surf gpio expander */
5278 UI_INT1_N,
5279 {
5280 .direction = PM_GPIO_DIR_IN,
5281 .pull = PM_GPIO_PULL_NO,
5282 .vin_sel = PM_GPIO_VIN_S3,
5283 .function = PM_GPIO_FUNC_NORMAL,
5284 .inv_int_pol = 0,
5285 },
5286 },
5287 { /* docking gpio expander */
5288 UI_INT2_N,
5289 {
5290 .direction = PM_GPIO_DIR_IN,
5291 .pull = PM_GPIO_PULL_NO,
5292 .vin_sel = PM_GPIO_VIN_S3,
5293 .function = PM_GPIO_FUNC_NORMAL,
5294 .inv_int_pol = 0,
5295 },
5296 },
5297 { /* FHA/keypad gpio expanders */
5298 UI_INT3_N,
5299 {
5300 .direction = PM_GPIO_DIR_IN,
5301 .pull = PM_GPIO_PULL_NO,
5302 .vin_sel = PM_GPIO_VIN_S3,
5303 .function = PM_GPIO_FUNC_NORMAL,
5304 .inv_int_pol = 0,
5305 },
5306 },
5307 { /* TouchDisc Interrupt */
5308 5,
5309 {
5310 .direction = PM_GPIO_DIR_IN,
5311 .pull = PM_GPIO_PULL_UP_1P5,
5312 .vin_sel = 2,
5313 .function = PM_GPIO_FUNC_NORMAL,
5314 .inv_int_pol = 0,
5315 }
5316 },
5317 { /* Timpani Reset */
5318 20,
5319 {
5320 .direction = PM_GPIO_DIR_OUT,
5321 .output_value = 1,
5322 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5323 .pull = PM_GPIO_PULL_DN,
5324 .out_strength = PM_GPIO_STRENGTH_HIGH,
5325 .function = PM_GPIO_FUNC_NORMAL,
5326 .vin_sel = 2,
5327 .inv_int_pol = 0,
5328 }
5329 },
5330 { /* PMIC ID interrupt */
5331 36,
5332 {
5333 .direction = PM_GPIO_DIR_IN,
5334 .pull = PM_GPIO_PULL_UP_1P5,
5335 .function = PM_GPIO_FUNC_NORMAL,
5336 .vin_sel = 2,
5337 .inv_int_pol = 0,
5338 }
5339 },
5340 };
5341
5342#if defined(CONFIG_HAPTIC_ISA1200) || \
5343 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5344
5345 struct pm8058_gpio_cfg en_hap_gpio_cfg = {
5346 PMIC_GPIO_HAP_ENABLE,
5347 {
5348 .direction = PM_GPIO_DIR_OUT,
5349 .pull = PM_GPIO_PULL_NO,
5350 .out_strength = PM_GPIO_STRENGTH_HIGH,
5351 .function = PM_GPIO_FUNC_NORMAL,
5352 .inv_int_pol = 0,
5353 .vin_sel = 2,
5354 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5355 .output_value = 0,
5356 }
5357
5358 };
5359#endif
5360
5361#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5362 struct pm8058_gpio_cfg line_in_gpio_cfg = {
5363 18,
5364 {
5365 .direction = PM_GPIO_DIR_IN,
5366 .pull = PM_GPIO_PULL_UP_1P5,
5367 .vin_sel = 2,
5368 .function = PM_GPIO_FUNC_NORMAL,
5369 .inv_int_pol = 0,
5370 }
5371 };
5372#endif
5373
5374#if defined(CONFIG_QS_S5K4E1)
5375 {
5376 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
5377 26,
5378 {
5379 .direction = PM_GPIO_DIR_OUT,
5380 .output_value = 0,
5381 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5382 .pull = PM_GPIO_PULL_DN,
5383 .out_strength = PM_GPIO_STRENGTH_HIGH,
5384 .function = PM_GPIO_FUNC_NORMAL,
5385 .vin_sel = 2,
5386 .inv_int_pol = 0,
5387 }
5388 };
5389#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005390#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5391 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
5392 GPIO_NT35582_BL_EN_HW_PIN - 1,
5393 {
5394 .direction = PM_GPIO_DIR_OUT,
5395 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5396 .output_value = 1,
5397 .pull = PM_GPIO_PULL_UP_30,
5398 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
5399 .vin_sel = PM_GPIO_VIN_L5,
5400 .out_strength = PM_GPIO_STRENGTH_HIGH,
5401 .function = PM_GPIO_FUNC_NORMAL,
5402 .inv_int_pol = 0,
5403 }
5404 };
5405#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005406#if defined(CONFIG_HAPTIC_ISA1200) || \
5407 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5408 if (machine_is_msm8x60_fluid()) {
5409 rc = pm8058_gpio_config(en_hap_gpio_cfg.gpio,
5410 &en_hap_gpio_cfg.cfg);
5411 if (rc < 0) {
5412 pr_err("%s pmic haptics gpio config failed\n",
5413 __func__);
5414 return rc;
5415 }
5416 }
5417#endif
5418
5419#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5420 /* Line_in only for 8660 ffa & surf */
5421 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005422 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005423 machine_is_msm8x60_fusn_ffa()) {
5424 rc = pm8058_gpio_config(line_in_gpio_cfg.gpio,
5425 &line_in_gpio_cfg.cfg);
5426 if (rc < 0) {
5427 pr_err("%s pmic line_in gpio config failed\n",
5428 __func__);
5429 return rc;
5430 }
5431 }
5432#endif
5433
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005434#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5435 if (machine_is_msm8x60_dragon()) {
5436 rc = pm8058_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
5437 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5438 if (rc < 0) {
5439 pr_err("%s pmic gpio config failed\n", __func__);
5440 return rc;
5441 }
5442 }
5443#endif
5444
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005445#if defined(CONFIG_QS_S5K4E1)
5446 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5447 if (machine_is_msm8x60_fluid()) {
5448 rc = pm8058_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
5449 &qs_hc37_cam_pd_gpio_cfg.cfg);
5450 if (rc < 0) {
5451 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5452 __func__);
5453 return rc;
5454 }
5455 }
5456 }
5457#endif
5458
5459 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
5460 rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
5461 &gpio_cfgs[i].cfg);
5462 if (rc < 0) {
5463 pr_err("%s pmic gpio config failed\n",
5464 __func__);
5465 return rc;
5466 }
5467 }
5468
5469 return 0;
5470}
5471
5472static const unsigned int ffa_keymap[] = {
5473 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5474 KEY(0, 1, KEY_UP), /* NAV - UP */
5475 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5476 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5477
5478 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5479 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5480 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5481 KEY(1, 3, KEY_VOLUMEDOWN),
5482
5483 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5484
5485 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5486 KEY(4, 1, KEY_UP), /* USER_UP */
5487 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5488 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5489 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5490
5491 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5492 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5493 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5494 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5495 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5496};
5497
Zhang Chang Ken683be172011-08-10 17:45:34 -04005498static const unsigned int dragon_keymap[] = {
5499 KEY(0, 0, KEY_MENU),
5500 KEY(0, 2, KEY_1),
5501 KEY(0, 3, KEY_4),
5502 KEY(0, 4, KEY_7),
5503
5504 KEY(1, 0, KEY_UP),
5505 KEY(1, 1, KEY_LEFT),
5506 KEY(1, 2, KEY_DOWN),
5507 KEY(1, 3, KEY_5),
5508 KEY(1, 4, KEY_8),
5509
5510 KEY(2, 0, KEY_HOME),
5511 KEY(2, 1, KEY_REPLY),
5512 KEY(2, 2, KEY_2),
5513 KEY(2, 3, KEY_6),
5514 KEY(2, 4, KEY_0),
5515
5516 KEY(3, 0, KEY_VOLUMEUP),
5517 KEY(3, 1, KEY_RIGHT),
5518 KEY(3, 2, KEY_3),
5519 KEY(3, 3, KEY_9),
5520 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5521
5522 KEY(4, 0, KEY_VOLUMEDOWN),
5523 KEY(4, 1, KEY_BACK),
5524 KEY(4, 2, KEY_CAMERA),
5525 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5526};
5527
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005528static struct resource resources_keypad[] = {
5529 {
5530 .start = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5531 .end = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5532 .flags = IORESOURCE_IRQ,
5533 },
5534 {
5535 .start = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5536 .end = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5537 .flags = IORESOURCE_IRQ,
5538 },
5539};
5540
5541static struct matrix_keymap_data ffa_keymap_data = {
5542 .keymap_size = ARRAY_SIZE(ffa_keymap),
5543 .keymap = ffa_keymap,
5544};
5545
5546static struct pmic8058_keypad_data ffa_keypad_data = {
5547 .input_name = "ffa-keypad",
5548 .input_phys_device = "ffa-keypad/input0",
5549 .num_rows = 6,
5550 .num_cols = 5,
5551 .rows_gpio_start = 8,
5552 .cols_gpio_start = 0,
5553 .debounce_ms = {8, 10},
5554 .scan_delay_ms = 32,
5555 .row_hold_ns = 91500,
5556 .wakeup = 1,
5557 .keymap_data = &ffa_keymap_data,
5558};
5559
Zhang Chang Ken683be172011-08-10 17:45:34 -04005560static struct matrix_keymap_data dragon_keymap_data = {
5561 .keymap_size = ARRAY_SIZE(dragon_keymap),
5562 .keymap = dragon_keymap,
5563};
5564
5565static struct pmic8058_keypad_data dragon_keypad_data = {
5566 .input_name = "dragon-keypad",
5567 .input_phys_device = "dragon-keypad/input0",
5568 .num_rows = 6,
5569 .num_cols = 5,
5570 .rows_gpio_start = 8,
5571 .cols_gpio_start = 0,
5572 .debounce_ms = {8, 10},
5573 .scan_delay_ms = 32,
5574 .row_hold_ns = 91500,
5575 .wakeup = 1,
5576 .keymap_data = &dragon_keymap_data,
5577};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005578static const unsigned int fluid_keymap[] = {
5579 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5580 KEY(0, 1, KEY_UP), /* NAV - UP */
5581 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5582 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5583
5584 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5585 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5586 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5587 KEY(1, 3, KEY_VOLUMEUP),
5588
5589 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5590
5591 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5592 KEY(4, 1, KEY_UP), /* USER_UP */
5593 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5594 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5595 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5596
Jilai Wang9a895102011-07-12 14:00:35 -04005597 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005598 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5599 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5600 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5601 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5602};
5603
5604static struct matrix_keymap_data fluid_keymap_data = {
5605 .keymap_size = ARRAY_SIZE(fluid_keymap),
5606 .keymap = fluid_keymap,
5607};
5608
5609static struct pmic8058_keypad_data fluid_keypad_data = {
5610 .input_name = "fluid-keypad",
5611 .input_phys_device = "fluid-keypad/input0",
5612 .num_rows = 6,
5613 .num_cols = 5,
5614 .rows_gpio_start = 8,
5615 .cols_gpio_start = 0,
5616 .debounce_ms = {8, 10},
5617 .scan_delay_ms = 32,
5618 .row_hold_ns = 91500,
5619 .wakeup = 1,
5620 .keymap_data = &fluid_keymap_data,
5621};
5622
5623static struct resource resources_pwrkey[] = {
5624 {
5625 .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5626 .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5627 .flags = IORESOURCE_IRQ,
5628 },
5629 {
5630 .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5631 .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5632 .flags = IORESOURCE_IRQ,
5633 },
5634};
5635
5636static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
5637 .pull_up = 1,
5638 .kpd_trigger_delay_us = 970,
5639 .wakeup = 1,
5640 .pwrkey_time_ms = 500,
5641};
5642
5643static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
5644 .initial_vibrate_ms = 500,
5645 .level_mV = 3000,
5646 .max_timeout_ms = 15000,
5647};
5648
5649#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5650#define PM8058_OTHC_CNTR_BASE0 0xA0
5651#define PM8058_OTHC_CNTR_BASE1 0x134
5652#define PM8058_OTHC_CNTR_BASE2 0x137
5653#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5654
5655static struct othc_accessory_info othc_accessories[] = {
5656 {
5657 .accessory = OTHC_SVIDEO_OUT,
5658 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5659 | OTHC_ADC_DETECT,
5660 .key_code = SW_VIDEOOUT_INSERT,
5661 .enabled = false,
5662 .adc_thres = {
5663 .min_threshold = 20,
5664 .max_threshold = 40,
5665 },
5666 },
5667 {
5668 .accessory = OTHC_ANC_HEADPHONE,
5669 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5670 OTHC_SWITCH_DETECT,
5671 .gpio = PM8058_LINE_IN_DET_GPIO,
5672 .active_low = 1,
5673 .key_code = SW_HEADPHONE_INSERT,
5674 .enabled = true,
5675 },
5676 {
5677 .accessory = OTHC_ANC_HEADSET,
5678 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5679 .gpio = PM8058_LINE_IN_DET_GPIO,
5680 .active_low = 1,
5681 .key_code = SW_HEADPHONE_INSERT,
5682 .enabled = true,
5683 },
5684 {
5685 .accessory = OTHC_HEADPHONE,
5686 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5687 .key_code = SW_HEADPHONE_INSERT,
5688 .enabled = true,
5689 },
5690 {
5691 .accessory = OTHC_MICROPHONE,
5692 .detect_flags = OTHC_GPIO_DETECT,
5693 .gpio = PM8058_LINE_IN_DET_GPIO,
5694 .active_low = 1,
5695 .key_code = SW_MICROPHONE_INSERT,
5696 .enabled = true,
5697 },
5698 {
5699 .accessory = OTHC_HEADSET,
5700 .detect_flags = OTHC_MICBIAS_DETECT,
5701 .key_code = SW_HEADPHONE_INSERT,
5702 .enabled = true,
5703 },
5704};
5705
5706static struct othc_switch_info switch_info[] = {
5707 {
5708 .min_adc_threshold = 0,
5709 .max_adc_threshold = 100,
5710 .key_code = KEY_PLAYPAUSE,
5711 },
5712 {
5713 .min_adc_threshold = 100,
5714 .max_adc_threshold = 200,
5715 .key_code = KEY_REWIND,
5716 },
5717 {
5718 .min_adc_threshold = 200,
5719 .max_adc_threshold = 500,
5720 .key_code = KEY_FASTFORWARD,
5721 },
5722};
5723
5724static struct othc_n_switch_config switch_config = {
5725 .voltage_settling_time_ms = 0,
5726 .num_adc_samples = 3,
5727 .adc_channel = CHANNEL_ADC_HDSET,
5728 .switch_info = switch_info,
5729 .num_keys = ARRAY_SIZE(switch_info),
5730 .default_sw_en = true,
5731 .default_sw_idx = 0,
5732};
5733
5734static struct hsed_bias_config hsed_bias_config = {
5735 /* HSED mic bias config info */
5736 .othc_headset = OTHC_HEADSET_NO,
5737 .othc_lowcurr_thresh_uA = 100,
5738 .othc_highcurr_thresh_uA = 600,
5739 .othc_hyst_prediv_us = 7800,
5740 .othc_period_clkdiv_us = 62500,
5741 .othc_hyst_clk_us = 121000,
5742 .othc_period_clk_us = 312500,
5743 .othc_wakeup = 1,
5744};
5745
5746static struct othc_hsed_config hsed_config_1 = {
5747 .hsed_bias_config = &hsed_bias_config,
5748 /*
5749 * The detection delay and switch reporting delay are
5750 * required to encounter a hardware bug (spurious switch
5751 * interrupts on slow insertion/removal of the headset).
5752 * This will introduce a delay in reporting the accessory
5753 * insertion and removal to the userspace.
5754 */
5755 .detection_delay_ms = 1500,
5756 /* Switch info */
5757 .switch_debounce_ms = 1500,
5758 .othc_support_n_switch = false,
5759 .switch_config = &switch_config,
5760 .ir_gpio = -1,
5761 /* Accessory info */
5762 .accessories_support = true,
5763 .accessories = othc_accessories,
5764 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5765};
5766
5767static struct othc_regulator_config othc_reg = {
5768 .regulator = "8058_l5",
5769 .max_uV = 2850000,
5770 .min_uV = 2850000,
5771};
5772
5773/* MIC_BIAS0 is configured as normal MIC BIAS */
5774static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5775 .micbias_select = OTHC_MICBIAS_0,
5776 .micbias_capability = OTHC_MICBIAS,
5777 .micbias_enable = OTHC_SIGNAL_OFF,
5778 .micbias_regulator = &othc_reg,
5779};
5780
5781/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5782static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5783 .micbias_select = OTHC_MICBIAS_1,
5784 .micbias_capability = OTHC_MICBIAS_HSED,
5785 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5786 .micbias_regulator = &othc_reg,
5787 .hsed_config = &hsed_config_1,
5788 .hsed_name = "8660_handset",
5789};
5790
5791/* MIC_BIAS2 is configured as normal MIC BIAS */
5792static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5793 .micbias_select = OTHC_MICBIAS_2,
5794 .micbias_capability = OTHC_MICBIAS,
5795 .micbias_enable = OTHC_SIGNAL_OFF,
5796 .micbias_regulator = &othc_reg,
5797};
5798
5799static struct resource resources_othc_0[] = {
5800 {
5801 .name = "othc_base",
5802 .start = PM8058_OTHC_CNTR_BASE0,
5803 .end = PM8058_OTHC_CNTR_BASE0,
5804 .flags = IORESOURCE_IO,
5805 },
5806};
5807
5808static struct resource resources_othc_1[] = {
5809 {
5810 .start = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5811 .end = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5812 .flags = IORESOURCE_IRQ,
5813 },
5814 {
5815 .start = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5816 .end = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5817 .flags = IORESOURCE_IRQ,
5818 },
5819 {
5820 .name = "othc_base",
5821 .start = PM8058_OTHC_CNTR_BASE1,
5822 .end = PM8058_OTHC_CNTR_BASE1,
5823 .flags = IORESOURCE_IO,
5824 },
5825};
5826
5827static struct resource resources_othc_2[] = {
5828 {
5829 .name = "othc_base",
5830 .start = PM8058_OTHC_CNTR_BASE2,
5831 .end = PM8058_OTHC_CNTR_BASE2,
5832 .flags = IORESOURCE_IO,
5833 },
5834};
5835
5836static void __init msm8x60_init_pm8058_othc(void)
5837{
5838 int i;
5839
5840 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5841 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5842 machine_is_msm8x60_fusn_ffa()) {
5843 /* 3-switch headset supported only by V2 FFA and FLUID */
5844 hsed_config_1.accessories_adc_support = true,
5845 /* ADC based accessory detection works only on V2 and FLUID */
5846 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5847 hsed_config_1.othc_support_n_switch = true;
5848 }
5849
5850 /* IR GPIO is absent on FLUID */
5851 if (machine_is_msm8x60_fluid())
5852 hsed_config_1.ir_gpio = -1;
5853
5854 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5855 if (machine_is_msm8x60_fluid()) {
5856 switch (othc_accessories[i].accessory) {
5857 case OTHC_ANC_HEADPHONE:
5858 case OTHC_ANC_HEADSET:
5859 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5860 break;
5861 case OTHC_MICROPHONE:
5862 othc_accessories[i].enabled = false;
5863 break;
5864 case OTHC_SVIDEO_OUT:
5865 othc_accessories[i].enabled = true;
5866 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5867 break;
5868 }
5869 }
5870 }
5871}
5872#endif
5873
5874static struct resource resources_pm8058_charger[] = {
5875 { .name = "CHGVAL",
5876 .start = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5877 .end = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5878 .flags = IORESOURCE_IRQ,
5879 },
5880 { .name = "CHGINVAL",
5881 .start = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5882 .end = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5883 .flags = IORESOURCE_IRQ,
5884 },
5885 {
5886 .name = "CHGILIM",
5887 .start = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5888 .end = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5889 .flags = IORESOURCE_IRQ,
5890 },
5891 {
5892 .name = "VCP",
5893 .start = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5894 .end = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5895 .flags = IORESOURCE_IRQ,
5896 },
5897 {
5898 .name = "ATC_DONE",
5899 .start = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5900 .end = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5901 .flags = IORESOURCE_IRQ,
5902 },
5903 {
5904 .name = "ATCFAIL",
5905 .start = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5906 .end = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5907 .flags = IORESOURCE_IRQ,
5908 },
5909 {
5910 .name = "AUTO_CHGDONE",
5911 .start = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5912 .end = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5913 .flags = IORESOURCE_IRQ,
5914 },
5915 {
5916 .name = "AUTO_CHGFAIL",
5917 .start = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5918 .end = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5919 .flags = IORESOURCE_IRQ,
5920 },
5921 {
5922 .name = "CHGSTATE",
5923 .start = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5924 .end = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5925 .flags = IORESOURCE_IRQ,
5926 },
5927 {
5928 .name = "FASTCHG",
5929 .start = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5930 .end = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5931 .flags = IORESOURCE_IRQ,
5932 },
5933 {
5934 .name = "CHG_END",
5935 .start = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5936 .end = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5937 .flags = IORESOURCE_IRQ,
5938 },
5939 {
5940 .name = "BATTTEMP",
5941 .start = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5942 .end = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5943 .flags = IORESOURCE_IRQ,
5944 },
5945 {
5946 .name = "CHGHOT",
5947 .start = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5948 .end = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5949 .flags = IORESOURCE_IRQ,
5950 },
5951 {
5952 .name = "CHGTLIMIT",
5953 .start = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5954 .end = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5955 .flags = IORESOURCE_IRQ,
5956 },
5957 {
5958 .name = "CHG_GONE",
5959 .start = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5960 .end = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5961 .flags = IORESOURCE_IRQ,
5962 },
5963 {
5964 .name = "VCPMAJOR",
5965 .start = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5966 .end = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5967 .flags = IORESOURCE_IRQ,
5968 },
5969 {
5970 .name = "VBATDET",
5971 .start = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5972 .end = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5973 .flags = IORESOURCE_IRQ,
5974 },
5975 {
5976 .name = "BATFET",
5977 .start = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5978 .end = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5979 .flags = IORESOURCE_IRQ,
5980 },
5981 {
5982 .name = "BATT_REPLACE",
5983 .start = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5984 .end = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5985 .flags = IORESOURCE_IRQ,
5986 },
5987 {
5988 .name = "BATTCONNECT",
5989 .start = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5990 .end = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5991 .flags = IORESOURCE_IRQ,
5992 },
5993 {
5994 .name = "VBATDET_LOW",
5995 .start = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
5996 .end = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
5997 .flags = IORESOURCE_IRQ,
5998 },
5999};
6000
6001static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
6002{
6003 struct pm8058_gpio pwm_gpio_config = {
6004 .direction = PM_GPIO_DIR_OUT,
6005 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
6006 .output_value = 0,
6007 .pull = PM_GPIO_PULL_NO,
6008 .vin_sel = PM_GPIO_VIN_VPH,
6009 .out_strength = PM_GPIO_STRENGTH_HIGH,
6010 .function = PM_GPIO_FUNC_2,
6011 };
6012
6013 int rc = -EINVAL;
6014 int id, mode, max_mA;
6015
6016 id = mode = max_mA = 0;
6017 switch (ch) {
6018 case 0:
6019 case 1:
6020 case 2:
6021 if (on) {
6022 id = 24 + ch;
6023 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
6024 if (rc)
6025 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
6026 __func__, id, rc);
6027 }
6028 break;
6029
6030 case 6:
6031 id = PM_PWM_LED_FLASH;
6032 mode = PM_PWM_CONF_PWM1;
6033 max_mA = 300;
6034 break;
6035
6036 case 7:
6037 id = PM_PWM_LED_FLASH1;
6038 mode = PM_PWM_CONF_PWM1;
6039 max_mA = 300;
6040 break;
6041
6042 default:
6043 break;
6044 }
6045
6046 if (ch >= 6 && ch <= 7) {
6047 if (!on) {
6048 mode = PM_PWM_CONF_NONE;
6049 max_mA = 0;
6050 }
6051 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6052 if (rc)
6053 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6054 __func__, ch, rc);
6055 }
6056 return rc;
6057
6058}
6059
6060static struct pm8058_pwm_pdata pm8058_pwm_data = {
6061 .config = pm8058_pwm_config,
6062};
6063
6064#define PM8058_GPIO_INT 88
6065
6066static struct pm8058_gpio_platform_data pm8058_gpio_data = {
6067 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6068 .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
6069 .init = pm8058_gpios_init,
6070};
6071
6072static struct pm8058_gpio_platform_data pm8058_mpp_data = {
6073 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
6074 .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
6075};
6076
6077static struct resource resources_rtc[] = {
6078 {
6079 .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6080 .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6081 .flags = IORESOURCE_IRQ,
6082 },
6083 {
6084 .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6085 .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6086 .flags = IORESOURCE_IRQ,
6087 },
6088};
6089
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306090static struct pm8058_rtc_platform_data pm8058_rtc_pdata = {
6091 .rtc_alarm_powerup = false,
6092};
6093
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006094static struct pmic8058_led pmic8058_flash_leds[] = {
6095 [0] = {
6096 .name = "camera:flash0",
6097 .max_brightness = 15,
6098 .id = PMIC8058_ID_FLASH_LED_0,
6099 },
6100 [1] = {
6101 .name = "camera:flash1",
6102 .max_brightness = 15,
6103 .id = PMIC8058_ID_FLASH_LED_1,
6104 },
6105};
6106
6107static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6108 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6109 .leds = pmic8058_flash_leds,
6110};
6111
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006112static struct pmic8058_led pmic8058_dragon_leds[] = {
6113 [0] = {
6114 /* RED */
6115 .name = "led_drv0",
6116 .max_brightness = 15,
6117 .id = PMIC8058_ID_LED_0,
6118 },/* 300 mA flash led0 drv sink */
6119 [1] = {
6120 /* Yellow */
6121 .name = "led_drv1",
6122 .max_brightness = 15,
6123 .id = PMIC8058_ID_LED_1,
6124 },/* 300 mA flash led0 drv sink */
6125 [2] = {
6126 /* Green */
6127 .name = "led_drv2",
6128 .max_brightness = 15,
6129 .id = PMIC8058_ID_LED_2,
6130 },/* 300 mA flash led0 drv sink */
6131 [3] = {
6132 .name = "led_psensor",
6133 .max_brightness = 15,
6134 .id = PMIC8058_ID_LED_KB_LIGHT,
6135 },/* 300 mA flash led0 drv sink */
6136};
6137
6138static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6139 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6140 .leds = pmic8058_dragon_leds,
6141};
6142
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006143static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6144 [0] = {
6145 .name = "led:drv0",
6146 .max_brightness = 15,
6147 .id = PMIC8058_ID_FLASH_LED_0,
6148 },/* 300 mA flash led0 drv sink */
6149 [1] = {
6150 .name = "led:drv1",
6151 .max_brightness = 15,
6152 .id = PMIC8058_ID_FLASH_LED_1,
6153 },/* 300 mA flash led1 sink */
6154 [2] = {
6155 .name = "led:drv2",
6156 .max_brightness = 20,
6157 .id = PMIC8058_ID_LED_0,
6158 },/* 40 mA led0 sink */
6159 [3] = {
6160 .name = "keypad:drv",
6161 .max_brightness = 15,
6162 .id = PMIC8058_ID_LED_KB_LIGHT,
6163 },/* 300 mA keypad drv sink */
6164};
6165
6166static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6167 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6168 .leds = pmic8058_fluid_flash_leds,
6169};
6170
6171static struct resource resources_temp_alarm[] = {
6172 {
6173 .start = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6174 .end = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6175 .flags = IORESOURCE_IRQ,
6176 },
6177};
6178
6179static struct resource resources_pm8058_misc[] = {
6180 {
6181 .start = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6182 .end = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6183 .flags = IORESOURCE_IRQ,
6184 },
6185};
6186
6187static struct resource resources_pm8058_batt_alarm[] = {
6188 {
6189 .start = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6190 .end = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6191 .flags = IORESOURCE_IRQ,
6192 },
6193};
6194
6195#define PM8058_SUBDEV_KPD 0
6196#define PM8058_SUBDEV_LED 1
6197#define PM8058_SUBDEV_VIB 2
6198
6199static struct mfd_cell pm8058_subdevs[] = {
6200 {
6201 .name = "pm8058-keypad",
6202 .id = -1,
6203 .num_resources = ARRAY_SIZE(resources_keypad),
6204 .resources = resources_keypad,
6205 },
6206 { .name = "pm8058-led",
6207 .id = -1,
6208 },
6209 {
6210 .name = "pm8058-vib",
6211 .id = -1,
6212 },
6213 { .name = "pm8058-gpio",
6214 .id = -1,
6215 .platform_data = &pm8058_gpio_data,
6216 .pdata_size = sizeof(pm8058_gpio_data),
6217 },
6218 { .name = "pm8058-mpp",
6219 .id = -1,
6220 .platform_data = &pm8058_mpp_data,
6221 .pdata_size = sizeof(pm8058_mpp_data),
6222 },
6223 { .name = "pm8058-pwrkey",
6224 .id = -1,
6225 .resources = resources_pwrkey,
6226 .num_resources = ARRAY_SIZE(resources_pwrkey),
6227 .platform_data = &pwrkey_pdata,
6228 .pdata_size = sizeof(pwrkey_pdata),
6229 },
6230 {
6231 .name = "pm8058-pwm",
6232 .id = -1,
6233 .platform_data = &pm8058_pwm_data,
6234 .pdata_size = sizeof(pm8058_pwm_data),
6235 },
6236#ifdef CONFIG_SENSORS_MSM_ADC
6237 {
6238 .name = "pm8058-xoadc",
6239 .id = -1,
6240 .num_resources = ARRAY_SIZE(resources_adc),
6241 .resources = resources_adc,
6242 .platform_data = &xoadc_pdata,
6243 .pdata_size = sizeof(xoadc_pdata),
6244 },
6245#endif
6246#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
6247 {
6248 .name = "pm8058-othc",
6249 .id = 0,
6250 .platform_data = &othc_config_pdata_0,
6251 .pdata_size = sizeof(othc_config_pdata_0),
6252 .num_resources = ARRAY_SIZE(resources_othc_0),
6253 .resources = resources_othc_0,
6254 },
6255 {
6256 /* OTHC1 module has headset/switch dection */
6257 .name = "pm8058-othc",
6258 .id = 1,
6259 .num_resources = ARRAY_SIZE(resources_othc_1),
6260 .resources = resources_othc_1,
6261 .platform_data = &othc_config_pdata_1,
6262 .pdata_size = sizeof(othc_config_pdata_1),
6263 },
6264 {
6265 .name = "pm8058-othc",
6266 .id = 2,
6267 .platform_data = &othc_config_pdata_2,
6268 .pdata_size = sizeof(othc_config_pdata_2),
6269 .num_resources = ARRAY_SIZE(resources_othc_2),
6270 .resources = resources_othc_2,
6271 },
6272#endif
6273 {
6274 .name = "pm8058-rtc",
6275 .id = -1,
6276 .num_resources = ARRAY_SIZE(resources_rtc),
6277 .resources = resources_rtc,
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306278 .platform_data = &pm8058_rtc_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006279 },
6280 {
6281 .name = "pm8058-tm",
6282 .id = -1,
6283 .num_resources = ARRAY_SIZE(resources_temp_alarm),
6284 .resources = resources_temp_alarm,
6285 },
6286 { .name = "pm8058-upl",
6287 .id = -1,
6288 },
6289 {
6290 .name = "pm8058-misc",
6291 .id = -1,
6292 .num_resources = ARRAY_SIZE(resources_pm8058_misc),
6293 .resources = resources_pm8058_misc,
6294 },
6295 { .name = "pm8058-batt-alarm",
6296 .id = -1,
6297 .num_resources = ARRAY_SIZE(resources_pm8058_batt_alarm),
6298 .resources = resources_pm8058_batt_alarm,
6299 },
6300};
6301
Terence Hampson90508a92011-08-09 10:40:08 -04006302static struct pmic8058_charger_data pmic8058_charger_dragon = {
6303 .max_source_current = 1800,
6304 .charger_type = CHG_TYPE_AC,
6305};
6306
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006307static struct mfd_cell pm8058_charger_sub_dev = {
6308 .name = "pm8058-charger",
6309 .id = -1,
6310 .num_resources = ARRAY_SIZE(resources_pm8058_charger),
6311 .resources = resources_pm8058_charger,
6312};
6313
6314static struct pm8058_platform_data pm8058_platform_data = {
6315 .irq_base = PM8058_IRQ_BASE,
6316
6317 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
6318 .sub_devices = pm8058_subdevs,
6319 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6320};
6321
6322static struct i2c_board_info pm8058_boardinfo[] __initdata = {
6323 {
6324 I2C_BOARD_INFO("pm8058-core", 0x55),
6325 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
6326 .platform_data = &pm8058_platform_data,
6327 },
6328};
6329#endif /* CONFIG_PMIC8058 */
6330
6331#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6332 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6333#define TDISC_I2C_SLAVE_ADDR 0x67
6334#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6335#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6336
6337static const char *vregs_tdisc_name[] = {
6338 "8058_l5",
6339 "8058_s3",
6340};
6341
6342static const int vregs_tdisc_val[] = {
6343 2850000,/* uV */
6344 1800000,
6345};
6346static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6347
6348static int tdisc_shinetsu_setup(void)
6349{
6350 int rc, i;
6351
6352 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6353 if (rc) {
6354 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6355 __func__);
6356 return rc;
6357 }
6358
6359 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6360 if (rc) {
6361 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6362 __func__);
6363 goto fail_gpio_oe;
6364 }
6365
6366 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6367 if (rc) {
6368 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6369 __func__);
6370 gpio_free(GPIO_JOYSTICK_EN);
6371 goto fail_gpio_oe;
6372 }
6373
6374 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6375 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6376 if (IS_ERR(vregs_tdisc[i])) {
6377 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6378 __func__, vregs_tdisc_name[i],
6379 PTR_ERR(vregs_tdisc[i]));
6380 rc = PTR_ERR(vregs_tdisc[i]);
6381 goto vreg_get_fail;
6382 }
6383
6384 rc = regulator_set_voltage(vregs_tdisc[i],
6385 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6386 if (rc) {
6387 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6388 __func__, rc);
6389 goto vreg_set_voltage_fail;
6390 }
6391 }
6392
6393 return rc;
6394vreg_set_voltage_fail:
6395 i++;
6396vreg_get_fail:
6397 while (i)
6398 regulator_put(vregs_tdisc[--i]);
6399fail_gpio_oe:
6400 gpio_free(PMIC_GPIO_TDISC);
6401 return rc;
6402}
6403
6404static void tdisc_shinetsu_release(void)
6405{
6406 int i;
6407
6408 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6409 regulator_put(vregs_tdisc[i]);
6410
6411 gpio_free(PMIC_GPIO_TDISC);
6412 gpio_free(GPIO_JOYSTICK_EN);
6413}
6414
6415static int tdisc_shinetsu_enable(void)
6416{
6417 int i, rc = -EINVAL;
6418
6419 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6420 rc = regulator_enable(vregs_tdisc[i]);
6421 if (rc < 0) {
6422 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6423 __func__, vregs_tdisc_name[i], rc);
6424 goto vreg_fail;
6425 }
6426 }
6427
6428 /* Enable the OE (output enable) gpio */
6429 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6430 /* voltage and gpio stabilization delay */
6431 msleep(50);
6432
6433 return 0;
6434vreg_fail:
6435 while (i)
6436 regulator_disable(vregs_tdisc[--i]);
6437 return rc;
6438}
6439
6440static int tdisc_shinetsu_disable(void)
6441{
6442 int i, rc;
6443
6444 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6445 rc = regulator_disable(vregs_tdisc[i]);
6446 if (rc < 0) {
6447 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6448 __func__, vregs_tdisc_name[i], rc);
6449 goto tdisc_reg_fail;
6450 }
6451 }
6452
6453 /* Disable the OE (output enable) gpio */
6454 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6455
6456 return 0;
6457
6458tdisc_reg_fail:
6459 while (i)
6460 regulator_enable(vregs_tdisc[--i]);
6461 return rc;
6462}
6463
6464static struct tdisc_abs_values tdisc_abs = {
6465 .x_max = 32,
6466 .y_max = 32,
6467 .x_min = -32,
6468 .y_min = -32,
6469 .pressure_max = 32,
6470 .pressure_min = 0,
6471};
6472
6473static struct tdisc_platform_data tdisc_data = {
6474 .tdisc_setup = tdisc_shinetsu_setup,
6475 .tdisc_release = tdisc_shinetsu_release,
6476 .tdisc_enable = tdisc_shinetsu_enable,
6477 .tdisc_disable = tdisc_shinetsu_disable,
6478 .tdisc_wakeup = 0,
6479 .tdisc_gpio = PMIC_GPIO_TDISC,
6480 .tdisc_report_keys = true,
6481 .tdisc_report_relative = true,
6482 .tdisc_report_absolute = false,
6483 .tdisc_report_wheel = false,
6484 .tdisc_reverse_x = false,
6485 .tdisc_reverse_y = true,
6486 .tdisc_abs = &tdisc_abs,
6487};
6488
6489static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6490 {
6491 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6492 .irq = TDISC_INT,
6493 .platform_data = &tdisc_data,
6494 },
6495};
6496#endif
6497
6498#define PM_GPIO_CDC_RST_N 20
6499#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6500
6501static struct regulator *vreg_timpani_1;
6502static struct regulator *vreg_timpani_2;
6503
6504static unsigned int msm_timpani_setup_power(void)
6505{
6506 int rc;
6507
6508 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6509 if (IS_ERR(vreg_timpani_1)) {
6510 pr_err("%s: Unable to get 8058_l0\n", __func__);
6511 return -ENODEV;
6512 }
6513
6514 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6515 if (IS_ERR(vreg_timpani_2)) {
6516 pr_err("%s: Unable to get 8058_s3\n", __func__);
6517 regulator_put(vreg_timpani_1);
6518 return -ENODEV;
6519 }
6520
6521 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6522 if (rc) {
6523 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6524 goto fail;
6525 }
6526
6527 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6528 if (rc) {
6529 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6530 goto fail;
6531 }
6532
6533 rc = regulator_enable(vreg_timpani_1);
6534 if (rc) {
6535 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6536 goto fail;
6537 }
6538
6539 /* The settings for LDO0 should be set such that
6540 * it doesn't require to reset the timpani. */
6541 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6542 if (rc < 0) {
6543 pr_err("Timpani regulator optimum mode setting failed\n");
6544 goto fail;
6545 }
6546
6547 rc = regulator_enable(vreg_timpani_2);
6548 if (rc) {
6549 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6550 regulator_disable(vreg_timpani_1);
6551 goto fail;
6552 }
6553
6554 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6555 if (rc) {
6556 pr_err("%s: GPIO Request %d failed\n", __func__,
6557 GPIO_CDC_RST_N);
6558 regulator_disable(vreg_timpani_1);
6559 regulator_disable(vreg_timpani_2);
6560 goto fail;
6561 } else {
6562 gpio_direction_output(GPIO_CDC_RST_N, 1);
6563 usleep_range(1000, 1050);
6564 gpio_direction_output(GPIO_CDC_RST_N, 0);
6565 usleep_range(1000, 1050);
6566 gpio_direction_output(GPIO_CDC_RST_N, 1);
6567 gpio_free(GPIO_CDC_RST_N);
6568 }
6569 return rc;
6570
6571fail:
6572 regulator_put(vreg_timpani_1);
6573 regulator_put(vreg_timpani_2);
6574 return rc;
6575}
6576
6577static void msm_timpani_shutdown_power(void)
6578{
6579 int rc;
6580
6581 rc = regulator_disable(vreg_timpani_1);
6582 if (rc)
6583 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6584
6585 regulator_put(vreg_timpani_1);
6586
6587 rc = regulator_disable(vreg_timpani_2);
6588 if (rc)
6589 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6590
6591 regulator_put(vreg_timpani_2);
6592}
6593
6594/* Power analog function of codec */
6595static struct regulator *vreg_timpani_cdc_apwr;
6596static int msm_timpani_codec_power(int vreg_on)
6597{
6598 int rc = 0;
6599
6600 if (!vreg_timpani_cdc_apwr) {
6601
6602 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6603
6604 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6605 pr_err("%s: vreg_get failed (%ld)\n",
6606 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6607 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6608 return rc;
6609 }
6610 }
6611
6612 if (vreg_on) {
6613
6614 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6615 2200000, 2200000);
6616 if (rc) {
6617 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6618 __func__);
6619 goto vreg_fail;
6620 }
6621
6622 rc = regulator_enable(vreg_timpani_cdc_apwr);
6623 if (rc) {
6624 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6625 goto vreg_fail;
6626 }
6627 } else {
6628 rc = regulator_disable(vreg_timpani_cdc_apwr);
6629 if (rc) {
6630 pr_err("%s: vreg_disable failed %d\n",
6631 __func__, rc);
6632 goto vreg_fail;
6633 }
6634 }
6635
6636 return 0;
6637
6638vreg_fail:
6639 regulator_put(vreg_timpani_cdc_apwr);
6640 vreg_timpani_cdc_apwr = NULL;
6641 return rc;
6642}
6643
6644static struct marimba_codec_platform_data timpani_codec_pdata = {
6645 .marimba_codec_power = msm_timpani_codec_power,
6646};
6647
6648#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6649#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6650
6651static struct marimba_platform_data timpani_pdata = {
6652 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6653 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6654 .marimba_setup = msm_timpani_setup_power,
6655 .marimba_shutdown = msm_timpani_shutdown_power,
6656 .codec = &timpani_codec_pdata,
6657 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6658};
6659
6660#define TIMPANI_I2C_SLAVE_ADDR 0xD
6661
6662static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6663 {
6664 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6665 .platform_data = &timpani_pdata,
6666 },
6667};
6668
6669#ifdef CONFIG_PMIC8901
6670
6671#define PM8901_GPIO_INT 91
6672
6673static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6674 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6675 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6676};
6677
6678static struct resource pm8901_temp_alarm[] = {
6679 {
6680 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6681 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6682 .flags = IORESOURCE_IRQ,
6683 },
6684 {
6685 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6686 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6687 .flags = IORESOURCE_IRQ,
6688 },
6689};
6690
6691/*
6692 * Consumer specific regulator names:
6693 * regulator name consumer dev_name
6694 */
6695static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6696 REGULATOR_SUPPLY("8901_mpp0", NULL),
6697};
6698static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6699 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6700};
6701static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6702 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6703};
6704
6705#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6706 _always_on, _active_high) \
6707 [PM8901_VREG_ID_##_id] = { \
6708 .init_data = { \
6709 .constraints = { \
6710 .valid_modes_mask = _modes, \
6711 .valid_ops_mask = _ops, \
6712 .min_uV = _min_uV, \
6713 .max_uV = _max_uV, \
6714 .input_uV = _min_uV, \
6715 .apply_uV = _apply_uV, \
6716 .always_on = _always_on, \
6717 }, \
6718 .consumer_supplies = vreg_consumers_8901_##_id, \
6719 .num_consumer_supplies = \
6720 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6721 }, \
6722 .active_high = _active_high, \
6723 }
6724
6725#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6726 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6727 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6728
6729#define PM8901_VREG_INIT_VS(_id) \
6730 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6731 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6732
6733static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6734 PM8901_VREG_INIT_MPP(MPP0, 1),
6735
6736 PM8901_VREG_INIT_VS(USB_OTG),
6737 PM8901_VREG_INIT_VS(HDMI_MVS),
6738};
6739
6740#define PM8901_VREG(_id) { \
6741 .name = "pm8901-regulator", \
6742 .id = _id, \
6743 .platform_data = &pm8901_vreg_init_pdata[_id], \
6744 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6745}
6746
6747static struct mfd_cell pm8901_subdevs[] = {
6748 { .name = "pm8901-mpp",
6749 .id = -1,
6750 .platform_data = &pm8901_mpp_data,
6751 .pdata_size = sizeof(pm8901_mpp_data),
6752 },
6753 { .name = "pm8901-tm",
6754 .id = -1,
6755 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6756 .resources = pm8901_temp_alarm,
6757 },
6758 PM8901_VREG(PM8901_VREG_ID_MPP0),
6759 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6760 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6761};
6762
6763static struct pm8901_platform_data pm8901_platform_data = {
6764 .irq_base = PM8901_IRQ_BASE,
6765 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6766 .sub_devices = pm8901_subdevs,
6767 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6768};
6769
6770static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6771 {
6772 I2C_BOARD_INFO("pm8901-core", 0x55),
6773 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6774 .platform_data = &pm8901_platform_data,
6775 },
6776};
6777
6778#endif /* CONFIG_PMIC8901 */
6779
6780#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6781 || defined(CONFIG_GPIO_SX150X_MODULE))
6782
6783static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006784static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006785
6786struct bahama_config_register{
6787 u8 reg;
6788 u8 value;
6789 u8 mask;
6790};
6791
6792enum version{
6793 VER_1_0,
6794 VER_2_0,
6795 VER_UNSUPPORTED = 0xFF
6796};
6797
6798static u8 read_bahama_ver(void)
6799{
6800 int rc;
6801 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6802 u8 bahama_version;
6803
6804 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6805 if (rc < 0) {
6806 printk(KERN_ERR
6807 "%s: version read failed: %d\n",
6808 __func__, rc);
6809 return VER_UNSUPPORTED;
6810 } else {
6811 printk(KERN_INFO
6812 "%s: version read got: 0x%x\n",
6813 __func__, bahama_version);
6814 }
6815
6816 switch (bahama_version) {
6817 case 0x08: /* varient of bahama v1 */
6818 case 0x10:
6819 case 0x00:
6820 return VER_1_0;
6821 case 0x09: /* variant of bahama v2 */
6822 return VER_2_0;
6823 default:
6824 return VER_UNSUPPORTED;
6825 }
6826}
6827
6828static unsigned int msm_bahama_setup_power(void)
6829{
6830 int rc = 0;
6831 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006832
6833 if (machine_is_msm8x60_dragon())
6834 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6835
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006836 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6837
6838 if (IS_ERR(vreg_bahama)) {
6839 rc = PTR_ERR(vreg_bahama);
6840 pr_err("%s: regulator_get %s = %d\n", __func__,
6841 msm_bahama_regulator, rc);
6842 }
6843
6844 if (!rc)
6845 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6846 else {
6847 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6848 msm_bahama_regulator, rc);
6849 goto unget;
6850 }
6851
6852 if (!rc)
6853 rc = regulator_enable(vreg_bahama);
6854 else {
6855 pr_err("%s: regulator_enable %s = %d\n", __func__,
6856 msm_bahama_regulator, rc);
6857 goto unget;
6858 }
6859
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006860 if (!rc) {
6861 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6862 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006863 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006864 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006865 goto unenable;
6866 }
6867
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006868 if (!rc) {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006869 gpio_direction_output(msm_bahama_sys_rst, 0);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006870 usleep_range(1000, 1050);
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006871 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006872 usleep_range(1000, 1050);
6873 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006874 pr_err("%s: gpio_direction_output %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006875 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006876 goto unrequest;
6877 }
6878
6879 return rc;
6880
6881unrequest:
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006882 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006883unenable:
6884 regulator_disable(vreg_bahama);
6885unget:
6886 regulator_put(vreg_bahama);
6887 return rc;
6888};
6889static unsigned int msm_bahama_shutdown_power(int value)
6890
6891
6892{
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006893 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006894
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006895 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006896
6897 regulator_disable(vreg_bahama);
6898
6899 regulator_put(vreg_bahama);
6900
6901 return 0;
6902};
6903
6904static unsigned int msm_bahama_core_config(int type)
6905{
6906 int rc = 0;
6907
6908 if (type == BAHAMA_ID) {
6909
6910 int i;
6911 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6912
6913 const struct bahama_config_register v20_init[] = {
6914 /* reg, value, mask */
6915 { 0xF4, 0x84, 0xFF }, /* AREG */
6916 { 0xF0, 0x04, 0xFF } /* DREG */
6917 };
6918
6919 if (read_bahama_ver() == VER_2_0) {
6920 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6921 u8 value = v20_init[i].value;
6922 rc = marimba_write_bit_mask(&config,
6923 v20_init[i].reg,
6924 &value,
6925 sizeof(v20_init[i].value),
6926 v20_init[i].mask);
6927 if (rc < 0) {
6928 printk(KERN_ERR
6929 "%s: reg %d write failed: %d\n",
6930 __func__, v20_init[i].reg, rc);
6931 return rc;
6932 }
6933 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6934 " mask 0x%02x\n",
6935 __func__, v20_init[i].reg,
6936 v20_init[i].value, v20_init[i].mask);
6937 }
6938 }
6939 }
6940 printk(KERN_INFO "core type: %d\n", type);
6941
6942 return rc;
6943}
6944
6945static struct regulator *fm_regulator_s3;
6946static struct msm_xo_voter *fm_clock;
6947
6948static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6949{
6950 int rc = 0;
6951 struct pm8058_gpio cfg = {
6952 .direction = PM_GPIO_DIR_IN,
6953 .pull = PM_GPIO_PULL_NO,
6954 .vin_sel = PM_GPIO_VIN_S3,
6955 .function = PM_GPIO_FUNC_NORMAL,
6956 .inv_int_pol = 0,
6957 };
6958
6959 if (!fm_regulator_s3) {
6960 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
6961 if (IS_ERR(fm_regulator_s3)) {
6962 rc = PTR_ERR(fm_regulator_s3);
6963 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
6964 __func__, rc);
6965 goto out;
6966 }
6967 }
6968
6969
6970 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
6971 if (rc < 0) {
6972 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
6973 __func__, rc);
6974 goto fm_fail_put;
6975 }
6976
6977 rc = regulator_enable(fm_regulator_s3);
6978 if (rc < 0) {
6979 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
6980 __func__, rc);
6981 goto fm_fail_put;
6982 }
6983
6984 /*Vote for XO clock*/
6985 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
6986
6987 if (IS_ERR(fm_clock)) {
6988 rc = PTR_ERR(fm_clock);
6989 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
6990 __func__, rc);
6991 goto fm_fail_switch;
6992 }
6993
6994 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
6995 if (rc < 0) {
6996 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
6997 __func__, rc);
6998 goto fm_fail_vote;
6999 }
7000
7001 /*GPIO 18 on PMIC is FM_IRQ*/
7002 rc = pm8058_gpio_config(FM_GPIO, &cfg);
7003 if (rc) {
7004 printk(KERN_ERR "%s: return val of pm8058_gpio_config: %d\n",
7005 __func__, rc);
7006 goto fm_fail_clock;
7007 }
7008 goto out;
7009
7010fm_fail_clock:
7011 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7012fm_fail_vote:
7013 msm_xo_put(fm_clock);
7014fm_fail_switch:
7015 regulator_disable(fm_regulator_s3);
7016fm_fail_put:
7017 regulator_put(fm_regulator_s3);
7018out:
7019 return rc;
7020};
7021
7022static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
7023{
7024 int rc = 0;
7025 if (fm_regulator_s3 != NULL) {
7026 rc = regulator_disable(fm_regulator_s3);
7027 if (rc < 0) {
7028 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
7029 __func__, rc);
7030 }
7031 regulator_put(fm_regulator_s3);
7032 fm_regulator_s3 = NULL;
7033 }
7034 printk(KERN_ERR "%s: Voting off for XO", __func__);
7035
7036 if (fm_clock != NULL) {
7037 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7038 if (rc < 0) {
7039 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
7040 __func__, rc);
7041 }
7042 msm_xo_put(fm_clock);
7043 }
7044 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
7045}
7046
7047/* Slave id address for FM/CDC/QMEMBIST
7048 * Values can be programmed using Marimba slave id 0
7049 * should there be a conflict with other I2C devices
7050 * */
7051#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
7052#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
7053
7054static struct marimba_fm_platform_data marimba_fm_pdata = {
7055 .fm_setup = fm_radio_setup,
7056 .fm_shutdown = fm_radio_shutdown,
7057 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
7058 .is_fm_soc_i2s_master = false,
7059 .config_i2s_gpio = NULL,
7060};
7061
7062/*
7063Just initializing the BAHAMA related slave
7064*/
7065static struct marimba_platform_data marimba_pdata = {
7066 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
7067 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
7068 .bahama_setup = msm_bahama_setup_power,
7069 .bahama_shutdown = msm_bahama_shutdown_power,
7070 .bahama_core_config = msm_bahama_core_config,
7071 .fm = &marimba_fm_pdata,
7072 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
7073};
7074
7075
7076static struct i2c_board_info msm_marimba_board_info[] = {
7077 {
7078 I2C_BOARD_INFO("marimba", 0xc),
7079 .platform_data = &marimba_pdata,
7080 }
7081};
7082#endif /* CONFIG_MAIMBA_CORE */
7083
7084#ifdef CONFIG_I2C
7085#define I2C_SURF 1
7086#define I2C_FFA (1 << 1)
7087#define I2C_RUMI (1 << 2)
7088#define I2C_SIM (1 << 3)
7089#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007090#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007091
7092struct i2c_registry {
7093 u8 machs;
7094 int bus;
7095 struct i2c_board_info *info;
7096 int len;
7097};
7098
7099static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
7100#ifdef CONFIG_PMIC8058
7101 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007102 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007103 MSM_SSBI1_I2C_BUS_ID,
7104 pm8058_boardinfo,
7105 ARRAY_SIZE(pm8058_boardinfo),
7106 },
7107#endif
7108#ifdef CONFIG_PMIC8901
7109 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007110 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007111 MSM_SSBI2_I2C_BUS_ID,
7112 pm8901_boardinfo,
7113 ARRAY_SIZE(pm8901_boardinfo),
7114 },
7115#endif
7116#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7117 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007118 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007119 MSM_GSBI8_QUP_I2C_BUS_ID,
7120 core_expander_i2c_info,
7121 ARRAY_SIZE(core_expander_i2c_info),
7122 },
7123 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007124 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007125 MSM_GSBI8_QUP_I2C_BUS_ID,
7126 docking_expander_i2c_info,
7127 ARRAY_SIZE(docking_expander_i2c_info),
7128 },
7129 {
7130 I2C_SURF,
7131 MSM_GSBI8_QUP_I2C_BUS_ID,
7132 surf_expanders_i2c_info,
7133 ARRAY_SIZE(surf_expanders_i2c_info),
7134 },
7135 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007136 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007137 MSM_GSBI3_QUP_I2C_BUS_ID,
7138 fha_expanders_i2c_info,
7139 ARRAY_SIZE(fha_expanders_i2c_info),
7140 },
7141 {
7142 I2C_FLUID,
7143 MSM_GSBI3_QUP_I2C_BUS_ID,
7144 fluid_expanders_i2c_info,
7145 ARRAY_SIZE(fluid_expanders_i2c_info),
7146 },
7147 {
7148 I2C_FLUID,
7149 MSM_GSBI8_QUP_I2C_BUS_ID,
7150 fluid_core_expander_i2c_info,
7151 ARRAY_SIZE(fluid_core_expander_i2c_info),
7152 },
7153#endif
7154#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
7155 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
7156 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007157 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007158 MSM_GSBI3_QUP_I2C_BUS_ID,
7159 msm_i2c_gsbi3_tdisc_info,
7160 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7161 },
7162#endif
7163 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007164 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007165 MSM_GSBI3_QUP_I2C_BUS_ID,
7166 cy8ctmg200_board_info,
7167 ARRAY_SIZE(cy8ctmg200_board_info),
7168 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007169 {
7170 I2C_DRAGON,
7171 MSM_GSBI3_QUP_I2C_BUS_ID,
7172 cy8ctma340_dragon_board_info,
7173 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7174 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007175#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7176 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7177 {
7178 I2C_FLUID,
7179 MSM_GSBI3_QUP_I2C_BUS_ID,
7180 cyttsp_fluid_info,
7181 ARRAY_SIZE(cyttsp_fluid_info),
7182 },
7183 {
7184 I2C_FFA | I2C_SURF,
7185 MSM_GSBI3_QUP_I2C_BUS_ID,
7186 cyttsp_ffa_info,
7187 ARRAY_SIZE(cyttsp_ffa_info),
7188 },
7189#endif
7190#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007191 {
7192 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007193 MSM_GSBI4_QUP_I2C_BUS_ID,
7194 msm_camera_boardinfo,
7195 ARRAY_SIZE(msm_camera_boardinfo),
7196 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007197 {
7198 I2C_DRAGON,
7199 MSM_GSBI4_QUP_I2C_BUS_ID,
7200 msm_camera_dragon_boardinfo,
7201 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7202 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007203#endif
7204 {
7205 I2C_SURF | I2C_FFA | I2C_FLUID,
7206 MSM_GSBI7_QUP_I2C_BUS_ID,
7207 msm_i2c_gsbi7_timpani_info,
7208 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7209 },
7210#if defined(CONFIG_MARIMBA_CORE)
7211 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007212 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007213 MSM_GSBI7_QUP_I2C_BUS_ID,
7214 msm_marimba_board_info,
7215 ARRAY_SIZE(msm_marimba_board_info),
7216 },
7217#endif /* CONFIG_MARIMBA_CORE */
7218#ifdef CONFIG_ISL9519_CHARGER
7219 {
7220 I2C_SURF | I2C_FFA,
7221 MSM_GSBI8_QUP_I2C_BUS_ID,
7222 isl_charger_i2c_info,
7223 ARRAY_SIZE(isl_charger_i2c_info),
7224 },
7225#endif
7226#if defined(CONFIG_HAPTIC_ISA1200) || \
7227 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7228 {
7229 I2C_FLUID,
7230 MSM_GSBI8_QUP_I2C_BUS_ID,
7231 msm_isa1200_board_info,
7232 ARRAY_SIZE(msm_isa1200_board_info),
7233 },
7234#endif
7235#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7236 {
7237 I2C_FLUID,
7238 MSM_GSBI8_QUP_I2C_BUS_ID,
7239 smb137b_charger_i2c_info,
7240 ARRAY_SIZE(smb137b_charger_i2c_info),
7241 },
7242#endif
7243#if defined(CONFIG_BATTERY_BQ27520) || \
7244 defined(CONFIG_BATTERY_BQ27520_MODULE)
7245 {
7246 I2C_FLUID,
7247 MSM_GSBI8_QUP_I2C_BUS_ID,
7248 msm_bq27520_board_info,
7249 ARRAY_SIZE(msm_bq27520_board_info),
7250 },
7251#endif
7252};
7253#endif /* CONFIG_I2C */
7254
7255static void fixup_i2c_configs(void)
7256{
7257#ifdef CONFIG_I2C
7258#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7259 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7260 sx150x_data[SX150X_CORE].irq_summary =
7261 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007262 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7263 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007264 sx150x_data[SX150X_CORE].irq_summary =
7265 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7266 else if (machine_is_msm8x60_fluid())
7267 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7268 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7269#endif
7270 /*
7271 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7272 * implies that the regulator connected to MPP0 is enabled when
7273 * MPP0 is low.
7274 */
7275 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7276 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7277 else
7278 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7279#endif
7280}
7281
7282static void register_i2c_devices(void)
7283{
7284#ifdef CONFIG_I2C
7285 u8 mach_mask = 0;
7286 int i;
7287
7288 /* Build the matching 'supported_machs' bitmask */
7289 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7290 mach_mask = I2C_SURF;
7291 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7292 mach_mask = I2C_FFA;
7293 else if (machine_is_msm8x60_rumi3())
7294 mach_mask = I2C_RUMI;
7295 else if (machine_is_msm8x60_sim())
7296 mach_mask = I2C_SIM;
7297 else if (machine_is_msm8x60_fluid())
7298 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007299 else if (machine_is_msm8x60_dragon())
7300 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007301 else
7302 pr_err("unmatched machine ID in register_i2c_devices\n");
7303
7304 /* Run the array and install devices as appropriate */
7305 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7306 if (msm8x60_i2c_devices[i].machs & mach_mask)
7307 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7308 msm8x60_i2c_devices[i].info,
7309 msm8x60_i2c_devices[i].len);
7310 }
7311#endif
7312}
7313
7314static void __init msm8x60_init_uart12dm(void)
7315{
7316#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7317 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7318 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7319
7320 if (!fpga_mem)
7321 pr_err("%s(): Error getting memory\n", __func__);
7322
7323 /* Advanced mode */
7324 writew(0xFFFF, fpga_mem + 0x15C);
7325 /* FPGA_UART_SEL */
7326 writew(0, fpga_mem + 0x172);
7327 /* FPGA_GPIO_CONFIG_117 */
7328 writew(1, fpga_mem + 0xEA);
7329 /* FPGA_GPIO_CONFIG_118 */
7330 writew(1, fpga_mem + 0xEC);
7331 mb();
7332 iounmap(fpga_mem);
7333#endif
7334}
7335
7336#define MSM_GSBI9_PHYS 0x19900000
7337#define GSBI_DUAL_MODE_CODE 0x60
7338
7339static void __init msm8x60_init_buses(void)
7340{
7341#ifdef CONFIG_I2C_QUP
7342 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7343 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7344 writel_relaxed(0x6 << 4, gsbi_mem);
7345 /* Ensure protocol code is written before proceeding further */
7346 mb();
7347 iounmap(gsbi_mem);
7348
7349 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7350 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7351 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7352 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7353
7354#ifdef CONFIG_MSM_GSBI9_UART
7355 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7356 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7357 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7358 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7359 iounmap(gsbi_mem);
7360 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7361 }
7362#endif
7363 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7364 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7365#endif
7366#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7367 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7368#endif
7369#ifdef CONFIG_I2C_SSBI
7370 msm_device_ssbi1.dev.platform_data = &msm_ssbi1_pdata;
7371 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7372 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7373#endif
7374
7375 if (machine_is_msm8x60_fluid()) {
7376#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7377 (defined(CONFIG_SMB137B_CHARGER) || \
7378 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7379 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7380#endif
7381#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7382 msm_gsbi10_qup_spi_device.dev.platform_data =
7383 &msm_gsbi10_qup_spi_pdata;
7384#endif
7385 }
7386
7387#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7388 /*
7389 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7390 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7391 * and ID notifications are available only on V2 surf and FFA
7392 * with a hardware workaround.
7393 */
7394 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7395 (machine_is_msm8x60_surf() ||
7396 (machine_is_msm8x60_ffa() &&
7397 pmic_id_notif_supported)))
7398 msm_otg_pdata.phy_can_powercollapse = 1;
7399 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7400#endif
7401
7402#ifdef CONFIG_USB_GADGET_MSM_72K
7403 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7404#endif
7405
7406#ifdef CONFIG_SERIAL_MSM_HS
7407 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7408 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7409#endif
7410#ifdef CONFIG_MSM_GSBI9_UART
7411 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7412 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7413 if (IS_ERR(msm_device_uart_gsbi9))
7414 pr_err("%s(): Failed to create uart gsbi9 device\n",
7415 __func__);
7416 }
7417#endif
7418
7419#ifdef CONFIG_MSM_BUS_SCALING
7420
7421 /* RPM calls are only enabled on V2 */
7422 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7423 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7424 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7425 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7426 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7427 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7428 }
7429
7430 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7431 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7432 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7433 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7434 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7435#endif
7436}
7437
7438static void __init msm8x60_map_io(void)
7439{
7440 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7441 msm_map_msm8x60_io();
7442}
7443
7444/*
7445 * Most segments of the EBI2 bus are disabled by default.
7446 */
7447static void __init msm8x60_init_ebi2(void)
7448{
7449 uint32_t ebi2_cfg;
7450 void *ebi2_cfg_ptr;
7451
7452 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7453 if (ebi2_cfg_ptr != 0) {
7454 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7455
7456 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007457 machine_is_msm8x60_fluid() ||
7458 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007459 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7460 else if (machine_is_msm8x60_sim())
7461 ebi2_cfg |= (1 << 4); /* CS2 */
7462 else if (machine_is_msm8x60_rumi3())
7463 ebi2_cfg |= (1 << 5); /* CS3 */
7464
7465 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7466 iounmap(ebi2_cfg_ptr);
7467 }
7468
7469 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007470 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007471 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7472 if (ebi2_cfg_ptr != 0) {
7473 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7474 writel_relaxed(0UL, ebi2_cfg_ptr);
7475
7476 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7477 * LAN9221 Ethernet controller reads and writes.
7478 * The lowest 4 bits are the read delay, the next
7479 * 4 are the write delay. */
7480 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7481#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7482 /*
7483 * RECOVERY=5, HOLD_WR=1
7484 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7485 * WAIT_WR=1, WAIT_RD=2
7486 */
7487 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7488 /*
7489 * HOLD_RD=1
7490 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7491 */
7492 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7493#else
7494 /* EBI2 CS3 muxed address/data,
7495 * two cyc addr enable */
7496 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7497
7498#endif
7499 iounmap(ebi2_cfg_ptr);
7500 }
7501 }
7502}
7503
7504static void __init msm8x60_configure_smc91x(void)
7505{
7506 if (machine_is_msm8x60_sim()) {
7507
7508 smc91x_resources[0].start = 0x1b800300;
7509 smc91x_resources[0].end = 0x1b8003ff;
7510
7511 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7512 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7513
7514 } else if (machine_is_msm8x60_rumi3()) {
7515
7516 smc91x_resources[0].start = 0x1d000300;
7517 smc91x_resources[0].end = 0x1d0003ff;
7518
7519 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7520 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7521 }
7522}
7523
7524static void __init msm8x60_init_tlmm(void)
7525{
7526 if (machine_is_msm8x60_rumi3())
7527 msm_gpio_install_direct_irq(0, 0, 1);
7528}
7529
7530#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7531 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7532 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7533 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7534 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7535
7536/* 8x60 is having 5 SDCC controllers */
7537#define MAX_SDCC_CONTROLLER 5
7538
7539struct msm_sdcc_gpio {
7540 /* maximum 10 GPIOs per SDCC controller */
7541 s16 no;
7542 /* name of this GPIO */
7543 const char *name;
7544 bool always_on;
7545 bool is_enabled;
7546};
7547
7548#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7549static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7550 {159, "sdc1_dat_0"},
7551 {160, "sdc1_dat_1"},
7552 {161, "sdc1_dat_2"},
7553 {162, "sdc1_dat_3"},
7554#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7555 {163, "sdc1_dat_4"},
7556 {164, "sdc1_dat_5"},
7557 {165, "sdc1_dat_6"},
7558 {166, "sdc1_dat_7"},
7559#endif
7560 {167, "sdc1_clk"},
7561 {168, "sdc1_cmd"}
7562};
7563#endif
7564
7565#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7566static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7567 {143, "sdc2_dat_0"},
7568 {144, "sdc2_dat_1", 1},
7569 {145, "sdc2_dat_2"},
7570 {146, "sdc2_dat_3"},
7571#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7572 {147, "sdc2_dat_4"},
7573 {148, "sdc2_dat_5"},
7574 {149, "sdc2_dat_6"},
7575 {150, "sdc2_dat_7"},
7576#endif
7577 {151, "sdc2_cmd"},
7578 {152, "sdc2_clk", 1}
7579};
7580#endif
7581
7582#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7583static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7584 {95, "sdc5_cmd"},
7585 {96, "sdc5_dat_3"},
7586 {97, "sdc5_clk", 1},
7587 {98, "sdc5_dat_2"},
7588 {99, "sdc5_dat_1", 1},
7589 {100, "sdc5_dat_0"}
7590};
7591#endif
7592
7593struct msm_sdcc_pad_pull_cfg {
7594 enum msm_tlmm_pull_tgt pull;
7595 u32 pull_val;
7596};
7597
7598struct msm_sdcc_pad_drv_cfg {
7599 enum msm_tlmm_hdrive_tgt drv;
7600 u32 drv_val;
7601};
7602
7603#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7604static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7605 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7606 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7607 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7608};
7609
7610static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7611 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7612 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7613};
7614
7615static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7616 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7617 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7618 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7619};
7620
7621static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7622 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7623 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7624};
7625#endif
7626
7627#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7628static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7629 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7630 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7631 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7632};
7633
7634static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7635 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7636 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7637};
7638
7639static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7640 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7641 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7642 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7643};
7644
7645static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7646 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7647 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7648};
7649#endif
7650
7651struct msm_sdcc_pin_cfg {
7652 /*
7653 * = 1 if controller pins are using gpios
7654 * = 0 if controller has dedicated MSM pins
7655 */
7656 u8 is_gpio;
7657 u8 cfg_sts;
7658 u8 gpio_data_size;
7659 struct msm_sdcc_gpio *gpio_data;
7660 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7661 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7662 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7663 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7664 u8 pad_drv_data_size;
7665 u8 pad_pull_data_size;
7666 u8 sdio_lpm_gpio_cfg;
7667};
7668
7669
7670static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7671#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7672 [0] = {
7673 .is_gpio = 1,
7674 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7675 .gpio_data = sdc1_gpio_cfg
7676 },
7677#endif
7678#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7679 [1] = {
7680 .is_gpio = 1,
7681 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7682 .gpio_data = sdc2_gpio_cfg
7683 },
7684#endif
7685#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7686 [2] = {
7687 .is_gpio = 0,
7688 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7689 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7690 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7691 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7692 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7693 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7694 },
7695#endif
7696#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7697 [3] = {
7698 .is_gpio = 0,
7699 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7700 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7701 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7702 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7703 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7704 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7705 },
7706#endif
7707#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7708 [4] = {
7709 .is_gpio = 1,
7710 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7711 .gpio_data = sdc5_gpio_cfg
7712 }
7713#endif
7714};
7715
7716static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7717{
7718 int rc = 0;
7719 struct msm_sdcc_pin_cfg *curr;
7720 int n;
7721
7722 curr = &sdcc_pin_cfg_data[dev_id - 1];
7723 if (!curr->gpio_data)
7724 goto out;
7725
7726 for (n = 0; n < curr->gpio_data_size; n++) {
7727 if (enable) {
7728
7729 if (curr->gpio_data[n].always_on &&
7730 curr->gpio_data[n].is_enabled)
7731 continue;
7732 pr_debug("%s: enable: %s\n", __func__,
7733 curr->gpio_data[n].name);
7734 rc = gpio_request(curr->gpio_data[n].no,
7735 curr->gpio_data[n].name);
7736 if (rc) {
7737 pr_err("%s: gpio_request(%d, %s)"
7738 "failed", __func__,
7739 curr->gpio_data[n].no,
7740 curr->gpio_data[n].name);
7741 goto free_gpios;
7742 }
7743 /* set direction as output for all GPIOs */
7744 rc = gpio_direction_output(
7745 curr->gpio_data[n].no, 1);
7746 if (rc) {
7747 pr_err("%s: gpio_direction_output"
7748 "(%d, 1) failed\n", __func__,
7749 curr->gpio_data[n].no);
7750 goto free_gpios;
7751 }
7752 curr->gpio_data[n].is_enabled = 1;
7753 } else {
7754 /*
7755 * now free this GPIO which will put GPIO
7756 * in low power mode and will also put GPIO
7757 * in input mode
7758 */
7759 if (curr->gpio_data[n].always_on)
7760 continue;
7761 pr_debug("%s: disable: %s\n", __func__,
7762 curr->gpio_data[n].name);
7763 gpio_free(curr->gpio_data[n].no);
7764 curr->gpio_data[n].is_enabled = 0;
7765 }
7766 }
7767 curr->cfg_sts = enable;
7768 goto out;
7769
7770free_gpios:
7771 for (; n >= 0; n--)
7772 gpio_free(curr->gpio_data[n].no);
7773out:
7774 return rc;
7775}
7776
7777static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7778{
7779 int rc = 0;
7780 struct msm_sdcc_pin_cfg *curr;
7781 int n;
7782
7783 curr = &sdcc_pin_cfg_data[dev_id - 1];
7784 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7785 goto out;
7786
7787 if (enable) {
7788 /*
7789 * set up the normal driver strength and
7790 * pull config for pads
7791 */
7792 for (n = 0; n < curr->pad_drv_data_size; n++) {
7793 if (curr->sdio_lpm_gpio_cfg) {
7794 if (curr->pad_drv_on_data[n].drv ==
7795 TLMM_HDRV_SDC4_DATA)
7796 continue;
7797 }
7798 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7799 curr->pad_drv_on_data[n].drv_val);
7800 }
7801 for (n = 0; n < curr->pad_pull_data_size; n++) {
7802 if (curr->sdio_lpm_gpio_cfg) {
7803 if (curr->pad_pull_on_data[n].pull ==
7804 TLMM_PULL_SDC4_DATA)
7805 continue;
7806 }
7807 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7808 curr->pad_pull_on_data[n].pull_val);
7809 }
7810 } else {
7811 /* set the low power config for pads */
7812 for (n = 0; n < curr->pad_drv_data_size; n++) {
7813 if (curr->sdio_lpm_gpio_cfg) {
7814 if (curr->pad_drv_off_data[n].drv ==
7815 TLMM_HDRV_SDC4_DATA)
7816 continue;
7817 }
7818 msm_tlmm_set_hdrive(
7819 curr->pad_drv_off_data[n].drv,
7820 curr->pad_drv_off_data[n].drv_val);
7821 }
7822 for (n = 0; n < curr->pad_pull_data_size; n++) {
7823 if (curr->sdio_lpm_gpio_cfg) {
7824 if (curr->pad_pull_off_data[n].pull ==
7825 TLMM_PULL_SDC4_DATA)
7826 continue;
7827 }
7828 msm_tlmm_set_pull(
7829 curr->pad_pull_off_data[n].pull,
7830 curr->pad_pull_off_data[n].pull_val);
7831 }
7832 }
7833 curr->cfg_sts = enable;
7834out:
7835 return rc;
7836}
7837
7838struct sdcc_reg {
7839 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7840 const char *reg_name;
7841 /*
7842 * is set voltage supported for this regulator?
7843 * 0 = not supported, 1 = supported
7844 */
7845 unsigned char set_voltage_sup;
7846 /* voltage level to be set */
7847 unsigned int level;
7848 /* VDD/VCC/VCCQ voltage regulator handle */
7849 struct regulator *reg;
7850 /* is this regulator enabled? */
7851 bool enabled;
7852 /* is this regulator needs to be always on? */
7853 bool always_on;
7854 /* is operating power mode setting required for this regulator? */
7855 bool op_pwr_mode_sup;
7856 /* Load values for low power and high power mode */
7857 unsigned int lpm_uA;
7858 unsigned int hpm_uA;
7859};
7860/* all SDCC controllers requires VDD/VCC voltage */
7861static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7862/* only SDCC1 requires VCCQ voltage */
7863static struct sdcc_reg sdcc_vccq_reg_data[1];
7864/* all SDCC controllers may require voting for VDD PAD voltage */
7865static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7866
7867struct sdcc_reg_data {
7868 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7869 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7870 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7871 unsigned char sts; /* regulator enable/disable status */
7872};
7873/* msm8x60 have 5 SDCC controllers */
7874static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7875
7876static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7877{
7878 int rc = 0;
7879
7880 /* Get the regulator handle */
7881 vreg->reg = regulator_get(NULL, vreg->reg_name);
7882 if (IS_ERR(vreg->reg)) {
7883 rc = PTR_ERR(vreg->reg);
7884 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7885 __func__, vreg->reg_name, rc);
7886 goto out;
7887 }
7888
7889 /* Set the voltage level if required */
7890 if (vreg->set_voltage_sup) {
7891 rc = regulator_set_voltage(vreg->reg, vreg->level,
7892 vreg->level);
7893 if (rc) {
7894 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7895 __func__, vreg->reg_name, rc);
7896 goto vreg_put;
7897 }
7898 }
7899 goto out;
7900
7901vreg_put:
7902 regulator_put(vreg->reg);
7903out:
7904 return rc;
7905}
7906
7907static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7908{
7909 regulator_put(vreg->reg);
7910}
7911
7912/* this init function should be called only once for each SDCC */
7913static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7914{
7915 int rc = 0;
7916 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7917 struct sdcc_reg_data *curr;
7918
7919 curr = &sdcc_vreg_data[dev_id - 1];
7920 curr_vdd_reg = curr->vdd_data;
7921 curr_vccq_reg = curr->vccq_data;
7922 curr_vddp_reg = curr->vddp_data;
7923
7924 if (init) {
7925 /*
7926 * get the regulator handle from voltage regulator framework
7927 * and then try to set the voltage level for the regulator
7928 */
7929 if (curr_vdd_reg) {
7930 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7931 if (rc)
7932 goto out;
7933 }
7934 if (curr_vccq_reg) {
7935 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
7936 if (rc)
7937 goto vdd_reg_deinit;
7938 }
7939 if (curr_vddp_reg) {
7940 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
7941 if (rc)
7942 goto vccq_reg_deinit;
7943 }
7944 goto out;
7945 } else
7946 /* deregister with all regulators from regulator framework */
7947 goto vddp_reg_deinit;
7948
7949vddp_reg_deinit:
7950 if (curr_vddp_reg)
7951 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
7952vccq_reg_deinit:
7953 if (curr_vccq_reg)
7954 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
7955vdd_reg_deinit:
7956 if (curr_vdd_reg)
7957 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
7958out:
7959 return rc;
7960}
7961
7962static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
7963{
7964 int rc;
7965
7966 if (!vreg->enabled) {
7967 rc = regulator_enable(vreg->reg);
7968 if (rc) {
7969 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
7970 __func__, vreg->reg_name, rc);
7971 goto out;
7972 }
7973 vreg->enabled = 1;
7974 }
7975
7976 /* Put always_on regulator in HPM (high power mode) */
7977 if (vreg->always_on && vreg->op_pwr_mode_sup) {
7978 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
7979 if (rc < 0) {
7980 pr_err("%s: reg=%s: HPM setting failed"
7981 " hpm_uA=%d, rc=%d\n",
7982 __func__, vreg->reg_name,
7983 vreg->hpm_uA, rc);
7984 goto vreg_disable;
7985 }
7986 rc = 0;
7987 }
7988 goto out;
7989
7990vreg_disable:
7991 regulator_disable(vreg->reg);
7992 vreg->enabled = 0;
7993out:
7994 return rc;
7995}
7996
7997static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
7998{
7999 int rc;
8000
8001 /* Never disable always_on regulator */
8002 if (!vreg->always_on) {
8003 rc = regulator_disable(vreg->reg);
8004 if (rc) {
8005 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
8006 __func__, vreg->reg_name, rc);
8007 goto out;
8008 }
8009 vreg->enabled = 0;
8010 }
8011
8012 /* Put always_on regulator in LPM (low power mode) */
8013 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8014 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
8015 if (rc < 0) {
8016 pr_err("%s: reg=%s: LPM setting failed"
8017 " lpm_uA=%d, rc=%d\n",
8018 __func__,
8019 vreg->reg_name,
8020 vreg->lpm_uA, rc);
8021 goto out;
8022 }
8023 rc = 0;
8024 }
8025
8026out:
8027 return rc;
8028}
8029
8030static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
8031{
8032 int rc = 0;
8033 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
8034 struct sdcc_reg_data *curr;
8035
8036 curr = &sdcc_vreg_data[dev_id - 1];
8037 curr_vdd_reg = curr->vdd_data;
8038 curr_vccq_reg = curr->vccq_data;
8039 curr_vddp_reg = curr->vddp_data;
8040
8041 /* check if regulators are initialized or not? */
8042 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
8043 (curr_vccq_reg && !curr_vccq_reg->reg) ||
8044 (curr_vddp_reg && !curr_vddp_reg->reg)) {
8045 /* initialize voltage regulators required for this SDCC */
8046 rc = msm_sdcc_vreg_init(dev_id, 1);
8047 if (rc) {
8048 pr_err("%s: regulator init failed = %d\n",
8049 __func__, rc);
8050 goto out;
8051 }
8052 }
8053
8054 if (curr->sts == enable)
8055 goto out;
8056
8057 if (curr_vdd_reg) {
8058 if (enable)
8059 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
8060 else
8061 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
8062 if (rc)
8063 goto out;
8064 }
8065
8066 if (curr_vccq_reg) {
8067 if (enable)
8068 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
8069 else
8070 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
8071 if (rc)
8072 goto out;
8073 }
8074
8075 if (curr_vddp_reg) {
8076 if (enable)
8077 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
8078 else
8079 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
8080 if (rc)
8081 goto out;
8082 }
8083 curr->sts = enable;
8084
8085out:
8086 return rc;
8087}
8088
8089static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
8090{
8091 u32 rc_pin_cfg = 0;
8092 u32 rc_vreg_cfg = 0;
8093 u32 rc = 0;
8094 struct platform_device *pdev;
8095 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8096
8097 pdev = container_of(dv, struct platform_device, dev);
8098
8099 /* setup gpio/pad */
8100 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8101 if (curr_pin_cfg->cfg_sts == !!vdd)
8102 goto setup_vreg;
8103
8104 if (curr_pin_cfg->is_gpio)
8105 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
8106 else
8107 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
8108
8109setup_vreg:
8110 /* setup voltage regulators */
8111 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
8112
8113 if (rc_pin_cfg || rc_vreg_cfg)
8114 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
8115
8116 return rc;
8117}
8118
8119static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
8120{
8121 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8122 struct platform_device *pdev;
8123
8124 pdev = container_of(dv, struct platform_device, dev);
8125 /* setup gpio/pad */
8126 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8127
8128 if (curr_pin_cfg->cfg_sts == active)
8129 return;
8130
8131 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
8132 if (curr_pin_cfg->is_gpio)
8133 msm_sdcc_setup_gpio(pdev->id, active);
8134 else
8135 msm_sdcc_setup_pad(pdev->id, active);
8136 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8137}
8138
8139static int msm_sdc3_get_wpswitch(struct device *dev)
8140{
8141 struct platform_device *pdev;
8142 int status;
8143 pdev = container_of(dev, struct platform_device, dev);
8144
8145 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8146 if (status) {
8147 pr_err("%s:Failed to request GPIO %d\n",
8148 __func__, GPIO_SDC_WP);
8149 } else {
8150 status = gpio_direction_input(GPIO_SDC_WP);
8151 if (!status) {
8152 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8153 pr_info("%s: WP Status for Slot %d = %d\n",
8154 __func__, pdev->id, status);
8155 }
8156 gpio_free(GPIO_SDC_WP);
8157 }
8158 return status;
8159}
8160
8161#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8162int sdc5_register_status_notify(void (*callback)(int, void *),
8163 void *dev_id)
8164{
8165 sdc5_status_notify_cb = callback;
8166 sdc5_status_notify_cb_devid = dev_id;
8167 return 0;
8168}
8169#endif
8170
8171#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8172int sdc2_register_status_notify(void (*callback)(int, void *),
8173 void *dev_id)
8174{
8175 sdc2_status_notify_cb = callback;
8176 sdc2_status_notify_cb_devid = dev_id;
8177 return 0;
8178}
8179#endif
8180
8181/* Interrupt handler for SDC2 and SDC5 detection
8182 * This function uses dual-edge interrputs settings in order
8183 * to get SDIO detection when the GPIO is rising and SDIO removal
8184 * when the GPIO is falling */
8185static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8186{
8187 int status;
8188
8189 if (!machine_is_msm8x60_fusion() &&
8190 !machine_is_msm8x60_fusn_ffa())
8191 return IRQ_NONE;
8192
8193 status = gpio_get_value(MDM2AP_SYNC);
8194 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8195 __func__, status);
8196
8197#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8198 if (sdc2_status_notify_cb) {
8199 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8200 sdc2_status_notify_cb(status,
8201 sdc2_status_notify_cb_devid);
8202 }
8203#endif
8204
8205#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8206 if (sdc5_status_notify_cb) {
8207 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8208 sdc5_status_notify_cb(status,
8209 sdc5_status_notify_cb_devid);
8210 }
8211#endif
8212 return IRQ_HANDLED;
8213}
8214
8215static int msm8x60_multi_sdio_init(void)
8216{
8217 int ret, irq_num;
8218
8219 if (!machine_is_msm8x60_fusion() &&
8220 !machine_is_msm8x60_fusn_ffa())
8221 return 0;
8222
8223 ret = msm_gpiomux_get(MDM2AP_SYNC);
8224 if (ret) {
8225 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8226 __func__, MDM2AP_SYNC, ret);
8227 return ret;
8228 }
8229
8230 irq_num = gpio_to_irq(MDM2AP_SYNC);
8231
8232 ret = request_irq(irq_num,
8233 msm8x60_multi_sdio_slot_status_irq,
8234 IRQ_TYPE_EDGE_BOTH,
8235 "sdio_multidetection", NULL);
8236
8237 if (ret) {
8238 pr_err("%s:Failed to request irq, ret=%d\n",
8239 __func__, ret);
8240 return ret;
8241 }
8242
8243 return ret;
8244}
8245
8246#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8247#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8248static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8249{
8250 int status;
8251
8252 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8253 , "SD_HW_Detect");
8254 if (status) {
8255 pr_err("%s:Failed to request GPIO %d\n", __func__,
8256 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8257 } else {
8258 status = gpio_direction_input(
8259 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8260 if (!status)
8261 status = !(gpio_get_value_cansleep(
8262 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8263 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8264 }
8265 return (unsigned int) status;
8266}
8267#endif
8268#endif
8269
8270#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8271static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8272{
8273 struct platform_device *pdev;
8274 enum msm_mpm_pin pin;
8275 int ret = 0;
8276
8277 pdev = container_of(dev, struct platform_device, dev);
8278
8279 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8280 if (pdev->id == 4)
8281 pin = MSM_MPM_PIN_SDC4_DAT1;
8282 else
8283 return -EINVAL;
8284
8285 switch (mode) {
8286 case SDC_DAT1_DISABLE:
8287 ret = msm_mpm_enable_pin(pin, 0);
8288 break;
8289 case SDC_DAT1_ENABLE:
8290 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8291 ret = msm_mpm_enable_pin(pin, 1);
8292 break;
8293 case SDC_DAT1_ENWAKE:
8294 ret = msm_mpm_set_pin_wake(pin, 1);
8295 break;
8296 case SDC_DAT1_DISWAKE:
8297 ret = msm_mpm_set_pin_wake(pin, 0);
8298 break;
8299 default:
8300 ret = -EINVAL;
8301 break;
8302 }
8303 return ret;
8304}
8305#endif
8306#endif
8307
8308#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8309static struct mmc_platform_data msm8x60_sdc1_data = {
8310 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8311 .translate_vdd = msm_sdcc_setup_power,
8312#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8313 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8314#else
8315 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8316#endif
8317 .msmsdcc_fmin = 400000,
8318 .msmsdcc_fmid = 24000000,
8319 .msmsdcc_fmax = 48000000,
8320 .nonremovable = 1,
8321 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008322};
8323#endif
8324
8325#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8326static struct mmc_platform_data msm8x60_sdc2_data = {
8327 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8328 .translate_vdd = msm_sdcc_setup_power,
8329 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8330 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8331 .msmsdcc_fmin = 400000,
8332 .msmsdcc_fmid = 24000000,
8333 .msmsdcc_fmax = 48000000,
8334 .nonremovable = 0,
8335 .pclk_src_dfab = 1,
8336 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008337#ifdef CONFIG_MSM_SDIO_AL
8338 .is_sdio_al_client = 1,
8339#endif
8340};
8341#endif
8342
8343#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8344static struct mmc_platform_data msm8x60_sdc3_data = {
8345 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8346 .translate_vdd = msm_sdcc_setup_power,
8347 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8348 .wpswitch = msm_sdc3_get_wpswitch,
8349#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8350 .status = msm8x60_sdcc_slot_status,
8351 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8352 PMIC_GPIO_SDC3_DET - 1),
8353 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8354#endif
8355 .msmsdcc_fmin = 400000,
8356 .msmsdcc_fmid = 24000000,
8357 .msmsdcc_fmax = 48000000,
8358 .nonremovable = 0,
8359 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008360};
8361#endif
8362
8363#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8364static struct mmc_platform_data msm8x60_sdc4_data = {
8365 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8366 .translate_vdd = msm_sdcc_setup_power,
8367 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8368 .msmsdcc_fmin = 400000,
8369 .msmsdcc_fmid = 24000000,
8370 .msmsdcc_fmax = 48000000,
8371 .nonremovable = 0,
8372 .pclk_src_dfab = 1,
8373 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008374};
8375#endif
8376
8377#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8378static struct mmc_platform_data msm8x60_sdc5_data = {
8379 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8380 .translate_vdd = msm_sdcc_setup_power,
8381 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8382 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8383 .msmsdcc_fmin = 400000,
8384 .msmsdcc_fmid = 24000000,
8385 .msmsdcc_fmax = 48000000,
8386 .nonremovable = 0,
8387 .pclk_src_dfab = 1,
8388 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008389#ifdef CONFIG_MSM_SDIO_AL
8390 .is_sdio_al_client = 1,
8391#endif
8392};
8393#endif
8394
8395static void __init msm8x60_init_mmc(void)
8396{
8397#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8398 /* SDCC1 : eMMC card connected */
8399 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8400 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8401 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8402 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308403 sdcc_vreg_data[0].vdd_data->always_on = 1;
8404 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8405 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8406 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008407
8408 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8409 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8410 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8411 sdcc_vreg_data[0].vccq_data->always_on = 1;
8412
8413 msm_add_sdcc(1, &msm8x60_sdc1_data);
8414#endif
8415#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8416 /*
8417 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8418 * and no card is connected on 8660 SURF/FFA/FLUID.
8419 */
8420 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8421 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8422 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8423 sdcc_vreg_data[1].vdd_data->level = 1800000;
8424
8425 sdcc_vreg_data[1].vccq_data = NULL;
8426
8427 if (machine_is_msm8x60_fusion())
8428 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8429 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8430#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8431 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8432 msm_sdcc_setup_gpio(2, 1);
8433#endif
8434 msm_add_sdcc(2, &msm8x60_sdc2_data);
8435 }
8436#endif
8437#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8438 /* SDCC3 : External card slot connected */
8439 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8440 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8441 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8442 sdcc_vreg_data[2].vdd_data->level = 2850000;
8443 sdcc_vreg_data[2].vdd_data->always_on = 1;
8444 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8445 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8446 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8447
8448 sdcc_vreg_data[2].vccq_data = NULL;
8449
8450 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8451 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8452 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8453 sdcc_vreg_data[2].vddp_data->level = 2850000;
8454 sdcc_vreg_data[2].vddp_data->always_on = 1;
8455 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8456 /* Sleep current required is ~300 uA. But min. RPM
8457 * vote can be in terms of mA (min. 1 mA).
8458 * So let's vote for 2 mA during sleep.
8459 */
8460 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8461 /* Max. Active current required is 16 mA */
8462 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8463
8464 if (machine_is_msm8x60_fluid())
8465 msm8x60_sdc3_data.wpswitch = NULL;
8466 msm_add_sdcc(3, &msm8x60_sdc3_data);
8467#endif
8468#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8469 /* SDCC4 : WLAN WCN1314 chip is connected */
8470 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8471 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8472 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8473 sdcc_vreg_data[3].vdd_data->level = 1800000;
8474
8475 sdcc_vreg_data[3].vccq_data = NULL;
8476
8477 msm_add_sdcc(4, &msm8x60_sdc4_data);
8478#endif
8479#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8480 /*
8481 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8482 * and no card is connected on 8660 SURF/FFA/FLUID.
8483 */
8484 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8485 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8486 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8487 sdcc_vreg_data[4].vdd_data->level = 1800000;
8488
8489 sdcc_vreg_data[4].vccq_data = NULL;
8490
8491 if (machine_is_msm8x60_fusion())
8492 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8493 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8494#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8495 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8496 msm_sdcc_setup_gpio(5, 1);
8497#endif
8498 msm_add_sdcc(5, &msm8x60_sdc5_data);
8499 }
8500#endif
8501}
8502
8503#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8504static inline void display_common_power(int on) {}
8505#else
8506
8507#define _GET_REGULATOR(var, name) do { \
8508 if (var == NULL) { \
8509 var = regulator_get(NULL, name); \
8510 if (IS_ERR(var)) { \
8511 pr_err("'%s' regulator not found, rc=%ld\n", \
8512 name, PTR_ERR(var)); \
8513 var = NULL; \
8514 } \
8515 } \
8516} while (0)
8517
8518static int dsub_regulator(int on)
8519{
8520 static struct regulator *dsub_reg;
8521 static struct regulator *mpp0_reg;
8522 static int dsub_reg_enabled;
8523 int rc = 0;
8524
8525 _GET_REGULATOR(dsub_reg, "8901_l3");
8526 if (IS_ERR(dsub_reg)) {
8527 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8528 __func__, PTR_ERR(dsub_reg));
8529 return PTR_ERR(dsub_reg);
8530 }
8531
8532 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8533 if (IS_ERR(mpp0_reg)) {
8534 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8535 __func__, PTR_ERR(mpp0_reg));
8536 return PTR_ERR(mpp0_reg);
8537 }
8538
8539 if (on && !dsub_reg_enabled) {
8540 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8541 if (rc) {
8542 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8543 " err=%d", __func__, rc);
8544 goto dsub_regulator_err;
8545 }
8546 rc = regulator_enable(dsub_reg);
8547 if (rc) {
8548 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8549 " err=%d", __func__, rc);
8550 goto dsub_regulator_err;
8551 }
8552 rc = regulator_enable(mpp0_reg);
8553 if (rc) {
8554 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8555 " err=%d", __func__, rc);
8556 goto dsub_regulator_err;
8557 }
8558 dsub_reg_enabled = 1;
8559 } else if (!on && dsub_reg_enabled) {
8560 rc = regulator_disable(dsub_reg);
8561 if (rc)
8562 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8563 " err=%d", __func__, rc);
8564 rc = regulator_disable(mpp0_reg);
8565 if (rc)
8566 printk(KERN_WARNING "%s: failed to disable reg "
8567 "8901_mpp0 err=%d", __func__, rc);
8568 dsub_reg_enabled = 0;
8569 }
8570
8571 return rc;
8572
8573dsub_regulator_err:
8574 regulator_put(mpp0_reg);
8575 regulator_put(dsub_reg);
8576 return rc;
8577}
8578
8579static int display_power_on;
8580static void setup_display_power(void)
8581{
8582 if (display_power_on)
8583 if (lcdc_vga_enabled) {
8584 dsub_regulator(1);
8585 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8586 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8587 if (machine_is_msm8x60_ffa() ||
8588 machine_is_msm8x60_fusn_ffa())
8589 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8590 } else {
8591 dsub_regulator(0);
8592 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8593 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8594 if (machine_is_msm8x60_ffa() ||
8595 machine_is_msm8x60_fusn_ffa())
8596 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8597 }
8598 else {
8599 dsub_regulator(0);
8600 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8601 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8602 /* BACKLIGHT */
8603 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8604 /* LVDS */
8605 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8606 }
8607}
8608
8609#define _GET_REGULATOR(var, name) do { \
8610 if (var == NULL) { \
8611 var = regulator_get(NULL, name); \
8612 if (IS_ERR(var)) { \
8613 pr_err("'%s' regulator not found, rc=%ld\n", \
8614 name, PTR_ERR(var)); \
8615 var = NULL; \
8616 } \
8617 } \
8618} while (0)
8619
8620#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8621
8622static void display_common_power(int on)
8623{
8624 int rc;
8625 static struct regulator *display_reg;
8626
8627 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8628 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8629 if (on) {
8630 /* LVDS */
8631 _GET_REGULATOR(display_reg, "8901_l2");
8632 if (!display_reg)
8633 return;
8634 rc = regulator_set_voltage(display_reg,
8635 3300000, 3300000);
8636 if (rc)
8637 goto out;
8638 rc = regulator_enable(display_reg);
8639 if (rc)
8640 goto out;
8641 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8642 "LVDS_STDN_OUT_N");
8643 if (rc) {
8644 printk(KERN_ERR "%s: LVDS gpio %d request"
8645 "failed\n", __func__,
8646 GPIO_LVDS_SHUTDOWN_N);
8647 goto out2;
8648 }
8649
8650 /* BACKLIGHT */
8651 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8652 if (rc) {
8653 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8654 "failed\n", __func__,
8655 GPIO_BACKLIGHT_EN);
8656 goto out3;
8657 }
8658
8659 if (machine_is_msm8x60_ffa() ||
8660 machine_is_msm8x60_fusn_ffa()) {
8661 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8662 "DONGLE_PWR_EN");
8663 if (rc) {
8664 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8665 " %d request failed\n", __func__,
8666 GPIO_DONGLE_PWR_EN);
8667 goto out4;
8668 }
8669 }
8670
8671 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8672 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8673 if (machine_is_msm8x60_ffa() ||
8674 machine_is_msm8x60_fusn_ffa())
8675 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8676 mdelay(20);
8677 display_power_on = 1;
8678 setup_display_power();
8679 } else {
8680 if (display_power_on) {
8681 display_power_on = 0;
8682 setup_display_power();
8683 mdelay(20);
8684 if (machine_is_msm8x60_ffa() ||
8685 machine_is_msm8x60_fusn_ffa())
8686 gpio_free(GPIO_DONGLE_PWR_EN);
8687 goto out4;
8688 }
8689 }
8690 }
8691#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8692 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8693 else if (machine_is_msm8x60_fluid()) {
8694 static struct regulator *fluid_reg;
8695 static struct regulator *fluid_reg2;
8696
8697 if (on) {
8698 _GET_REGULATOR(fluid_reg, "8901_l2");
8699 if (!fluid_reg)
8700 return;
8701 _GET_REGULATOR(fluid_reg2, "8058_s3");
8702 if (!fluid_reg2) {
8703 regulator_put(fluid_reg);
8704 return;
8705 }
8706 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8707 if (rc) {
8708 regulator_put(fluid_reg2);
8709 regulator_put(fluid_reg);
8710 return;
8711 }
8712 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8713 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8714 regulator_enable(fluid_reg);
8715 regulator_enable(fluid_reg2);
8716 msleep(20);
8717 gpio_direction_output(GPIO_RESX_N, 0);
8718 udelay(10);
8719 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8720 display_power_on = 1;
8721 setup_display_power();
8722 } else {
8723 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8724 gpio_free(GPIO_RESX_N);
8725 msleep(20);
8726 regulator_disable(fluid_reg2);
8727 regulator_disable(fluid_reg);
8728 regulator_put(fluid_reg2);
8729 regulator_put(fluid_reg);
8730 display_power_on = 0;
8731 setup_display_power();
8732 fluid_reg = NULL;
8733 fluid_reg2 = NULL;
8734 }
8735 }
8736#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008737#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8738 else if (machine_is_msm8x60_dragon()) {
8739 static struct regulator *dragon_reg;
8740 static struct regulator *dragon_reg2;
8741
8742 if (on) {
8743 _GET_REGULATOR(dragon_reg, "8901_l2");
8744 if (!dragon_reg)
8745 return;
8746 _GET_REGULATOR(dragon_reg2, "8058_l16");
8747 if (!dragon_reg2) {
8748 regulator_put(dragon_reg);
8749 dragon_reg = NULL;
8750 return;
8751 }
8752
8753 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8754 if (rc) {
8755 pr_err("%s: gpio %d request failed with rc=%d\n",
8756 __func__, GPIO_NT35582_BL_EN, rc);
8757 regulator_put(dragon_reg);
8758 regulator_put(dragon_reg2);
8759 dragon_reg = NULL;
8760 dragon_reg2 = NULL;
8761 return;
8762 }
8763
8764 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8765 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8766 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8767 pr_err("%s: config gpio '%d' failed!\n",
8768 __func__, GPIO_NT35582_RESET);
8769 gpio_free(GPIO_NT35582_BL_EN);
8770 regulator_put(dragon_reg);
8771 regulator_put(dragon_reg2);
8772 dragon_reg = NULL;
8773 dragon_reg2 = NULL;
8774 return;
8775 }
8776
8777 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8778 if (rc) {
8779 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8780 __func__, GPIO_NT35582_RESET, rc);
8781 gpio_free(GPIO_NT35582_BL_EN);
8782 regulator_put(dragon_reg);
8783 regulator_put(dragon_reg2);
8784 dragon_reg = NULL;
8785 dragon_reg2 = NULL;
8786 return;
8787 }
8788
8789 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8790 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8791 regulator_enable(dragon_reg);
8792 regulator_enable(dragon_reg2);
8793 msleep(20);
8794
8795 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8796 msleep(20);
8797 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8798 msleep(20);
8799 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8800 msleep(50);
8801
8802 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8803
8804 display_power_on = 1;
8805 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8806 gpio_free(GPIO_NT35582_RESET);
8807 gpio_free(GPIO_NT35582_BL_EN);
8808 regulator_disable(dragon_reg2);
8809 regulator_disable(dragon_reg);
8810 regulator_put(dragon_reg2);
8811 regulator_put(dragon_reg);
8812 display_power_on = 0;
8813 dragon_reg = NULL;
8814 dragon_reg2 = NULL;
8815 }
8816 }
8817#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008818 return;
8819
8820out4:
8821 gpio_free(GPIO_BACKLIGHT_EN);
8822out3:
8823 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8824out2:
8825 regulator_disable(display_reg);
8826out:
8827 regulator_put(display_reg);
8828 display_reg = NULL;
8829}
8830#undef _GET_REGULATOR
8831#endif
8832
8833static int mipi_dsi_panel_power(int on);
8834
8835#define LCDC_NUM_GPIO 28
8836#define LCDC_GPIO_START 0
8837
8838static void lcdc_samsung_panel_power(int on)
8839{
8840 int n, ret = 0;
8841
8842 display_common_power(on);
8843
8844 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8845 if (on) {
8846 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8847 if (unlikely(ret)) {
8848 pr_err("%s not able to get gpio\n", __func__);
8849 break;
8850 }
8851 } else
8852 gpio_free(LCDC_GPIO_START + n);
8853 }
8854
8855 if (ret) {
8856 for (n--; n >= 0; n--)
8857 gpio_free(LCDC_GPIO_START + n);
8858 }
8859
8860 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8861}
8862
8863#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8864#define _GET_REGULATOR(var, name) do { \
8865 var = regulator_get(NULL, name); \
8866 if (IS_ERR(var)) { \
8867 pr_err("'%s' regulator not found, rc=%ld\n", \
8868 name, IS_ERR(var)); \
8869 var = NULL; \
8870 return -ENODEV; \
8871 } \
8872} while (0)
8873
8874static int hdmi_enable_5v(int on)
8875{
8876 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8877 static struct regulator *reg_8901_mpp0; /* External 5V */
8878 static int prev_on;
8879 int rc;
8880
8881 if (on == prev_on)
8882 return 0;
8883
8884 if (!reg_8901_hdmi_mvs)
8885 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8886 if (!reg_8901_mpp0)
8887 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8888
8889 if (on) {
8890 rc = regulator_enable(reg_8901_mpp0);
8891 if (rc) {
8892 pr_err("'%s' regulator enable failed, rc=%d\n",
8893 "reg_8901_mpp0", rc);
8894 return rc;
8895 }
8896 rc = regulator_enable(reg_8901_hdmi_mvs);
8897 if (rc) {
8898 pr_err("'%s' regulator enable failed, rc=%d\n",
8899 "8901_hdmi_mvs", rc);
8900 return rc;
8901 }
8902 pr_info("%s(on): success\n", __func__);
8903 } else {
8904 rc = regulator_disable(reg_8901_hdmi_mvs);
8905 if (rc)
8906 pr_warning("'%s' regulator disable failed, rc=%d\n",
8907 "8901_hdmi_mvs", rc);
8908 rc = regulator_disable(reg_8901_mpp0);
8909 if (rc)
8910 pr_warning("'%s' regulator disable failed, rc=%d\n",
8911 "reg_8901_mpp0", rc);
8912 pr_info("%s(off): success\n", __func__);
8913 }
8914
8915 prev_on = on;
8916
8917 return 0;
8918}
8919
8920static int hdmi_core_power(int on, int show)
8921{
8922 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8923 static int prev_on;
8924 int rc;
8925
8926 if (on == prev_on)
8927 return 0;
8928
8929 if (!reg_8058_l16)
8930 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8931
8932 if (on) {
8933 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8934 if (!rc)
8935 rc = regulator_enable(reg_8058_l16);
8936 if (rc) {
8937 pr_err("'%s' regulator enable failed, rc=%d\n",
8938 "8058_l16", rc);
8939 return rc;
8940 }
8941 rc = gpio_request(170, "HDMI_DDC_CLK");
8942 if (rc) {
8943 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8944 "HDMI_DDC_CLK", 170, rc);
8945 goto error1;
8946 }
8947 rc = gpio_request(171, "HDMI_DDC_DATA");
8948 if (rc) {
8949 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8950 "HDMI_DDC_DATA", 171, rc);
8951 goto error2;
8952 }
8953 rc = gpio_request(172, "HDMI_HPD");
8954 if (rc) {
8955 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8956 "HDMI_HPD", 172, rc);
8957 goto error3;
8958 }
8959 pr_info("%s(on): success\n", __func__);
8960 } else {
8961 gpio_free(170);
8962 gpio_free(171);
8963 gpio_free(172);
8964 rc = regulator_disable(reg_8058_l16);
8965 if (rc)
8966 pr_warning("'%s' regulator disable failed, rc=%d\n",
8967 "8058_l16", rc);
8968 pr_info("%s(off): success\n", __func__);
8969 }
8970
8971 prev_on = on;
8972
8973 return 0;
8974
8975error3:
8976 gpio_free(171);
8977error2:
8978 gpio_free(170);
8979error1:
8980 regulator_disable(reg_8058_l16);
8981 return rc;
8982}
8983
8984static int hdmi_cec_power(int on)
8985{
8986 static struct regulator *reg_8901_l3; /* HDMI_CEC */
8987 static int prev_on;
8988 int rc;
8989
8990 if (on == prev_on)
8991 return 0;
8992
8993 if (!reg_8901_l3)
8994 _GET_REGULATOR(reg_8901_l3, "8901_l3");
8995
8996 if (on) {
8997 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
8998 if (!rc)
8999 rc = regulator_enable(reg_8901_l3);
9000 if (rc) {
9001 pr_err("'%s' regulator enable failed, rc=%d\n",
9002 "8901_l3", rc);
9003 return rc;
9004 }
9005 rc = gpio_request(169, "HDMI_CEC_VAR");
9006 if (rc) {
9007 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9008 "HDMI_CEC_VAR", 169, rc);
9009 goto error;
9010 }
9011 pr_info("%s(on): success\n", __func__);
9012 } else {
9013 gpio_free(169);
9014 rc = regulator_disable(reg_8901_l3);
9015 if (rc)
9016 pr_warning("'%s' regulator disable failed, rc=%d\n",
9017 "8901_l3", rc);
9018 pr_info("%s(off): success\n", __func__);
9019 }
9020
9021 prev_on = on;
9022
9023 return 0;
9024error:
9025 regulator_disable(reg_8901_l3);
9026 return rc;
9027}
9028
9029#undef _GET_REGULATOR
9030
9031#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
9032
9033static int lcdc_panel_power(int on)
9034{
9035 int flag_on = !!on;
9036 static int lcdc_power_save_on;
9037
9038 if (lcdc_power_save_on == flag_on)
9039 return 0;
9040
9041 lcdc_power_save_on = flag_on;
9042
9043 lcdc_samsung_panel_power(on);
9044
9045 return 0;
9046}
9047
9048#ifdef CONFIG_MSM_BUS_SCALING
9049#ifdef CONFIG_FB_MSM_LCDC_DSUB
9050static struct msm_bus_vectors mdp_init_vectors[] = {
9051 /* For now, 0th array entry is reserved.
9052 * Please leave 0 as is and don't use it
9053 */
9054 {
9055 .src = MSM_BUS_MASTER_MDP_PORT0,
9056 .dst = MSM_BUS_SLAVE_SMI,
9057 .ab = 0,
9058 .ib = 0,
9059 },
9060 /* Master and slaves can be from different fabrics */
9061 {
9062 .src = MSM_BUS_MASTER_MDP_PORT0,
9063 .dst = MSM_BUS_SLAVE_EBI_CH0,
9064 .ab = 0,
9065 .ib = 0,
9066 },
9067};
9068
9069static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9070 /* Default case static display/UI/2d/3d if FB SMI */
9071 {
9072 .src = MSM_BUS_MASTER_MDP_PORT0,
9073 .dst = MSM_BUS_SLAVE_SMI,
9074 .ab = 388800000,
9075 .ib = 486000000,
9076 },
9077 /* Master and slaves can be from different fabrics */
9078 {
9079 .src = MSM_BUS_MASTER_MDP_PORT0,
9080 .dst = MSM_BUS_SLAVE_EBI_CH0,
9081 .ab = 0,
9082 .ib = 0,
9083 },
9084};
9085
9086static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9087 /* Default case static display/UI/2d/3d if FB SMI */
9088 {
9089 .src = MSM_BUS_MASTER_MDP_PORT0,
9090 .dst = MSM_BUS_SLAVE_SMI,
9091 .ab = 0,
9092 .ib = 0,
9093 },
9094 /* Master and slaves can be from different fabrics */
9095 {
9096 .src = MSM_BUS_MASTER_MDP_PORT0,
9097 .dst = MSM_BUS_SLAVE_EBI_CH0,
9098 .ab = 388800000,
9099 .ib = 486000000 * 2,
9100 },
9101};
9102static struct msm_bus_vectors mdp_vga_vectors[] = {
9103 /* VGA and less video */
9104 {
9105 .src = MSM_BUS_MASTER_MDP_PORT0,
9106 .dst = MSM_BUS_SLAVE_SMI,
9107 .ab = 458092800,
9108 .ib = 572616000,
9109 },
9110 {
9111 .src = MSM_BUS_MASTER_MDP_PORT0,
9112 .dst = MSM_BUS_SLAVE_EBI_CH0,
9113 .ab = 458092800,
9114 .ib = 572616000 * 2,
9115 },
9116};
9117static struct msm_bus_vectors mdp_720p_vectors[] = {
9118 /* 720p and less video */
9119 {
9120 .src = MSM_BUS_MASTER_MDP_PORT0,
9121 .dst = MSM_BUS_SLAVE_SMI,
9122 .ab = 471744000,
9123 .ib = 589680000,
9124 },
9125 /* Master and slaves can be from different fabrics */
9126 {
9127 .src = MSM_BUS_MASTER_MDP_PORT0,
9128 .dst = MSM_BUS_SLAVE_EBI_CH0,
9129 .ab = 471744000,
9130 .ib = 589680000 * 2,
9131 },
9132};
9133
9134static struct msm_bus_vectors mdp_1080p_vectors[] = {
9135 /* 1080p and less video */
9136 {
9137 .src = MSM_BUS_MASTER_MDP_PORT0,
9138 .dst = MSM_BUS_SLAVE_SMI,
9139 .ab = 575424000,
9140 .ib = 719280000,
9141 },
9142 /* Master and slaves can be from different fabrics */
9143 {
9144 .src = MSM_BUS_MASTER_MDP_PORT0,
9145 .dst = MSM_BUS_SLAVE_EBI_CH0,
9146 .ab = 575424000,
9147 .ib = 719280000 * 2,
9148 },
9149};
9150
9151#else
9152static struct msm_bus_vectors mdp_init_vectors[] = {
9153 /* For now, 0th array entry is reserved.
9154 * Please leave 0 as is and don't use it
9155 */
9156 {
9157 .src = MSM_BUS_MASTER_MDP_PORT0,
9158 .dst = MSM_BUS_SLAVE_SMI,
9159 .ab = 0,
9160 .ib = 0,
9161 },
9162 /* Master and slaves can be from different fabrics */
9163 {
9164 .src = MSM_BUS_MASTER_MDP_PORT0,
9165 .dst = MSM_BUS_SLAVE_EBI_CH0,
9166 .ab = 0,
9167 .ib = 0,
9168 },
9169};
9170
9171static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9172 /* Default case static display/UI/2d/3d if FB SMI */
9173 {
9174 .src = MSM_BUS_MASTER_MDP_PORT0,
9175 .dst = MSM_BUS_SLAVE_SMI,
9176 .ab = 175110000,
9177 .ib = 218887500,
9178 },
9179 /* Master and slaves can be from different fabrics */
9180 {
9181 .src = MSM_BUS_MASTER_MDP_PORT0,
9182 .dst = MSM_BUS_SLAVE_EBI_CH0,
9183 .ab = 0,
9184 .ib = 0,
9185 },
9186};
9187
9188static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9189 /* Default case static display/UI/2d/3d if FB SMI */
9190 {
9191 .src = MSM_BUS_MASTER_MDP_PORT0,
9192 .dst = MSM_BUS_SLAVE_SMI,
9193 .ab = 0,
9194 .ib = 0,
9195 },
9196 /* Master and slaves can be from different fabrics */
9197 {
9198 .src = MSM_BUS_MASTER_MDP_PORT0,
9199 .dst = MSM_BUS_SLAVE_EBI_CH0,
9200 .ab = 216000000,
9201 .ib = 270000000 * 2,
9202 },
9203};
9204static struct msm_bus_vectors mdp_vga_vectors[] = {
9205 /* VGA and less video */
9206 {
9207 .src = MSM_BUS_MASTER_MDP_PORT0,
9208 .dst = MSM_BUS_SLAVE_SMI,
9209 .ab = 216000000,
9210 .ib = 270000000,
9211 },
9212 {
9213 .src = MSM_BUS_MASTER_MDP_PORT0,
9214 .dst = MSM_BUS_SLAVE_EBI_CH0,
9215 .ab = 216000000,
9216 .ib = 270000000 * 2,
9217 },
9218};
9219
9220static struct msm_bus_vectors mdp_720p_vectors[] = {
9221 /* 720p and less video */
9222 {
9223 .src = MSM_BUS_MASTER_MDP_PORT0,
9224 .dst = MSM_BUS_SLAVE_SMI,
9225 .ab = 230400000,
9226 .ib = 288000000,
9227 },
9228 /* Master and slaves can be from different fabrics */
9229 {
9230 .src = MSM_BUS_MASTER_MDP_PORT0,
9231 .dst = MSM_BUS_SLAVE_EBI_CH0,
9232 .ab = 230400000,
9233 .ib = 288000000 * 2,
9234 },
9235};
9236
9237static struct msm_bus_vectors mdp_1080p_vectors[] = {
9238 /* 1080p and less video */
9239 {
9240 .src = MSM_BUS_MASTER_MDP_PORT0,
9241 .dst = MSM_BUS_SLAVE_SMI,
9242 .ab = 334080000,
9243 .ib = 417600000,
9244 },
9245 /* Master and slaves can be from different fabrics */
9246 {
9247 .src = MSM_BUS_MASTER_MDP_PORT0,
9248 .dst = MSM_BUS_SLAVE_EBI_CH0,
9249 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009250 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009251 },
9252};
9253
9254#endif
9255static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9256 {
9257 ARRAY_SIZE(mdp_init_vectors),
9258 mdp_init_vectors,
9259 },
9260 {
9261 ARRAY_SIZE(mdp_sd_smi_vectors),
9262 mdp_sd_smi_vectors,
9263 },
9264 {
9265 ARRAY_SIZE(mdp_sd_ebi_vectors),
9266 mdp_sd_ebi_vectors,
9267 },
9268 {
9269 ARRAY_SIZE(mdp_vga_vectors),
9270 mdp_vga_vectors,
9271 },
9272 {
9273 ARRAY_SIZE(mdp_720p_vectors),
9274 mdp_720p_vectors,
9275 },
9276 {
9277 ARRAY_SIZE(mdp_1080p_vectors),
9278 mdp_1080p_vectors,
9279 },
9280};
9281static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9282 mdp_bus_scale_usecases,
9283 ARRAY_SIZE(mdp_bus_scale_usecases),
9284 .name = "mdp",
9285};
9286
9287#endif
9288#ifdef CONFIG_MSM_BUS_SCALING
9289static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9290 /* For now, 0th array entry is reserved.
9291 * Please leave 0 as is and don't use it
9292 */
9293 {
9294 .src = MSM_BUS_MASTER_MDP_PORT0,
9295 .dst = MSM_BUS_SLAVE_SMI,
9296 .ab = 0,
9297 .ib = 0,
9298 },
9299 /* Master and slaves can be from different fabrics */
9300 {
9301 .src = MSM_BUS_MASTER_MDP_PORT0,
9302 .dst = MSM_BUS_SLAVE_EBI_CH0,
9303 .ab = 0,
9304 .ib = 0,
9305 },
9306};
9307static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9308 /* For now, 0th array entry is reserved.
9309 * Please leave 0 as is and don't use it
9310 */
9311 {
9312 .src = MSM_BUS_MASTER_MDP_PORT0,
9313 .dst = MSM_BUS_SLAVE_SMI,
9314 .ab = 566092800,
9315 .ib = 707616000,
9316 },
9317 /* Master and slaves can be from different fabrics */
9318 {
9319 .src = MSM_BUS_MASTER_MDP_PORT0,
9320 .dst = MSM_BUS_SLAVE_EBI_CH0,
9321 .ab = 566092800,
9322 .ib = 707616000,
9323 },
9324};
9325static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9326 {
9327 ARRAY_SIZE(dtv_bus_init_vectors),
9328 dtv_bus_init_vectors,
9329 },
9330 {
9331 ARRAY_SIZE(dtv_bus_def_vectors),
9332 dtv_bus_def_vectors,
9333 },
9334};
9335static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9336 dtv_bus_scale_usecases,
9337 ARRAY_SIZE(dtv_bus_scale_usecases),
9338 .name = "dtv",
9339};
9340
9341static struct lcdc_platform_data dtv_pdata = {
9342 .bus_scale_table = &dtv_bus_scale_pdata,
9343};
9344#endif
9345
9346
9347static struct lcdc_platform_data lcdc_pdata = {
9348 .lcdc_power_save = lcdc_panel_power,
9349};
9350
9351
9352#define MDP_VSYNC_GPIO 28
9353
9354/*
9355 * MIPI_DSI only use 8058_LDO0 which need always on
9356 * therefore it need to be put at low power mode if
9357 * it was not used instead of turn it off.
9358 */
9359static int mipi_dsi_panel_power(int on)
9360{
9361 int flag_on = !!on;
9362 static int mipi_dsi_power_save_on;
9363 static struct regulator *ldo0;
9364 int rc = 0;
9365
9366 if (mipi_dsi_power_save_on == flag_on)
9367 return 0;
9368
9369 mipi_dsi_power_save_on = flag_on;
9370
9371 if (ldo0 == NULL) { /* init */
9372 ldo0 = regulator_get(NULL, "8058_l0");
9373 if (IS_ERR(ldo0)) {
9374 pr_debug("%s: LDO0 failed\n", __func__);
9375 rc = PTR_ERR(ldo0);
9376 return rc;
9377 }
9378
9379 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9380 if (rc)
9381 goto out;
9382
9383 rc = regulator_enable(ldo0);
9384 if (rc)
9385 goto out;
9386 }
9387
9388 if (on) {
9389 /* set ldo0 to HPM */
9390 rc = regulator_set_optimum_mode(ldo0, 100000);
9391 if (rc < 0)
9392 goto out;
9393 } else {
9394 /* set ldo0 to LPM */
9395 rc = regulator_set_optimum_mode(ldo0, 9000);
9396 if (rc < 0)
9397 goto out;
9398 }
9399
9400 return 0;
9401out:
9402 regulator_disable(ldo0);
9403 regulator_put(ldo0);
9404 ldo0 = NULL;
9405 return rc;
9406}
9407
9408static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9409 .vsync_gpio = MDP_VSYNC_GPIO,
9410 .dsi_power_save = mipi_dsi_panel_power,
9411};
9412
9413#ifdef CONFIG_FB_MSM_TVOUT
9414static struct regulator *reg_8058_l13;
9415
9416static int atv_dac_power(int on)
9417{
9418 int rc = 0;
9419 #define _GET_REGULATOR(var, name) do { \
9420 var = regulator_get(NULL, name); \
9421 if (IS_ERR(var)) { \
9422 pr_info("'%s' regulator not found, rc=%ld\n", \
9423 name, IS_ERR(var)); \
9424 var = NULL; \
9425 return -ENODEV; \
9426 } \
9427 } while (0)
9428
9429 if (!reg_8058_l13)
9430 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9431 #undef _GET_REGULATOR
9432
9433 if (on) {
9434 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9435 if (rc) {
9436 pr_info("%s: '%s' regulator set voltage failed,\
9437 rc=%d\n", __func__, "8058_l13", rc);
9438 return rc;
9439 }
9440
9441 rc = regulator_enable(reg_8058_l13);
9442 if (rc) {
9443 pr_err("%s: '%s' regulator enable failed,\
9444 rc=%d\n", __func__, "8058_l13", rc);
9445 return rc;
9446 }
9447 } else {
9448 rc = regulator_force_disable(reg_8058_l13);
9449 if (rc)
9450 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9451 __func__, "8058_l13", rc);
9452 }
9453 return rc;
9454
9455}
9456#endif
9457
9458#ifdef CONFIG_FB_MSM_MIPI_DSI
9459int mdp_core_clk_rate_table[] = {
9460 85330000,
9461 85330000,
9462 160000000,
9463 200000000,
9464};
9465#else
9466int mdp_core_clk_rate_table[] = {
9467 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009468 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009469 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009470 200000000,
9471};
9472#endif
9473
9474static struct msm_panel_common_pdata mdp_pdata = {
9475 .gpio = MDP_VSYNC_GPIO,
9476 .mdp_core_clk_rate = 59080000,
9477 .mdp_core_clk_table = mdp_core_clk_rate_table,
9478 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9479#ifdef CONFIG_MSM_BUS_SCALING
9480 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9481#endif
9482 .mdp_rev = MDP_REV_41,
9483};
9484
9485#ifdef CONFIG_FB_MSM_TVOUT
9486
9487#ifdef CONFIG_MSM_BUS_SCALING
9488static struct msm_bus_vectors atv_bus_init_vectors[] = {
9489 /* For now, 0th array entry is reserved.
9490 * Please leave 0 as is and don't use it
9491 */
9492 {
9493 .src = MSM_BUS_MASTER_MDP_PORT0,
9494 .dst = MSM_BUS_SLAVE_SMI,
9495 .ab = 0,
9496 .ib = 0,
9497 },
9498 /* Master and slaves can be from different fabrics */
9499 {
9500 .src = MSM_BUS_MASTER_MDP_PORT0,
9501 .dst = MSM_BUS_SLAVE_EBI_CH0,
9502 .ab = 0,
9503 .ib = 0,
9504 },
9505};
9506static struct msm_bus_vectors atv_bus_def_vectors[] = {
9507 /* For now, 0th array entry is reserved.
9508 * Please leave 0 as is and don't use it
9509 */
9510 {
9511 .src = MSM_BUS_MASTER_MDP_PORT0,
9512 .dst = MSM_BUS_SLAVE_SMI,
9513 .ab = 236390400,
9514 .ib = 265939200,
9515 },
9516 /* Master and slaves can be from different fabrics */
9517 {
9518 .src = MSM_BUS_MASTER_MDP_PORT0,
9519 .dst = MSM_BUS_SLAVE_EBI_CH0,
9520 .ab = 236390400,
9521 .ib = 265939200,
9522 },
9523};
9524static struct msm_bus_paths atv_bus_scale_usecases[] = {
9525 {
9526 ARRAY_SIZE(atv_bus_init_vectors),
9527 atv_bus_init_vectors,
9528 },
9529 {
9530 ARRAY_SIZE(atv_bus_def_vectors),
9531 atv_bus_def_vectors,
9532 },
9533};
9534static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9535 atv_bus_scale_usecases,
9536 ARRAY_SIZE(atv_bus_scale_usecases),
9537 .name = "atv",
9538};
9539#endif
9540
9541static struct tvenc_platform_data atv_pdata = {
9542 .poll = 0,
9543 .pm_vid_en = atv_dac_power,
9544#ifdef CONFIG_MSM_BUS_SCALING
9545 .bus_scale_table = &atv_bus_scale_pdata,
9546#endif
9547};
9548#endif
9549
9550static void __init msm_fb_add_devices(void)
9551{
9552#ifdef CONFIG_FB_MSM_LCDC_DSUB
9553 mdp_pdata.mdp_core_clk_table = NULL;
9554 mdp_pdata.num_mdp_clk = 0;
9555 mdp_pdata.mdp_core_clk_rate = 200000000;
9556#endif
9557 if (machine_is_msm8x60_rumi3())
9558 msm_fb_register_device("mdp", NULL);
9559 else
9560 msm_fb_register_device("mdp", &mdp_pdata);
9561
9562 msm_fb_register_device("lcdc", &lcdc_pdata);
9563 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9564#ifdef CONFIG_MSM_BUS_SCALING
9565 msm_fb_register_device("dtv", &dtv_pdata);
9566#endif
9567#ifdef CONFIG_FB_MSM_TVOUT
9568 msm_fb_register_device("tvenc", &atv_pdata);
9569 msm_fb_register_device("tvout_device", NULL);
9570#endif
9571}
9572
9573#if (defined(CONFIG_MARIMBA_CORE)) && \
9574 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9575
9576static const struct {
9577 char *name;
9578 int vmin;
9579 int vmax;
9580} bt_regs_info[] = {
9581 { "8058_s3", 1800000, 1800000 },
9582 { "8058_s2", 1300000, 1300000 },
9583 { "8058_l8", 2900000, 3050000 },
9584};
9585
9586static struct {
9587 bool enabled;
9588} bt_regs_status[] = {
9589 { false },
9590 { false },
9591 { false },
9592};
9593static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9594
9595static int bahama_bt(int on)
9596{
9597 int rc;
9598 int i;
9599 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9600
9601 struct bahama_variant_register {
9602 const size_t size;
9603 const struct bahama_config_register *set;
9604 };
9605
9606 const struct bahama_config_register *p;
9607
9608 u8 version;
9609
9610 const struct bahama_config_register v10_bt_on[] = {
9611 { 0xE9, 0x00, 0xFF },
9612 { 0xF4, 0x80, 0xFF },
9613 { 0xE4, 0x00, 0xFF },
9614 { 0xE5, 0x00, 0x0F },
9615#ifdef CONFIG_WLAN
9616 { 0xE6, 0x38, 0x7F },
9617 { 0xE7, 0x06, 0xFF },
9618#endif
9619 { 0xE9, 0x21, 0xFF },
9620 { 0x01, 0x0C, 0x1F },
9621 { 0x01, 0x08, 0x1F },
9622 };
9623
9624 const struct bahama_config_register v20_bt_on_fm_off[] = {
9625 { 0x11, 0x0C, 0xFF },
9626 { 0x13, 0x01, 0xFF },
9627 { 0xF4, 0x80, 0xFF },
9628 { 0xF0, 0x00, 0xFF },
9629 { 0xE9, 0x00, 0xFF },
9630#ifdef CONFIG_WLAN
9631 { 0x81, 0x00, 0x7F },
9632 { 0x82, 0x00, 0xFF },
9633 { 0xE6, 0x38, 0x7F },
9634 { 0xE7, 0x06, 0xFF },
9635#endif
9636 { 0xE9, 0x21, 0xFF },
9637 };
9638
9639 const struct bahama_config_register v20_bt_on_fm_on[] = {
9640 { 0x11, 0x0C, 0xFF },
9641 { 0x13, 0x01, 0xFF },
9642 { 0xF4, 0x86, 0xFF },
9643 { 0xF0, 0x06, 0xFF },
9644 { 0xE9, 0x00, 0xFF },
9645#ifdef CONFIG_WLAN
9646 { 0x81, 0x00, 0x7F },
9647 { 0x82, 0x00, 0xFF },
9648 { 0xE6, 0x38, 0x7F },
9649 { 0xE7, 0x06, 0xFF },
9650#endif
9651 { 0xE9, 0x21, 0xFF },
9652 };
9653
9654 const struct bahama_config_register v10_bt_off[] = {
9655 { 0xE9, 0x00, 0xFF },
9656 };
9657
9658 const struct bahama_config_register v20_bt_off_fm_off[] = {
9659 { 0xF4, 0x84, 0xFF },
9660 { 0xF0, 0x04, 0xFF },
9661 { 0xE9, 0x00, 0xFF }
9662 };
9663
9664 const struct bahama_config_register v20_bt_off_fm_on[] = {
9665 { 0xF4, 0x86, 0xFF },
9666 { 0xF0, 0x06, 0xFF },
9667 { 0xE9, 0x00, 0xFF }
9668 };
9669 const struct bahama_variant_register bt_bahama[2][3] = {
9670 {
9671 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9672 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9673 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9674 },
9675 {
9676 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9677 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9678 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9679 }
9680 };
9681
9682 u8 offset = 0; /* index into bahama configs */
9683
9684 on = on ? 1 : 0;
9685 version = read_bahama_ver();
9686
9687 if (version == VER_UNSUPPORTED) {
9688 dev_err(&msm_bt_power_device.dev,
9689 "%s: unsupported version\n",
9690 __func__);
9691 return -EIO;
9692 }
9693
9694 if (version == VER_2_0) {
9695 if (marimba_get_fm_status(&config))
9696 offset = 0x01;
9697 }
9698
9699 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9700 if (on && (version == VER_2_0)) {
9701 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9702 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9703 && (bt_regs_status[i].enabled == true)) {
9704 if (regulator_disable(bt_regs[i])) {
9705 dev_err(&msm_bt_power_device.dev,
9706 "%s: regulator disable failed",
9707 __func__);
9708 }
9709 bt_regs_status[i].enabled = false;
9710 break;
9711 }
9712 }
9713 }
9714
9715 p = bt_bahama[on][version + offset].set;
9716
9717 dev_info(&msm_bt_power_device.dev,
9718 "%s: found version %d\n", __func__, version);
9719
9720 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9721 u8 value = (p+i)->value;
9722 rc = marimba_write_bit_mask(&config,
9723 (p+i)->reg,
9724 &value,
9725 sizeof((p+i)->value),
9726 (p+i)->mask);
9727 if (rc < 0) {
9728 dev_err(&msm_bt_power_device.dev,
9729 "%s: reg %d write failed: %d\n",
9730 __func__, (p+i)->reg, rc);
9731 return rc;
9732 }
9733 dev_dbg(&msm_bt_power_device.dev,
9734 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9735 __func__, (p+i)->reg,
9736 value, (p+i)->mask);
9737 }
9738 /* Update BT Status */
9739 if (on)
9740 marimba_set_bt_status(&config, true);
9741 else
9742 marimba_set_bt_status(&config, false);
9743
9744 return 0;
9745}
9746
9747static int bluetooth_use_regulators(int on)
9748{
9749 int i, recover = -1, rc = 0;
9750
9751 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9752 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9753 bt_regs_info[i].name) :
9754 (regulator_put(bt_regs[i]), NULL);
9755 if (IS_ERR(bt_regs[i])) {
9756 rc = PTR_ERR(bt_regs[i]);
9757 dev_err(&msm_bt_power_device.dev,
9758 "regulator %s get failed (%d)\n",
9759 bt_regs_info[i].name, rc);
9760 recover = i - 1;
9761 bt_regs[i] = NULL;
9762 break;
9763 }
9764
9765 if (!on)
9766 continue;
9767
9768 rc = regulator_set_voltage(bt_regs[i],
9769 bt_regs_info[i].vmin,
9770 bt_regs_info[i].vmax);
9771 if (rc < 0) {
9772 dev_err(&msm_bt_power_device.dev,
9773 "regulator %s voltage set (%d)\n",
9774 bt_regs_info[i].name, rc);
9775 recover = i;
9776 break;
9777 }
9778 }
9779
9780 if (on && (recover > -1))
9781 for (i = recover; i >= 0; i--) {
9782 regulator_put(bt_regs[i]);
9783 bt_regs[i] = NULL;
9784 }
9785
9786 return rc;
9787}
9788
9789static int bluetooth_switch_regulators(int on)
9790{
9791 int i, rc = 0;
9792
9793 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9794 if (on && (bt_regs_status[i].enabled == false)) {
9795 rc = regulator_enable(bt_regs[i]);
9796 if (rc < 0) {
9797 dev_err(&msm_bt_power_device.dev,
9798 "regulator %s %s failed (%d)\n",
9799 bt_regs_info[i].name,
9800 "enable", rc);
9801 if (i > 0) {
9802 while (--i) {
9803 regulator_disable(bt_regs[i]);
9804 bt_regs_status[i].enabled
9805 = false;
9806 }
9807 break;
9808 }
9809 }
9810 bt_regs_status[i].enabled = true;
9811 } else if (!on && (bt_regs_status[i].enabled == true)) {
9812 rc = regulator_disable(bt_regs[i]);
9813 if (rc < 0) {
9814 dev_err(&msm_bt_power_device.dev,
9815 "regulator %s %s failed (%d)\n",
9816 bt_regs_info[i].name,
9817 "disable", rc);
9818 break;
9819 }
9820 bt_regs_status[i].enabled = false;
9821 }
9822 }
9823 return rc;
9824}
9825
9826static struct msm_xo_voter *bt_clock;
9827
9828static int bluetooth_power(int on)
9829{
9830 int rc = 0;
9831 int id;
9832
9833 /* In case probe function fails, cur_connv_type would be -1 */
9834 id = adie_get_detected_connectivity_type();
9835 if (id != BAHAMA_ID) {
9836 pr_err("%s: unexpected adie connectivity type: %d\n",
9837 __func__, id);
9838 return -ENODEV;
9839 }
9840
9841 if (on) {
9842
9843 rc = bluetooth_use_regulators(1);
9844 if (rc < 0)
9845 goto out;
9846
9847 rc = bluetooth_switch_regulators(1);
9848
9849 if (rc < 0)
9850 goto fail_put;
9851
9852 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9853
9854 if (IS_ERR(bt_clock)) {
9855 pr_err("Couldn't get TCXO_D0 voter\n");
9856 goto fail_switch;
9857 }
9858
9859 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9860
9861 if (rc < 0) {
9862 pr_err("Failed to vote for TCXO_DO ON\n");
9863 goto fail_vote;
9864 }
9865
9866 rc = bahama_bt(1);
9867
9868 if (rc < 0)
9869 goto fail_clock;
9870
9871 msleep(10);
9872
9873 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9874
9875 if (rc < 0) {
9876 pr_err("Failed to vote for TCXO_DO pin control\n");
9877 goto fail_vote;
9878 }
9879 } else {
9880 /* check for initial RFKILL block (power off) */
9881 /* some RFKILL versions/configurations rfkill_register */
9882 /* calls here for an initial set_block */
9883 /* avoid calling i2c and regulator before unblock (on) */
9884 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
9885 dev_info(&msm_bt_power_device.dev,
9886 "%s: initialized OFF/blocked\n", __func__);
9887 goto out;
9888 }
9889
9890 bahama_bt(0);
9891
9892fail_clock:
9893 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
9894fail_vote:
9895 msm_xo_put(bt_clock);
9896fail_switch:
9897 bluetooth_switch_regulators(0);
9898fail_put:
9899 bluetooth_use_regulators(0);
9900 }
9901
9902out:
9903 if (rc < 0)
9904 on = 0;
9905 dev_info(&msm_bt_power_device.dev,
9906 "Bluetooth power switch: state %d result %d\n", on, rc);
9907
9908 return rc;
9909}
9910
9911#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
9912
9913static void __init msm8x60_cfg_smsc911x(void)
9914{
9915 smsc911x_resources[1].start =
9916 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
9917 smsc911x_resources[1].end =
9918 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
9919}
9920
9921#ifdef CONFIG_MSM_RPM
9922static struct msm_rpm_platform_data msm_rpm_data = {
9923 .reg_base_addrs = {
9924 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
9925 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
9926 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
9927 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
9928 },
9929
9930 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
9931 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
9932 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
9933 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
9934 .msm_apps_ipc_rpm_val = 4,
9935};
9936#endif
9937
Laura Abbott5d2d1e62011-08-10 16:27:35 -07009938void msm_fusion_setup_pinctrl(void)
9939{
9940 struct msm_xo_voter *a1;
9941
9942 if (socinfo_get_platform_subtype() == 0x3) {
9943 /*
9944 * Vote for the A1 clock to be in pin control mode before
9945 * the external images are loaded.
9946 */
9947 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
9948 BUG_ON(!a1);
9949 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
9950 }
9951}
9952
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009953struct msm_board_data {
9954 struct msm_gpiomux_configs *gpiomux_cfgs;
9955};
9956
9957static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
9958 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9959};
9960
9961static struct msm_board_data msm8x60_sim_board_data __initdata = {
9962 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9963};
9964
9965static struct msm_board_data msm8x60_surf_board_data __initdata = {
9966 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9967};
9968
9969static struct msm_board_data msm8x60_ffa_board_data __initdata = {
9970 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9971};
9972
9973static struct msm_board_data msm8x60_fluid_board_data __initdata = {
9974 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
9975};
9976
9977static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
9978 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
9979};
9980
9981static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
9982 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
9983};
9984
Zhang Chang Kenef05b172011-07-27 15:28:13 -04009985static struct msm_board_data msm8x60_dragon_board_data __initdata = {
9986 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
9987};
9988
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009989static void __init msm8x60_init(struct msm_board_data *board_data)
9990{
9991 uint32_t soc_platform_version;
9992
9993 /*
9994 * Initialize RPM first as other drivers and devices may need
9995 * it for their initialization.
9996 */
9997#ifdef CONFIG_MSM_RPM
9998 BUG_ON(msm_rpm_init(&msm_rpm_data));
9999#endif
10000 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
10001 ARRAY_SIZE(msm_rpmrs_levels)));
10002 if (msm_xo_init())
10003 pr_err("Failed to initialize XO votes\n");
10004
10005 if (socinfo_init() < 0)
10006 printk(KERN_ERR "%s: socinfo_init() failed!\n",
10007 __func__);
10008 msm8x60_check_2d_hardware();
10009
10010 /* Change SPM handling of core 1 if PMM 8160 is present. */
10011 soc_platform_version = socinfo_get_platform_version();
10012 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
10013 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
10014 struct msm_spm_platform_data *spm_data;
10015
10016 spm_data = &msm_spm_data_v1[1];
10017 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10018 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10019
10020 spm_data = &msm_spm_data[1];
10021 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10022 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10023 }
10024
10025 /*
10026 * Initialize SPM before acpuclock as the latter calls into SPM
10027 * driver to set ACPU voltages.
10028 */
10029 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10030 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
10031 else
10032 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
10033
10034 /*
10035 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
10036 * devices so that the RPM doesn't drop into a low power mode that an
10037 * un-reworked SURF cannot resume from.
10038 */
10039 if (machine_is_msm8x60_surf()) {
10040 rpm_vreg_init_pdata[RPM_VREG_ID_PM8901_L4]
10041 .init_data.constraints.always_on = 1;
10042 rpm_vreg_init_pdata[RPM_VREG_ID_PM8901_L6]
10043 .init_data.constraints.always_on = 1;
10044 }
10045
10046 /*
10047 * Disable regulator info printing so that regulator registration
10048 * messages do not enter the kmsg log.
10049 */
10050 regulator_suppress_info_printing();
10051
10052 /* Initialize regulators needed for clock_init. */
10053 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
10054
Stephen Boydbb600ae2011-08-02 20:11:40 -070010055 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010056
10057 /* Buses need to be initialized before early-device registration
10058 * to get the platform data for fabrics.
10059 */
10060 msm8x60_init_buses();
10061 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
10062 /* CPU frequency control is not supported on simulated targets. */
10063 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
10064 msm_acpu_clock_init(&msm8x60_acpu_clock_data);
10065
10066 /* No EBI2 on 8660 charm targets */
10067 if (!machine_is_msm8x60_fusion() && !machine_is_msm8x60_fusn_ffa())
10068 msm8x60_init_ebi2();
10069 msm8x60_init_tlmm();
10070 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10071 msm8x60_init_uart12dm();
10072 msm8x60_init_mmc();
10073
10074#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10075 msm8x60_init_pm8058_othc();
10076#endif
10077
10078 if (machine_is_msm8x60_fluid()) {
10079 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10080 platform_data = &fluid_keypad_data;
10081 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10082 = sizeof(fluid_keypad_data);
Zhang Chang Ken683be172011-08-10 17:45:34 -040010083 } else if (machine_is_msm8x60_dragon()) {
10084 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10085 platform_data = &dragon_keypad_data;
10086 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10087 = sizeof(dragon_keypad_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010088 } else {
10089 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10090 platform_data = &ffa_keypad_data;
10091 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10092 = sizeof(ffa_keypad_data);
10093
10094 }
10095
10096 /* Disable END_CALL simulation function of powerkey on fluid */
10097 if (machine_is_msm8x60_fluid()) {
10098 pwrkey_pdata.pwrkey_time_ms = 0;
10099 }
10100
Jilai Wang53d27a82011-07-13 14:32:58 -040010101 /* Specify reset pin for OV9726 */
10102 if (machine_is_msm8x60_dragon()) {
10103 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10104 ov9726_sensor_8660_info.mount_angle = 270;
10105 }
10106
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010107 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10108 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010109 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010110 msm8x60_cfg_smsc911x();
10111 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10112 platform_add_devices(msm_footswitch_devices,
10113 msm_num_footswitch_devices);
10114 platform_add_devices(surf_devices,
10115 ARRAY_SIZE(surf_devices));
10116
10117#ifdef CONFIG_MSM_DSPS
10118 if (machine_is_msm8x60_fluid()) {
10119 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10120 msm8x60_init_dsps();
10121 }
10122#endif
10123
10124#ifdef CONFIG_USB_EHCI_MSM_72K
10125 /*
10126 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10127 * fluid
10128 */
10129 if (machine_is_msm8x60_fluid()) {
10130 pm8901_mpp_config_digital_out(1,
10131 PM8901_MPP_DIG_LEVEL_L5, 1);
10132 }
10133 msm_add_host(0, &msm_usb_host_pdata);
10134#endif
10135 } else {
10136 msm8x60_configure_smc91x();
10137 platform_add_devices(rumi_sim_devices,
10138 ARRAY_SIZE(rumi_sim_devices));
10139 }
10140#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010141 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10142 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010143 msm8x60_cfg_isp1763();
10144#endif
10145#ifdef CONFIG_BATTERY_MSM8X60
10146 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010147 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010148 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10149 platform_device_register(&msm_charger_device);
10150#endif
10151
10152 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10153 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10154
Terence Hampson90508a92011-08-09 10:40:08 -040010155 if (machine_is_msm8x60_dragon()) {
10156 pm8058_charger_sub_dev.platform_data
10157 = &pmic8058_charger_dragon;
10158 pm8058_charger_sub_dev.pdata_size
10159 = sizeof(pmic8058_charger_dragon);
10160 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010161 if (!machine_is_msm8x60_fluid())
10162 pm8058_platform_data.charger_sub_device
10163 = &pm8058_charger_sub_dev;
10164
10165#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10166 if (machine_is_msm8x60_fluid())
10167 platform_device_register(&msm_gsbi10_qup_spi_device);
10168 else
10169 platform_device_register(&msm_gsbi1_qup_spi_device);
10170#endif
10171
10172#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10173 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10174 if (machine_is_msm8x60_fluid())
10175 cyttsp_set_params();
10176#endif
10177 if (!machine_is_msm8x60_sim())
10178 msm_fb_add_devices();
10179 fixup_i2c_configs();
10180 register_i2c_devices();
10181
Terence Hampson1c73fef2011-07-19 17:10:49 -040010182 if (machine_is_msm8x60_dragon())
10183 smsc911x_config.reset_gpio
10184 = GPIO_ETHERNET_RESET_N_DRAGON;
10185
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010186 platform_device_register(&smsc911x_device);
10187
10188#if (defined(CONFIG_SPI_QUP)) && \
10189 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010190 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10191 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010192
10193 if (machine_is_msm8x60_fluid()) {
10194#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10195 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10196 spi_register_board_info(lcdc_samsung_spi_board_info,
10197 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10198 } else
10199#endif
10200 {
10201#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10202 spi_register_board_info(lcdc_auo_spi_board_info,
10203 ARRAY_SIZE(lcdc_auo_spi_board_info));
10204#endif
10205 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010206#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10207 } else if (machine_is_msm8x60_dragon()) {
10208 spi_register_board_info(lcdc_nt35582_spi_board_info,
10209 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10210#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010211 }
10212#endif
10213
10214 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10215 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10216 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10217 msm_pm_data);
10218
10219#ifdef CONFIG_SENSORS_MSM_ADC
10220 if (machine_is_msm8x60_fluid()) {
10221 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10222 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10223 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10224 msm_adc_pdata.gpio_config = APROC_CONFIG;
10225 else
10226 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10227 }
10228 msm_adc_pdata.target_hw = MSM_8x60;
10229#endif
10230#ifdef CONFIG_MSM8X60_AUDIO
10231 msm_snddev_init();
10232#endif
10233#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10234 if (machine_is_msm8x60_fluid())
10235 platform_device_register(&fluid_leds_gpio);
10236 else
10237 platform_device_register(&gpio_leds);
10238#endif
10239
10240 /* configure pmic leds */
10241 if (machine_is_msm8x60_fluid()) {
10242 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10243 platform_data = &pm8058_fluid_flash_leds_data;
10244 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10245 = sizeof(pm8058_fluid_flash_leds_data);
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -040010246 } else if (machine_is_msm8x60_dragon()) {
10247 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10248 platform_data = &pm8058_dragon_leds_data;
10249 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10250 = sizeof(pm8058_dragon_leds_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010251 } else {
10252 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10253 platform_data = &pm8058_flash_leds_data;
10254 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10255 = sizeof(pm8058_flash_leds_data);
10256 }
10257
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010258 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10259 machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010260 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10261 platform_data = &pmic_vib_pdata;
10262 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10263 pdata_size = sizeof(pmic_vib_pdata);
10264 }
10265
10266 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010267
10268 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10269 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010270}
10271
10272static void __init msm8x60_rumi3_init(void)
10273{
10274 msm8x60_init(&msm8x60_rumi3_board_data);
10275}
10276
10277static void __init msm8x60_sim_init(void)
10278{
10279 msm8x60_init(&msm8x60_sim_board_data);
10280}
10281
10282static void __init msm8x60_surf_init(void)
10283{
10284 msm8x60_init(&msm8x60_surf_board_data);
10285}
10286
10287static void __init msm8x60_ffa_init(void)
10288{
10289 msm8x60_init(&msm8x60_ffa_board_data);
10290}
10291
10292static void __init msm8x60_fluid_init(void)
10293{
10294 msm8x60_init(&msm8x60_fluid_board_data);
10295}
10296
10297static void __init msm8x60_charm_surf_init(void)
10298{
10299 msm8x60_init(&msm8x60_charm_surf_board_data);
10300}
10301
10302static void __init msm8x60_charm_ffa_init(void)
10303{
10304 msm8x60_init(&msm8x60_charm_ffa_board_data);
10305}
10306
10307static void __init msm8x60_charm_init_early(void)
10308{
10309 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010310}
10311
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010312static void __init msm8x60_dragon_init(void)
10313{
10314 msm8x60_init(&msm8x60_dragon_board_data);
10315}
10316
Steve Mucklea55df6e2010-01-07 12:43:24 -080010317MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10318 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010319 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010320 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010321 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010322 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010323 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010324MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010325
10326MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10327 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010328 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010329 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010330 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010331 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010332 .init_early = msm8x60_charm_init_early,
10333MACHINE_END
10334
10335MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10336 .map_io = msm8x60_map_io,
10337 .reserve = msm8x60_reserve,
10338 .init_irq = msm8x60_init_irq,
10339 .init_machine = msm8x60_surf_init,
10340 .timer = &msm_timer,
10341 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010342MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010343
10344MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10345 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010346 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010347 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010348 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010349 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010350 .init_early = msm8x60_charm_init_early,
10351MACHINE_END
10352
10353MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10354 .map_io = msm8x60_map_io,
10355 .reserve = msm8x60_reserve,
10356 .init_irq = msm8x60_init_irq,
10357 .init_machine = msm8x60_fluid_init,
10358 .timer = &msm_timer,
10359 .init_early = msm8x60_charm_init_early,
10360MACHINE_END
10361
10362MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10363 .map_io = msm8x60_map_io,
10364 .reserve = msm8x60_reserve,
10365 .init_irq = msm8x60_init_irq,
10366 .init_machine = msm8x60_charm_surf_init,
10367 .timer = &msm_timer,
10368 .init_early = msm8x60_charm_init_early,
10369MACHINE_END
10370
10371MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10372 .map_io = msm8x60_map_io,
10373 .reserve = msm8x60_reserve,
10374 .init_irq = msm8x60_init_irq,
10375 .init_machine = msm8x60_charm_ffa_init,
10376 .timer = &msm_timer,
10377 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010378MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010379
10380MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10381 .map_io = msm8x60_map_io,
10382 .reserve = msm8x60_reserve,
10383 .init_irq = msm8x60_init_irq,
10384 .init_machine = msm8x60_dragon_init,
10385 .timer = &msm_timer,
10386 .init_early = msm8x60_charm_init_early,
10387MACHINE_END