blob: 022feb45c15e30d9a68c25fce3f01d7e04f697cf [file] [log] [blame]
Huang Shijie45dfc1a2011-09-08 10:47:10 +08001/*
2 * Freescale GPMI NAND Flash Driver
3 *
4 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21#include <linux/mtd/gpmi-nand.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <mach/mxs.h>
25
26#include "gpmi-nand.h"
27#include "gpmi-regs.h"
28#include "bch-regs.h"
29
30struct timing_threshod timing_default_threshold = {
31 .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
32 BP_GPMI_TIMING0_DATA_SETUP),
33 .internal_data_setup_in_ns = 0,
34 .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
35 BP_GPMI_CTRL1_RDN_DELAY),
36 .max_dll_clock_period_in_ns = 32,
37 .max_dll_delay_in_ns = 16,
38};
39
40/*
41 * Clear the bit and poll it cleared. This is usually called with
42 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
43 * (bit 30).
44 */
45static int clear_poll_bit(void __iomem *addr, u32 mask)
46{
47 int timeout = 0x400;
48
49 /* clear the bit */
50 __mxs_clrl(mask, addr);
51
52 /*
53 * SFTRST needs 3 GPMI clocks to settle, the reference manual
54 * recommends to wait 1us.
55 */
56 udelay(1);
57
58 /* poll the bit becoming clear */
59 while ((readl(addr) & mask) && --timeout)
60 /* nothing */;
61
62 return !timeout;
63}
64
65#define MODULE_CLKGATE (1 << 30)
66#define MODULE_SFTRST (1 << 31)
67/*
68 * The current mxs_reset_block() will do two things:
69 * [1] enable the module.
70 * [2] reset the module.
71 *
Huang Shijie9398d1c2012-01-04 11:18:46 +080072 * In most of the cases, it's ok.
73 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
Huang Shijie45dfc1a2011-09-08 10:47:10 +080074 * If you try to soft reset the BCH block, it becomes unusable until
75 * the next hard reset. This case occurs in the NAND boot mode. When the board
76 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
77 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
Huang Shijie9398d1c2012-01-04 11:18:46 +080078 * You will see a DMA timeout in this case. The bug has been fixed
79 * in the following chips, such as MX28.
Huang Shijie45dfc1a2011-09-08 10:47:10 +080080 *
81 * To avoid this bug, just add a new parameter `just_enable` for
82 * the mxs_reset_block(), and rewrite it here.
83 */
Huang Shijie9398d1c2012-01-04 11:18:46 +080084static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
Huang Shijie45dfc1a2011-09-08 10:47:10 +080085{
86 int ret;
87 int timeout = 0x400;
88
89 /* clear and poll SFTRST */
90 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
91 if (unlikely(ret))
92 goto error;
93
94 /* clear CLKGATE */
95 __mxs_clrl(MODULE_CLKGATE, reset_addr);
96
97 if (!just_enable) {
98 /* set SFTRST to reset the block */
99 __mxs_setl(MODULE_SFTRST, reset_addr);
100 udelay(1);
101
102 /* poll CLKGATE becoming set */
103 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
104 /* nothing */;
105 if (unlikely(!timeout))
106 goto error;
107 }
108
109 /* clear and poll SFTRST */
110 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
111 if (unlikely(ret))
112 goto error;
113
114 /* clear and poll CLKGATE */
115 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
116 if (unlikely(ret))
117 goto error;
118
119 return 0;
120
121error:
122 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
123 return -ETIMEDOUT;
124}
125
126int gpmi_init(struct gpmi_nand_data *this)
127{
128 struct resources *r = &this->resources;
129 int ret;
130
Shawn Guof1f802c2011-12-20 14:02:05 +0800131 ret = clk_prepare_enable(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800132 if (ret)
133 goto err_out;
134 ret = gpmi_reset_block(r->gpmi_regs, false);
135 if (ret)
136 goto err_out;
137
Wolfram Sangb53673d2012-12-05 21:46:02 +0100138 /*
139 * Reset BCH here, too. We got failures otherwise :(
140 * See later BCH reset for explanation of MX23 handling
141 */
142 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
143 if (ret)
144 goto err_out;
145
146
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800147 /* Choose NAND mode. */
148 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
149
150 /* Set the IRQ polarity. */
151 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
152 r->gpmi_regs + HW_GPMI_CTRL1_SET);
153
154 /* Disable Write-Protection. */
155 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
156
157 /* Select BCH ECC. */
158 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
159
Shawn Guof1f802c2011-12-20 14:02:05 +0800160 clk_disable_unprepare(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800161 return 0;
162err_out:
163 return ret;
164}
165
166/* This function is very useful. It is called only when the bug occur. */
167void gpmi_dump_info(struct gpmi_nand_data *this)
168{
169 struct resources *r = &this->resources;
170 struct bch_geometry *geo = &this->bch_geometry;
171 u32 reg;
172 int i;
173
174 pr_err("Show GPMI registers :\n");
175 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
176 reg = readl(r->gpmi_regs + i * 0x10);
177 pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
178 }
179
180 /* start to print out the BCH info */
181 pr_err("BCH Geometry :\n");
182 pr_err("GF length : %u\n", geo->gf_len);
183 pr_err("ECC Strength : %u\n", geo->ecc_strength);
184 pr_err("Page Size in Bytes : %u\n", geo->page_size);
185 pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
186 pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
187 pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
188 pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
189 pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
190 pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
191 pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
192 pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
193}
194
195/* Configures the geometry for BCH. */
196int bch_set_geometry(struct gpmi_nand_data *this)
197{
198 struct resources *r = &this->resources;
199 struct bch_geometry *bch_geo = &this->bch_geometry;
200 unsigned int block_count;
201 unsigned int block_size;
202 unsigned int metadata_size;
203 unsigned int ecc_strength;
204 unsigned int page_size;
205 int ret;
206
207 if (common_nfc_set_geometry(this))
208 return !0;
209
210 block_count = bch_geo->ecc_chunk_count - 1;
211 block_size = bch_geo->ecc_chunk_size;
212 metadata_size = bch_geo->metadata_size;
213 ecc_strength = bch_geo->ecc_strength >> 1;
214 page_size = bch_geo->page_size;
215
Shawn Guof1f802c2011-12-20 14:02:05 +0800216 ret = clk_prepare_enable(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800217 if (ret)
218 goto err_out;
219
Huang Shijie9398d1c2012-01-04 11:18:46 +0800220 /*
221 * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
222 * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
223 * On the other hand, the MX28 needs the reset, because one case has been
224 * seen where the BCH produced ECC errors constantly after 10000
225 * consecutive reboots. The latter case has not been seen on the MX23 yet,
226 * still we don't know if it could happen there as well.
227 */
228 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800229 if (ret)
230 goto err_out;
231
232 /* Configure layout 0. */
233 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
234 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
235 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)
236 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size),
237 r->bch_regs + HW_BCH_FLASH0LAYOUT0);
238
239 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
240 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)
241 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size),
242 r->bch_regs + HW_BCH_FLASH0LAYOUT1);
243
244 /* Set *all* chip selects to use layout 0. */
245 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
246
247 /* Enable interrupts. */
248 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
249 r->bch_regs + HW_BCH_CTRL_SET);
250
Shawn Guof1f802c2011-12-20 14:02:05 +0800251 clk_disable_unprepare(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800252 return 0;
253err_out:
254 return ret;
255}
256
257/* Converts time in nanoseconds to cycles. */
258static unsigned int ns_to_cycles(unsigned int time,
259 unsigned int period, unsigned int min)
260{
261 unsigned int k;
262
263 k = (time + period - 1) / period;
264 return max(k, min);
265}
266
267/* Apply timing to current hardware conditions. */
268static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
269 struct gpmi_nfc_hardware_timing *hw)
270{
271 struct gpmi_nand_platform_data *pdata = this->pdata;
272 struct timing_threshod *nfc = &timing_default_threshold;
273 struct nand_chip *nand = &this->nand;
274 struct nand_timing target = this->timing;
275 bool improved_timing_is_available;
276 unsigned long clock_frequency_in_hz;
277 unsigned int clock_period_in_ns;
278 bool dll_use_half_periods;
279 unsigned int dll_delay_shift;
280 unsigned int max_sample_delay_in_ns;
281 unsigned int address_setup_in_cycles;
282 unsigned int data_setup_in_ns;
283 unsigned int data_setup_in_cycles;
284 unsigned int data_hold_in_cycles;
285 int ideal_sample_delay_in_ns;
286 unsigned int sample_delay_factor;
287 int tEYE;
288 unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
289 unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
290
291 /*
292 * If there are multiple chips, we need to relax the timings to allow
293 * for signal distortion due to higher capacitance.
294 */
295 if (nand->numchips > 2) {
296 target.data_setup_in_ns += 10;
297 target.data_hold_in_ns += 10;
298 target.address_setup_in_ns += 10;
299 } else if (nand->numchips > 1) {
300 target.data_setup_in_ns += 5;
301 target.data_hold_in_ns += 5;
302 target.address_setup_in_ns += 5;
303 }
304
305 /* Check if improved timing information is available. */
306 improved_timing_is_available =
307 (target.tREA_in_ns >= 0) &&
308 (target.tRLOH_in_ns >= 0) &&
309 (target.tRHOH_in_ns >= 0) ;
310
311 /* Inspect the clock. */
312 clock_frequency_in_hz = nfc->clock_frequency_in_hz;
313 clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
314
315 /*
316 * The NFC quantizes setup and hold parameters in terms of clock cycles.
317 * Here, we quantize the setup and hold timing parameters to the
318 * next-highest clock period to make sure we apply at least the
319 * specified times.
320 *
321 * For data setup and data hold, the hardware interprets a value of zero
322 * as the largest possible delay. This is not what's intended by a zero
323 * in the input parameter, so we impose a minimum of one cycle.
324 */
325 data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
326 clock_period_in_ns, 1);
327 data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
328 clock_period_in_ns, 1);
329 address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
330 clock_period_in_ns, 0);
331
332 /*
333 * The clock's period affects the sample delay in a number of ways:
334 *
335 * (1) The NFC HAL tells us the maximum clock period the sample delay
336 * DLL can tolerate. If the clock period is greater than half that
337 * maximum, we must configure the DLL to be driven by half periods.
338 *
339 * (2) We need to convert from an ideal sample delay, in ns, to a
340 * "sample delay factor," which the NFC uses. This factor depends on
341 * whether we're driving the DLL with full or half periods.
342 * Paraphrasing the reference manual:
343 *
344 * AD = SDF x 0.125 x RP
345 *
346 * where:
347 *
348 * AD is the applied delay, in ns.
349 * SDF is the sample delay factor, which is dimensionless.
350 * RP is the reference period, in ns, which is a full clock period
351 * if the DLL is being driven by full periods, or half that if
352 * the DLL is being driven by half periods.
353 *
354 * Let's re-arrange this in a way that's more useful to us:
355 *
356 * 8
357 * SDF = AD x ----
358 * RP
359 *
360 * The reference period is either the clock period or half that, so this
361 * is:
362 *
363 * 8 AD x DDF
364 * SDF = AD x ----- = --------
365 * f x P P
366 *
367 * where:
368 *
369 * f is 1 or 1/2, depending on how we're driving the DLL.
370 * P is the clock period.
371 * DDF is the DLL Delay Factor, a dimensionless value that
372 * incorporates all the constants in the conversion.
373 *
374 * DDF will be either 8 or 16, both of which are powers of two. We can
375 * reduce the cost of this conversion by using bit shifts instead of
376 * multiplication or division. Thus:
377 *
378 * AD << DDS
379 * SDF = ---------
380 * P
381 *
382 * or
383 *
384 * AD = (SDF >> DDS) x P
385 *
386 * where:
387 *
388 * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
389 */
390 if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
391 dll_use_half_periods = true;
392 dll_delay_shift = 3 + 1;
393 } else {
394 dll_use_half_periods = false;
395 dll_delay_shift = 3;
396 }
397
398 /*
399 * Compute the maximum sample delay the NFC allows, under current
400 * conditions. If the clock is running too slowly, no sample delay is
401 * possible.
402 */
403 if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
404 max_sample_delay_in_ns = 0;
405 else {
406 /*
407 * Compute the delay implied by the largest sample delay factor
408 * the NFC allows.
409 */
410 max_sample_delay_in_ns =
411 (nfc->max_sample_delay_factor * clock_period_in_ns) >>
412 dll_delay_shift;
413
414 /*
415 * Check if the implied sample delay larger than the NFC
416 * actually allows.
417 */
418 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
419 max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
420 }
421
422 /*
423 * Check if improved timing information is available. If not, we have to
424 * use a less-sophisticated algorithm.
425 */
426 if (!improved_timing_is_available) {
427 /*
428 * Fold the read setup time required by the NFC into the ideal
429 * sample delay.
430 */
431 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
432 nfc->internal_data_setup_in_ns;
433
434 /*
435 * The ideal sample delay may be greater than the maximum
436 * allowed by the NFC. If so, we can trade off sample delay time
437 * for more data setup time.
438 *
439 * In each iteration of the following loop, we add a cycle to
440 * the data setup time and subtract a corresponding amount from
441 * the sample delay until we've satisified the constraints or
442 * can't do any better.
443 */
444 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
445 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
446
447 data_setup_in_cycles++;
448 ideal_sample_delay_in_ns -= clock_period_in_ns;
449
450 if (ideal_sample_delay_in_ns < 0)
451 ideal_sample_delay_in_ns = 0;
452
453 }
454
455 /*
456 * Compute the sample delay factor that corresponds most closely
457 * to the ideal sample delay. If the result is too large for the
458 * NFC, use the maximum value.
459 *
460 * Notice that we use the ns_to_cycles function to compute the
461 * sample delay factor. We do this because the form of the
462 * computation is the same as that for calculating cycles.
463 */
464 sample_delay_factor =
465 ns_to_cycles(
466 ideal_sample_delay_in_ns << dll_delay_shift,
467 clock_period_in_ns, 0);
468
469 if (sample_delay_factor > nfc->max_sample_delay_factor)
470 sample_delay_factor = nfc->max_sample_delay_factor;
471
472 /* Skip to the part where we return our results. */
473 goto return_results;
474 }
475
476 /*
477 * If control arrives here, we have more detailed timing information,
478 * so we can use a better algorithm.
479 */
480
481 /*
482 * Fold the read setup time required by the NFC into the maximum
483 * propagation delay.
484 */
485 max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
486
487 /*
488 * Earlier, we computed the number of clock cycles required to satisfy
489 * the data setup time. Now, we need to know the actual nanoseconds.
490 */
491 data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
492
493 /*
494 * Compute tEYE, the width of the data eye when reading from the NAND
495 * Flash. The eye width is fundamentally determined by the data setup
496 * time, perturbed by propagation delays and some characteristics of the
497 * NAND Flash device.
498 *
499 * start of the eye = max_prop_delay + tREA
500 * end of the eye = min_prop_delay + tRHOH + data_setup
501 */
502 tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
503 (int)data_setup_in_ns;
504
505 tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
506
507 /*
508 * The eye must be open. If it's not, we can try to open it by
509 * increasing its main forcer, the data setup time.
510 *
511 * In each iteration of the following loop, we increase the data setup
512 * time by a single clock cycle. We do this until either the eye is
513 * open or we run into NFC limits.
514 */
515 while ((tEYE <= 0) &&
516 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
517 /* Give a cycle to data setup. */
518 data_setup_in_cycles++;
519 /* Synchronize the data setup time with the cycles. */
520 data_setup_in_ns += clock_period_in_ns;
521 /* Adjust tEYE accordingly. */
522 tEYE += clock_period_in_ns;
523 }
524
525 /*
526 * When control arrives here, the eye is open. The ideal time to sample
527 * the data is in the center of the eye:
528 *
529 * end of the eye + start of the eye
530 * --------------------------------- - data_setup
531 * 2
532 *
533 * After some algebra, this simplifies to the code immediately below.
534 */
535 ideal_sample_delay_in_ns =
536 ((int)max_prop_delay_in_ns +
537 (int)target.tREA_in_ns +
538 (int)min_prop_delay_in_ns +
539 (int)target.tRHOH_in_ns -
540 (int)data_setup_in_ns) >> 1;
541
542 /*
543 * The following figure illustrates some aspects of a NAND Flash read:
544 *
545 *
546 * __ _____________________________________
547 * RDN \_________________/
548 *
549 * <---- tEYE ----->
550 * /-----------------\
551 * Read Data ----------------------------< >---------
552 * \-----------------/
553 * ^ ^ ^ ^
554 * | | | |
555 * |<--Data Setup -->|<--Delay Time -->| |
556 * | | | |
557 * | | |
558 * | |<-- Quantized Delay Time -->|
559 * | | |
560 *
561 *
562 * We have some issues we must now address:
563 *
564 * (1) The *ideal* sample delay time must not be negative. If it is, we
565 * jam it to zero.
566 *
567 * (2) The *ideal* sample delay time must not be greater than that
568 * allowed by the NFC. If it is, we can increase the data setup
569 * time, which will reduce the delay between the end of the data
570 * setup and the center of the eye. It will also make the eye
571 * larger, which might help with the next issue...
572 *
573 * (3) The *quantized* sample delay time must not fall either before the
574 * eye opens or after it closes (the latter is the problem
575 * illustrated in the above figure).
576 */
577
578 /* Jam a negative ideal sample delay to zero. */
579 if (ideal_sample_delay_in_ns < 0)
580 ideal_sample_delay_in_ns = 0;
581
582 /*
583 * Extend the data setup as needed to reduce the ideal sample delay
584 * below the maximum permitted by the NFC.
585 */
586 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
587 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
588
589 /* Give a cycle to data setup. */
590 data_setup_in_cycles++;
591 /* Synchronize the data setup time with the cycles. */
592 data_setup_in_ns += clock_period_in_ns;
593 /* Adjust tEYE accordingly. */
594 tEYE += clock_period_in_ns;
595
596 /*
597 * Decrease the ideal sample delay by one half cycle, to keep it
598 * in the middle of the eye.
599 */
600 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
601
602 /* Jam a negative ideal sample delay to zero. */
603 if (ideal_sample_delay_in_ns < 0)
604 ideal_sample_delay_in_ns = 0;
605 }
606
607 /*
608 * Compute the sample delay factor that corresponds to the ideal sample
609 * delay. If the result is too large, then use the maximum allowed
610 * value.
611 *
612 * Notice that we use the ns_to_cycles function to compute the sample
613 * delay factor. We do this because the form of the computation is the
614 * same as that for calculating cycles.
615 */
616 sample_delay_factor =
617 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
618 clock_period_in_ns, 0);
619
620 if (sample_delay_factor > nfc->max_sample_delay_factor)
621 sample_delay_factor = nfc->max_sample_delay_factor;
622
623 /*
624 * These macros conveniently encapsulate a computation we'll use to
625 * continuously evaluate whether or not the data sample delay is inside
626 * the eye.
627 */
628 #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
629
630 #define QUANTIZED_DELAY \
631 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
632 dll_delay_shift))
633
634 #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
635
636 #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
637
638 /*
639 * While the quantized sample time falls outside the eye, reduce the
640 * sample delay or extend the data setup to move the sampling point back
641 * toward the eye. Do not allow the number of data setup cycles to
642 * exceed the maximum allowed by the NFC.
643 */
644 while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
645 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
646 /*
647 * If control arrives here, the quantized sample delay falls
648 * outside the eye. Check if it's before the eye opens, or after
649 * the eye closes.
650 */
651 if (QUANTIZED_DELAY > IDEAL_DELAY) {
652 /*
653 * If control arrives here, the quantized sample delay
654 * falls after the eye closes. Decrease the quantized
655 * delay time and then go back to re-evaluate.
656 */
657 if (sample_delay_factor != 0)
658 sample_delay_factor--;
659 continue;
660 }
661
662 /*
663 * If control arrives here, the quantized sample delay falls
664 * before the eye opens. Shift the sample point by increasing
665 * data setup time. This will also make the eye larger.
666 */
667
668 /* Give a cycle to data setup. */
669 data_setup_in_cycles++;
670 /* Synchronize the data setup time with the cycles. */
671 data_setup_in_ns += clock_period_in_ns;
672 /* Adjust tEYE accordingly. */
673 tEYE += clock_period_in_ns;
674
675 /*
676 * Decrease the ideal sample delay by one half cycle, to keep it
677 * in the middle of the eye.
678 */
679 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
680
681 /* ...and one less period for the delay time. */
682 ideal_sample_delay_in_ns -= clock_period_in_ns;
683
684 /* Jam a negative ideal sample delay to zero. */
685 if (ideal_sample_delay_in_ns < 0)
686 ideal_sample_delay_in_ns = 0;
687
688 /*
689 * We have a new ideal sample delay, so re-compute the quantized
690 * delay.
691 */
692 sample_delay_factor =
693 ns_to_cycles(
694 ideal_sample_delay_in_ns << dll_delay_shift,
695 clock_period_in_ns, 0);
696
697 if (sample_delay_factor > nfc->max_sample_delay_factor)
698 sample_delay_factor = nfc->max_sample_delay_factor;
699 }
700
701 /* Control arrives here when we're ready to return our results. */
702return_results:
703 hw->data_setup_in_cycles = data_setup_in_cycles;
704 hw->data_hold_in_cycles = data_hold_in_cycles;
705 hw->address_setup_in_cycles = address_setup_in_cycles;
706 hw->use_half_periods = dll_use_half_periods;
707 hw->sample_delay_factor = sample_delay_factor;
708
709 /* Return success. */
710 return 0;
711}
712
713/* Begin the I/O */
714void gpmi_begin(struct gpmi_nand_data *this)
715{
716 struct resources *r = &this->resources;
717 struct timing_threshod *nfc = &timing_default_threshold;
718 unsigned char *gpmi_regs = r->gpmi_regs;
719 unsigned int clock_period_in_ns;
720 uint32_t reg;
721 unsigned int dll_wait_time_in_us;
722 struct gpmi_nfc_hardware_timing hw;
723 int ret;
724
725 /* Enable the clock. */
Shawn Guof1f802c2011-12-20 14:02:05 +0800726 ret = clk_prepare_enable(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800727 if (ret) {
728 pr_err("We failed in enable the clk\n");
729 goto err_out;
730 }
731
732 /* set ready/busy timeout */
733 writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
734 gpmi_regs + HW_GPMI_TIMING1);
735
736 /* Get the timing information we need. */
737 nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
738 clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
739
740 gpmi_nfc_compute_hardware_timing(this, &hw);
741
742 /* Set up all the simple timing parameters. */
743 reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
744 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
745 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
746
747 writel(reg, gpmi_regs + HW_GPMI_TIMING0);
748
749 /*
750 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
751 */
752 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
753
754 /* Clear out the DLL control fields. */
755 writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
756 writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
757
758 /* If no sample delay is called for, return immediately. */
759 if (!hw.sample_delay_factor)
760 return;
761
762 /* Configure the HALF_PERIOD flag. */
763 if (hw.use_half_periods)
764 writel(BM_GPMI_CTRL1_HALF_PERIOD,
765 gpmi_regs + HW_GPMI_CTRL1_SET);
766
767 /* Set the delay factor. */
768 writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
769 gpmi_regs + HW_GPMI_CTRL1_SET);
770
771 /* Enable the DLL. */
772 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
773
774 /*
775 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
776 * we can use the GPMI.
777 *
778 * Calculate the amount of time we need to wait, in microseconds.
779 */
780 dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
781
782 if (!dll_wait_time_in_us)
783 dll_wait_time_in_us = 1;
784
785 /* Wait for the DLL to settle. */
786 udelay(dll_wait_time_in_us);
787
788err_out:
789 return;
790}
791
792void gpmi_end(struct gpmi_nand_data *this)
793{
794 struct resources *r = &this->resources;
Shawn Guof1f802c2011-12-20 14:02:05 +0800795 clk_disable_unprepare(r->clock);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800796}
797
798/* Clears a BCH interrupt. */
799void gpmi_clear_bch(struct gpmi_nand_data *this)
800{
801 struct resources *r = &this->resources;
802 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
803}
804
805/* Returns the Ready/Busy status of the given chip. */
806int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
807{
808 struct resources *r = &this->resources;
809 uint32_t mask = 0;
810 uint32_t reg = 0;
811
812 if (GPMI_IS_MX23(this)) {
813 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
814 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
815 } else if (GPMI_IS_MX28(this)) {
816 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
817 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
818 } else
819 pr_err("unknow arch.\n");
820 return reg & mask;
821}
822
823static inline void set_dma_type(struct gpmi_nand_data *this,
824 enum dma_ops_type type)
825{
826 this->last_dma_type = this->dma_type;
827 this->dma_type = type;
828}
829
830int gpmi_send_command(struct gpmi_nand_data *this)
831{
832 struct dma_chan *channel = get_dma_chan(this);
833 struct dma_async_tx_descriptor *desc;
834 struct scatterlist *sgl;
835 int chip = this->current_chip;
836 u32 pio[3];
837
838 /* [1] send out the PIO words */
839 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
840 | BM_GPMI_CTRL0_WORD_LENGTH
841 | BF_GPMI_CTRL0_CS(chip, this)
842 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
843 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
844 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
845 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
846 pio[1] = pio[2] = 0;
Alexandre Bounine16052822012-03-08 16:11:18 -0500847 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800848 (struct scatterlist *)pio,
Shawn Guo0ef7e202011-12-13 23:48:06 +0800849 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800850 if (!desc) {
851 pr_err("step 1 error\n");
852 return -1;
853 }
854
855 /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
856 sgl = &this->cmd_sgl;
857
858 sg_init_one(sgl, this->cmd_buffer, this->command_length);
859 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
Linus Torvalds623ff772012-03-30 17:31:56 -0700860 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie921de862012-02-16 14:17:33 +0800861 sgl, 1, DMA_MEM_TO_DEV,
862 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
863
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800864 if (!desc) {
865 pr_err("step 2 error\n");
866 return -1;
867 }
868
869 /* [3] submit the DMA */
870 set_dma_type(this, DMA_FOR_COMMAND);
871 return start_dma_without_bch_irq(this, desc);
872}
873
874int gpmi_send_data(struct gpmi_nand_data *this)
875{
876 struct dma_async_tx_descriptor *desc;
877 struct dma_chan *channel = get_dma_chan(this);
878 int chip = this->current_chip;
879 uint32_t command_mode;
880 uint32_t address;
881 u32 pio[2];
882
883 /* [1] PIO */
884 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
885 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
886
887 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
888 | BM_GPMI_CTRL0_WORD_LENGTH
889 | BF_GPMI_CTRL0_CS(chip, this)
890 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
891 | BF_GPMI_CTRL0_ADDRESS(address)
892 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
893 pio[1] = 0;
Alexandre Bounine16052822012-03-08 16:11:18 -0500894 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
Shawn Guo0ef7e202011-12-13 23:48:06 +0800895 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800896 if (!desc) {
897 pr_err("step 1 error\n");
898 return -1;
899 }
900
901 /* [2] send DMA request */
902 prepare_data_dma(this, DMA_TO_DEVICE);
Alexandre Bounine16052822012-03-08 16:11:18 -0500903 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
Huang Shijie921de862012-02-16 14:17:33 +0800904 1, DMA_MEM_TO_DEV,
905 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800906 if (!desc) {
907 pr_err("step 2 error\n");
908 return -1;
909 }
910 /* [3] submit the DMA */
911 set_dma_type(this, DMA_FOR_WRITE_DATA);
912 return start_dma_without_bch_irq(this, desc);
913}
914
915int gpmi_read_data(struct gpmi_nand_data *this)
916{
917 struct dma_async_tx_descriptor *desc;
918 struct dma_chan *channel = get_dma_chan(this);
919 int chip = this->current_chip;
920 u32 pio[2];
921
922 /* [1] : send PIO */
923 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
924 | BM_GPMI_CTRL0_WORD_LENGTH
925 | BF_GPMI_CTRL0_CS(chip, this)
926 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
927 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
928 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
929 pio[1] = 0;
Alexandre Bounine16052822012-03-08 16:11:18 -0500930 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800931 (struct scatterlist *)pio,
Shawn Guo0ef7e202011-12-13 23:48:06 +0800932 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800933 if (!desc) {
934 pr_err("step 1 error\n");
935 return -1;
936 }
937
938 /* [2] : send DMA request */
939 prepare_data_dma(this, DMA_FROM_DEVICE);
Alexandre Bounine16052822012-03-08 16:11:18 -0500940 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
Huang Shijie921de862012-02-16 14:17:33 +0800941 1, DMA_DEV_TO_MEM,
942 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800943 if (!desc) {
944 pr_err("step 2 error\n");
945 return -1;
946 }
947
948 /* [3] : submit the DMA */
949 set_dma_type(this, DMA_FOR_READ_DATA);
950 return start_dma_without_bch_irq(this, desc);
951}
952
953int gpmi_send_page(struct gpmi_nand_data *this,
954 dma_addr_t payload, dma_addr_t auxiliary)
955{
956 struct bch_geometry *geo = &this->bch_geometry;
957 uint32_t command_mode;
958 uint32_t address;
959 uint32_t ecc_command;
960 uint32_t buffer_mask;
961 struct dma_async_tx_descriptor *desc;
962 struct dma_chan *channel = get_dma_chan(this);
963 int chip = this->current_chip;
964 u32 pio[6];
965
966 /* A DMA descriptor that does an ECC page read. */
967 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
968 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
969 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
970 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
971 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
972
973 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
974 | BM_GPMI_CTRL0_WORD_LENGTH
975 | BF_GPMI_CTRL0_CS(chip, this)
976 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
977 | BF_GPMI_CTRL0_ADDRESS(address)
978 | BF_GPMI_CTRL0_XFER_COUNT(0);
979 pio[1] = 0;
980 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
981 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
982 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
983 pio[3] = geo->page_size;
984 pio[4] = payload;
985 pio[5] = auxiliary;
986
Linus Torvalds623ff772012-03-30 17:31:56 -0700987 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800988 (struct scatterlist *)pio,
Huang Shijie921de862012-02-16 14:17:33 +0800989 ARRAY_SIZE(pio), DMA_TRANS_NONE,
990 DMA_CTRL_ACK);
Huang Shijie45dfc1a2011-09-08 10:47:10 +0800991 if (!desc) {
992 pr_err("step 2 error\n");
993 return -1;
994 }
995 set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
996 return start_dma_with_bch_irq(this, desc);
997}
998
999int gpmi_read_page(struct gpmi_nand_data *this,
1000 dma_addr_t payload, dma_addr_t auxiliary)
1001{
1002 struct bch_geometry *geo = &this->bch_geometry;
1003 uint32_t command_mode;
1004 uint32_t address;
1005 uint32_t ecc_command;
1006 uint32_t buffer_mask;
1007 struct dma_async_tx_descriptor *desc;
1008 struct dma_chan *channel = get_dma_chan(this);
1009 int chip = this->current_chip;
1010 u32 pio[6];
1011
1012 /* [1] Wait for the chip to report ready. */
1013 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1014 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1015
1016 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1017 | BM_GPMI_CTRL0_WORD_LENGTH
1018 | BF_GPMI_CTRL0_CS(chip, this)
1019 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1020 | BF_GPMI_CTRL0_ADDRESS(address)
1021 | BF_GPMI_CTRL0_XFER_COUNT(0);
1022 pio[1] = 0;
Alexandre Bounine16052822012-03-08 16:11:18 -05001023 desc = dmaengine_prep_slave_sg(channel,
Shawn Guo0ef7e202011-12-13 23:48:06 +08001024 (struct scatterlist *)pio, 2,
1025 DMA_TRANS_NONE, 0);
Huang Shijie45dfc1a2011-09-08 10:47:10 +08001026 if (!desc) {
1027 pr_err("step 1 error\n");
1028 return -1;
1029 }
1030
1031 /* [2] Enable the BCH block and read. */
1032 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1033 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1034 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1035 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1036 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1037
1038 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1039 | BM_GPMI_CTRL0_WORD_LENGTH
1040 | BF_GPMI_CTRL0_CS(chip, this)
1041 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1042 | BF_GPMI_CTRL0_ADDRESS(address)
1043 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1044
1045 pio[1] = 0;
1046 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1047 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1048 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1049 pio[3] = geo->page_size;
1050 pio[4] = payload;
1051 pio[5] = auxiliary;
Alexandre Bounine16052822012-03-08 16:11:18 -05001052 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie45dfc1a2011-09-08 10:47:10 +08001053 (struct scatterlist *)pio,
Huang Shijie921de862012-02-16 14:17:33 +08001054 ARRAY_SIZE(pio), DMA_TRANS_NONE,
1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Huang Shijie45dfc1a2011-09-08 10:47:10 +08001056 if (!desc) {
1057 pr_err("step 2 error\n");
1058 return -1;
1059 }
1060
1061 /* [3] Disable the BCH block */
1062 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1063 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1064
1065 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1066 | BM_GPMI_CTRL0_WORD_LENGTH
1067 | BF_GPMI_CTRL0_CS(chip, this)
1068 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1069 | BF_GPMI_CTRL0_ADDRESS(address)
1070 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1071 pio[1] = 0;
Huang Shijie09ef90d2012-03-12 10:22:18 +08001072 pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
Alexandre Bounine16052822012-03-08 16:11:18 -05001073 desc = dmaengine_prep_slave_sg(channel,
Huang Shijie09ef90d2012-03-12 10:22:18 +08001074 (struct scatterlist *)pio, 3,
Huang Shijie921de862012-02-16 14:17:33 +08001075 DMA_TRANS_NONE,
1076 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Huang Shijie45dfc1a2011-09-08 10:47:10 +08001077 if (!desc) {
1078 pr_err("step 3 error\n");
1079 return -1;
1080 }
1081
1082 /* [4] submit the DMA */
1083 set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1084 return start_dma_with_bch_irq(this, desc);
1085}