| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*-*- linux-c -*- |
| 2 | * linux/drivers/video/i810_regs.h -- Intel 810/815 Register List |
| 3 | * |
| 4 | * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> |
| 5 | * All Rights Reserved |
| 6 | * |
| 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file COPYING in the main directory of this archive for |
| 10 | * more details. |
| 11 | */ |
| 12 | |
| 13 | |
| 14 | /* |
| 15 | * Intel 810 Chipset Family PRM 15 3.1 |
| 16 | * GC Register Memory Address Map |
| 17 | * |
| 18 | * Based on: |
| 19 | * Intel (R) 810 Chipset Family |
| 20 | * Programmer s Reference Manual |
| 21 | * November 1999 |
| 22 | * Revision 1.0 |
| 23 | * Order Number: 298026-001 R |
| 24 | * |
| 25 | * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers |
| 26 | * are I/O mapped. |
| 27 | */ |
| 28 | |
| 29 | #ifndef __I810_REGS_H__ |
| 30 | #define __I810_REGS_H__ |
| 31 | |
| 32 | /* Instruction and Interrupt Control Registers (01000h 02FFFh) */ |
| 33 | #define FENCE 0x02000 |
| 34 | #define PGTBL_CTL 0x02020 |
| 35 | #define PGTBL_ER 0x02024 |
| 36 | #define LRING 0x02030 |
| 37 | #define IRING 0x02040 |
| 38 | #define HWS_PGA 0x02080 |
| 39 | #define IPEIR 0x02088 |
| 40 | #define IPEHR 0x0208C |
| 41 | #define INSTDONE 0x02090 |
| 42 | #define NOPID 0x02094 |
| 43 | #define HWSTAM 0x02098 |
| 44 | #define IER 0x020A0 |
| 45 | #define IIR 0x020A4 |
| 46 | #define IMR 0x020A8 |
| 47 | #define ISR 0x020AC |
| 48 | #define EIR 0x020B0 |
| 49 | #define EMR 0x020B4 |
| 50 | #define ESR 0x020B8 |
| 51 | #define INSTPM 0x020C0 |
| 52 | #define INSTPS 0x020C4 |
| 53 | #define BBP_PTR 0x020C8 |
| 54 | #define ABB_SRT 0x020CC |
| 55 | #define ABB_END 0x020D0 |
| 56 | #define DMA_FADD 0x020D4 |
| 57 | #define FW_BLC 0x020D8 |
| 58 | #define MEM_MODE 0x020DC |
| 59 | |
| 60 | /* Memory Control Registers (03000h 03FFFh) */ |
| 61 | #define DRT 0x03000 |
| 62 | #define DRAMCL 0x03001 |
| 63 | #define DRAMCH 0x03002 |
| 64 | |
| 65 | |
| 66 | /* Span Cursor Registers (04000h 04FFFh) */ |
| 67 | #define UI_SC_CTL 0x04008 |
| 68 | |
| 69 | /* I/O Control Registers (05000h 05FFFh) */ |
| 70 | #define HVSYNC 0x05000 |
| 71 | #define GPIOA 0x05010 |
| 72 | #define GPIOB 0x05014 |
| Antonino A. Daplas | 5fab851 | 2005-11-07 01:00:50 -0800 | [diff] [blame] | 73 | #define GPIOC 0x0501C |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* Clock Control and Power Management Registers (06000h 06FFFh) */ |
| 76 | #define DCLK_0D 0x06000 |
| 77 | #define DCLK_1D 0x06004 |
| 78 | #define DCLK_2D 0x06008 |
| 79 | #define LCD_CLKD 0x0600C |
| 80 | #define DCLK_0DS 0x06010 |
| 81 | #define PWR_CLKC 0x06014 |
| 82 | |
| 83 | /* Graphics Translation Table Range Definition (10000h 1FFFFh) */ |
| 84 | #define GTT 0x10000 |
| 85 | |
| 86 | /* Overlay Registers (30000h 03FFFFh) */ |
| 87 | #define OVOADDR 0x30000 |
| 88 | #define DOVOSTA 0x30008 |
| 89 | #define GAMMA 0x30010 |
| 90 | #define OBUF_0Y 0x30100 |
| 91 | #define OBUF_1Y 0x30104 |
| 92 | #define OBUF_0U 0x30108 |
| 93 | #define OBUF_0V 0x3010C |
| 94 | #define OBUF_1U 0x30110 |
| 95 | #define OBUF_1V 0x30114 |
| 96 | #define OVOSTRIDE 0x30118 |
| 97 | #define YRGB_VPH 0x3011C |
| 98 | #define UV_VPH 0x30120 |
| 99 | #define HORZ_PH 0x30124 |
| 100 | #define INIT_PH 0x30128 |
| 101 | #define DWINPOS 0x3012C |
| 102 | #define DWINSZ 0x30130 |
| 103 | #define SWID 0x30134 |
| 104 | #define SWIDQW 0x30138 |
| 105 | #define SHEIGHT 0x3013F |
| 106 | #define YRGBSCALE 0x30140 |
| 107 | #define UVSCALE 0x30144 |
| 108 | #define OVOCLRCO 0x30148 |
| 109 | #define OVOCLRC1 0x3014C |
| 110 | #define DCLRKV 0x30150 |
| 111 | #define DLCRKM 0x30154 |
| 112 | #define SCLRKVH 0x30158 |
| 113 | #define SCLRKVL 0x3015C |
| 114 | #define SCLRKM 0x30160 |
| 115 | #define OVOCONF 0x30164 |
| 116 | #define OVOCMD 0x30168 |
| 117 | #define AWINPOS 0x30170 |
| 118 | #define AWINZ 0x30174 |
| 119 | |
| 120 | /* BLT Engine Status (40000h 4FFFFh) (Software Debug) */ |
| 121 | #define BR00 0x40000 |
| 122 | #define BRO1 0x40004 |
| 123 | #define BR02 0x40008 |
| 124 | #define BR03 0x4000C |
| 125 | #define BR04 0x40010 |
| 126 | #define BR05 0x40014 |
| 127 | #define BR06 0x40018 |
| 128 | #define BR07 0x4001C |
| 129 | #define BR08 0x40020 |
| 130 | #define BR09 0x40024 |
| 131 | #define BR10 0x40028 |
| 132 | #define BR11 0x4002C |
| 133 | #define BR12 0x40030 |
| 134 | #define BR13 0x40034 |
| 135 | #define BR14 0x40038 |
| 136 | #define BR15 0x4003C |
| 137 | #define BR16 0x40040 |
| 138 | #define BR17 0x40044 |
| 139 | #define BR18 0x40048 |
| 140 | #define BR19 0x4004C |
| 141 | #define SSLADD 0x40074 |
| 142 | #define DSLH 0x40078 |
| 143 | #define DSLRADD 0x4007C |
| 144 | |
| 145 | |
| 146 | /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */ |
| 147 | /* LCD/TV-Out */ |
| 148 | #define HTOTAL 0x60000 |
| 149 | #define HBLANK 0x60004 |
| 150 | #define HSYNC 0x60008 |
| 151 | #define VTOTAL 0x6000C |
| 152 | #define VBLANK 0x60010 |
| 153 | #define VSYNC 0x60014 |
| 154 | #define LCDTV_C 0x60018 |
| 155 | #define OVRACT 0x6001C |
| 156 | #define BCLRPAT 0x60020 |
| 157 | |
| 158 | /* Display and Cursor Control Registers (70000h 7FFFFh) */ |
| 159 | #define DISP_SL 0x70000 |
| 160 | #define DISP_SLC 0x70004 |
| 161 | #define PIXCONF 0x70008 |
| 162 | #define PIXCONF1 0x70009 |
| 163 | #define BLTCNTL 0x7000C |
| 164 | #define SWF 0x70014 |
| 165 | #define DPLYBASE 0x70020 |
| 166 | #define DPLYSTAS 0x70024 |
| 167 | #define CURCNTR 0x70080 |
| 168 | #define CURBASE 0x70084 |
| 169 | #define CURPOS 0x70088 |
| 170 | |
| 171 | |
| 172 | /* VGA Registers */ |
| 173 | |
| 174 | /* SMRAM Registers */ |
| 175 | #define SMRAM 0x10 |
| 176 | |
| 177 | /* Graphics Control Registers */ |
| 178 | #define GR_INDEX 0x3CE |
| 179 | #define GR_DATA 0x3CF |
| 180 | |
| 181 | #define GR10 0x10 |
| 182 | #define GR11 0x11 |
| 183 | |
| 184 | /* CRT Controller Registers */ |
| 185 | #define CR_INDEX_MDA 0x3B4 |
| 186 | #define CR_INDEX_CGA 0x3D4 |
| 187 | #define CR_DATA_MDA 0x3B5 |
| 188 | #define CR_DATA_CGA 0x3D5 |
| 189 | |
| 190 | #define CR30 0x30 |
| 191 | #define CR31 0x31 |
| 192 | #define CR32 0x32 |
| 193 | #define CR33 0x33 |
| 194 | #define CR35 0x35 |
| 195 | #define CR39 0x39 |
| 196 | #define CR40 0x40 |
| 197 | #define CR41 0x41 |
| 198 | #define CR42 0x42 |
| 199 | #define CR70 0x70 |
| 200 | #define CR80 0x80 |
| 201 | #define CR81 0x82 |
| 202 | |
| 203 | /* Extended VGA Registers */ |
| 204 | |
| 205 | /* General Control and Status Registers */ |
| 206 | #define ST00 0x3C2 |
| 207 | #define ST01_MDA 0x3BA |
| 208 | #define ST01_CGA 0x3DA |
| 209 | #define FRC_READ 0x3CA |
| 210 | #define FRC_WRITE_MDA 0x3BA |
| 211 | #define FRC_WRITE_CGA 0x3DA |
| 212 | #define MSR_READ 0x3CC |
| 213 | #define MSR_WRITE 0x3C2 |
| 214 | |
| 215 | /* Sequencer Registers */ |
| 216 | #define SR_INDEX 0x3C4 |
| 217 | #define SR_DATA 0x3C5 |
| 218 | |
| 219 | #define SR01 0x01 |
| 220 | #define SR02 0x02 |
| 221 | #define SR03 0x03 |
| 222 | #define SR04 0x04 |
| 223 | #define SR07 0x07 |
| 224 | |
| 225 | /* Graphics Controller Registers */ |
| 226 | #define GR00 0x00 |
| 227 | #define GR01 0x01 |
| 228 | #define GR02 0x02 |
| 229 | #define GR03 0x03 |
| 230 | #define GR04 0x04 |
| 231 | #define GR05 0x05 |
| 232 | #define GR06 0x06 |
| 233 | #define GR07 0x07 |
| 234 | #define GR08 0x08 |
| 235 | |
| 236 | /* Attribute Controller Registers */ |
| 237 | #define ATTR_WRITE 0x3C0 |
| 238 | #define ATTR_READ 0x3C1 |
| 239 | |
| 240 | /* VGA Color Palette Registers */ |
| 241 | |
| 242 | /* CLUT */ |
| 243 | #define CLUT_DATA 0x3C9 /* DACDATA */ |
| 244 | #define CLUT_INDEX_READ 0x3C7 /* DACRX */ |
| 245 | #define CLUT_INDEX_WRITE 0x3C8 /* DACWX */ |
| 246 | #define DACMASK 0x3C6 |
| 247 | |
| 248 | /* CRT Controller Registers */ |
| 249 | #define CR00 0x00 |
| 250 | #define CR01 0x01 |
| 251 | #define CR02 0x02 |
| 252 | #define CR03 0x03 |
| 253 | #define CR04 0x04 |
| 254 | #define CR05 0x05 |
| 255 | #define CR06 0x06 |
| 256 | #define CR07 0x07 |
| 257 | #define CR08 0x08 |
| 258 | #define CR09 0x09 |
| 259 | #define CR0A 0x0A |
| 260 | #define CR0B 0x0B |
| 261 | #define CR0C 0x0C |
| 262 | #define CR0D 0x0D |
| 263 | #define CR0E 0x0E |
| 264 | #define CR0F 0x0F |
| 265 | #define CR10 0x10 |
| 266 | #define CR11 0x11 |
| 267 | #define CR12 0x12 |
| 268 | #define CR13 0x13 |
| 269 | #define CR14 0x14 |
| 270 | #define CR15 0x15 |
| 271 | #define CR16 0x16 |
| 272 | #define CR17 0x17 |
| 273 | #define CR18 0x18 |
| 274 | |
| 275 | #endif /* __I810_REGS_H__ */ |