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review.evervolv.com / android_kernel_htc_msm8960 / b82cab6b331b51d82f90d2207f3bbfdf09361ac9 / . / drivers / ieee1394 / ohci1394.h
blob: cc66c1cae250c1cb105599810637e1ff77ba58bb [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * ohci1394.h - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef _OHCI1394_H
22#define _OHCI1394_H
23
24#include "ieee1394_types.h"
25#include <asm/io.h>
26
27#define OHCI1394_DRIVER_NAME "ohci1394"
28
29#define OHCI1394_MAX_AT_REQ_RETRIES 0x2
30#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
31#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
32#define OHCI1394_MAX_SELF_ID_ERRORS 16
33
34#define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */
35#define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */
36#define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
37
38#define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */
39#define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */
40#define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
41
42#define IR_NUM_DESC 16 /* number of IR descriptors */
43#define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */
44#define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
45
46#define IT_NUM_DESC 16 /* number of IT descriptors */
47
48#define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */
49#define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */
50
51#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
52
53#define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */
54
55#define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer */
56
57/* PCI configuration space addresses */
58#define OHCI1394_PCI_HCI_Control 0x40
59
60struct dma_cmd {
61 u32 control;
62 u32 address;
63 u32 branchAddress;
64 u32 status;
65};
66
67/*
68 * FIXME:
69 * It is important that a single at_dma_prg does not cross a page boundary
70 * The proper way to do it would be to do the check dynamically as the
71 * programs are inserted into the AT fifo.
72 */
73struct at_dma_prg {
74 struct dma_cmd begin;
75 quadlet_t data[4];
76 struct dma_cmd end;
77 quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
78};
79
80/* identify whether a DMA context is asynchronous or isochronous */
81enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO };
82
83/* DMA receive context */
84struct dma_rcv_ctx {
85 struct ti_ohci *ohci;
86 enum context_type type;
87 int ctx;
88 unsigned int num_desc;
89
90 unsigned int buf_size;
91 unsigned int split_buf_size;
92
93 /* dma block descriptors */
94 struct dma_cmd **prg_cpu;
95 dma_addr_t *prg_bus;
96 struct pci_pool *prg_pool;
97
98 /* dma buffers */
99 quadlet_t **buf_cpu;
100 dma_addr_t *buf_bus;
101
102 unsigned int buf_ind;
103 unsigned int buf_offset;
104 quadlet_t *spb;
105 spinlock_t lock;
106 struct tasklet_struct task;
107 int ctrlClear;
108 int ctrlSet;
109 int cmdPtr;
110 int ctxtMatch;
111};
112
113/* DMA transmit context */
114struct dma_trm_ctx {
115 struct ti_ohci *ohci;
116 enum context_type type;
117 int ctx;
118 unsigned int num_desc;
119
120 /* dma block descriptors */
121 struct at_dma_prg **prg_cpu;
122 dma_addr_t *prg_bus;
123 struct pci_pool *prg_pool;
124
125 unsigned int prg_ind;
126 unsigned int sent_ind;
127 int free_prgs;
128 quadlet_t *branchAddrPtr;
129
130 /* list of packets inserted in the AT FIFO */
131 struct list_head fifo_list;
132
133 /* list of pending packets to be inserted in the AT FIFO */
134 struct list_head pending_list;
135
136 spinlock_t lock;
137 struct tasklet_struct task;
138 int ctrlClear;
139 int ctrlSet;
140 int cmdPtr;
141};
142
143struct ohci1394_iso_tasklet {
144 struct tasklet_struct tasklet;
145 struct list_head link;
146 int context;
147 enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE,
148 OHCI_ISO_MULTICHANNEL_RECEIVE } type;
149};
150
151struct ti_ohci {
152 struct pci_dev *dev;
153
154 enum {
155 OHCI_INIT_ALLOC_HOST,
156 OHCI_INIT_HAVE_MEM_REGION,
157 OHCI_INIT_HAVE_IOMAPPING,
158 OHCI_INIT_HAVE_CONFIG_ROM_BUFFER,
159 OHCI_INIT_HAVE_SELFID_BUFFER,
160 OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE,
161 OHCI_INIT_HAVE_IRQ,
162 OHCI_INIT_DONE,
163 } init_state;
164
165 /* remapped memory spaces */
166 void __iomem *registers;
167
168 /* dma buffer for self-id packets */
169 quadlet_t *selfid_buf_cpu;
170 dma_addr_t selfid_buf_bus;
171
172 /* buffer for csr config rom */
173 quadlet_t *csr_config_rom_cpu;
174 dma_addr_t csr_config_rom_bus;
175 int csr_config_rom_length;
176
177 unsigned int max_packet_size;
178
179 /* async receive */
180 struct dma_rcv_ctx ar_resp_context;
181 struct dma_rcv_ctx ar_req_context;
182
183 /* async transmit */
184 struct dma_trm_ctx at_resp_context;
185 struct dma_trm_ctx at_req_context;
186
187 /* iso receive */
188 int nb_iso_rcv_ctx;
189 unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */
190 unsigned long ir_multichannel_used; /* ditto */
191 spinlock_t IR_channel_lock;
192
193 /* iso receive (legacy API) */
194 u64 ir_legacy_channels; /* note: this differs from ISO_channel_usage;
195 it only accounts for channels listened to
196 by the legacy API, so that we can know when
197 it is safe to free the legacy API context */
198
199 struct dma_rcv_ctx ir_legacy_context;
200 struct ohci1394_iso_tasklet ir_legacy_tasklet;
201
202 /* iso transmit */
203 int nb_iso_xmit_ctx;
204 unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */
205
206 /* iso transmit (legacy API) */
207 struct dma_trm_ctx it_legacy_context;
208 struct ohci1394_iso_tasklet it_legacy_tasklet;
209
210 u64 ISO_channel_usage;
211
212 /* IEEE-1394 part follows */
213 struct hpsb_host *host;
214
215 int phyid, isroot;
216
217 spinlock_t phy_reg_lock;
218 spinlock_t event_lock;
219
220 int self_id_errors;
221
222 /* Tasklets for iso receive and transmit, used by video1394,
223 * amdtp and dv1394 */
224
225 struct list_head iso_tasklet_list;
226 spinlock_t iso_tasklet_list_lock;
227
228 /* Swap the selfid buffer? */
229 unsigned int selfid_swap:1;
230 /* Some Apple chipset seem to swap incoming headers for us */
231 unsigned int no_swap_incoming:1;
232
233 /* Force extra paranoia checking on bus-reset handling */
234 unsigned int check_busreset:1;
235};
236
237static inline int cross_bound(unsigned long addr, unsigned int size)
238{
Jody McIntyre74a01d12005-05-16 21:54:05 -0700[diff] [blame]239 if (size == 0)
240 return 0;
241
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]242 if (size > PAGE_SIZE)
243 return 1;
244
245 if (addr >> PAGE_SHIFT != (addr + size - 1) >> PAGE_SHIFT)
246 return 1;
247
248 return 0;
249}
250
251/*
252 * Register read and write helper functions.
253 */
254static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
255{
256 writel(data, ohci->registers + offset);
257}
258
259static inline u32 reg_read(const struct ti_ohci *ohci, int offset)
260{
261 return readl(ohci->registers + offset);
262}
263
264
265/* 2 KiloBytes of register space */
266#define OHCI1394_REGISTER_SIZE 0x800
267
268/* Offsets relative to context bases defined below */
269
270#define OHCI1394_ContextControlSet 0x000
271#define OHCI1394_ContextControlClear 0x004
272#define OHCI1394_ContextCommandPtr 0x00C
273
274/* register map */
275#define OHCI1394_Version 0x000
276#define OHCI1394_GUID_ROM 0x004
277#define OHCI1394_ATRetries 0x008
278#define OHCI1394_CSRData 0x00C
279#define OHCI1394_CSRCompareData 0x010
280#define OHCI1394_CSRControl 0x014
281#define OHCI1394_ConfigROMhdr 0x018
282#define OHCI1394_BusID 0x01C
283#define OHCI1394_BusOptions 0x020
284#define OHCI1394_GUIDHi 0x024
285#define OHCI1394_GUIDLo 0x028
286#define OHCI1394_ConfigROMmap 0x034
287#define OHCI1394_PostedWriteAddressLo 0x038
288#define OHCI1394_PostedWriteAddressHi 0x03C
289#define OHCI1394_VendorID 0x040
290#define OHCI1394_HCControlSet 0x050
291#define OHCI1394_HCControlClear 0x054
292#define OHCI1394_HCControl_noByteSwap 0x40000000
293#define OHCI1394_HCControl_programPhyEnable 0x00800000
294#define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
295#define OHCI1394_HCControl_LPS 0x00080000
296#define OHCI1394_HCControl_postedWriteEnable 0x00040000
297#define OHCI1394_HCControl_linkEnable 0x00020000
298#define OHCI1394_HCControl_softReset 0x00010000
299#define OHCI1394_SelfIDBuffer 0x064
300#define OHCI1394_SelfIDCount 0x068
301#define OHCI1394_IRMultiChanMaskHiSet 0x070
302#define OHCI1394_IRMultiChanMaskHiClear 0x074
303#define OHCI1394_IRMultiChanMaskLoSet 0x078
304#define OHCI1394_IRMultiChanMaskLoClear 0x07C
305#define OHCI1394_IntEventSet 0x080
306#define OHCI1394_IntEventClear 0x084
307#define OHCI1394_IntMaskSet 0x088
308#define OHCI1394_IntMaskClear 0x08C
309#define OHCI1394_IsoXmitIntEventSet 0x090
310#define OHCI1394_IsoXmitIntEventClear 0x094
311#define OHCI1394_IsoXmitIntMaskSet 0x098
312#define OHCI1394_IsoXmitIntMaskClear 0x09C
313#define OHCI1394_IsoRecvIntEventSet 0x0A0
314#define OHCI1394_IsoRecvIntEventClear 0x0A4
315#define OHCI1394_IsoRecvIntMaskSet 0x0A8
316#define OHCI1394_IsoRecvIntMaskClear 0x0AC
317#define OHCI1394_InitialBandwidthAvailable 0x0B0
318#define OHCI1394_InitialChannelsAvailableHi 0x0B4
319#define OHCI1394_InitialChannelsAvailableLo 0x0B8
320#define OHCI1394_FairnessControl 0x0DC
321#define OHCI1394_LinkControlSet 0x0E0
322#define OHCI1394_LinkControlClear 0x0E4
323#define OHCI1394_LinkControl_RcvSelfID 0x00000200
324#define OHCI1394_LinkControl_RcvPhyPkt 0x00000400
325#define OHCI1394_LinkControl_CycleTimerEnable 0x00100000
326#define OHCI1394_LinkControl_CycleMaster 0x00200000
327#define OHCI1394_LinkControl_CycleSource 0x00400000
328#define OHCI1394_NodeID 0x0E8
329#define OHCI1394_PhyControl 0x0EC
330#define OHCI1394_IsochronousCycleTimer 0x0F0
331#define OHCI1394_AsReqFilterHiSet 0x100
332#define OHCI1394_AsReqFilterHiClear 0x104
333#define OHCI1394_AsReqFilterLoSet 0x108
334#define OHCI1394_AsReqFilterLoClear 0x10C
335#define OHCI1394_PhyReqFilterHiSet 0x110
336#define OHCI1394_PhyReqFilterHiClear 0x114
337#define OHCI1394_PhyReqFilterLoSet 0x118
338#define OHCI1394_PhyReqFilterLoClear 0x11C
339#define OHCI1394_PhyUpperBound 0x120
340
341#define OHCI1394_AsReqTrContextBase 0x180
342#define OHCI1394_AsReqTrContextControlSet 0x180
343#define OHCI1394_AsReqTrContextControlClear 0x184
344#define OHCI1394_AsReqTrCommandPtr 0x18C
345
346#define OHCI1394_AsRspTrContextBase 0x1A0
347#define OHCI1394_AsRspTrContextControlSet 0x1A0
348#define OHCI1394_AsRspTrContextControlClear 0x1A4
349#define OHCI1394_AsRspTrCommandPtr 0x1AC
350
351#define OHCI1394_AsReqRcvContextBase 0x1C0
352#define OHCI1394_AsReqRcvContextControlSet 0x1C0
353#define OHCI1394_AsReqRcvContextControlClear 0x1C4
354#define OHCI1394_AsReqRcvCommandPtr 0x1CC
355
356#define OHCI1394_AsRspRcvContextBase 0x1E0
357#define OHCI1394_AsRspRcvContextControlSet 0x1E0
358#define OHCI1394_AsRspRcvContextControlClear 0x1E4
359#define OHCI1394_AsRspRcvCommandPtr 0x1EC
360
361/* Isochronous transmit registers */
362/* Add (16 * n) for context n */
363#define OHCI1394_IsoXmitContextBase 0x200
364#define OHCI1394_IsoXmitContextControlSet 0x200
365#define OHCI1394_IsoXmitContextControlClear 0x204
366#define OHCI1394_IsoXmitCommandPtr 0x20C
367
368/* Isochronous receive registers */
369/* Add (32 * n) for context n */
370#define OHCI1394_IsoRcvContextBase 0x400
371#define OHCI1394_IsoRcvContextControlSet 0x400
372#define OHCI1394_IsoRcvContextControlClear 0x404
373#define OHCI1394_IsoRcvCommandPtr 0x40C
374#define OHCI1394_IsoRcvContextMatch 0x410
375
376/* Interrupts Mask/Events */
377
378#define OHCI1394_reqTxComplete 0x00000001
379#define OHCI1394_respTxComplete 0x00000002
380#define OHCI1394_ARRQ 0x00000004
381#define OHCI1394_ARRS 0x00000008
382#define OHCI1394_RQPkt 0x00000010
383#define OHCI1394_RSPkt 0x00000020
384#define OHCI1394_isochTx 0x00000040
385#define OHCI1394_isochRx 0x00000080
386#define OHCI1394_postedWriteErr 0x00000100
387#define OHCI1394_lockRespErr 0x00000200
388#define OHCI1394_selfIDComplete 0x00010000
389#define OHCI1394_busReset 0x00020000
390#define OHCI1394_phy 0x00080000
391#define OHCI1394_cycleSynch 0x00100000
392#define OHCI1394_cycle64Seconds 0x00200000
393#define OHCI1394_cycleLost 0x00400000
394#define OHCI1394_cycleInconsistent 0x00800000
395#define OHCI1394_unrecoverableError 0x01000000
396#define OHCI1394_cycleTooLong 0x02000000
397#define OHCI1394_phyRegRcvd 0x04000000
398#define OHCI1394_masterIntEnable 0x80000000
399
400/* DMA Control flags */
401#define DMA_CTL_OUTPUT_MORE 0x00000000
402#define DMA_CTL_OUTPUT_LAST 0x10000000
403#define DMA_CTL_INPUT_MORE 0x20000000
404#define DMA_CTL_INPUT_LAST 0x30000000
405#define DMA_CTL_UPDATE 0x08000000
406#define DMA_CTL_IMMEDIATE 0x02000000
407#define DMA_CTL_IRQ 0x00300000
408#define DMA_CTL_BRANCH 0x000c0000
409#define DMA_CTL_WAIT 0x00030000
410
411/* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */
412#define EVT_NO_STATUS 0x0 /* No event status */
413#define EVT_RESERVED_A 0x1 /* Reserved, not used !!! */
414#define EVT_LONG_PACKET 0x2 /* The revc data was longer than the buf */
415#define EVT_MISSING_ACK 0x3 /* A subaction gap was detected before an ack
416 arrived, or recv'd ack had a parity error */
417#define EVT_UNDERRUN 0x4 /* Underrun on corresponding FIFO, packet
418 truncated */
419#define EVT_OVERRUN 0x5 /* A recv FIFO overflowed on reception of ISO
420 packet */
421#define EVT_DESCRIPTOR_READ 0x6 /* An unrecoverable error occurred while host was
422 reading a descriptor block */
423#define EVT_DATA_READ 0x7 /* An error occurred while host controller was
424 attempting to read from host memory in the data
425 stage of descriptor processing */
426#define EVT_DATA_WRITE 0x8 /* An error occurred while host controller was
427 attempting to write either during the data stage
428 of descriptor processing, or when processing a single
429 16-bit host memory write */
430#define EVT_BUS_RESET 0x9 /* Identifies a PHY packet in the recv buffer as
431 being a synthesized bus reset packet */
432#define EVT_TIMEOUT 0xa /* Indicates that the asynchronous transmit response
433 packet expired and was not transmitted, or that an
434 IT DMA context experienced a skip processing overflow */
435#define EVT_TCODE_ERR 0xb /* A bad tCode is associated with this packet.
436 The packet was flushed */
437#define EVT_RESERVED_B 0xc /* Reserved, not used !!! */
438#define EVT_RESERVED_C 0xd /* Reserved, not used !!! */
439#define EVT_UNKNOWN 0xe /* An error condition has occurred that cannot be
440 represented by any other event codes defined herein. */
441#define EVT_FLUSHED 0xf /* Send by the link side of output FIFO when asynchronous
442 packets are being flushed due to a bus reset. */
443
444#define OHCI1394_TCODE_PHY 0xE
445
446void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet,
447 int type,
448 void (*func)(unsigned long),
449 unsigned long data);
450int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
451 struct ohci1394_iso_tasklet *tasklet);
452void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
453 struct ohci1394_iso_tasklet *tasklet);
454
455/* returns zero if successful, one if DMA context is locked up */
456int ohci1394_stop_context (struct ti_ohci *ohci, int reg, char *msg);
457struct ti_ohci *ohci1394_get_struct(int card_num);
458
459#endif