| Jamie Iles | 775c3220 | 2011-12-18 10:00:49 +0000 | [diff] [blame] | 1 | GPIO assisted NAND flash |
| 2 | |
| 3 | The GPIO assisted NAND flash uses a memory mapped interface to |
| 4 | read/write the NAND commands and data and GPIO pins for the control |
| 5 | signals. |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible : "gpio-control-nand" |
| 9 | - reg : should specify localbus chip select and size used for the chip. The |
| 10 | resource describes the data bus connected to the NAND flash and all accesses |
| 11 | are made in native endianness. |
| 12 | - #address-cells, #size-cells : Must be present if the device has sub-nodes |
| 13 | representing partitions. |
| 14 | - gpios : specifies the gpio pins to control the NAND device. nwp is an |
| 15 | optional gpio and may be set to 0 if not present. |
| 16 | |
| 17 | Optional properties: |
| 18 | - bank-width : Width (in bytes) of the device. If not present, the width |
| 19 | defaults to 1 byte. |
| 20 | - chip-delay : chip dependent delay for transferring data from array to |
| 21 | read registers (tR). If not present then a default of 20us is used. |
| 22 | - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read |
| 23 | location used to guard against bus reordering with regards to accesses to |
| 24 | the GPIO's and the NAND flash data bus. If present, then after changing |
| 25 | GPIO state and before and after command byte writes, this register will be |
| 26 | read to ensure that the GPIO accesses have completed. |
| 27 | |
| 28 | Examples: |
| 29 | |
| 30 | gpio-nand@1,0 { |
| 31 | compatible = "gpio-control-nand"; |
| 32 | reg = <1 0x0000 0x2>; |
| 33 | #address-cells = <1>; |
| 34 | #size-cells = <1>; |
| 35 | gpios = <&banka 1 0 /* rdy */ |
| 36 | &banka 2 0 /* nce */ |
| 37 | &banka 3 0 /* ale */ |
| 38 | &banka 4 0 /* cle */ |
| 39 | 0 /* nwp */>; |
| 40 | |
| 41 | partition@0 { |
| 42 | ... |
| 43 | }; |
| 44 | }; |