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review.evervolv.com / android_kernel_htc_msm8960 / b8b47bfbe4eb1ae0e6891e49c86a5f4fb00413be / . / arch / sh / drivers / pci / fixups-r7780rp.c
blob: 5b25021bbd62a0cb2ad63ee1fcfc9f9208ae799a [file] [log] [blame]
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]1/*
2 * arch/sh/drivers/pci/fixups-r7780rp.c
3 *
4 * Highlander R7780RP-1 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]7 * Copyright (C) 2004 - 2006 Paul Mundt
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]13#include <linux/pci.h>
14#include "pci-sh4.h"
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]15#include <asm/io.h>
16
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]17int pci_fixup_pcic(struct pci_channel *chan)
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]18{
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]19 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
20 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]21
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]22 pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
23 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]24
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]25 pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
26 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
27 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
28 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
29 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]30
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]31 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
32 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]33
34#ifdef CONFIG_32BIT
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]35 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
36 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]37#endif
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]38
39 /* Set IOBR for windows containing area specified in pci.h */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]40 pci_write_reg(chan, (PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
Paul Mundt959f85f2006-09-27 16:43:28 +0900[diff] [blame]41 SH7780_PCIIOBR);
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]42 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
43 SH7780_PCIIOBMR);
Paul Mundt5283ecb2006-09-27 15:59:17 +0900[diff] [blame]44
45 return 0;
46}