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review.evervolv.com / android_kernel_htc_msm8960 / b8b47bfbe4eb1ae0e6891e49c86a5f4fb00413be / . / arch / sh / drivers / pci / fixups-sdk7780.c
blob: 3f6754a120ed5e0e186c7ecb2a5798c5619f4fa7 [file] [log] [blame]
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]1/*
2 * arch/sh/drivers/pci/fixups-sdk7780.c
3 *
4 * PCI fixups for the SDK7780SE03
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/pci.h>
14#include "pci-sh4.h"
15#include <asm/io.h>
16
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]17int pci_fixup_pcic(struct pci_channel *chan)
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]18{
19 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
20
21 /* Enable all interrupts, so we know what to fix */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]22 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
23 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]24
25 /* Set up standard PCI config registers */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]26 pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
27 pci_write_reg(chan, 0x0047, SH7780_PCICMD);
28 pci_write_reg(chan, 0x00, SH7780_PCIPIF);
29 pci_write_reg(chan, 0x00, SH7780_PCISUB);
30 pci_write_reg(chan, 0x06, SH7780_PCIBCC);
31 pci_write_reg(chan, 0x1912, SH7780_PCISVID);
32 pci_write_reg(chan, 0x0001, SH7780_PCISID);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]33
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]34 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
35 pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
36 pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]37
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]38 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
39 pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
40 pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]41
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]42 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]43
44 /*
45 * Set the MBR so PCI address is one-to-one with window,
46 * meaning all calls go straight through... use ifdef to
47 * catch erroneous assumption.
48 */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]49 pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
50 pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]51
52 /* Set IOBR for window containing area specified in pci.h */
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]53 pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),
54 SH7780_PCIIOBR);
55 pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
56 SH7780_PCIIOBMR);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]57
Magnus Dammb8b47bf2009-03-11 15:41:51 +0900[diff] [blame^]58 pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
Nicholas Beck4862ec02008-01-23 12:50:51 +0900[diff] [blame]59
60 return 0;
61}