| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 1 | /* | 
 | 2 |  *  linux/arch/arm/mm/copypage-v4wt.S | 
 | 3 |  * | 
 | 4 |  *  Copyright (C) 1995-1999 Russell King | 
 | 5 |  * | 
 | 6 |  * This program is free software; you can redistribute it and/or modify | 
 | 7 |  * it under the terms of the GNU General Public License version 2 as | 
 | 8 |  * published by the Free Software Foundation. | 
 | 9 |  * | 
 | 10 |  *  This is for CPUs with a writethrough cache and 'flush ID cache' is | 
 | 11 |  *  the only supported cache operation. | 
 | 12 |  */ | 
 | 13 | #include <linux/init.h> | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 14 | #include <linux/highmem.h> | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 15 |  | 
 | 16 | /* | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 17 |  * ARMv4 optimised copy_user_highpage | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 18 |  * | 
 | 19 |  * Since we have writethrough caches, we don't have to worry about | 
 | 20 |  * dirty data in the cache.  However, we do have to ensure that | 
 | 21 |  * subsequent reads are up to date. | 
 | 22 |  */ | 
| Uwe Kleine-König | 446c92b | 2009-03-12 18:03:16 +0100 | [diff] [blame] | 23 | static void __naked | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 24 | v4wt_copy_user_page(void *kto, const void *kfrom) | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 25 | { | 
 | 26 | 	asm("\ | 
 | 27 | 	stmfd	sp!, {r4, lr}			@ 2\n\ | 
 | 28 | 	mov	r2, %0				@ 1\n\ | 
 | 29 | 	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 30 | 1:	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 31 | 	ldmia	r1!, {r3, r4, ip, lr}		@ 4+1\n\ | 
 | 32 | 	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 33 | 	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 34 | 	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 35 | 	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 36 | 	subs	r2, r2, #1			@ 1\n\ | 
 | 37 | 	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 38 | 	ldmneia	r1!, {r3, r4, ip, lr}		@ 4\n\ | 
 | 39 | 	bne	1b				@ 1\n\ | 
 | 40 | 	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache\n\ | 
 | 41 | 	ldmfd	sp!, {r4, pc}			@ 3" | 
 | 42 | 	: | 
 | 43 | 	: "I" (PAGE_SIZE / 64)); | 
 | 44 | } | 
 | 45 |  | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 46 | void v4wt_copy_user_highpage(struct page *to, struct page *from, | 
| Russell King | f00a75c | 2009-10-05 15:17:45 +0100 | [diff] [blame] | 47 | 	unsigned long vaddr, struct vm_area_struct *vma) | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 48 | { | 
 | 49 | 	void *kto, *kfrom; | 
 | 50 |  | 
 | 51 | 	kto = kmap_atomic(to, KM_USER0); | 
 | 52 | 	kfrom = kmap_atomic(from, KM_USER1); | 
 | 53 | 	v4wt_copy_user_page(kto, kfrom); | 
 | 54 | 	kunmap_atomic(kfrom, KM_USER1); | 
 | 55 | 	kunmap_atomic(kto, KM_USER0); | 
 | 56 | } | 
 | 57 |  | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 58 | /* | 
 | 59 |  * ARMv4 optimised clear_user_page | 
 | 60 |  * | 
 | 61 |  * Same story as above. | 
 | 62 |  */ | 
| Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 63 | void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 64 | { | 
| Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 65 | 	void *ptr, *kaddr = kmap_atomic(page, KM_USER0); | 
 | 66 | 	asm volatile("\ | 
 | 67 | 	mov	r1, %2				@ 1\n\ | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 68 | 	mov	r2, #0				@ 1\n\ | 
 | 69 | 	mov	r3, #0				@ 1\n\ | 
 | 70 | 	mov	ip, #0				@ 1\n\ | 
 | 71 | 	mov	lr, #0				@ 1\n\ | 
| Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 72 | 1:	stmia	%0!, {r2, r3, ip, lr}		@ 4\n\ | 
 | 73 | 	stmia	%0!, {r2, r3, ip, lr}		@ 4\n\ | 
 | 74 | 	stmia	%0!, {r2, r3, ip, lr}		@ 4\n\ | 
 | 75 | 	stmia	%0!, {r2, r3, ip, lr}		@ 4\n\ | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 76 | 	subs	r1, r1, #1			@ 1\n\ | 
 | 77 | 	bne	1b				@ 1\n\ | 
| Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 78 | 	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache" | 
| Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 79 | 	: "=r" (ptr) | 
 | 80 | 	: "0" (kaddr), "I" (PAGE_SIZE / 64) | 
| Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 81 | 	: "r1", "r2", "r3", "ip", "lr"); | 
 | 82 | 	kunmap_atomic(kaddr, KM_USER0); | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 83 | } | 
 | 84 |  | 
 | 85 | struct cpu_user_fns v4wt_user_fns __initdata = { | 
| Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 86 | 	.cpu_clear_user_highpage = v4wt_clear_user_highpage, | 
| Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 87 | 	.cpu_copy_user_highpage	= v4wt_copy_user_highpage, | 
| Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 88 | }; |