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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053019#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080021
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <linux/leds.h>
23#include <linux/pmic8058-othc.h>
24#include <linux/mfd/pmic8901.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <linux/regulator/pmic8901-regulator.h>
26#include <linux/bootmem.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070027#include <linux/msm_adc.h>
28#include <linux/m_adcproc.h>
29#include <linux/mfd/marimba.h>
30#include <linux/msm-charger.h>
31#include <linux/i2c.h>
32#include <linux/i2c/sx150x.h>
33#include <linux/smsc911x.h>
34#include <linux/spi/spi.h>
35#include <linux/input/tdisc_shinetsu.h>
36#include <linux/input/cy8c_ts.h>
37#include <linux/cyttsp.h>
38#include <linux/i2c/isa1200.h>
39#include <linux/dma-mapping.h>
40#include <linux/i2c/bq27520.h>
41
42#ifdef CONFIG_ANDROID_PMEM
43#include <linux/android_pmem.h>
44#endif
45
46#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
47#include <linux/i2c/smb137b.h>
48#endif
Lei Zhou338cab82011-08-19 13:38:17 -040049#ifdef CONFIG_SND_SOC_WM8903
50#include <sound/wm8903.h>
51#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080052#include <asm/mach-types.h>
53#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080055
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#include <mach/dma.h>
57#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080058#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#include <mach/irqs.h>
60#include <mach/msm_spi.h>
61#include <mach/msm_serial_hs.h>
62#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080063#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064#include <mach/msm_memtypes.h>
65#include <asm/mach/mmc.h>
66#include <mach/msm_battery.h>
67#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070068#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#ifdef CONFIG_MSM_DSPS
70#include <mach/msm_dsps.h>
71#endif
72#include <mach/msm_xo.h>
73#include <mach/msm_bus_board.h>
74#include <mach/socinfo.h>
75#include <linux/i2c/isl9519.h>
76#ifdef CONFIG_USB_G_ANDROID
77#include <linux/usb/android.h>
78#include <mach/usbdiag.h>
79#endif
80#include <linux/regulator/consumer.h>
81#include <linux/regulator/machine.h>
82#include <mach/sdio_al.h>
83#include <mach/rpm.h>
84#include <mach/rpm-regulator.h>
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070085#include <mach/restart.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080086
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070087#include "devices.h"
88#include "devices-msm8x60.h"
89#include "cpuidle.h"
90#include "pm.h"
91#include "mpm.h"
92#include "spm.h"
93#include "rpm_log.h"
94#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095#include "gpiomux-8x60.h"
96#include "rpm_stats.h"
97#include "peripheral-loader.h"
98#include <linux/platform_data/qcom_crypto_device.h>
99#include "rpm_resources.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -0700100#include "acpuclock.h"
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -0600101#include "pm-boot.h"
Laura Abbott63cfd7e2011-10-10 18:21:01 -0700102
103#include <linux/ion.h>
104#include <mach/ion.h>
105
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700106#define MSM_SHARED_RAM_PHYS 0x40000000
107
108/* Macros assume PMIC GPIOs start at 0 */
109#define PM8058_GPIO_BASE NR_MSM_GPIOS
110#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
111#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
112#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
113#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
114#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
115#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
116
117#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
118 PM8058_GPIOS + PM8058_MPPS)
119#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
120#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
121#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
122 NR_PMIC8058_IRQS)
123
124#define MDM2AP_SYNC 129
125
Terence Hampson1c73fef2011-07-19 17:10:49 -0400126#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700127#define LCDC_SPI_GPIO_CLK 73
128#define LCDC_SPI_GPIO_CS 72
129#define LCDC_SPI_GPIO_MOSI 70
130#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
131#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
132#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
133#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
134#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400135#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700136
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -0700137#define PANEL_NAME_MAX_LEN 30
138#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
139#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
140#define MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME "mipi_video_toshiba_wvga"
141#define HDMI_PANEL_NAME "hdmi_msm"
142#define TVOUT_PANEL_NAME "tvout_msm"
143
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700144#define DSPS_PIL_GENERIC_NAME "dsps"
145#define DSPS_PIL_FLUID_NAME "dsps_fluid"
146
147enum {
148 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
149 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
150 /* CORE expander */
151 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
152 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
153 GPIO_WLAN_DEEP_SLEEP_N,
154 GPIO_LVDS_SHUTDOWN_N,
155 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
156 GPIO_MS_SYS_RESET_N,
157 GPIO_CAP_TS_RESOUT_N,
158 GPIO_CAP_GAUGE_BI_TOUT,
159 GPIO_ETHERNET_PME,
160 GPIO_EXT_GPS_LNA_EN,
161 GPIO_MSM_WAKES_BT,
162 GPIO_ETHERNET_RESET_N,
163 GPIO_HEADSET_DET_N,
164 GPIO_USB_UICC_EN,
165 GPIO_BACKLIGHT_EN,
166 GPIO_EXT_CAMIF_PWR_EN,
167 GPIO_BATT_GAUGE_INT_N,
168 GPIO_BATT_GAUGE_EN,
169 /* DOCKING expander */
170 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
171 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
172 GPIO_AUX_JTAG_DET_N,
173 GPIO_DONGLE_DET_N,
174 GPIO_SVIDEO_LOAD_DET,
175 GPIO_SVID_AMP_SHUTDOWN1_N,
176 GPIO_SVID_AMP_SHUTDOWN0_N,
177 GPIO_SDC_WP,
178 GPIO_IRDA_PWDN,
179 GPIO_IRDA_RESET_N,
180 GPIO_DONGLE_GPIO0,
181 GPIO_DONGLE_GPIO1,
182 GPIO_DONGLE_GPIO2,
183 GPIO_DONGLE_GPIO3,
184 GPIO_DONGLE_PWR_EN,
185 GPIO_EMMC_RESET_N,
186 GPIO_TP_EXP2_IO15,
187 /* SURF expander */
188 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
189 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
190 GPIO_SD_CARD_DET_2,
191 GPIO_SD_CARD_DET_4,
192 GPIO_SD_CARD_DET_5,
193 GPIO_UIM3_RST,
194 GPIO_SURF_EXPANDER_IO5,
195 GPIO_SURF_EXPANDER_IO6,
196 GPIO_ADC_I2C_EN,
197 GPIO_SURF_EXPANDER_IO8,
198 GPIO_SURF_EXPANDER_IO9,
199 GPIO_SURF_EXPANDER_IO10,
200 GPIO_SURF_EXPANDER_IO11,
201 GPIO_SURF_EXPANDER_IO12,
202 GPIO_SURF_EXPANDER_IO13,
203 GPIO_SURF_EXPANDER_IO14,
204 GPIO_SURF_EXPANDER_IO15,
205 /* LEFT KB IO expander */
206 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
207 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
208 GPIO_LEFT_LED_2,
209 GPIO_LEFT_LED_3,
210 GPIO_LEFT_LED_WLAN,
211 GPIO_JOYSTICK_EN,
212 GPIO_CAP_TS_SLEEP,
213 GPIO_LEFT_KB_IO6,
214 GPIO_LEFT_LED_5,
215 /* RIGHT KB IO expander */
216 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
217 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
218 GPIO_RIGHT_LED_2,
219 GPIO_RIGHT_LED_3,
220 GPIO_RIGHT_LED_BT,
221 GPIO_WEB_CAMIF_STANDBY,
222 GPIO_COMPASS_RST_N,
223 GPIO_WEB_CAMIF_RESET_N,
224 GPIO_RIGHT_LED_5,
225 GPIO_R_ALTIMETER_RESET_N,
226 /* FLUID S IO expander */
227 GPIO_SOUTH_EXPANDER_BASE,
228 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
229 GPIO_MIC1_ANCL_SEL,
230 GPIO_HS_MIC4_SEL,
231 GPIO_FML_MIC3_SEL,
232 GPIO_FMR_MIC5_SEL,
233 GPIO_TS_SLEEP,
234 GPIO_HAP_SHIFT_LVL_OE,
235 GPIO_HS_SW_DIR,
236 /* FLUID N IO expander */
237 GPIO_NORTH_EXPANDER_BASE,
238 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
239 GPIO_EPM_5V_BOOST_EN,
240 GPIO_AUX_CAM_2P7_EN,
241 GPIO_LED_FLASH_EN,
242 GPIO_LED1_GREEN_N,
243 GPIO_LED2_RED_N,
244 GPIO_FRONT_CAM_RESET_N,
245 GPIO_EPM_LVLSFT_EN,
246 GPIO_N_ALTIMETER_RESET_N,
247 /* EPM expander */
248 GPIO_EPM_EXPANDER_BASE,
249 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
250 GPIO_PWR_MON_RESET_N,
251 GPIO_ADC1_PWDN_N,
252 GPIO_ADC2_PWDN_N,
253 GPIO_EPM_EXPANDER_IO4,
254 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
255 GPIO_ADC2_MUX_SPI_INT_N,
256 GPIO_EPM_EXPANDER_IO7,
257 GPIO_PWR_MON_ENABLE,
258 GPIO_EPM_SPI_ADC1_CS_N,
259 GPIO_EPM_SPI_ADC2_CS_N,
260 GPIO_EPM_EXPANDER_IO11,
261 GPIO_EPM_EXPANDER_IO12,
262 GPIO_EPM_EXPANDER_IO13,
263 GPIO_EPM_EXPANDER_IO14,
264 GPIO_EPM_EXPANDER_IO15,
265};
266
Anirudh Ghayalc2019332011-11-12 06:29:10 +0530267struct pm8xxx_mpp_init_info {
268 unsigned mpp;
269 struct pm8xxx_mpp_config_data config;
270};
271
272#define PM8XXX_MPP_INIT(_mpp, _type, _level, _control) \
273{ \
274 .mpp = PM8058_MPP_PM_TO_SYS(_mpp), \
275 .config = { \
276 .type = PM8XXX_MPP_TYPE_##_type, \
277 .level = _level, \
278 .control = PM8XXX_MPP_##_control, \
279 } \
280}
281
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700282/*
283 * The UI_INTx_N lines are pmic gpio lines which connect i2c
284 * gpio expanders to the pm8058.
285 */
286#define UI_INT1_N 25
287#define UI_INT2_N 34
288#define UI_INT3_N 14
289/*
290FM GPIO is GPIO 18 on PMIC 8058.
291As the index starts from 0 in the PMIC driver, and hence 17
292corresponds to GPIO 18 on PMIC 8058.
293*/
294#define FM_GPIO 17
295
296#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
297static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
298static void *sdc2_status_notify_cb_devid;
299#endif
300
301#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
302static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
303static void *sdc5_status_notify_cb_devid;
304#endif
305
306static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
307 [0] = {
308 .reg_base_addr = MSM_SAW0_BASE,
309
310#ifdef CONFIG_MSM_AVS_HW
311 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
312#endif
313 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
314 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
315 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
316 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
317
318 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
319 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
320 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
321
322 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
323 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
324 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
325
326 .awake_vlevel = 0x94,
327 .retention_vlevel = 0x81,
328 .collapse_vlevel = 0x20,
329 .retention_mid_vlevel = 0x94,
330 .collapse_mid_vlevel = 0x8C,
331
332 .vctl_timeout_us = 50,
333 },
334
335 [1] = {
336 .reg_base_addr = MSM_SAW1_BASE,
337
338#ifdef CONFIG_MSM_AVS_HW
339 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
340#endif
341 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
342 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
343 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
344 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
345
346 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
347 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
348 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
349
350 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
351 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
352 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
353
354 .awake_vlevel = 0x94,
355 .retention_vlevel = 0x81,
356 .collapse_vlevel = 0x20,
357 .retention_mid_vlevel = 0x94,
358 .collapse_mid_vlevel = 0x8C,
359
360 .vctl_timeout_us = 50,
361 },
362};
363
364static struct msm_spm_platform_data msm_spm_data[] __initdata = {
365 [0] = {
366 .reg_base_addr = MSM_SAW0_BASE,
367
368#ifdef CONFIG_MSM_AVS_HW
369 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
370#endif
371 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
372 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
373 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
374 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
375
376 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
377 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
378 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
379
380 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
381 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
382 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
383
384 .awake_vlevel = 0xA0,
385 .retention_vlevel = 0x89,
386 .collapse_vlevel = 0x20,
387 .retention_mid_vlevel = 0x89,
388 .collapse_mid_vlevel = 0x89,
389
390 .vctl_timeout_us = 50,
391 },
392
393 [1] = {
394 .reg_base_addr = MSM_SAW1_BASE,
395
396#ifdef CONFIG_MSM_AVS_HW
397 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
398#endif
399 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
400 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
401 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
402 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
403
404 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
405 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
406 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
407
408 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
409 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
410 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
411
412 .awake_vlevel = 0xA0,
413 .retention_vlevel = 0x89,
414 .collapse_vlevel = 0x20,
415 .retention_mid_vlevel = 0x89,
416 .collapse_mid_vlevel = 0x89,
417
418 .vctl_timeout_us = 50,
419 },
420};
421
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700422/*
423 * Consumer specific regulator names:
424 * regulator name consumer dev_name
425 */
426static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
427 REGULATOR_SUPPLY("8901_s0", NULL),
428};
429static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
430 REGULATOR_SUPPLY("8901_s1", NULL),
431};
432
433static struct regulator_init_data saw_s0_init_data = {
434 .constraints = {
435 .name = "8901_s0",
436 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700437 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700438 .max_uV = 1250000,
439 },
440 .consumer_supplies = vreg_consumers_8901_S0,
441 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
442};
443
444static struct regulator_init_data saw_s1_init_data = {
445 .constraints = {
446 .name = "8901_s1",
447 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700448 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700449 .max_uV = 1250000,
450 },
451 .consumer_supplies = vreg_consumers_8901_S1,
452 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
453};
454
455static struct platform_device msm_device_saw_s0 = {
456 .name = "saw-regulator",
457 .id = 0,
458 .dev = {
459 .platform_data = &saw_s0_init_data,
460 },
461};
462
463static struct platform_device msm_device_saw_s1 = {
464 .name = "saw-regulator",
465 .id = 1,
466 .dev = {
467 .platform_data = &saw_s1_init_data,
468 },
469};
470
471/*
472 * The smc91x configuration varies depending on platform.
473 * The resources data structure is filled in at runtime.
474 */
475static struct resource smc91x_resources[] = {
476 [0] = {
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .flags = IORESOURCE_IRQ,
481 },
482};
483
484static struct platform_device smc91x_device = {
485 .name = "smc91x",
486 .id = 0,
487 .num_resources = ARRAY_SIZE(smc91x_resources),
488 .resource = smc91x_resources,
489};
490
491static struct resource smsc911x_resources[] = {
492 [0] = {
493 .flags = IORESOURCE_MEM,
494 .start = 0x1b800000,
495 .end = 0x1b8000ff
496 },
497 [1] = {
498 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
499 },
500};
501
502static struct smsc911x_platform_config smsc911x_config = {
503 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
504 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
505 .flags = SMSC911X_USE_16BIT,
506 .has_reset_gpio = 1,
507 .reset_gpio = GPIO_ETHERNET_RESET_N
508};
509
510static struct platform_device smsc911x_device = {
511 .name = "smsc911x",
512 .id = 0,
513 .num_resources = ARRAY_SIZE(smsc911x_resources),
514 .resource = smsc911x_resources,
515 .dev = {
516 .platform_data = &smsc911x_config
517 }
518};
519
520#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
521 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
522 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
523 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
524
525#define QCE_SIZE 0x10000
526#define QCE_0_BASE 0x18500000
527
528#define QCE_HW_KEY_SUPPORT 0
529#define QCE_SHA_HMAC_SUPPORT 0
530#define QCE_SHARE_CE_RESOURCE 2
531#define QCE_CE_SHARED 1
532
533static struct resource qcrypto_resources[] = {
534 [0] = {
535 .start = QCE_0_BASE,
536 .end = QCE_0_BASE + QCE_SIZE - 1,
537 .flags = IORESOURCE_MEM,
538 },
539 [1] = {
540 .name = "crypto_channels",
541 .start = DMOV_CE_IN_CHAN,
542 .end = DMOV_CE_OUT_CHAN,
543 .flags = IORESOURCE_DMA,
544 },
545 [2] = {
546 .name = "crypto_crci_in",
547 .start = DMOV_CE_IN_CRCI,
548 .end = DMOV_CE_IN_CRCI,
549 .flags = IORESOURCE_DMA,
550 },
551 [3] = {
552 .name = "crypto_crci_out",
553 .start = DMOV_CE_OUT_CRCI,
554 .end = DMOV_CE_OUT_CRCI,
555 .flags = IORESOURCE_DMA,
556 },
557 [4] = {
558 .name = "crypto_crci_hash",
559 .start = DMOV_CE_HASH_CRCI,
560 .end = DMOV_CE_HASH_CRCI,
561 .flags = IORESOURCE_DMA,
562 },
563};
564
565static struct resource qcedev_resources[] = {
566 [0] = {
567 .start = QCE_0_BASE,
568 .end = QCE_0_BASE + QCE_SIZE - 1,
569 .flags = IORESOURCE_MEM,
570 },
571 [1] = {
572 .name = "crypto_channels",
573 .start = DMOV_CE_IN_CHAN,
574 .end = DMOV_CE_OUT_CHAN,
575 .flags = IORESOURCE_DMA,
576 },
577 [2] = {
578 .name = "crypto_crci_in",
579 .start = DMOV_CE_IN_CRCI,
580 .end = DMOV_CE_IN_CRCI,
581 .flags = IORESOURCE_DMA,
582 },
583 [3] = {
584 .name = "crypto_crci_out",
585 .start = DMOV_CE_OUT_CRCI,
586 .end = DMOV_CE_OUT_CRCI,
587 .flags = IORESOURCE_DMA,
588 },
589 [4] = {
590 .name = "crypto_crci_hash",
591 .start = DMOV_CE_HASH_CRCI,
592 .end = DMOV_CE_HASH_CRCI,
593 .flags = IORESOURCE_DMA,
594 },
595};
596
597#endif
598
599#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
600 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
601
602static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
603 .ce_shared = QCE_CE_SHARED,
604 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
605 .hw_key_support = QCE_HW_KEY_SUPPORT,
606 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
607};
608
609static struct platform_device qcrypto_device = {
610 .name = "qcrypto",
611 .id = 0,
612 .num_resources = ARRAY_SIZE(qcrypto_resources),
613 .resource = qcrypto_resources,
614 .dev = {
615 .coherent_dma_mask = DMA_BIT_MASK(32),
616 .platform_data = &qcrypto_ce_hw_suppport,
617 },
618};
619#endif
620
621#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
622 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
623
624static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
625 .ce_shared = QCE_CE_SHARED,
626 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
627 .hw_key_support = QCE_HW_KEY_SUPPORT,
628 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
629};
630
631static struct platform_device qcedev_device = {
632 .name = "qce",
633 .id = 0,
634 .num_resources = ARRAY_SIZE(qcedev_resources),
635 .resource = qcedev_resources,
636 .dev = {
637 .coherent_dma_mask = DMA_BIT_MASK(32),
638 .platform_data = &qcedev_ce_hw_suppport,
639 },
640};
641#endif
642
643#if defined(CONFIG_HAPTIC_ISA1200) || \
644 defined(CONFIG_HAPTIC_ISA1200_MODULE)
645
646static const char *vregs_isa1200_name[] = {
647 "8058_s3",
648 "8901_l4",
649};
650
651static const int vregs_isa1200_val[] = {
652 1800000,/* uV */
653 2600000,
654};
655static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
656static struct msm_xo_voter *xo_handle_a1;
657
658static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800659{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700660 int i, rc = 0;
661
662 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
663 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
664 regulator_disable(vregs_isa1200[i]);
665 if (rc < 0) {
666 pr_err("%s: vreg %s %s failed (%d)\n",
667 __func__, vregs_isa1200_name[i],
668 vreg_on ? "enable" : "disable", rc);
669 goto vreg_fail;
670 }
671 }
672
673 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
674 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
675 if (rc < 0) {
676 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
677 __func__, vreg_on ? "" : "de-", rc);
678 goto vreg_fail;
679 }
680 return 0;
681
682vreg_fail:
683 while (i--)
684 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
685 regulator_disable(vregs_isa1200[i]);
686 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800687}
688
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700689static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800690{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700691 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800692
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700693 if (enable == true) {
694 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
695 vregs_isa1200[i] = regulator_get(NULL,
696 vregs_isa1200_name[i]);
697 if (IS_ERR(vregs_isa1200[i])) {
698 pr_err("%s: regulator get of %s failed (%ld)\n",
699 __func__, vregs_isa1200_name[i],
700 PTR_ERR(vregs_isa1200[i]));
701 rc = PTR_ERR(vregs_isa1200[i]);
702 goto vreg_get_fail;
703 }
704 rc = regulator_set_voltage(vregs_isa1200[i],
705 vregs_isa1200_val[i], vregs_isa1200_val[i]);
706 if (rc) {
707 pr_err("%s: regulator_set_voltage(%s) failed\n",
708 __func__, vregs_isa1200_name[i]);
709 goto vreg_get_fail;
710 }
711 }
Steve Muckle9161d302010-02-11 11:50:40 -0800712
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700713 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
714 if (rc) {
715 pr_err("%s: unable to request gpio %d (%d)\n",
716 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
717 goto vreg_get_fail;
718 }
Steve Muckle9161d302010-02-11 11:50:40 -0800719
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700720 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
721 if (rc) {
722 pr_err("%s: Unable to set direction\n", __func__);;
723 goto free_gpio;
724 }
725
726 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
727 if (IS_ERR(xo_handle_a1)) {
728 rc = PTR_ERR(xo_handle_a1);
729 pr_err("%s: failed to get the handle for A1(%d)\n",
730 __func__, rc);
731 goto gpio_set_dir;
732 }
733 } else {
734 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
735 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
736
737 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
738 regulator_put(vregs_isa1200[i]);
739
740 msm_xo_put(xo_handle_a1);
741 }
742
743 return 0;
744gpio_set_dir:
745 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
746free_gpio:
747 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
748vreg_get_fail:
749 while (i)
750 regulator_put(vregs_isa1200[--i]);
751 return rc;
752}
753
754#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
Mohan Pallaka4a1160d2011-09-09 15:17:45 +0530755#define PMIC_GPIO_HAP_LDO_ENABLE 5 /* PMIC GPIO Number 6 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700756static struct isa1200_platform_data isa1200_1_pdata = {
757 .name = "vibrator",
758 .power_on = isa1200_power,
759 .dev_setup = isa1200_dev_setup,
760 /*gpio to enable haptic*/
761 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
Mohan Pallaka4a1160d2011-09-09 15:17:45 +0530762 .hap_len_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_LDO_ENABLE),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700763 .max_timeout = 15000,
764 .mode_ctrl = PWM_GEN_MODE,
765 .pwm_fd = {
766 .pwm_div = 256,
767 },
768 .is_erm = false,
769 .smart_en = true,
770 .ext_clk_en = true,
771 .chip_en = 1,
772};
773
774static struct i2c_board_info msm_isa1200_board_info[] = {
775 {
776 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
777 .platform_data = &isa1200_1_pdata,
778 },
779};
780#endif
781
782#if defined(CONFIG_BATTERY_BQ27520) || \
783 defined(CONFIG_BATTERY_BQ27520_MODULE)
784static struct bq27520_platform_data bq27520_pdata = {
785 .name = "fuel-gauge",
786 .vreg_name = "8058_s3",
787 .vreg_value = 1800000,
788 .soc_int = GPIO_BATT_GAUGE_INT_N,
789 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
790 .chip_en = GPIO_BATT_GAUGE_EN,
791 .enable_dlog = 0, /* if enable coulomb counter logger */
792};
793
794static struct i2c_board_info msm_bq27520_board_info[] = {
795 {
796 I2C_BOARD_INFO("bq27520", 0xaa>>1),
797 .platform_data = &bq27520_pdata,
798 },
799};
800#endif
801
802static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
803 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
804 .idle_supported = 1,
805 .suspend_supported = 1,
806 .idle_enabled = 0,
807 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700808 },
809
810 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
811 .idle_supported = 1,
812 .suspend_supported = 1,
813 .idle_enabled = 0,
814 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700815 },
816
817 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
818 .idle_supported = 1,
819 .suspend_supported = 1,
820 .idle_enabled = 1,
821 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822 },
823
824 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
825 .idle_supported = 1,
826 .suspend_supported = 1,
827 .idle_enabled = 0,
828 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700829 },
830
831 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
832 .idle_supported = 1,
833 .suspend_supported = 1,
834 .idle_enabled = 0,
835 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700836 },
837
838 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
839 .idle_supported = 1,
840 .suspend_supported = 1,
841 .idle_enabled = 1,
842 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700843 },
844};
845
846static struct msm_cpuidle_state msm_cstates[] __initdata = {
847 {0, 0, "C0", "WFI",
848 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
849
850 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
851 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
852
853 {0, 2, "C2", "POWER_COLLAPSE",
854 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
855
856 {1, 0, "C0", "WFI",
857 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
858
859 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
860 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
861};
862
863static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
864 {
865 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
866 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
867 true,
868 1, 8000, 100000, 1,
869 },
870
871 {
872 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
873 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
874 true,
875 1500, 5000, 60100000, 3000,
876 },
877
878 {
879 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
880 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
881 false,
882 1800, 5000, 60350000, 3500,
883 },
884 {
885 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
886 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
887 false,
888 3800, 4500, 65350000, 5500,
889 },
890
891 {
892 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
893 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
894 false,
895 2800, 2500, 66850000, 4800,
896 },
897
898 {
899 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
900 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
901 false,
902 4800, 2000, 71850000, 6800,
903 },
904
905 {
906 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
907 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
908 false,
909 6800, 500, 75850000, 8800,
910 },
911
912 {
913 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
914 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
915 false,
916 7800, 0, 76350000, 9800,
917 },
918};
919
920#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
921
922#define ISP1763_INT_GPIO 117
923#define ISP1763_RST_GPIO 152
924static struct resource isp1763_resources[] = {
925 [0] = {
926 .flags = IORESOURCE_MEM,
927 .start = 0x1D000000,
928 .end = 0x1D005FFF, /* 24KB */
929 },
930 [1] = {
931 .flags = IORESOURCE_IRQ,
932 },
933};
934static void __init msm8x60_cfg_isp1763(void)
935{
936 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
937 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
938}
939
940static int isp1763_setup_gpio(int enable)
941{
942 int status = 0;
943
944 if (enable) {
945 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
946 if (status) {
947 pr_err("%s:Failed to request GPIO %d\n",
948 __func__, ISP1763_INT_GPIO);
949 return status;
950 }
951 status = gpio_direction_input(ISP1763_INT_GPIO);
952 if (status) {
953 pr_err("%s:Failed to configure GPIO %d\n",
954 __func__, ISP1763_INT_GPIO);
955 goto gpio_free_int;
956 }
957 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
958 if (status) {
959 pr_err("%s:Failed to request GPIO %d\n",
960 __func__, ISP1763_RST_GPIO);
961 goto gpio_free_int;
962 }
963 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
964 if (status) {
965 pr_err("%s:Failed to configure GPIO %d\n",
966 __func__, ISP1763_RST_GPIO);
967 goto gpio_free_rst;
968 }
969 pr_debug("\nISP GPIO configuration done\n");
970 return status;
971 }
972
973gpio_free_rst:
974 gpio_free(ISP1763_RST_GPIO);
975gpio_free_int:
976 gpio_free(ISP1763_INT_GPIO);
977
978 return status;
979}
980static struct isp1763_platform_data isp1763_pdata = {
981 .reset_gpio = ISP1763_RST_GPIO,
982 .setup_gpio = isp1763_setup_gpio
983};
984
985static struct platform_device isp1763_device = {
986 .name = "isp1763_usb",
987 .num_resources = ARRAY_SIZE(isp1763_resources),
988 .resource = isp1763_resources,
989 .dev = {
990 .platform_data = &isp1763_pdata
991 }
992};
993#endif
994
995#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
Anji jonnalaeb9e60d2011-10-05 12:19:46 +0530996static struct msm_otg_platform_data msm_otg_pdata;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700997static struct regulator *ldo6_3p3;
998static struct regulator *ldo7_1p8;
999static struct regulator *vdd_cx;
1000#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
Anji jonnalaae745e92011-11-14 18:34:31 +05301001#define PMIC_ID_GPIO 36
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001002notify_vbus_state notify_vbus_state_func_ptr;
1003static int usb_phy_susp_dig_vol = 750000;
1004static int pmic_id_notif_supported;
1005
1006#ifdef CONFIG_USB_EHCI_MSM_72K
1007#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
1008struct delayed_work pmic_id_det;
1009
1010static int __init usb_id_pin_rework_setup(char *support)
1011{
1012 if (strncmp(support, "true", 4) == 0)
1013 pmic_id_notif_supported = 1;
1014
1015 return 1;
1016}
1017__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1018
1019static void pmic_id_detect(struct work_struct *w)
1020{
1021 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1022 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1023
1024 if (notify_vbus_state_func_ptr)
1025 (*notify_vbus_state_func_ptr) (val);
1026}
1027
1028static irqreturn_t pmic_id_on_irq(int irq, void *data)
1029{
1030 /*
1031 * Spurious interrupts are observed on pmic gpio line
1032 * even though there is no state change on USB ID. Schedule the
1033 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001034 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001035 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001036
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001037 return IRQ_HANDLED;
1038}
1039
Anji jonnalaae745e92011-11-14 18:34:31 +05301040static int msm_hsusb_phy_id_setup_init(int init)
1041{
1042 unsigned ret;
1043
1044 if (init) {
1045 ret = pm8901_mpp_config_digital_out(1,
1046 PM8901_MPP_DIG_LEVEL_L5, 1);
1047 if (ret < 0)
1048 pr_err("%s:MPP2 configuration failed\n", __func__);
1049 } else {
1050 ret = pm8901_mpp_config_digital_out(1,
1051 PM8901_MPP_DIG_LEVEL_L5, 0);
1052 if (ret < 0)
1053 pr_err("%s:MPP2 un config failed\n", __func__);
1054 }
1055 return ret;
1056}
1057
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001058static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1059{
1060 unsigned ret = -ENODEV;
1061
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301062 struct pm_gpio pmic_id_cfg = {
Anji jonnalaae745e92011-11-14 18:34:31 +05301063 .direction = PM_GPIO_DIR_IN,
1064 .pull = PM_GPIO_PULL_UP_1P5,
1065 .function = PM_GPIO_FUNC_NORMAL,
1066 .vin_sel = 2,
1067 .inv_int_pol = 0,
1068 };
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301069 struct pm_gpio pmic_id_uncfg = {
Anji jonnalaae745e92011-11-14 18:34:31 +05301070 .direction = PM_GPIO_DIR_IN,
1071 .pull = PM_GPIO_PULL_NO,
1072 .function = PM_GPIO_FUNC_NORMAL,
1073 .vin_sel = 2,
1074 .inv_int_pol = 0,
1075 };
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001076 if (!callback)
1077 return -EINVAL;
1078
1079 if (machine_is_msm8x60_fluid())
1080 return -ENOTSUPP;
1081
1082 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1083 pr_debug("%s: USB_ID pin is not routed to PMIC"
1084 "on V1 surf/ffa\n", __func__);
1085 return -ENOTSUPP;
1086 }
1087
1088 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1089 !pmic_id_notif_supported) {
1090 pr_debug("%s: USB_ID is not routed to PMIC"
1091 "on V2 ffa\n", __func__);
1092 return -ENOTSUPP;
1093 }
1094
1095 usb_phy_susp_dig_vol = 500000;
1096
1097 if (init) {
1098 notify_vbus_state_func_ptr = callback;
Manu Gautame8420ef2011-11-11 15:37:21 +05301099 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301100 ret = pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(PMIC_ID_GPIO),
1101 &pmic_id_cfg);
Anji jonnalaae745e92011-11-14 18:34:31 +05301102 if (ret) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301103 pr_err("%s:return val of pm8xxx_gpio_config: %d\n",
Anji jonnalaae745e92011-11-14 18:34:31 +05301104 __func__, ret);
1105 return ret;
1106 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001107 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1108 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1109 "msm_otg_id", NULL);
1110 if (ret) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001111 pr_err("%s:pmic_usb_id interrupt registration failed",
1112 __func__);
1113 return ret;
1114 }
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301115 msm_otg_pdata.pmic_id_irq = PMICID_INT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001116 } else {
Anji jonnalaae745e92011-11-14 18:34:31 +05301117 usb_phy_susp_dig_vol = 750000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001118 free_irq(PMICID_INT, 0);
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301119 ret = pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(PMIC_ID_GPIO),
1120 &pmic_id_uncfg);
Anji jonnalaae745e92011-11-14 18:34:31 +05301121 if (ret) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05301122 pr_err("%s: return val of pm8xxx_gpio_config: %d\n",
Anji jonnalaae745e92011-11-14 18:34:31 +05301123 __func__, ret);
1124 return ret;
1125 }
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301126 msm_otg_pdata.pmic_id_irq = 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001127 cancel_delayed_work_sync(&pmic_id_det);
1128 notify_vbus_state_func_ptr = NULL;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001129 }
1130 return 0;
1131}
1132#endif
1133
1134#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1135#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1136static int msm_hsusb_init_vddcx(int init)
1137{
1138 int ret = 0;
1139
1140 if (init) {
1141 vdd_cx = regulator_get(NULL, "8058_s1");
1142 if (IS_ERR(vdd_cx)) {
1143 return PTR_ERR(vdd_cx);
1144 }
1145
1146 ret = regulator_set_voltage(vdd_cx,
1147 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1148 USB_PHY_MAX_VDD_DIG_VOL);
1149 if (ret) {
1150 pr_err("%s: unable to set the voltage for regulator"
1151 "vdd_cx\n", __func__);
1152 regulator_put(vdd_cx);
1153 return ret;
1154 }
1155
1156 ret = regulator_enable(vdd_cx);
1157 if (ret) {
1158 pr_err("%s: unable to enable regulator"
1159 "vdd_cx\n", __func__);
1160 regulator_put(vdd_cx);
1161 }
1162 } else {
1163 ret = regulator_disable(vdd_cx);
1164 if (ret) {
1165 pr_err("%s: Unable to disable the regulator:"
1166 "vdd_cx\n", __func__);
1167 return ret;
1168 }
1169
1170 regulator_put(vdd_cx);
1171 }
1172
1173 return ret;
1174}
1175
1176static int msm_hsusb_config_vddcx(int high)
1177{
1178 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1179 int min_vol;
1180 int ret;
1181
1182 if (high)
1183 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1184 else
1185 min_vol = usb_phy_susp_dig_vol;
1186
1187 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1188 if (ret) {
1189 pr_err("%s: unable to set the voltage for regulator"
1190 "vdd_cx\n", __func__);
1191 return ret;
1192 }
1193
1194 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1195
1196 return ret;
1197}
1198
1199#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1200#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1201#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1202#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1203
1204#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1205#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1206#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1207#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1208static int msm_hsusb_ldo_init(int init)
1209{
1210 int rc = 0;
1211
1212 if (init) {
1213 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1214 if (IS_ERR(ldo6_3p3))
1215 return PTR_ERR(ldo6_3p3);
1216
1217 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1218 if (IS_ERR(ldo7_1p8)) {
1219 rc = PTR_ERR(ldo7_1p8);
1220 goto put_3p3;
1221 }
1222
1223 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1224 USB_PHY_3P3_VOL_MAX);
1225 if (rc) {
1226 pr_err("%s: Unable to set voltage level for"
1227 "ldo6_3p3 regulator\n", __func__);
1228 goto put_1p8;
1229 }
1230 rc = regulator_enable(ldo6_3p3);
1231 if (rc) {
1232 pr_err("%s: Unable to enable the regulator:"
1233 "ldo6_3p3\n", __func__);
1234 goto put_1p8;
1235 }
1236 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1237 USB_PHY_1P8_VOL_MAX);
1238 if (rc) {
1239 pr_err("%s: Unable to set voltage level for"
1240 "ldo7_1p8 regulator\n", __func__);
1241 goto disable_3p3;
1242 }
1243 rc = regulator_enable(ldo7_1p8);
1244 if (rc) {
1245 pr_err("%s: Unable to enable the regulator:"
1246 "ldo7_1p8\n", __func__);
1247 goto disable_3p3;
1248 }
1249
1250 return 0;
1251 }
1252
1253 regulator_disable(ldo7_1p8);
1254disable_3p3:
1255 regulator_disable(ldo6_3p3);
1256put_1p8:
1257 regulator_put(ldo7_1p8);
1258put_3p3:
1259 regulator_put(ldo6_3p3);
1260 return rc;
1261}
1262
1263static int msm_hsusb_ldo_enable(int on)
1264{
1265 int ret = 0;
1266
1267 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1268 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1269 return -ENODEV;
1270 }
1271
1272 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1273 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1274 return -ENODEV;
1275 }
1276
1277 if (on) {
1278 ret = regulator_set_optimum_mode(ldo7_1p8,
1279 USB_PHY_1P8_HPM_LOAD);
1280 if (ret < 0) {
1281 pr_err("%s: Unable to set HPM of the regulator:"
1282 "ldo7_1p8\n", __func__);
1283 return ret;
1284 }
1285 ret = regulator_set_optimum_mode(ldo6_3p3,
1286 USB_PHY_3P3_HPM_LOAD);
1287 if (ret < 0) {
1288 pr_err("%s: Unable to set HPM of the regulator:"
1289 "ldo6_3p3\n", __func__);
1290 regulator_set_optimum_mode(ldo7_1p8,
1291 USB_PHY_1P8_LPM_LOAD);
1292 return ret;
1293 }
1294 } else {
1295 ret = regulator_set_optimum_mode(ldo7_1p8,
1296 USB_PHY_1P8_LPM_LOAD);
1297 if (ret < 0)
1298 pr_err("%s: Unable to set LPM of the regulator:"
1299 "ldo7_1p8\n", __func__);
1300 ret = regulator_set_optimum_mode(ldo6_3p3,
1301 USB_PHY_3P3_LPM_LOAD);
1302 if (ret < 0)
1303 pr_err("%s: Unable to set LPM of the regulator:"
1304 "ldo6_3p3\n", __func__);
1305 }
1306
1307 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1308 return ret < 0 ? ret : 0;
1309 }
1310#endif
1311#ifdef CONFIG_USB_EHCI_MSM_72K
1312#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1313static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1314{
1315 static int vbus_is_on;
1316
1317 /* If VBUS is already on (or off), do nothing. */
1318 if (on == vbus_is_on)
1319 return;
1320 smb137b_otg_power(on);
1321 vbus_is_on = on;
1322}
1323#endif
1324static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1325{
1326 static struct regulator *votg_5v_switch;
1327 static struct regulator *ext_5v_reg;
1328 static int vbus_is_on;
1329
1330 /* If VBUS is already on (or off), do nothing. */
1331 if (on == vbus_is_on)
1332 return;
1333
1334 if (!votg_5v_switch) {
1335 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1336 if (IS_ERR(votg_5v_switch)) {
1337 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1338 return;
1339 }
1340 }
1341 if (!ext_5v_reg) {
1342 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1343 if (IS_ERR(ext_5v_reg)) {
1344 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1345 return;
1346 }
1347 }
1348 if (on) {
1349 if (regulator_enable(ext_5v_reg)) {
1350 pr_err("%s: Unable to enable the regulator:"
1351 " ext_5v_reg\n", __func__);
1352 return;
1353 }
1354 if (regulator_enable(votg_5v_switch)) {
1355 pr_err("%s: Unable to enable the regulator:"
1356 " votg_5v_switch\n", __func__);
1357 return;
1358 }
1359 } else {
1360 if (regulator_disable(votg_5v_switch))
1361 pr_err("%s: Unable to enable the regulator:"
1362 " votg_5v_switch\n", __func__);
1363 if (regulator_disable(ext_5v_reg))
1364 pr_err("%s: Unable to enable the regulator:"
1365 " ext_5v_reg\n", __func__);
1366 }
1367
1368 vbus_is_on = on;
1369}
1370
1371static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1372 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1373 .power_budget = 390,
1374};
1375#endif
1376
1377#ifdef CONFIG_BATTERY_MSM8X60
1378static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1379 int init)
1380{
1381 int ret = -ENOTSUPP;
1382
1383#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1384 if (machine_is_msm8x60_fluid()) {
1385 if (init)
1386 msm_charger_register_vbus_sn(callback);
1387 else
1388 msm_charger_unregister_vbus_sn(callback);
1389 return 0;
1390 }
1391#endif
1392 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1393 * hence, irrespective of either peripheral only mode or
1394 * OTG (host and peripheral) modes, can depend on pmic for
1395 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001396 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001397 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1398 && (machine_is_msm8x60_surf() ||
1399 pmic_id_notif_supported)) {
1400 if (init)
1401 ret = msm_charger_register_vbus_sn(callback);
1402 else {
1403 msm_charger_unregister_vbus_sn(callback);
1404 ret = 0;
1405 }
1406 } else {
1407#if !defined(CONFIG_USB_EHCI_MSM_72K)
1408 if (init)
1409 ret = msm_charger_register_vbus_sn(callback);
1410 else {
1411 msm_charger_unregister_vbus_sn(callback);
1412 ret = 0;
1413 }
1414#endif
1415 }
1416 return ret;
1417}
1418#endif
1419
1420#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1421static struct msm_otg_platform_data msm_otg_pdata = {
1422 /* if usb link is in sps there is no need for
1423 * usb pclk as dayatona fabric clock will be
1424 * used instead
1425 */
1426 .pclk_src_name = "dfab_usb_hs_clk",
1427 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1428 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1429 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301430 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001431#ifdef CONFIG_USB_EHCI_MSM_72K
1432 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
Anji jonnalaae745e92011-11-14 18:34:31 +05301433 .phy_id_setup_init = msm_hsusb_phy_id_setup_init,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001434#endif
1435#ifdef CONFIG_USB_EHCI_MSM_72K
1436 .vbus_power = msm_hsusb_vbus_power,
1437#endif
1438#ifdef CONFIG_BATTERY_MSM8X60
1439 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1440#endif
1441 .ldo_init = msm_hsusb_ldo_init,
1442 .ldo_enable = msm_hsusb_ldo_enable,
1443 .config_vddcx = msm_hsusb_config_vddcx,
1444 .init_vddcx = msm_hsusb_init_vddcx,
1445#ifdef CONFIG_BATTERY_MSM8X60
1446 .chg_vbus_draw = msm_charger_vbus_draw,
1447#endif
1448};
1449#endif
1450
1451#ifdef CONFIG_USB_GADGET_MSM_72K
1452static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1453 .is_phy_status_timer_on = 1,
1454};
1455#endif
1456
1457#ifdef CONFIG_USB_G_ANDROID
1458
1459#define PID_MAGIC_ID 0x71432909
1460#define SERIAL_NUM_MAGIC_ID 0x61945374
1461#define SERIAL_NUMBER_LENGTH 127
1462#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1463
1464struct magic_num_struct {
1465 uint32_t pid;
1466 uint32_t serial_num;
1467};
1468
1469struct dload_struct {
1470 uint32_t reserved1;
1471 uint32_t reserved2;
1472 uint32_t reserved3;
1473 uint16_t reserved4;
1474 uint16_t pid;
1475 char serial_number[SERIAL_NUMBER_LENGTH];
1476 uint16_t reserved5;
1477 struct magic_num_struct
1478 magic_struct;
1479};
1480
1481static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1482{
1483 struct dload_struct __iomem *dload = 0;
1484
1485 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1486 if (!dload) {
1487 pr_err("%s: cannot remap I/O memory region: %08x\n",
1488 __func__, DLOAD_USB_BASE_ADD);
1489 return -ENXIO;
1490 }
1491
1492 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1493 __func__, dload, pid, snum);
1494 /* update pid */
1495 dload->magic_struct.pid = PID_MAGIC_ID;
1496 dload->pid = pid;
1497
1498 /* update serial number */
1499 dload->magic_struct.serial_num = 0;
1500 if (!snum)
1501 return 0;
1502
1503 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1504 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1505 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1506
1507 iounmap(dload);
1508
1509 return 0;
1510}
1511
1512static struct android_usb_platform_data android_usb_pdata = {
1513 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1514};
1515
1516static struct platform_device android_usb_device = {
1517 .name = "android_usb",
1518 .id = -1,
1519 .dev = {
1520 .platform_data = &android_usb_pdata,
1521 },
1522};
1523
1524
1525#endif
1526
1527#ifdef CONFIG_MSM_VPE
1528static struct resource msm_vpe_resources[] = {
1529 {
1530 .start = 0x05300000,
1531 .end = 0x05300000 + SZ_1M - 1,
1532 .flags = IORESOURCE_MEM,
1533 },
1534 {
1535 .start = INT_VPE,
1536 .end = INT_VPE,
1537 .flags = IORESOURCE_IRQ,
1538 },
1539};
1540
1541static struct platform_device msm_vpe_device = {
1542 .name = "msm_vpe",
1543 .id = 0,
1544 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1545 .resource = msm_vpe_resources,
1546};
1547#endif
1548
1549#ifdef CONFIG_MSM_CAMERA
1550#ifdef CONFIG_MSM_CAMERA_FLASH
1551#define VFE_CAMIF_TIMER1_GPIO 29
1552#define VFE_CAMIF_TIMER2_GPIO 30
1553#define VFE_CAMIF_TIMER3_GPIO_INT 31
1554#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1555static struct msm_camera_sensor_flash_src msm_flash_src = {
1556 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1557 ._fsrc.pmic_src.num_of_src = 2,
1558 ._fsrc.pmic_src.low_current = 100,
1559 ._fsrc.pmic_src.high_current = 300,
1560 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1561 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1562 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1563};
1564#ifdef CONFIG_IMX074
1565static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1566 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1567 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1568 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1569 .flash_recharge_duration = 50000,
1570 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1571};
1572#endif
1573#endif
1574
1575int msm_cam_gpio_tbl[] = {
1576 32,/*CAMIF_MCLK*/
1577 47,/*CAMIF_I2C_DATA*/
1578 48,/*CAMIF_I2C_CLK*/
1579 105,/*STANDBY*/
1580};
1581
1582enum msm_cam_stat{
1583 MSM_CAM_OFF,
1584 MSM_CAM_ON,
1585};
1586
1587static int config_gpio_table(enum msm_cam_stat stat)
1588{
1589 int rc = 0, i = 0;
1590 if (stat == MSM_CAM_ON) {
1591 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1592 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1593 if (unlikely(rc < 0)) {
1594 pr_err("%s not able to get gpio\n", __func__);
1595 for (i--; i >= 0; i--)
1596 gpio_free(msm_cam_gpio_tbl[i]);
1597 break;
1598 }
1599 }
1600 } else {
1601 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1602 gpio_free(msm_cam_gpio_tbl[i]);
1603 }
1604 return rc;
1605}
1606
1607static struct msm_camera_sensor_platform_info sensor_board_info = {
1608 .mount_angle = 0
1609};
1610
1611/*external regulator VREG_5V*/
1612static struct regulator *reg_flash_5V;
1613
1614static int config_camera_on_gpios_fluid(void)
1615{
1616 int rc = 0;
1617
1618 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1619 if (IS_ERR(reg_flash_5V)) {
1620 pr_err("'%s' regulator not found, rc=%ld\n",
1621 "8901_mpp0", IS_ERR(reg_flash_5V));
1622 return -ENODEV;
1623 }
1624
1625 rc = regulator_enable(reg_flash_5V);
1626 if (rc) {
1627 pr_err("'%s' regulator enable failed, rc=%d\n",
1628 "8901_mpp0", rc);
1629 regulator_put(reg_flash_5V);
1630 return rc;
1631 }
1632
1633#ifdef CONFIG_IMX074
1634 sensor_board_info.mount_angle = 90;
1635#endif
1636 rc = config_gpio_table(MSM_CAM_ON);
1637 if (rc < 0) {
1638 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1639 "failed\n", __func__);
1640 return rc;
1641 }
1642
1643 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1644 if (rc < 0) {
1645 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1646 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1647 regulator_disable(reg_flash_5V);
1648 regulator_put(reg_flash_5V);
1649 return rc;
1650 }
1651 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1652 msleep(20);
1653 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1654
1655
1656 /*Enable LED_FLASH_EN*/
1657 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1658 if (rc < 0) {
1659 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1660 "failed\n", __func__, GPIO_LED_FLASH_EN);
1661
1662 regulator_disable(reg_flash_5V);
1663 regulator_put(reg_flash_5V);
1664 config_gpio_table(MSM_CAM_OFF);
1665 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1666 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1667 return rc;
1668 }
1669 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1670 msleep(20);
1671 return rc;
1672}
1673
1674
1675static void config_camera_off_gpios_fluid(void)
1676{
1677 regulator_disable(reg_flash_5V);
1678 regulator_put(reg_flash_5V);
1679
1680 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1681 gpio_free(GPIO_LED_FLASH_EN);
1682
1683 config_gpio_table(MSM_CAM_OFF);
1684
1685 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1686 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1687}
1688static int config_camera_on_gpios(void)
1689{
1690 int rc = 0;
1691
1692 if (machine_is_msm8x60_fluid())
1693 return config_camera_on_gpios_fluid();
1694
1695 rc = config_gpio_table(MSM_CAM_ON);
1696 if (rc < 0) {
1697 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1698 "failed\n", __func__);
1699 return rc;
1700 }
1701
Jilai Wang971f97f2011-07-13 14:25:25 -04001702 if (!machine_is_msm8x60_dragon()) {
1703 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1704 if (rc < 0) {
1705 config_gpio_table(MSM_CAM_OFF);
1706 pr_err("%s: CAMSENSOR gpio %d request"
1707 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1708 return rc;
1709 }
1710 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1711 msleep(20);
1712 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001713 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001714
1715#ifdef CONFIG_MSM_CAMERA_FLASH
1716#ifdef CONFIG_IMX074
1717 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1718 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1719#endif
1720#endif
1721 return rc;
1722}
1723
1724static void config_camera_off_gpios(void)
1725{
1726 if (machine_is_msm8x60_fluid())
1727 return config_camera_off_gpios_fluid();
1728
1729
1730 config_gpio_table(MSM_CAM_OFF);
1731
Jilai Wang971f97f2011-07-13 14:25:25 -04001732 if (!machine_is_msm8x60_dragon()) {
1733 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1734 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1735 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001736}
1737
1738#ifdef CONFIG_QS_S5K4E1
1739
1740#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1741
1742static int config_camera_on_gpios_qs_cam_fluid(void)
1743{
1744 int rc = 0;
1745
1746 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1747 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1748 if (rc < 0) {
1749 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1750 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1751 return rc;
1752 }
1753 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1754 msleep(20);
1755 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1756 msleep(20);
1757
1758 /*
1759 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1760 * to enable 2.7V power to Camera
1761 */
1762 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1763 if (rc < 0) {
1764 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1765 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1766 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1767 gpio_free(QS_CAM_HC37_CAM_PD);
1768 return rc;
1769 }
1770 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1771 msleep(20);
1772 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1773 msleep(20);
1774
1775 rc = config_camera_on_gpios_fluid();
1776 if (rc < 0) {
1777 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1778 " failed\n", __func__);
1779 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1780 gpio_free(QS_CAM_HC37_CAM_PD);
1781 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1782 gpio_free(GPIO_AUX_CAM_2P7_EN);
1783 return rc;
1784 }
1785 return rc;
1786}
1787
1788static void config_camera_off_gpios_qs_cam_fluid(void)
1789{
1790 /*
1791 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1792 * to disable 2.7V power to Camera
1793 */
1794 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1795 gpio_free(GPIO_AUX_CAM_2P7_EN);
1796
1797 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1798 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1799 gpio_free(QS_CAM_HC37_CAM_PD);
1800
1801 config_camera_off_gpios_fluid();
1802 return;
1803}
1804
1805static int config_camera_on_gpios_qs_cam(void)
1806{
1807 int rc = 0;
1808
1809 if (machine_is_msm8x60_fluid())
1810 return config_camera_on_gpios_qs_cam_fluid();
1811
1812 rc = config_camera_on_gpios();
1813 return rc;
1814}
1815
1816static void config_camera_off_gpios_qs_cam(void)
1817{
1818 if (machine_is_msm8x60_fluid())
1819 return config_camera_off_gpios_qs_cam_fluid();
1820
1821 config_camera_off_gpios();
1822 return;
1823}
1824#endif
1825
1826static int config_camera_on_gpios_web_cam(void)
1827{
1828 int rc = 0;
1829 rc = config_gpio_table(MSM_CAM_ON);
1830 if (rc < 0) {
1831 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1832 "failed\n", __func__);
1833 return rc;
1834 }
1835
Jilai Wang53d27a82011-07-13 14:32:58 -04001836 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001837 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1838 if (rc < 0) {
1839 config_gpio_table(MSM_CAM_OFF);
1840 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1841 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1842 return rc;
1843 }
1844 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1845 }
1846 return rc;
1847}
1848
1849static void config_camera_off_gpios_web_cam(void)
1850{
1851 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001852 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001853 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1854 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1855 }
1856 return;
1857}
1858
1859#ifdef CONFIG_MSM_BUS_SCALING
1860static struct msm_bus_vectors cam_init_vectors[] = {
1861 {
1862 .src = MSM_BUS_MASTER_VFE,
1863 .dst = MSM_BUS_SLAVE_SMI,
1864 .ab = 0,
1865 .ib = 0,
1866 },
1867 {
1868 .src = MSM_BUS_MASTER_VFE,
1869 .dst = MSM_BUS_SLAVE_EBI_CH0,
1870 .ab = 0,
1871 .ib = 0,
1872 },
1873 {
1874 .src = MSM_BUS_MASTER_VPE,
1875 .dst = MSM_BUS_SLAVE_SMI,
1876 .ab = 0,
1877 .ib = 0,
1878 },
1879 {
1880 .src = MSM_BUS_MASTER_VPE,
1881 .dst = MSM_BUS_SLAVE_EBI_CH0,
1882 .ab = 0,
1883 .ib = 0,
1884 },
1885 {
1886 .src = MSM_BUS_MASTER_JPEG_ENC,
1887 .dst = MSM_BUS_SLAVE_SMI,
1888 .ab = 0,
1889 .ib = 0,
1890 },
1891 {
1892 .src = MSM_BUS_MASTER_JPEG_ENC,
1893 .dst = MSM_BUS_SLAVE_EBI_CH0,
1894 .ab = 0,
1895 .ib = 0,
1896 },
1897};
1898
1899static struct msm_bus_vectors cam_preview_vectors[] = {
1900 {
1901 .src = MSM_BUS_MASTER_VFE,
1902 .dst = MSM_BUS_SLAVE_SMI,
1903 .ab = 0,
1904 .ib = 0,
1905 },
1906 {
1907 .src = MSM_BUS_MASTER_VFE,
1908 .dst = MSM_BUS_SLAVE_EBI_CH0,
1909 .ab = 283115520,
1910 .ib = 452984832,
1911 },
1912 {
1913 .src = MSM_BUS_MASTER_VPE,
1914 .dst = MSM_BUS_SLAVE_SMI,
1915 .ab = 0,
1916 .ib = 0,
1917 },
1918 {
1919 .src = MSM_BUS_MASTER_VPE,
1920 .dst = MSM_BUS_SLAVE_EBI_CH0,
1921 .ab = 0,
1922 .ib = 0,
1923 },
1924 {
1925 .src = MSM_BUS_MASTER_JPEG_ENC,
1926 .dst = MSM_BUS_SLAVE_SMI,
1927 .ab = 0,
1928 .ib = 0,
1929 },
1930 {
1931 .src = MSM_BUS_MASTER_JPEG_ENC,
1932 .dst = MSM_BUS_SLAVE_EBI_CH0,
1933 .ab = 0,
1934 .ib = 0,
1935 },
1936};
1937
1938static struct msm_bus_vectors cam_video_vectors[] = {
1939 {
1940 .src = MSM_BUS_MASTER_VFE,
1941 .dst = MSM_BUS_SLAVE_SMI,
1942 .ab = 283115520,
1943 .ib = 452984832,
1944 },
1945 {
1946 .src = MSM_BUS_MASTER_VFE,
1947 .dst = MSM_BUS_SLAVE_EBI_CH0,
1948 .ab = 283115520,
1949 .ib = 452984832,
1950 },
1951 {
1952 .src = MSM_BUS_MASTER_VPE,
1953 .dst = MSM_BUS_SLAVE_SMI,
1954 .ab = 319610880,
1955 .ib = 511377408,
1956 },
1957 {
1958 .src = MSM_BUS_MASTER_VPE,
1959 .dst = MSM_BUS_SLAVE_EBI_CH0,
1960 .ab = 0,
1961 .ib = 0,
1962 },
1963 {
1964 .src = MSM_BUS_MASTER_JPEG_ENC,
1965 .dst = MSM_BUS_SLAVE_SMI,
1966 .ab = 0,
1967 .ib = 0,
1968 },
1969 {
1970 .src = MSM_BUS_MASTER_JPEG_ENC,
1971 .dst = MSM_BUS_SLAVE_EBI_CH0,
1972 .ab = 0,
1973 .ib = 0,
1974 },
1975};
1976
1977static struct msm_bus_vectors cam_snapshot_vectors[] = {
1978 {
1979 .src = MSM_BUS_MASTER_VFE,
1980 .dst = MSM_BUS_SLAVE_SMI,
1981 .ab = 566231040,
1982 .ib = 905969664,
1983 },
1984 {
1985 .src = MSM_BUS_MASTER_VFE,
1986 .dst = MSM_BUS_SLAVE_EBI_CH0,
1987 .ab = 69984000,
1988 .ib = 111974400,
1989 },
1990 {
1991 .src = MSM_BUS_MASTER_VPE,
1992 .dst = MSM_BUS_SLAVE_SMI,
1993 .ab = 0,
1994 .ib = 0,
1995 },
1996 {
1997 .src = MSM_BUS_MASTER_VPE,
1998 .dst = MSM_BUS_SLAVE_EBI_CH0,
1999 .ab = 0,
2000 .ib = 0,
2001 },
2002 {
2003 .src = MSM_BUS_MASTER_JPEG_ENC,
2004 .dst = MSM_BUS_SLAVE_SMI,
2005 .ab = 320864256,
2006 .ib = 513382810,
2007 },
2008 {
2009 .src = MSM_BUS_MASTER_JPEG_ENC,
2010 .dst = MSM_BUS_SLAVE_EBI_CH0,
2011 .ab = 320864256,
2012 .ib = 513382810,
2013 },
2014};
2015
2016static struct msm_bus_vectors cam_zsl_vectors[] = {
2017 {
2018 .src = MSM_BUS_MASTER_VFE,
2019 .dst = MSM_BUS_SLAVE_SMI,
2020 .ab = 566231040,
2021 .ib = 905969664,
2022 },
2023 {
2024 .src = MSM_BUS_MASTER_VFE,
2025 .dst = MSM_BUS_SLAVE_EBI_CH0,
2026 .ab = 706199040,
2027 .ib = 1129918464,
2028 },
2029 {
2030 .src = MSM_BUS_MASTER_VPE,
2031 .dst = MSM_BUS_SLAVE_SMI,
2032 .ab = 0,
2033 .ib = 0,
2034 },
2035 {
2036 .src = MSM_BUS_MASTER_VPE,
2037 .dst = MSM_BUS_SLAVE_EBI_CH0,
2038 .ab = 0,
2039 .ib = 0,
2040 },
2041 {
2042 .src = MSM_BUS_MASTER_JPEG_ENC,
2043 .dst = MSM_BUS_SLAVE_SMI,
2044 .ab = 320864256,
2045 .ib = 513382810,
2046 },
2047 {
2048 .src = MSM_BUS_MASTER_JPEG_ENC,
2049 .dst = MSM_BUS_SLAVE_EBI_CH0,
2050 .ab = 320864256,
2051 .ib = 513382810,
2052 },
2053};
2054
2055static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2056 {
2057 .src = MSM_BUS_MASTER_VFE,
2058 .dst = MSM_BUS_SLAVE_SMI,
2059 .ab = 212336640,
2060 .ib = 339738624,
2061 },
2062 {
2063 .src = MSM_BUS_MASTER_VFE,
2064 .dst = MSM_BUS_SLAVE_EBI_CH0,
2065 .ab = 25090560,
2066 .ib = 40144896,
2067 },
2068 {
2069 .src = MSM_BUS_MASTER_VPE,
2070 .dst = MSM_BUS_SLAVE_SMI,
2071 .ab = 239708160,
2072 .ib = 383533056,
2073 },
2074 {
2075 .src = MSM_BUS_MASTER_VPE,
2076 .dst = MSM_BUS_SLAVE_EBI_CH0,
2077 .ab = 79902720,
2078 .ib = 127844352,
2079 },
2080 {
2081 .src = MSM_BUS_MASTER_JPEG_ENC,
2082 .dst = MSM_BUS_SLAVE_SMI,
2083 .ab = 0,
2084 .ib = 0,
2085 },
2086 {
2087 .src = MSM_BUS_MASTER_JPEG_ENC,
2088 .dst = MSM_BUS_SLAVE_EBI_CH0,
2089 .ab = 0,
2090 .ib = 0,
2091 },
2092};
2093
2094static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2095 {
2096 .src = MSM_BUS_MASTER_VFE,
2097 .dst = MSM_BUS_SLAVE_SMI,
2098 .ab = 0,
2099 .ib = 0,
2100 },
2101 {
2102 .src = MSM_BUS_MASTER_VFE,
2103 .dst = MSM_BUS_SLAVE_EBI_CH0,
2104 .ab = 300902400,
2105 .ib = 481443840,
2106 },
2107 {
2108 .src = MSM_BUS_MASTER_VPE,
2109 .dst = MSM_BUS_SLAVE_SMI,
2110 .ab = 230307840,
2111 .ib = 368492544,
2112 },
2113 {
2114 .src = MSM_BUS_MASTER_VPE,
2115 .dst = MSM_BUS_SLAVE_EBI_CH0,
2116 .ab = 245113344,
2117 .ib = 392181351,
2118 },
2119 {
2120 .src = MSM_BUS_MASTER_JPEG_ENC,
2121 .dst = MSM_BUS_SLAVE_SMI,
2122 .ab = 106536960,
2123 .ib = 170459136,
2124 },
2125 {
2126 .src = MSM_BUS_MASTER_JPEG_ENC,
2127 .dst = MSM_BUS_SLAVE_EBI_CH0,
2128 .ab = 106536960,
2129 .ib = 170459136,
2130 },
2131};
2132
2133static struct msm_bus_paths cam_bus_client_config[] = {
2134 {
2135 ARRAY_SIZE(cam_init_vectors),
2136 cam_init_vectors,
2137 },
2138 {
2139 ARRAY_SIZE(cam_preview_vectors),
2140 cam_preview_vectors,
2141 },
2142 {
2143 ARRAY_SIZE(cam_video_vectors),
2144 cam_video_vectors,
2145 },
2146 {
2147 ARRAY_SIZE(cam_snapshot_vectors),
2148 cam_snapshot_vectors,
2149 },
2150 {
2151 ARRAY_SIZE(cam_zsl_vectors),
2152 cam_zsl_vectors,
2153 },
2154 {
2155 ARRAY_SIZE(cam_stereo_video_vectors),
2156 cam_stereo_video_vectors,
2157 },
2158 {
2159 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2160 cam_stereo_snapshot_vectors,
2161 },
2162};
2163
2164static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2165 cam_bus_client_config,
2166 ARRAY_SIZE(cam_bus_client_config),
2167 .name = "msm_camera",
2168};
2169#endif
2170
2171struct msm_camera_device_platform_data msm_camera_device_data = {
2172 .camera_gpio_on = config_camera_on_gpios,
2173 .camera_gpio_off = config_camera_off_gpios,
2174 .ioext.csiphy = 0x04800000,
2175 .ioext.csisz = 0x00000400,
2176 .ioext.csiirq = CSI_0_IRQ,
2177 .ioclk.mclk_clk_rate = 24000000,
2178 .ioclk.vfe_clk_rate = 228570000,
2179#ifdef CONFIG_MSM_BUS_SCALING
2180 .cam_bus_scale_table = &cam_bus_client_pdata,
2181#endif
2182};
2183
2184#ifdef CONFIG_QS_S5K4E1
2185struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2186 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2187 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2188 .ioext.csiphy = 0x04800000,
2189 .ioext.csisz = 0x00000400,
2190 .ioext.csiirq = CSI_0_IRQ,
2191 .ioclk.mclk_clk_rate = 24000000,
2192 .ioclk.vfe_clk_rate = 228570000,
2193#ifdef CONFIG_MSM_BUS_SCALING
2194 .cam_bus_scale_table = &cam_bus_client_pdata,
2195#endif
2196};
2197#endif
2198
2199struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2200 .camera_gpio_on = config_camera_on_gpios_web_cam,
2201 .camera_gpio_off = config_camera_off_gpios_web_cam,
2202 .ioext.csiphy = 0x04900000,
2203 .ioext.csisz = 0x00000400,
2204 .ioext.csiirq = CSI_1_IRQ,
2205 .ioclk.mclk_clk_rate = 24000000,
2206 .ioclk.vfe_clk_rate = 228570000,
2207#ifdef CONFIG_MSM_BUS_SCALING
2208 .cam_bus_scale_table = &cam_bus_client_pdata,
2209#endif
2210};
2211
2212struct resource msm_camera_resources[] = {
2213 {
2214 .start = 0x04500000,
2215 .end = 0x04500000 + SZ_1M - 1,
2216 .flags = IORESOURCE_MEM,
2217 },
2218 {
2219 .start = VFE_IRQ,
2220 .end = VFE_IRQ,
2221 .flags = IORESOURCE_IRQ,
2222 },
2223};
2224#ifdef CONFIG_MT9E013
2225static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2226 .mount_angle = 0
2227};
2228
2229static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2230 .flash_type = MSM_CAMERA_FLASH_LED,
2231 .flash_src = &msm_flash_src
2232};
2233
2234static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2235 .sensor_name = "mt9e013",
2236 .sensor_reset = 106,
2237 .sensor_pwd = 85,
2238 .vcm_pwd = 1,
2239 .vcm_enable = 0,
2240 .pdata = &msm_camera_device_data,
2241 .resource = msm_camera_resources,
2242 .num_resources = ARRAY_SIZE(msm_camera_resources),
2243 .flash_data = &flash_mt9e013,
2244 .strobe_flash_data = &strobe_flash_xenon,
2245 .sensor_platform_info = &mt9e013_sensor_8660_info,
2246 .csi_if = 1
2247};
2248struct platform_device msm_camera_sensor_mt9e013 = {
2249 .name = "msm_camera_mt9e013",
2250 .dev = {
2251 .platform_data = &msm_camera_sensor_mt9e013_data,
2252 },
2253};
2254#endif
2255
2256#ifdef CONFIG_IMX074
Roja Rani Yarubandi68ebb4d2011-10-20 10:33:16 +05302257static struct msm_camera_sensor_platform_info imx074_sensor_board_info = {
2258 .mount_angle = 180
2259};
2260
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002261static struct msm_camera_sensor_flash_data flash_imx074 = {
2262 .flash_type = MSM_CAMERA_FLASH_LED,
2263 .flash_src = &msm_flash_src
2264};
2265
2266static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2267 .sensor_name = "imx074",
2268 .sensor_reset = 106,
2269 .sensor_pwd = 85,
2270 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2271 .vcm_enable = 1,
2272 .pdata = &msm_camera_device_data,
2273 .resource = msm_camera_resources,
2274 .num_resources = ARRAY_SIZE(msm_camera_resources),
2275 .flash_data = &flash_imx074,
2276 .strobe_flash_data = &strobe_flash_xenon,
Roja Rani Yarubandi68ebb4d2011-10-20 10:33:16 +05302277 .sensor_platform_info = &imx074_sensor_board_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002278 .csi_if = 1
2279};
2280struct platform_device msm_camera_sensor_imx074 = {
2281 .name = "msm_camera_imx074",
2282 .dev = {
2283 .platform_data = &msm_camera_sensor_imx074_data,
2284 },
2285};
2286#endif
2287#ifdef CONFIG_WEBCAM_OV9726
2288
2289static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2290 .mount_angle = 0
2291};
2292
2293static struct msm_camera_sensor_flash_data flash_ov9726 = {
2294 .flash_type = MSM_CAMERA_FLASH_LED,
2295 .flash_src = &msm_flash_src
2296};
2297static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2298 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002299 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002300 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2301 .sensor_pwd = 85,
2302 .vcm_pwd = 1,
2303 .vcm_enable = 0,
2304 .pdata = &msm_camera_device_data_web_cam,
2305 .resource = msm_camera_resources,
2306 .num_resources = ARRAY_SIZE(msm_camera_resources),
2307 .flash_data = &flash_ov9726,
2308 .sensor_platform_info = &ov9726_sensor_8660_info,
2309 .csi_if = 1
2310};
2311struct platform_device msm_camera_sensor_webcam_ov9726 = {
2312 .name = "msm_camera_ov9726",
2313 .dev = {
2314 .platform_data = &msm_camera_sensor_ov9726_data,
2315 },
2316};
2317#endif
2318#ifdef CONFIG_WEBCAM_OV7692
2319static struct msm_camera_sensor_flash_data flash_ov7692 = {
2320 .flash_type = MSM_CAMERA_FLASH_LED,
2321 .flash_src = &msm_flash_src
2322};
2323static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2324 .sensor_name = "ov7692",
2325 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2326 .sensor_pwd = 85,
2327 .vcm_pwd = 1,
2328 .vcm_enable = 0,
2329 .pdata = &msm_camera_device_data_web_cam,
2330 .resource = msm_camera_resources,
2331 .num_resources = ARRAY_SIZE(msm_camera_resources),
2332 .flash_data = &flash_ov7692,
2333 .csi_if = 1
2334};
2335
2336static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2337 .name = "msm_camera_ov7692",
2338 .dev = {
2339 .platform_data = &msm_camera_sensor_ov7692_data,
2340 },
2341};
2342#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002343#ifdef CONFIG_VX6953
2344static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2345 .mount_angle = 270
2346};
2347
2348static struct msm_camera_sensor_flash_data flash_vx6953 = {
2349 .flash_type = MSM_CAMERA_FLASH_NONE,
2350 .flash_src = &msm_flash_src
2351};
2352
2353static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2354 .sensor_name = "vx6953",
2355 .sensor_reset = 63,
2356 .sensor_pwd = 63,
2357 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2358 .vcm_enable = 1,
2359 .pdata = &msm_camera_device_data,
2360 .resource = msm_camera_resources,
2361 .num_resources = ARRAY_SIZE(msm_camera_resources),
2362 .flash_data = &flash_vx6953,
2363 .sensor_platform_info = &vx6953_sensor_8660_info,
2364 .csi_if = 1
2365};
2366struct platform_device msm_camera_sensor_vx6953 = {
2367 .name = "msm_camera_vx6953",
2368 .dev = {
2369 .platform_data = &msm_camera_sensor_vx6953_data,
2370 },
2371};
2372#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002373#ifdef CONFIG_QS_S5K4E1
2374
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302375static struct msm_camera_sensor_platform_info qs_s5k4e1_sensor_8660_info = {
2376#ifdef CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
2377 .mount_angle = 90
2378#else
2379 .mount_angle = 0
2380#endif
2381};
2382
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002383static char eeprom_data[864];
2384static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2385 .flash_type = MSM_CAMERA_FLASH_LED,
2386 .flash_src = &msm_flash_src
2387};
2388
2389static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2390 .sensor_name = "qs_s5k4e1",
2391 .sensor_reset = 106,
2392 .sensor_pwd = 85,
2393 .vcm_pwd = 1,
2394 .vcm_enable = 0,
2395 .pdata = &msm_camera_device_data_qs_cam,
2396 .resource = msm_camera_resources,
2397 .num_resources = ARRAY_SIZE(msm_camera_resources),
2398 .flash_data = &flash_qs_s5k4e1,
2399 .strobe_flash_data = &strobe_flash_xenon,
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302400 .sensor_platform_info = &qs_s5k4e1_sensor_8660_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002401 .csi_if = 1,
2402 .eeprom_data = eeprom_data,
2403};
2404struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2405 .name = "msm_camera_qs_s5k4e1",
2406 .dev = {
2407 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2408 },
2409};
2410#endif
2411static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2412 #ifdef CONFIG_MT9E013
2413 {
2414 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2415 },
2416 #endif
2417 #ifdef CONFIG_IMX074
2418 {
2419 I2C_BOARD_INFO("imx074", 0x1A),
2420 },
2421 #endif
2422 #ifdef CONFIG_WEBCAM_OV7692
2423 {
2424 I2C_BOARD_INFO("ov7692", 0x78),
2425 },
2426 #endif
2427 #ifdef CONFIG_WEBCAM_OV9726
2428 {
2429 I2C_BOARD_INFO("ov9726", 0x10),
2430 },
2431 #endif
2432 #ifdef CONFIG_QS_S5K4E1
2433 {
2434 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2435 },
2436 #endif
2437};
Jilai Wang971f97f2011-07-13 14:25:25 -04002438
2439static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002440 #ifdef CONFIG_WEBCAM_OV9726
2441 {
2442 I2C_BOARD_INFO("ov9726", 0x10),
2443 },
2444 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002445 #ifdef CONFIG_VX6953
2446 {
2447 I2C_BOARD_INFO("vx6953", 0x20),
2448 },
2449 #endif
2450};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002451#endif
2452
2453#ifdef CONFIG_MSM_GEMINI
2454static struct resource msm_gemini_resources[] = {
2455 {
2456 .start = 0x04600000,
2457 .end = 0x04600000 + SZ_1M - 1,
2458 .flags = IORESOURCE_MEM,
2459 },
2460 {
2461 .start = INT_JPEG,
2462 .end = INT_JPEG,
2463 .flags = IORESOURCE_IRQ,
2464 },
2465};
2466
2467static struct platform_device msm_gemini_device = {
2468 .name = "msm_gemini",
2469 .resource = msm_gemini_resources,
2470 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2471};
2472#endif
2473
2474#ifdef CONFIG_I2C_QUP
2475static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2476{
2477}
2478
2479static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2480 .clk_freq = 384000,
2481 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002482 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2483};
2484
2485static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2486 .clk_freq = 100000,
2487 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002488 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2489};
2490
2491static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2492 .clk_freq = 100000,
2493 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002494 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2495};
2496
2497static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2498 .clk_freq = 100000,
2499 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002500 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2501};
2502
2503static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2504 .clk_freq = 100000,
2505 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002506 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2507};
2508
2509static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2510 .clk_freq = 100000,
2511 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002512 .use_gsbi_shared_mode = 1,
2513 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2514};
2515#endif
2516
2517#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2518static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2519 .max_clock_speed = 24000000,
2520};
2521
2522static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2523 .max_clock_speed = 24000000,
2524};
2525#endif
2526
2527#ifdef CONFIG_I2C_SSBI
2528/* PMIC SSBI */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002529static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2530 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2531};
2532
2533/* CODEC/TSSC SSBI */
2534static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2535 .controller_type = MSM_SBI_CTRL_SSBI,
2536};
2537#endif
2538
2539#ifdef CONFIG_BATTERY_MSM
2540/* Use basic value for fake MSM battery */
2541static struct msm_psy_batt_pdata msm_psy_batt_data = {
2542 .avail_chg_sources = AC_CHG,
2543};
2544
2545static struct platform_device msm_batt_device = {
2546 .name = "msm-battery",
2547 .id = -1,
2548 .dev.platform_data = &msm_psy_batt_data,
2549};
2550#endif
2551
2552#ifdef CONFIG_FB_MSM_LCDC_DSUB
2553/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2554 prim = 1024 x 600 x 4(bpp) x 2(pages)
2555 This is the difference. */
2556#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2557#else
2558#define MSM_FB_DSUB_PMEM_ADDER (0)
2559#endif
2560
2561/* Sensors DSPS platform data */
2562#ifdef CONFIG_MSM_DSPS
2563
2564static struct dsps_gpio_info dsps_surf_gpios[] = {
2565 {
2566 .name = "compass_rst_n",
2567 .num = GPIO_COMPASS_RST_N,
2568 .on_val = 1, /* device not in reset */
2569 .off_val = 0, /* device in reset */
2570 },
2571 {
2572 .name = "gpio_r_altimeter_reset_n",
2573 .num = GPIO_R_ALTIMETER_RESET_N,
2574 .on_val = 1, /* device not in reset */
2575 .off_val = 0, /* device in reset */
2576 }
2577};
2578
2579static struct dsps_gpio_info dsps_fluid_gpios[] = {
2580 {
2581 .name = "gpio_n_altimeter_reset_n",
2582 .num = GPIO_N_ALTIMETER_RESET_N,
2583 .on_val = 1, /* device not in reset */
2584 .off_val = 0, /* device in reset */
2585 }
2586};
2587
2588static void __init msm8x60_init_dsps(void)
2589{
2590 struct msm_dsps_platform_data *pdata =
2591 msm_dsps_device.dev.platform_data;
2592 /*
2593 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2594 * to the power supply and not controled via GPIOs. Fluid uses a
2595 * different IO-Expender (north) than used on surf/ffa.
2596 */
2597 if (machine_is_msm8x60_fluid()) {
2598 /* fluid has different firmware, gpios */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002599 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2600 pdata->gpios = dsps_fluid_gpios;
2601 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2602 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002603 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2604 pdata->gpios = dsps_surf_gpios;
2605 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2606 }
2607
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002608 platform_device_register(&msm_dsps_device);
2609}
2610#endif /* CONFIG_MSM_DSPS */
2611
2612#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002613#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002614#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002615#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002616#endif
2617
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002618#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2619#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
2620#elif defined(CONFIG_FB_MSM_TVOUT)
2621#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
2622#else
2623#define MSM_FB_EXT_BUFT_SIZE 0
2624#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002625
2626#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002627/* width x height x 3 bpp x 2 frame buffer */
2628#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002629#define MSM_FB_WRITEBACK_OFFSET \
2630 (MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002631#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002632#define MSM_FB_WRITEBACK_SIZE 0
2633#define MSM_FB_WRITEBACK_OFFSET 0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002634#endif
2635
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002636#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2637/* 4 bpp x 2 page HDMI case */
2638#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
2639#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002640/* Note: must be multiple of 4096 */
2641#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
2642 MSM_FB_WRITEBACK_SIZE + \
2643 MSM_FB_DSUB_PMEM_ADDER, 4096)
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002644#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002645
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002646#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2647#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
2648#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002649#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002650#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002651
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002652static int writeback_offset(void)
2653{
2654 return MSM_FB_WRITEBACK_OFFSET;
2655}
2656
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002657#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2658#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002659#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002660
2661#define MSM_SMI_BASE 0x38000000
2662#define MSM_SMI_SIZE 0x4000000
2663
2664#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2665#define KERNEL_SMI_SIZE 0x300000
2666
2667#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2668#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2669#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2670
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002671#define MSM_ION_EBI_SIZE MSM_PMEM_SF_SIZE
2672#define MSM_ION_ADSP_SIZE MSM_PMEM_ADSP_SIZE
Laura Abbottdf8b8a82011-11-02 23:13:45 -07002673#define MSM_ION_SMI_SIZE MSM_PMEM_SMIPOOL_SIZE
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002674
2675#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
2676#define MSM_ION_HEAP_NUM 5
2677#else
2678#define MSM_ION_HEAP_NUM 2
2679#endif
2680
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002681static unsigned fb_size;
2682static int __init fb_size_setup(char *p)
2683{
2684 fb_size = memparse(p, NULL);
2685 return 0;
2686}
2687early_param("fb_size", fb_size_setup);
2688
2689static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2690static int __init pmem_kernel_ebi1_size_setup(char *p)
2691{
2692 pmem_kernel_ebi1_size = memparse(p, NULL);
2693 return 0;
2694}
2695early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2696
2697#ifdef CONFIG_ANDROID_PMEM
2698static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2699static int __init pmem_sf_size_setup(char *p)
2700{
2701 pmem_sf_size = memparse(p, NULL);
2702 return 0;
2703}
2704early_param("pmem_sf_size", pmem_sf_size_setup);
2705
2706static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2707
2708static int __init pmem_adsp_size_setup(char *p)
2709{
2710 pmem_adsp_size = memparse(p, NULL);
2711 return 0;
2712}
2713early_param("pmem_adsp_size", pmem_adsp_size_setup);
2714
2715static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2716
2717static int __init pmem_audio_size_setup(char *p)
2718{
2719 pmem_audio_size = memparse(p, NULL);
2720 return 0;
2721}
2722early_param("pmem_audio_size", pmem_audio_size_setup);
2723#endif
2724
2725static struct resource msm_fb_resources[] = {
2726 {
2727 .flags = IORESOURCE_DMA,
2728 }
2729};
2730
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002731static int msm_fb_detect_panel(const char *name)
2732{
2733 if (machine_is_msm8x60_fluid()) {
2734 uint32_t soc_platform_version = socinfo_get_platform_version();
2735 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2736#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2737 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002738 strnlen(LCDC_SAMSUNG_OLED_PANEL_NAME,
2739 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002740 return 0;
2741#endif
2742 } else { /*P3 and up use AUO panel */
2743#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2744 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002745 strnlen(LCDC_AUO_PANEL_NAME,
2746 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002747 return 0;
2748#endif
2749 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002750#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2751 } else if machine_is_msm8x60_dragon() {
2752 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002753 strnlen(LCDC_NT35582_PANEL_NAME,
2754 PANEL_NAME_MAX_LEN)))
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002755 return 0;
2756#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002757 } else {
2758 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002759 strnlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2760 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002761 return 0;
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002762
2763#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
2764 !defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
2765 !defined(CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT)
2766 if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2767 strnlen(MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2768 PANEL_NAME_MAX_LEN)))
2769 return 0;
2770
2771 if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2772 strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2773 PANEL_NAME_MAX_LEN)))
2774 return 0;
2775
2776 if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2777 strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2778 PANEL_NAME_MAX_LEN)))
2779 return 0;
2780#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002781 }
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002782
2783 if (!strncmp(name, HDMI_PANEL_NAME,
2784 strnlen(HDMI_PANEL_NAME,
2785 PANEL_NAME_MAX_LEN)))
2786 return 0;
2787
2788 if (!strncmp(name, TVOUT_PANEL_NAME,
2789 strnlen(TVOUT_PANEL_NAME,
2790 PANEL_NAME_MAX_LEN)))
2791 return 0;
2792
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002793 pr_warning("%s: not supported '%s'", __func__, name);
2794 return -ENODEV;
2795}
2796
2797static struct msm_fb_platform_data msm_fb_pdata = {
2798 .detect_client = msm_fb_detect_panel,
2799};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002800
2801static struct platform_device msm_fb_device = {
2802 .name = "msm_fb",
2803 .id = 0,
2804 .num_resources = ARRAY_SIZE(msm_fb_resources),
2805 .resource = msm_fb_resources,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002806 .dev.platform_data = &msm_fb_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002807};
2808
2809#ifdef CONFIG_ANDROID_PMEM
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002810#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002811static struct android_pmem_platform_data android_pmem_pdata = {
2812 .name = "pmem",
2813 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2814 .cached = 1,
2815 .memory_type = MEMTYPE_EBI1,
2816};
2817
2818static struct platform_device android_pmem_device = {
2819 .name = "android_pmem",
2820 .id = 0,
2821 .dev = {.platform_data = &android_pmem_pdata},
2822};
2823
2824static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2825 .name = "pmem_adsp",
2826 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2827 .cached = 0,
2828 .memory_type = MEMTYPE_EBI1,
2829};
2830
2831static struct platform_device android_pmem_adsp_device = {
2832 .name = "android_pmem",
2833 .id = 2,
2834 .dev = { .platform_data = &android_pmem_adsp_pdata },
2835};
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002836#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002837static struct android_pmem_platform_data android_pmem_audio_pdata = {
2838 .name = "pmem_audio",
2839 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2840 .cached = 0,
2841 .memory_type = MEMTYPE_EBI1,
2842};
2843
2844static struct platform_device android_pmem_audio_device = {
2845 .name = "android_pmem",
2846 .id = 4,
2847 .dev = { .platform_data = &android_pmem_audio_pdata },
2848};
2849
Laura Abbott1e36a022011-06-22 17:08:13 -07002850#define PMEM_BUS_WIDTH(_bw) \
2851 { \
2852 .vectors = &(struct msm_bus_vectors){ \
2853 .src = MSM_BUS_MASTER_AMPSS_M0, \
2854 .dst = MSM_BUS_SLAVE_SMI, \
2855 .ib = (_bw), \
2856 .ab = 0, \
2857 }, \
2858 .num_paths = 1, \
2859 }
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002860#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Laura Abbott1e36a022011-06-22 17:08:13 -07002861static struct msm_bus_paths pmem_smi_table[] = {
2862 [0] = PMEM_BUS_WIDTH(0), /* Off */
2863 [1] = PMEM_BUS_WIDTH(1), /* On */
2864};
2865
2866static struct msm_bus_scale_pdata smi_client_pdata = {
2867 .usecase = pmem_smi_table,
2868 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2869 .name = "pmem_smi",
2870};
2871
Alex Bird199980e2011-10-21 11:29:27 -07002872void request_smi_region(void *data)
Laura Abbott1e36a022011-06-22 17:08:13 -07002873{
2874 int bus_id = (int) data;
2875
2876 msm_bus_scale_client_update_request(bus_id, 1);
2877}
2878
Alex Bird199980e2011-10-21 11:29:27 -07002879void release_smi_region(void *data)
Laura Abbott1e36a022011-06-22 17:08:13 -07002880{
2881 int bus_id = (int) data;
2882
2883 msm_bus_scale_client_update_request(bus_id, 0);
2884}
2885
Alex Bird199980e2011-10-21 11:29:27 -07002886void *setup_smi_region(void)
Laura Abbott1e36a022011-06-22 17:08:13 -07002887{
2888 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2889}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002890static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2891 .name = "pmem_smipool",
2892 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2893 .cached = 0,
2894 .memory_type = MEMTYPE_SMI,
Alex Bird199980e2011-10-21 11:29:27 -07002895 .request_region = request_smi_region,
2896 .release_region = release_smi_region,
2897 .setup_region = setup_smi_region,
Laura Abbott1e36a022011-06-22 17:08:13 -07002898 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002899};
2900static struct platform_device android_pmem_smipool_device = {
2901 .name = "android_pmem",
2902 .id = 7,
2903 .dev = { .platform_data = &android_pmem_smipool_pdata },
2904};
Laura Abbott63cfd7e2011-10-10 18:21:01 -07002905#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002906#endif
2907
2908#define GPIO_DONGLE_PWR_EN 258
2909static void setup_display_power(void);
2910static int lcdc_vga_enabled;
2911static int vga_enable_request(int enable)
2912{
2913 if (enable)
2914 lcdc_vga_enabled = 1;
2915 else
2916 lcdc_vga_enabled = 0;
2917 setup_display_power();
2918
2919 return 0;
2920}
2921
2922#define GPIO_BACKLIGHT_PWM0 0
2923#define GPIO_BACKLIGHT_PWM1 1
2924
2925static int pmic_backlight_gpio[2]
2926 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2927static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2928 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2929 .vga_switch = vga_enable_request,
2930};
2931
2932static struct platform_device lcdc_samsung_panel_device = {
2933 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2934 .id = 0,
2935 .dev = {
2936 .platform_data = &lcdc_samsung_panel_data,
2937 }
2938};
2939#if (!defined(CONFIG_SPI_QUP)) && \
2940 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2941 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2942
2943static int lcdc_spi_gpio_array_num[] = {
2944 LCDC_SPI_GPIO_CLK,
2945 LCDC_SPI_GPIO_CS,
2946 LCDC_SPI_GPIO_MOSI,
2947};
2948
2949static uint32_t lcdc_spi_gpio_config_data[] = {
2950 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2951 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2952 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2953 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2954 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2955 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2956};
2957
2958static void lcdc_config_spi_gpios(int enable)
2959{
2960 int n;
2961 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2962 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2963}
2964#endif
2965
2966#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2967#ifdef CONFIG_SPI_QUP
2968static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2969 {
2970 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2971 .mode = SPI_MODE_3,
2972 .bus_num = 1,
2973 .chip_select = 0,
2974 .max_speed_hz = 10800000,
2975 }
2976};
2977#endif /* CONFIG_SPI_QUP */
2978
2979static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2980#ifndef CONFIG_SPI_QUP
2981 .panel_config_gpio = lcdc_config_spi_gpios,
2982 .gpio_num = lcdc_spi_gpio_array_num,
2983#endif
2984};
2985
2986static struct platform_device lcdc_samsung_oled_panel_device = {
2987 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2988 .id = 0,
2989 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2990};
2991#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2992
2993#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2994#ifdef CONFIG_SPI_QUP
2995static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2996 {
2997 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2998 .mode = SPI_MODE_3,
2999 .bus_num = 1,
3000 .chip_select = 0,
3001 .max_speed_hz = 10800000,
3002 }
3003};
3004#endif
3005
3006static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
3007#ifndef CONFIG_SPI_QUP
3008 .panel_config_gpio = lcdc_config_spi_gpios,
3009 .gpio_num = lcdc_spi_gpio_array_num,
3010#endif
3011};
3012
3013static struct platform_device lcdc_auo_wvga_panel_device = {
3014 .name = LCDC_AUO_PANEL_NAME,
3015 .id = 0,
3016 .dev.platform_data = &lcdc_auo_wvga_panel_data,
3017};
3018#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
3019
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04003020#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
3021
3022#define GPIO_NT35582_RESET 94
3023#define GPIO_NT35582_BL_EN_HW_PIN 24
3024#define GPIO_NT35582_BL_EN \
3025 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
3026
3027static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
3028
3029static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
3030 .gpio_num = lcdc_nt35582_pmic_gpio,
3031};
3032
3033static struct platform_device lcdc_nt35582_panel_device = {
3034 .name = LCDC_NT35582_PANEL_NAME,
3035 .id = 0,
3036 .dev = {
3037 .platform_data = &lcdc_nt35582_panel_data,
3038 }
3039};
3040
3041static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
3042 {
3043 .modalias = "lcdc_nt35582_spi",
3044 .mode = SPI_MODE_0,
3045 .bus_num = 0,
3046 .chip_select = 0,
3047 .max_speed_hz = 1100000,
3048 }
3049};
3050#endif
3051
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003052#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
3053static struct resource hdmi_msm_resources[] = {
3054 {
3055 .name = "hdmi_msm_qfprom_addr",
3056 .start = 0x00700000,
3057 .end = 0x007060FF,
3058 .flags = IORESOURCE_MEM,
3059 },
3060 {
3061 .name = "hdmi_msm_hdmi_addr",
3062 .start = 0x04A00000,
3063 .end = 0x04A00FFF,
3064 .flags = IORESOURCE_MEM,
3065 },
3066 {
3067 .name = "hdmi_msm_irq",
3068 .start = HDMI_IRQ,
3069 .end = HDMI_IRQ,
3070 .flags = IORESOURCE_IRQ,
3071 },
3072};
3073
3074static int hdmi_enable_5v(int on);
3075static int hdmi_core_power(int on, int show);
3076static int hdmi_cec_power(int on);
3077
3078static struct msm_hdmi_platform_data hdmi_msm_data = {
3079 .irq = HDMI_IRQ,
3080 .enable_5v = hdmi_enable_5v,
3081 .core_power = hdmi_core_power,
3082 .cec_power = hdmi_cec_power,
3083};
3084
3085static struct platform_device hdmi_msm_device = {
3086 .name = "hdmi_msm",
3087 .id = 0,
3088 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
3089 .resource = hdmi_msm_resources,
3090 .dev.platform_data = &hdmi_msm_data,
3091};
3092#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
3093
3094#ifdef CONFIG_FB_MSM_MIPI_DSI
3095static struct platform_device mipi_dsi_toshiba_panel_device = {
3096 .name = "mipi_toshiba",
3097 .id = 0,
3098};
3099
3100#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3101
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003102static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003103 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
Chandan Uddaraju83eac3c2011-09-11 18:32:23 -07003104 .fpga_ctrl_mode = FPGA_EBI2_INTF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003105};
3106
3107static struct platform_device mipi_dsi_novatek_panel_device = {
3108 .name = "mipi_novatek",
3109 .id = 0,
3110 .dev = {
3111 .platform_data = &novatek_pdata,
3112 }
3113};
3114#endif
3115
3116static void __init msm8x60_allocate_memory_regions(void)
3117{
3118 void *addr;
3119 unsigned long size;
3120
3121 size = MSM_FB_SIZE;
3122 addr = alloc_bootmem_align(size, 0x1000);
3123 msm_fb_resources[0].start = __pa(addr);
3124 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3125 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3126 size, addr, __pa(addr));
3127
3128}
3129
3130#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3131 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3132/*virtual key support */
3133static ssize_t tma300_vkeys_show(struct kobject *kobj,
3134 struct kobj_attribute *attr, char *buf)
3135{
3136 return sprintf(buf,
3137 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3138 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3139 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3140 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3141 "\n");
3142}
3143
3144static struct kobj_attribute tma300_vkeys_attr = {
3145 .attr = {
3146 .mode = S_IRUGO,
3147 },
3148 .show = &tma300_vkeys_show,
3149};
3150
3151static struct attribute *tma300_properties_attrs[] = {
3152 &tma300_vkeys_attr.attr,
3153 NULL
3154};
3155
3156static struct attribute_group tma300_properties_attr_group = {
3157 .attrs = tma300_properties_attrs,
3158};
3159
3160static struct kobject *properties_kobj;
3161
3162
3163
3164#define CYTTSP_TS_GPIO_IRQ 61
3165static int cyttsp_platform_init(struct i2c_client *client)
3166{
3167 int rc = -EINVAL;
3168 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3169
3170 if (machine_is_msm8x60_fluid()) {
3171 pm8058_l5 = regulator_get(NULL, "8058_l5");
3172 if (IS_ERR(pm8058_l5)) {
3173 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3174 __func__, PTR_ERR(pm8058_l5));
3175 rc = PTR_ERR(pm8058_l5);
3176 return rc;
3177 }
3178 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3179 if (rc) {
3180 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3181 __func__, rc);
3182 goto reg_l5_put;
3183 }
3184
3185 rc = regulator_enable(pm8058_l5);
3186 if (rc) {
3187 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3188 __func__, rc);
3189 goto reg_l5_put;
3190 }
3191 }
3192 /* vote for s3 to enable i2c communication lines */
3193 pm8058_s3 = regulator_get(NULL, "8058_s3");
3194 if (IS_ERR(pm8058_s3)) {
3195 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3196 __func__, PTR_ERR(pm8058_s3));
3197 rc = PTR_ERR(pm8058_s3);
3198 goto reg_l5_disable;
3199 }
3200
3201 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3202 if (rc) {
3203 pr_err("%s: regulator_set_voltage() = %d\n",
3204 __func__, rc);
3205 goto reg_s3_put;
3206 }
3207
3208 rc = regulator_enable(pm8058_s3);
3209 if (rc) {
3210 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3211 __func__, rc);
3212 goto reg_s3_put;
3213 }
3214
3215 /* wait for vregs to stabilize */
3216 usleep_range(10000, 10000);
3217
3218 /* check this device active by reading first byte/register */
3219 rc = i2c_smbus_read_byte_data(client, 0x01);
3220 if (rc < 0) {
3221 pr_err("%s: i2c sanity check failed\n", __func__);
3222 goto reg_s3_disable;
3223 }
3224
3225 /* virtual keys */
3226 if (machine_is_msm8x60_fluid()) {
3227 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3228 properties_kobj = kobject_create_and_add("board_properties",
3229 NULL);
3230 if (properties_kobj)
3231 rc = sysfs_create_group(properties_kobj,
3232 &tma300_properties_attr_group);
3233 if (!properties_kobj || rc)
3234 pr_err("%s: failed to create board_properties\n",
3235 __func__);
3236 }
3237 return CY_OK;
3238
3239reg_s3_disable:
3240 regulator_disable(pm8058_s3);
3241reg_s3_put:
3242 regulator_put(pm8058_s3);
3243reg_l5_disable:
3244 if (machine_is_msm8x60_fluid())
3245 regulator_disable(pm8058_l5);
3246reg_l5_put:
3247 if (machine_is_msm8x60_fluid())
3248 regulator_put(pm8058_l5);
3249 return rc;
3250}
3251
Anirudh Ghayalf9929b12011-09-07 15:57:36 +05303252/* TODO: Put the regulator to LPM / HPM in suspend/resume*/
3253static int cyttsp_platform_suspend(struct i2c_client *client)
3254{
3255 msleep(20);
3256
3257 return CY_OK;
3258}
3259
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003260static int cyttsp_platform_resume(struct i2c_client *client)
3261{
3262 /* add any special code to strobe a wakeup pin or chip reset */
3263 msleep(10);
3264
3265 return CY_OK;
3266}
3267
3268static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3269 .flags = 0x04,
3270 .gen = CY_GEN3, /* or */
3271 .use_st = CY_USE_ST,
3272 .use_mt = CY_USE_MT,
3273 .use_hndshk = CY_SEND_HNDSHK,
3274 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303275 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003276 .use_gestures = CY_USE_GESTURES,
3277 /* activate up to 4 groups
3278 * and set active distance
3279 */
3280 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3281 CY_GEST_GRP3 | CY_GEST_GRP4 |
3282 CY_ACT_DIST,
3283 /* change act_intrvl to customize the Active power state
3284 * scanning/processing refresh interval for Operating mode
3285 */
3286 .act_intrvl = CY_ACT_INTRVL_DFLT,
3287 /* change tch_tmout to customize the touch timeout for the
3288 * Active power state for Operating mode
3289 */
3290 .tch_tmout = CY_TCH_TMOUT_DFLT,
3291 /* change lp_intrvl to customize the Low Power power state
3292 * scanning/processing refresh interval for Operating mode
3293 */
3294 .lp_intrvl = CY_LP_INTRVL_DFLT,
3295 .sleep_gpio = -1,
3296 .resout_gpio = -1,
3297 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3298 .resume = cyttsp_platform_resume,
Anirudh Ghayalf9929b12011-09-07 15:57:36 +05303299 .suspend = cyttsp_platform_suspend,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003300 .init = cyttsp_platform_init,
3301};
3302
3303static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3304 .panel_maxx = 1083,
3305 .panel_maxy = 659,
3306 .disp_minx = 30,
3307 .disp_maxx = 1053,
3308 .disp_miny = 30,
3309 .disp_maxy = 629,
3310 .correct_fw_ver = 8,
3311 .fw_fname = "cyttsp_8660_ffa.hex",
3312 .flags = 0x00,
3313 .gen = CY_GEN2, /* or */
3314 .use_st = CY_USE_ST,
3315 .use_mt = CY_USE_MT,
3316 .use_hndshk = CY_SEND_HNDSHK,
3317 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303318 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003319 .use_gestures = CY_USE_GESTURES,
3320 /* activate up to 4 groups
3321 * and set active distance
3322 */
3323 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3324 CY_GEST_GRP3 | CY_GEST_GRP4 |
3325 CY_ACT_DIST,
3326 /* change act_intrvl to customize the Active power state
3327 * scanning/processing refresh interval for Operating mode
3328 */
3329 .act_intrvl = CY_ACT_INTRVL_DFLT,
3330 /* change tch_tmout to customize the touch timeout for the
3331 * Active power state for Operating mode
3332 */
3333 .tch_tmout = CY_TCH_TMOUT_DFLT,
3334 /* change lp_intrvl to customize the Low Power power state
3335 * scanning/processing refresh interval for Operating mode
3336 */
3337 .lp_intrvl = CY_LP_INTRVL_DFLT,
3338 .sleep_gpio = -1,
3339 .resout_gpio = -1,
3340 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3341 .resume = cyttsp_platform_resume,
Anirudh Ghayalf9929b12011-09-07 15:57:36 +05303342 .suspend = cyttsp_platform_suspend,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003343 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303344 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003345};
3346static void cyttsp_set_params(void)
3347{
3348 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3349 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3350 cyttsp_fluid_pdata.panel_maxx = 539;
3351 cyttsp_fluid_pdata.panel_maxy = 994;
3352 cyttsp_fluid_pdata.disp_minx = 30;
3353 cyttsp_fluid_pdata.disp_maxx = 509;
3354 cyttsp_fluid_pdata.disp_miny = 60;
3355 cyttsp_fluid_pdata.disp_maxy = 859;
3356 cyttsp_fluid_pdata.correct_fw_ver = 4;
3357 } else {
3358 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3359 cyttsp_fluid_pdata.panel_maxx = 550;
3360 cyttsp_fluid_pdata.panel_maxy = 1013;
3361 cyttsp_fluid_pdata.disp_minx = 35;
3362 cyttsp_fluid_pdata.disp_maxx = 515;
3363 cyttsp_fluid_pdata.disp_miny = 69;
3364 cyttsp_fluid_pdata.disp_maxy = 869;
3365 cyttsp_fluid_pdata.correct_fw_ver = 5;
3366 }
3367
3368}
3369
3370static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3371 {
3372 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3373 .platform_data = &cyttsp_fluid_pdata,
3374#ifndef CY_USE_TIMER
3375 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3376#endif /* CY_USE_TIMER */
3377 },
3378};
3379
3380static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3381 {
3382 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3383 .platform_data = &cyttsp_tmg240_pdata,
3384#ifndef CY_USE_TIMER
3385 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3386#endif /* CY_USE_TIMER */
3387 },
3388};
3389#endif
3390
3391static struct regulator *vreg_tmg200;
3392
3393#define TS_PEN_IRQ_GPIO 61
3394static int tmg200_power(int vreg_on)
3395{
3396 int rc = -EINVAL;
3397
3398 if (!vreg_tmg200) {
3399 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3400 __func__, rc);
3401 return rc;
3402 }
3403
3404 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3405 regulator_disable(vreg_tmg200);
3406 if (rc < 0)
3407 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3408 __func__, vreg_on ? "enable" : "disable", rc);
3409
3410 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003411 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003412
3413 return rc;
3414}
3415
3416static int tmg200_dev_setup(bool enable)
3417{
3418 int rc;
3419
3420 if (enable) {
3421 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3422 if (IS_ERR(vreg_tmg200)) {
3423 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3424 __func__, PTR_ERR(vreg_tmg200));
3425 rc = PTR_ERR(vreg_tmg200);
3426 return rc;
3427 }
3428
3429 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3430 if (rc) {
3431 pr_err("%s: regulator_set_voltage() = %d\n",
3432 __func__, rc);
3433 goto reg_put;
3434 }
3435 } else {
3436 /* put voltage sources */
3437 regulator_put(vreg_tmg200);
3438 }
3439 return 0;
3440reg_put:
3441 regulator_put(vreg_tmg200);
3442 return rc;
3443}
3444
3445static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3446 .ts_name = "msm_tmg200_ts",
3447 .dis_min_x = 0,
3448 .dis_max_x = 1023,
3449 .dis_min_y = 0,
3450 .dis_max_y = 599,
3451 .min_tid = 0,
3452 .max_tid = 255,
3453 .min_touch = 0,
3454 .max_touch = 255,
3455 .min_width = 0,
3456 .max_width = 255,
3457 .power_on = tmg200_power,
3458 .dev_setup = tmg200_dev_setup,
3459 .nfingers = 2,
3460 .irq_gpio = TS_PEN_IRQ_GPIO,
3461 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3462};
3463
3464static struct i2c_board_info cy8ctmg200_board_info[] = {
3465 {
3466 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3467 .platform_data = &cy8ctmg200_pdata,
3468 }
3469};
3470
Zhang Chang Ken211df572011-07-05 19:16:39 -04003471static struct regulator *vreg_tma340;
3472
3473static int tma340_power(int vreg_on)
3474{
3475 int rc = -EINVAL;
3476
3477 if (!vreg_tma340) {
3478 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3479 __func__, rc);
3480 return rc;
3481 }
3482
3483 rc = vreg_on ? regulator_enable(vreg_tma340) :
3484 regulator_disable(vreg_tma340);
3485 if (rc < 0)
3486 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3487 __func__, vreg_on ? "enable" : "disable", rc);
3488
3489 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003490 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003491
3492 return rc;
3493}
3494
3495static struct kobject *tma340_prop_kobj;
3496
3497static int tma340_dragon_dev_setup(bool enable)
3498{
3499 int rc;
3500
3501 if (enable) {
3502 vreg_tma340 = regulator_get(NULL, "8901_l2");
3503 if (IS_ERR(vreg_tma340)) {
3504 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3505 __func__, PTR_ERR(vreg_tma340));
3506 rc = PTR_ERR(vreg_tma340);
3507 return rc;
3508 }
3509
3510 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3511 if (rc) {
3512 pr_err("%s: regulator_set_voltage() = %d\n",
3513 __func__, rc);
3514 goto reg_put;
3515 }
3516 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3517 tma340_prop_kobj = kobject_create_and_add("board_properties",
3518 NULL);
3519 if (tma340_prop_kobj) {
3520 rc = sysfs_create_group(tma340_prop_kobj,
3521 &tma300_properties_attr_group);
3522 if (rc) {
3523 kobject_put(tma340_prop_kobj);
3524 pr_err("%s: failed to create board_properties\n",
3525 __func__);
3526 goto reg_put;
3527 }
3528 }
3529
3530 } else {
3531 /* put voltage sources */
3532 regulator_put(vreg_tma340);
3533 /* destroy virtual keys */
3534 if (tma340_prop_kobj) {
3535 sysfs_remove_group(tma340_prop_kobj,
3536 &tma300_properties_attr_group);
3537 kobject_put(tma340_prop_kobj);
3538 }
3539 }
3540 return 0;
3541reg_put:
3542 regulator_put(vreg_tma340);
3543 return rc;
3544}
3545
3546
3547static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3548 .ts_name = "cy8ctma340",
3549 .dis_min_x = 0,
3550 .dis_max_x = 479,
3551 .dis_min_y = 0,
3552 .dis_max_y = 799,
3553 .min_tid = 0,
3554 .max_tid = 255,
3555 .min_touch = 0,
3556 .max_touch = 255,
3557 .min_width = 0,
3558 .max_width = 255,
3559 .power_on = tma340_power,
3560 .dev_setup = tma340_dragon_dev_setup,
3561 .nfingers = 2,
3562 .irq_gpio = TS_PEN_IRQ_GPIO,
3563 .resout_gpio = -1,
3564};
3565
3566static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3567 {
3568 I2C_BOARD_INFO("cy8ctma340", 0x24),
3569 .platform_data = &cy8ctma340_dragon_pdata,
3570 }
3571};
3572
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003573#ifdef CONFIG_SERIAL_MSM_HS
3574static int configure_uart_gpios(int on)
3575{
3576 int ret = 0, i;
3577 int uart_gpios[] = {53, 54, 55, 56};
3578 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3579 if (on) {
3580 ret = msm_gpiomux_get(uart_gpios[i]);
3581 if (unlikely(ret))
3582 break;
3583 } else {
3584 ret = msm_gpiomux_put(uart_gpios[i]);
3585 if (unlikely(ret))
3586 return ret;
3587 }
3588 }
3589 if (ret)
3590 for (; i >= 0; i--)
3591 msm_gpiomux_put(uart_gpios[i]);
3592 return ret;
3593}
3594static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3595 .inject_rx_on_wakeup = 1,
3596 .rx_to_inject = 0xFD,
3597 .gpio_config = configure_uart_gpios,
3598};
3599#endif
3600
3601
3602#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3603
3604static struct gpio_led gpio_exp_leds_config[] = {
3605 {
3606 .name = "left_led1:green",
3607 .gpio = GPIO_LEFT_LED_1,
3608 .active_low = 1,
3609 .retain_state_suspended = 0,
3610 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3611 },
3612 {
3613 .name = "left_led2:red",
3614 .gpio = GPIO_LEFT_LED_2,
3615 .active_low = 1,
3616 .retain_state_suspended = 0,
3617 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3618 },
3619 {
3620 .name = "left_led3:green",
3621 .gpio = GPIO_LEFT_LED_3,
3622 .active_low = 1,
3623 .retain_state_suspended = 0,
3624 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3625 },
3626 {
3627 .name = "wlan_led:orange",
3628 .gpio = GPIO_LEFT_LED_WLAN,
3629 .active_low = 1,
3630 .retain_state_suspended = 0,
3631 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3632 },
3633 {
3634 .name = "left_led5:green",
3635 .gpio = GPIO_LEFT_LED_5,
3636 .active_low = 1,
3637 .retain_state_suspended = 0,
3638 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3639 },
3640 {
3641 .name = "right_led1:green",
3642 .gpio = GPIO_RIGHT_LED_1,
3643 .active_low = 1,
3644 .retain_state_suspended = 0,
3645 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3646 },
3647 {
3648 .name = "right_led2:red",
3649 .gpio = GPIO_RIGHT_LED_2,
3650 .active_low = 1,
3651 .retain_state_suspended = 0,
3652 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3653 },
3654 {
3655 .name = "right_led3:green",
3656 .gpio = GPIO_RIGHT_LED_3,
3657 .active_low = 1,
3658 .retain_state_suspended = 0,
3659 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3660 },
3661 {
3662 .name = "bt_led:blue",
3663 .gpio = GPIO_RIGHT_LED_BT,
3664 .active_low = 1,
3665 .retain_state_suspended = 0,
3666 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3667 },
3668 {
3669 .name = "right_led5:green",
3670 .gpio = GPIO_RIGHT_LED_5,
3671 .active_low = 1,
3672 .retain_state_suspended = 0,
3673 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3674 },
3675};
3676
3677static struct gpio_led_platform_data gpio_leds_pdata = {
3678 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3679 .leds = gpio_exp_leds_config,
3680};
3681
3682static struct platform_device gpio_leds = {
3683 .name = "leds-gpio",
3684 .id = -1,
3685 .dev = {
3686 .platform_data = &gpio_leds_pdata,
3687 },
3688};
3689
3690static struct gpio_led fluid_gpio_leds[] = {
3691 {
3692 .name = "dual_led:green",
3693 .gpio = GPIO_LED1_GREEN_N,
3694 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3695 .active_low = 1,
3696 .retain_state_suspended = 0,
3697 },
3698 {
3699 .name = "dual_led:red",
3700 .gpio = GPIO_LED2_RED_N,
3701 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3702 .active_low = 1,
3703 .retain_state_suspended = 0,
3704 },
3705};
3706
3707static struct gpio_led_platform_data gpio_led_pdata = {
3708 .leds = fluid_gpio_leds,
3709 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3710};
3711
3712static struct platform_device fluid_leds_gpio = {
3713 .name = "leds-gpio",
3714 .id = -1,
3715 .dev = {
3716 .platform_data = &gpio_led_pdata,
3717 },
3718};
3719
3720#endif
3721
3722#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3723
3724static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3725 .phys_addr_base = 0x00106000,
3726 .reg_offsets = {
3727 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3728 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3729 },
3730 .phys_size = SZ_8K,
3731 .log_len = 4096, /* log's buffer length in bytes */
3732 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3733};
3734
3735static struct platform_device msm_rpm_log_device = {
3736 .name = "msm_rpm_log",
3737 .id = -1,
3738 .dev = {
3739 .platform_data = &msm_rpm_log_pdata,
3740 },
3741};
3742#endif
3743
3744#ifdef CONFIG_BATTERY_MSM8X60
3745static struct msm_charger_platform_data msm_charger_data = {
3746 .safety_time = 180,
3747 .update_time = 1,
3748 .max_voltage = 4200,
3749 .min_voltage = 3200,
3750};
3751
3752static struct platform_device msm_charger_device = {
3753 .name = "msm-charger",
3754 .id = -1,
3755 .dev = {
3756 .platform_data = &msm_charger_data,
3757 }
3758};
3759#endif
3760
3761/*
3762 * Consumer specific regulator names:
3763 * regulator name consumer dev_name
3764 */
3765static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3766 REGULATOR_SUPPLY("8058_l0", NULL),
3767};
3768static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3769 REGULATOR_SUPPLY("8058_l1", NULL),
3770};
3771static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3772 REGULATOR_SUPPLY("8058_l2", NULL),
3773};
3774static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3775 REGULATOR_SUPPLY("8058_l3", NULL),
3776};
3777static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3778 REGULATOR_SUPPLY("8058_l4", NULL),
3779};
3780static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3781 REGULATOR_SUPPLY("8058_l5", NULL),
3782};
3783static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3784 REGULATOR_SUPPLY("8058_l6", NULL),
3785};
3786static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3787 REGULATOR_SUPPLY("8058_l7", NULL),
3788};
3789static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3790 REGULATOR_SUPPLY("8058_l8", NULL),
3791};
3792static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3793 REGULATOR_SUPPLY("8058_l9", NULL),
3794};
3795static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3796 REGULATOR_SUPPLY("8058_l10", NULL),
3797};
3798static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3799 REGULATOR_SUPPLY("8058_l11", NULL),
3800};
3801static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3802 REGULATOR_SUPPLY("8058_l12", NULL),
3803};
3804static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3805 REGULATOR_SUPPLY("8058_l13", NULL),
3806};
3807static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3808 REGULATOR_SUPPLY("8058_l14", NULL),
3809};
3810static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3811 REGULATOR_SUPPLY("8058_l15", NULL),
3812};
3813static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3814 REGULATOR_SUPPLY("8058_l16", NULL),
3815};
3816static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3817 REGULATOR_SUPPLY("8058_l17", NULL),
3818};
3819static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3820 REGULATOR_SUPPLY("8058_l18", NULL),
3821};
3822static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3823 REGULATOR_SUPPLY("8058_l19", NULL),
3824};
3825static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3826 REGULATOR_SUPPLY("8058_l20", NULL),
3827};
3828static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3829 REGULATOR_SUPPLY("8058_l21", NULL),
3830};
3831static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3832 REGULATOR_SUPPLY("8058_l22", NULL),
3833};
3834static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3835 REGULATOR_SUPPLY("8058_l23", NULL),
3836};
3837static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3838 REGULATOR_SUPPLY("8058_l24", NULL),
3839};
3840static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3841 REGULATOR_SUPPLY("8058_l25", NULL),
3842};
3843static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3844 REGULATOR_SUPPLY("8058_s0", NULL),
3845};
3846static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3847 REGULATOR_SUPPLY("8058_s1", NULL),
3848};
3849static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3850 REGULATOR_SUPPLY("8058_s2", NULL),
3851};
3852static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3853 REGULATOR_SUPPLY("8058_s3", NULL),
3854};
3855static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3856 REGULATOR_SUPPLY("8058_s4", NULL),
3857};
3858static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3859 REGULATOR_SUPPLY("8058_lvs0", NULL),
3860};
3861static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3862 REGULATOR_SUPPLY("8058_lvs1", NULL),
3863};
3864static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3865 REGULATOR_SUPPLY("8058_ncp", NULL),
3866};
3867
3868static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3869 REGULATOR_SUPPLY("8901_l0", NULL),
3870};
3871static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3872 REGULATOR_SUPPLY("8901_l1", NULL),
3873};
3874static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3875 REGULATOR_SUPPLY("8901_l2", NULL),
3876};
3877static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3878 REGULATOR_SUPPLY("8901_l3", NULL),
3879};
3880static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3881 REGULATOR_SUPPLY("8901_l4", NULL),
3882};
3883static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3884 REGULATOR_SUPPLY("8901_l5", NULL),
3885};
3886static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3887 REGULATOR_SUPPLY("8901_l6", NULL),
3888};
3889static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3890 REGULATOR_SUPPLY("8901_s2", NULL),
3891};
3892static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3893 REGULATOR_SUPPLY("8901_s3", NULL),
3894};
3895static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3896 REGULATOR_SUPPLY("8901_s4", NULL),
3897};
3898static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3899 REGULATOR_SUPPLY("8901_lvs0", NULL),
3900};
3901static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3902 REGULATOR_SUPPLY("8901_lvs1", NULL),
3903};
3904static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3905 REGULATOR_SUPPLY("8901_lvs2", NULL),
3906};
3907static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3908 REGULATOR_SUPPLY("8901_lvs3", NULL),
3909};
3910static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3911 REGULATOR_SUPPLY("8901_mvs0", NULL),
3912};
3913
David Collins6f032ba2011-08-31 14:08:15 -07003914/* Pin control regulators */
3915static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
3916 REGULATOR_SUPPLY("8058_l8_pc", NULL),
3917};
3918static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
3919 REGULATOR_SUPPLY("8058_l20_pc", NULL),
3920};
3921static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
3922 REGULATOR_SUPPLY("8058_l21_pc", NULL),
3923};
3924static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
3925 REGULATOR_SUPPLY("8058_s2_pc", NULL),
3926};
3927static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
3928 REGULATOR_SUPPLY("8901_l0_pc", NULL),
3929};
3930static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
3931 REGULATOR_SUPPLY("8901_s4_pc", NULL),
3932};
3933
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003934#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3935 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
David Collins6f032ba2011-08-31 14:08:15 -07003936 _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003937 _always_on) \
David Collins6f032ba2011-08-31 14:08:15 -07003938 { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003939 .init_data = { \
3940 .constraints = { \
David Collins6f032ba2011-08-31 14:08:15 -07003941 .valid_modes_mask = _modes, \
3942 .valid_ops_mask = _ops, \
3943 .min_uV = _min_uV, \
3944 .max_uV = _max_uV, \
3945 .input_uV = _min_uV, \
3946 .apply_uV = _apply_uV, \
3947 .always_on = _always_on, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003948 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003949 .consumer_supplies = vreg_consumers_##_id, \
3950 .num_consumer_supplies = \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003951 ARRAY_SIZE(vreg_consumers_##_id), \
3952 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003953 .id = RPM_VREG_ID_##_id, \
3954 .default_uV = _default_uV, \
3955 .peak_uA = _peak_uA, \
3956 .avg_uA = _avg_uA, \
3957 .pull_down_enable = _pull_down, \
3958 .pin_ctrl = _pin_ctrl, \
3959 .freq = RPM_VREG_FREQ_##_freq, \
3960 .pin_fn = _pin_fn, \
3961 .force_mode = _force_mode, \
3962 .state = _state, \
3963 .sleep_selectable = _sleep_selectable, \
3964 }
3965
3966/* Pin control initialization */
3967#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
3968 { \
3969 .init_data = { \
3970 .constraints = { \
3971 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
3972 .always_on = _always_on, \
3973 }, \
3974 .num_consumer_supplies = \
3975 ARRAY_SIZE(vreg_consumers_##_id##_PC), \
3976 .consumer_supplies = vreg_consumers_##_id##_PC, \
3977 }, \
3978 .id = RPM_VREG_ID_##_id##_PC, \
3979 .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003980 .pin_ctrl = _pin_ctrl, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003981 }
3982
3983/*
3984 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3985 * via the peak_uA value specified in the table below. If the value is less
3986 * than the high power min threshold for the regulator, then the regulator will
3987 * be set to LPM. Otherwise, it will be set to HPM.
3988 *
3989 * This value can be further overridden by specifying an initial mode via
3990 * .init_data.constraints.initial_mode.
3991 */
3992
David Collins6f032ba2011-08-31 14:08:15 -07003993#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3994 _init_peak_uA) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003995 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3996 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3997 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3998 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3999 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07004000 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
4001 RPM_VREG_PIN_FN_8660_ENABLE, \
4002 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004003 _sleep_selectable, _always_on)
4004
David Collins6f032ba2011-08-31 14:08:15 -07004005#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
4006 _init_peak_uA, _freq) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004007 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
4008 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
4009 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
4010 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
4011 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07004012 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
4013 RPM_VREG_PIN_FN_8660_ENABLE, \
4014 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
4015 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004016
David Collins6f032ba2011-08-31 14:08:15 -07004017#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004018 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
4019 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07004020 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
4021 RPM_VREG_PIN_FN_8660_ENABLE, \
4022 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
4023 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004024
David Collins6f032ba2011-08-31 14:08:15 -07004025#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004026 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
4027 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07004028 _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
4029 RPM_VREG_PIN_FN_8660_ENABLE, \
4030 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
4031 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004032
David Collins6f032ba2011-08-31 14:08:15 -07004033#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
4034#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
4035#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
4036#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
4037#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004038
David Collins6f032ba2011-08-31 14:08:15 -07004039/* RPM early regulator constraints */
4040static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
4041 /* ID a_on pd ss min_uV max_uV init_ip freq */
4042 RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
4043 RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004044};
4045
David Collins6f032ba2011-08-31 14:08:15 -07004046/* RPM regulator constraints */
4047static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
4048 /* ID a_on pd ss min_uV max_uV init_ip */
4049 RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4050 RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4051 RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
4052 RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4053 RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
4054 RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4055 RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
4056 RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
4057 RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
4058 RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
4059 RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4060 RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
4061 RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
4062 RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
4063 RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
4064 RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4065 RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
4066 RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
4067 RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
4068 RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
4069 RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4070 RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
4071 RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
4072 RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4073 RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4074 RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004075
David Collins6f032ba2011-08-31 14:08:15 -07004076 /* ID a_on pd ss min_uV max_uV init_ip freq */
4077 RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
4078 RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
4079 RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
4080
4081 /* ID a_on pd ss */
4082 RPM_VS(PM8058_LVS0, 0, 1, 0),
4083 RPM_VS(PM8058_LVS1, 0, 1, 0),
4084
4085 /* ID a_on pd ss min_uV max_uV */
4086 RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
4087
4088 /* ID a_on pd ss min_uV max_uV init_ip */
4089 RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4090 RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4091 RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
4092 RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4093 RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4094 RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4095 RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
4096
4097 /* ID a_on pd ss min_uV max_uV init_ip freq */
4098 RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
4099 RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
4100 RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
4101
4102 /* ID a_on pd ss */
4103 RPM_VS(PM8901_LVS0, 1, 1, 0),
4104 RPM_VS(PM8901_LVS1, 0, 1, 0),
4105 RPM_VS(PM8901_LVS2, 0, 1, 0),
4106 RPM_VS(PM8901_LVS3, 0, 1, 0),
4107 RPM_VS(PM8901_MVS0, 0, 1, 0),
4108
4109 /* ID a_on pin_func pin_ctrl */
4110 RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4111 RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4112 RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4113 RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
4114 RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4115 RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4116};
4117
4118static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
4119 .init_data = rpm_regulator_early_init_data,
4120 .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
4121 .version = RPM_VREG_VERSION_8660,
4122 .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
4123 .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
4124};
4125
4126static struct rpm_regulator_platform_data rpm_regulator_pdata = {
4127 .init_data = rpm_regulator_init_data,
4128 .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
4129 .version = RPM_VREG_VERSION_8660,
4130};
4131
4132static struct platform_device rpm_regulator_early_device = {
4133 .name = "rpm-regulator",
4134 .id = 0,
4135 .dev = {
4136 .platform_data = &rpm_regulator_early_pdata,
4137 },
4138};
4139
4140static struct platform_device rpm_regulator_device = {
4141 .name = "rpm-regulator",
4142 .id = 1,
4143 .dev = {
4144 .platform_data = &rpm_regulator_pdata,
4145 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004146};
4147
4148static struct platform_device *early_regulators[] __initdata = {
4149 &msm_device_saw_s0,
4150 &msm_device_saw_s1,
David Collins6f032ba2011-08-31 14:08:15 -07004151 &rpm_regulator_early_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004152};
4153
4154static struct platform_device *early_devices[] __initdata = {
4155#ifdef CONFIG_MSM_BUS_SCALING
4156 &msm_bus_apps_fabric,
4157 &msm_bus_sys_fabric,
4158 &msm_bus_mm_fabric,
4159 &msm_bus_sys_fpb,
4160 &msm_bus_cpss_fpb,
4161#endif
4162 &msm_device_dmov_adm0,
4163 &msm_device_dmov_adm1,
4164};
4165
4166#if (defined(CONFIG_MARIMBA_CORE)) && \
4167 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4168
4169static int bluetooth_power(int);
4170static struct platform_device msm_bt_power_device = {
4171 .name = "bt_power",
4172 .id = -1,
4173 .dev = {
4174 .platform_data = &bluetooth_power,
4175 },
4176};
4177#endif
4178
4179static struct platform_device msm_tsens_device = {
4180 .name = "tsens-tm",
4181 .id = -1,
4182};
4183
4184static struct platform_device *rumi_sim_devices[] __initdata = {
4185 &smc91x_device,
4186 &msm_device_uart_dm12,
4187#ifdef CONFIG_I2C_QUP
4188 &msm_gsbi3_qup_i2c_device,
4189 &msm_gsbi4_qup_i2c_device,
4190 &msm_gsbi7_qup_i2c_device,
4191 &msm_gsbi8_qup_i2c_device,
4192 &msm_gsbi9_qup_i2c_device,
4193 &msm_gsbi12_qup_i2c_device,
4194#endif
4195#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004196 &msm_device_ssbi2,
4197 &msm_device_ssbi3,
4198#endif
4199#ifdef CONFIG_ANDROID_PMEM
Laura Abbottdf8b8a82011-11-02 23:13:45 -07004200#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004201 &android_pmem_device,
4202 &android_pmem_adsp_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004203 &android_pmem_smipool_device,
4204#endif
Laura Abbottdf8b8a82011-11-02 23:13:45 -07004205 &android_pmem_audio_device,
4206#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004207#ifdef CONFIG_MSM_ROTATOR
4208 &msm_rotator_device,
4209#endif
4210 &msm_fb_device,
4211 &msm_kgsl_3d0,
4212 &msm_kgsl_2d0,
4213 &msm_kgsl_2d1,
4214 &lcdc_samsung_panel_device,
4215#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4216 &hdmi_msm_device,
4217#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4218#ifdef CONFIG_MSM_CAMERA
4219#ifdef CONFIG_MT9E013
4220 &msm_camera_sensor_mt9e013,
4221#endif
4222#ifdef CONFIG_IMX074
4223 &msm_camera_sensor_imx074,
4224#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004225#ifdef CONFIG_VX6953
4226 &msm_camera_sensor_vx6953,
4227#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004228#ifdef CONFIG_WEBCAM_OV7692
4229 &msm_camera_sensor_webcam_ov7692,
4230#endif
4231#ifdef CONFIG_WEBCAM_OV9726
4232 &msm_camera_sensor_webcam_ov9726,
4233#endif
4234#ifdef CONFIG_QS_S5K4E1
4235 &msm_camera_sensor_qs_s5k4e1,
4236#endif
4237#endif
4238#ifdef CONFIG_MSM_GEMINI
4239 &msm_gemini_device,
4240#endif
4241#ifdef CONFIG_MSM_VPE
4242 &msm_vpe_device,
4243#endif
4244 &msm_device_vidc,
4245};
4246
4247#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4248enum {
4249 SX150X_CORE,
4250 SX150X_DOCKING,
4251 SX150X_SURF,
4252 SX150X_LEFT_FHA,
4253 SX150X_RIGHT_FHA,
4254 SX150X_SOUTH,
4255 SX150X_NORTH,
4256 SX150X_CORE_FLUID,
4257};
4258
4259static struct sx150x_platform_data sx150x_data[] __initdata = {
4260 [SX150X_CORE] = {
4261 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4262 .oscio_is_gpo = false,
4263 .io_pullup_ena = 0x0c08,
4264 .io_pulldn_ena = 0x4060,
4265 .io_open_drain_ena = 0x000c,
4266 .io_polarity = 0,
4267 .irq_summary = -1, /* see fixup_i2c_configs() */
4268 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4269 },
4270 [SX150X_DOCKING] = {
4271 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4272 .oscio_is_gpo = false,
4273 .io_pullup_ena = 0x5e06,
4274 .io_pulldn_ena = 0x81b8,
4275 .io_open_drain_ena = 0,
4276 .io_polarity = 0,
4277 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4278 UI_INT2_N),
4279 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4280 GPIO_DOCKING_EXPANDER_BASE -
4281 GPIO_EXPANDER_GPIO_BASE,
4282 },
4283 [SX150X_SURF] = {
4284 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4285 .oscio_is_gpo = false,
4286 .io_pullup_ena = 0,
4287 .io_pulldn_ena = 0,
4288 .io_open_drain_ena = 0,
4289 .io_polarity = 0,
4290 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4291 UI_INT1_N),
4292 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4293 GPIO_SURF_EXPANDER_BASE -
4294 GPIO_EXPANDER_GPIO_BASE,
4295 },
4296 [SX150X_LEFT_FHA] = {
4297 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4298 .oscio_is_gpo = false,
4299 .io_pullup_ena = 0,
4300 .io_pulldn_ena = 0x40,
4301 .io_open_drain_ena = 0,
4302 .io_polarity = 0,
4303 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4304 UI_INT3_N),
4305 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4306 GPIO_LEFT_KB_EXPANDER_BASE -
4307 GPIO_EXPANDER_GPIO_BASE,
4308 },
4309 [SX150X_RIGHT_FHA] = {
4310 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4311 .oscio_is_gpo = true,
4312 .io_pullup_ena = 0,
4313 .io_pulldn_ena = 0,
4314 .io_open_drain_ena = 0,
4315 .io_polarity = 0,
4316 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4317 UI_INT3_N),
4318 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4319 GPIO_RIGHT_KB_EXPANDER_BASE -
4320 GPIO_EXPANDER_GPIO_BASE,
4321 },
4322 [SX150X_SOUTH] = {
4323 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4324 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4325 GPIO_SOUTH_EXPANDER_BASE -
4326 GPIO_EXPANDER_GPIO_BASE,
4327 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4328 },
4329 [SX150X_NORTH] = {
4330 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4331 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4332 GPIO_NORTH_EXPANDER_BASE -
4333 GPIO_EXPANDER_GPIO_BASE,
4334 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4335 .oscio_is_gpo = true,
4336 .io_open_drain_ena = 0x30,
4337 },
4338 [SX150X_CORE_FLUID] = {
4339 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4340 .oscio_is_gpo = false,
4341 .io_pullup_ena = 0x0408,
4342 .io_pulldn_ena = 0x4060,
4343 .io_open_drain_ena = 0x0008,
4344 .io_polarity = 0,
4345 .irq_summary = -1, /* see fixup_i2c_configs() */
4346 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4347 },
4348};
4349
4350#ifdef CONFIG_SENSORS_MSM_ADC
4351/* Configuration of EPM expander is done when client
4352 * request an adc read
4353 */
4354static struct sx150x_platform_data sx150x_epmdata = {
4355 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4356 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4357 GPIO_EPM_EXPANDER_BASE -
4358 GPIO_EXPANDER_GPIO_BASE,
4359 .irq_summary = -1,
4360};
4361#endif
4362
4363/* sx150x_low_power_cfg
4364 *
4365 * This data and init function are used to put unused gpio-expander output
4366 * lines into their low-power states at boot. The init
4367 * function must be deferred until a later init stage because the i2c
4368 * gpio expander drivers do not probe until after they are registered
4369 * (see register_i2c_devices) and the work-queues for those registrations
4370 * are processed. Because these lines are unused, there is no risk of
4371 * competing with a device driver for the gpio.
4372 *
4373 * gpio lines whose low-power states are input are naturally in their low-
4374 * power configurations once probed, see the platform data structures above.
4375 */
4376struct sx150x_low_power_cfg {
4377 unsigned gpio;
4378 unsigned val;
4379};
4380
4381static struct sx150x_low_power_cfg
4382common_sx150x_lp_cfgs[] __initdata = {
4383 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4384 {GPIO_EXT_GPS_LNA_EN, 0},
4385 {GPIO_MSM_WAKES_BT, 0},
4386 {GPIO_USB_UICC_EN, 0},
4387 {GPIO_BATT_GAUGE_EN, 0},
4388};
4389
4390static struct sx150x_low_power_cfg
4391surf_ffa_sx150x_lp_cfgs[] __initdata = {
4392 {GPIO_MIPI_DSI_RST_N, 0},
4393 {GPIO_DONGLE_PWR_EN, 0},
4394 {GPIO_CAP_TS_SLEEP, 1},
4395 {GPIO_WEB_CAMIF_RESET_N, 0},
4396};
4397
4398static void __init
4399cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4400{
4401 unsigned n;
4402 int rc;
4403
4404 for (n = 0; n < nelems; ++n) {
4405 rc = gpio_request(cfgs[n].gpio, NULL);
4406 if (!rc) {
4407 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4408 gpio_free(cfgs[n].gpio);
4409 }
4410
4411 if (rc) {
4412 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4413 __func__, cfgs[n].gpio, rc);
4414 }
Steve Muckle9161d302010-02-11 11:50:40 -08004415 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004416}
4417
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004418static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004419{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004420 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4421 ARRAY_SIZE(common_sx150x_lp_cfgs));
4422 if (!machine_is_msm8x60_fluid())
4423 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4424 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4425 return 0;
4426}
4427module_init(cfg_sx150xs_low_power);
4428
4429#ifdef CONFIG_I2C
4430static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4431 {
4432 I2C_BOARD_INFO("sx1509q", 0x3e),
4433 .platform_data = &sx150x_data[SX150X_CORE]
4434 },
4435};
4436
4437static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4438 {
4439 I2C_BOARD_INFO("sx1509q", 0x3f),
4440 .platform_data = &sx150x_data[SX150X_DOCKING]
4441 },
4442};
4443
4444static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4445 {
4446 I2C_BOARD_INFO("sx1509q", 0x70),
4447 .platform_data = &sx150x_data[SX150X_SURF]
4448 }
4449};
4450
4451static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4452 {
4453 I2C_BOARD_INFO("sx1508q", 0x21),
4454 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4455 },
4456 {
4457 I2C_BOARD_INFO("sx1508q", 0x22),
4458 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4459 }
4460};
4461
4462static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4463 {
4464 I2C_BOARD_INFO("sx1508q", 0x23),
4465 .platform_data = &sx150x_data[SX150X_SOUTH]
4466 },
4467 {
4468 I2C_BOARD_INFO("sx1508q", 0x20),
4469 .platform_data = &sx150x_data[SX150X_NORTH]
4470 }
4471};
4472
4473static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4474 {
4475 I2C_BOARD_INFO("sx1509q", 0x3e),
4476 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4477 },
4478};
4479
4480#ifdef CONFIG_SENSORS_MSM_ADC
4481static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4482 {
4483 I2C_BOARD_INFO("sx1509q", 0x3e),
4484 .platform_data = &sx150x_epmdata
4485 },
4486};
4487#endif
4488#endif
4489#endif
4490
4491#ifdef CONFIG_SENSORS_MSM_ADC
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004492
4493static struct adc_access_fn xoadc_fn = {
4494 pm8058_xoadc_select_chan_and_start_conv,
4495 pm8058_xoadc_read_adc_code,
4496 pm8058_xoadc_get_properties,
4497 pm8058_xoadc_slot_request,
4498 pm8058_xoadc_restore_slot,
4499 pm8058_xoadc_calibrate,
4500};
4501
4502#if defined(CONFIG_I2C) && \
4503 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4504static struct regulator *vreg_adc_epm1;
4505
4506static struct i2c_client *epm_expander_i2c_register_board(void)
4507
4508{
4509 struct i2c_adapter *i2c_adap;
4510 struct i2c_client *client = NULL;
4511 i2c_adap = i2c_get_adapter(0x0);
4512
4513 if (i2c_adap == NULL)
4514 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4515
4516 if (i2c_adap != NULL)
4517 client = i2c_new_device(i2c_adap,
4518 &fluid_expanders_i2c_epm_info[0]);
4519 return client;
4520
4521}
4522
4523static unsigned int msm_adc_gpio_configure_expander_enable(void)
4524{
4525 int rc = 0;
4526 static struct i2c_client *epm_i2c_client;
4527
4528 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4529
4530 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4531
4532 if (IS_ERR(vreg_adc_epm1)) {
4533 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4534 return 0;
4535 }
4536
4537 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4538 if (rc)
4539 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4540 "regulator set voltage failed\n");
4541
4542 rc = regulator_enable(vreg_adc_epm1);
4543 if (rc) {
4544 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4545 "Error while enabling regulator for epm s3 %d\n", rc);
4546 return rc;
4547 }
4548
4549 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4550 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4551
4552 msleep(1000);
4553
4554 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4555 if (!rc) {
4556 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4557 "Configure 5v boost\n");
4558 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4559 } else {
4560 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4561 "Error for epm 5v boost en\n");
4562 goto exit_vreg_epm;
4563 }
4564
4565 msleep(500);
4566
4567 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4568 if (!rc) {
4569 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4570 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4571 "Configure epm 3.3v\n");
4572 } else {
4573 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4574 "Error for gpio 3.3ven\n");
4575 goto exit_vreg_epm;
4576 }
4577 msleep(500);
4578
4579 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4580 "Trying to request EPM LVLSFT_EN\n");
4581 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4582 if (!rc) {
4583 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4584 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4585 "Configure the lvlsft\n");
4586 } else {
4587 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4588 "Error for epm lvlsft_en\n");
4589 goto exit_vreg_epm;
4590 }
4591
4592 msleep(500);
4593
4594 if (!epm_i2c_client)
4595 epm_i2c_client = epm_expander_i2c_register_board();
4596
4597 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4598 if (!rc)
4599 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4600 if (rc) {
4601 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4602 ": GPIO PWR MON Enable issue\n");
4603 goto exit_vreg_epm;
4604 }
4605
4606 msleep(1000);
4607
4608 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4609 if (!rc) {
4610 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4611 if (rc) {
4612 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4613 ": ADC1_PWDN error direction out\n");
4614 goto exit_vreg_epm;
4615 }
4616 }
4617
4618 msleep(100);
4619
4620 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4621 if (!rc) {
4622 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4623 if (rc) {
4624 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4625 ": ADC2_PWD error direction out\n");
4626 goto exit_vreg_epm;
4627 }
4628 }
4629
4630 msleep(1000);
4631
4632 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4633 if (!rc) {
4634 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4635 if (rc) {
4636 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4637 "Gpio request problem %d\n", rc);
4638 goto exit_vreg_epm;
4639 }
4640 }
4641
4642 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4643 if (!rc) {
4644 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4645 if (rc) {
4646 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4647 ": EPM_SPI_ADC1_CS_N error\n");
4648 goto exit_vreg_epm;
4649 }
4650 }
4651
4652 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4653 if (!rc) {
4654 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4655 if (rc) {
4656 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4657 ": EPM_SPI_ADC2_Cs_N error\n");
4658 goto exit_vreg_epm;
4659 }
4660 }
4661
4662 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4663 "the power monitor reset for epm\n");
4664
4665 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4666 if (!rc) {
4667 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4668 if (rc) {
4669 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4670 ": Error in the power mon reset\n");
4671 goto exit_vreg_epm;
4672 }
4673 }
4674
4675 msleep(1000);
4676
4677 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4678
4679 msleep(500);
4680
4681 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4682
4683 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4684
4685 return rc;
4686
4687exit_vreg_epm:
4688 regulator_disable(vreg_adc_epm1);
4689
4690 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4691 " rc = %d.\n", rc);
4692 return rc;
4693};
4694
4695static unsigned int msm_adc_gpio_configure_expander_disable(void)
4696{
4697 int rc = 0;
4698
4699 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4700 gpio_free(GPIO_PWR_MON_RESET_N);
4701
4702 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4703 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4704
4705 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4706 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4707
4708 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4709 gpio_free(GPIO_PWR_MON_START);
4710
4711 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4712 gpio_free(GPIO_ADC1_PWDN_N);
4713
4714 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4715 gpio_free(GPIO_ADC2_PWDN_N);
4716
4717 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4718 gpio_free(GPIO_PWR_MON_ENABLE);
4719
4720 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4721 gpio_free(GPIO_EPM_LVLSFT_EN);
4722
4723 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4724 gpio_free(GPIO_EPM_5V_BOOST_EN);
4725
4726 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4727 gpio_free(GPIO_EPM_3_3V_EN);
4728
4729 rc = regulator_disable(vreg_adc_epm1);
4730 if (rc)
4731 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4732 "Error while enabling regulator for epm s3 %d\n", rc);
4733 regulator_put(vreg_adc_epm1);
4734
4735 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4736 return rc;
4737};
4738
4739unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4740{
4741 int rc = 0;
4742
4743 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4744 cs_enable);
4745
4746 if (cs_enable < 16) {
4747 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4748 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4749 } else {
4750 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4751 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4752 }
4753 return rc;
4754};
4755
4756unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4757{
4758 int rc = 0;
4759
4760 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4761
4762 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4763
4764 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4765
4766 return rc;
4767};
4768#endif
4769
4770static struct msm_adc_channels msm_adc_channels_data[] = {
4771 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4772 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4773 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4774 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4775 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4776 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4777 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4778 CHAN_PATH_TYPE4,
4779 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4780 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4781 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4782 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4783 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4784 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4785 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4786 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4787 CHAN_PATH_TYPE12,
4788 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4789 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4790 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4791 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4792 CHAN_PATH_TYPE_NONE,
4793 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4794 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4795 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4796 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4797 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4798 scale_xtern_chgr_cur},
4799 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4800 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4801 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4802 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4803 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4804 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4805 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4806 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4807 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4808 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4809 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4810 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4811};
4812
4813static char *msm_adc_fluid_device_names[] = {
4814 "ADS_ADC1",
4815 "ADS_ADC2",
4816};
4817
4818static struct msm_adc_platform_data msm_adc_pdata = {
4819 .channel = msm_adc_channels_data,
4820 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4821#if defined(CONFIG_I2C) && \
4822 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4823 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4824 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4825 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4826 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4827#endif
4828};
4829
4830static struct platform_device msm_adc_device = {
4831 .name = "msm_adc",
4832 .id = -1,
4833 .dev = {
4834 .platform_data = &msm_adc_pdata,
4835 },
4836};
4837
4838static void pmic8058_xoadc_mpp_config(void)
4839{
Anirudh Ghayalc2019332011-11-12 06:29:10 +05304840 int rc, i;
4841 struct pm8xxx_mpp_init_info xoadc_mpps[] = {
4842 PM8XXX_MPP_INIT(XOADC_MPP_3, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH5,
4843 AOUT_CTRL_DISABLE),
4844 PM8XXX_MPP_INIT(XOADC_MPP_5, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH9,
4845 AOUT_CTRL_DISABLE),
4846 PM8XXX_MPP_INIT(XOADC_MPP_7, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH6,
4847 AOUT_CTRL_DISABLE),
4848 PM8XXX_MPP_INIT(XOADC_MPP_8, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH8,
4849 AOUT_CTRL_DISABLE),
4850 PM8XXX_MPP_INIT(XOADC_MPP_10, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH7,
4851 AOUT_CTRL_DISABLE),
4852 };
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004853
4854 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4855 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4856 if (rc)
4857 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4858
Anirudh Ghayalc2019332011-11-12 06:29:10 +05304859 for (i = 0; i < ARRAY_SIZE(xoadc_mpps); i++) {
4860 rc = pm8xxx_mpp_config(xoadc_mpps[i].mpp,
4861 &xoadc_mpps[i].config);
4862 if (rc) {
4863 pr_err("%s: Config MPP %d of PM8058 failed\n",
4864 __func__, xoadc_mpps[i].mpp);
4865 }
4866 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004867}
4868
4869static struct regulator *vreg_ldo18_adc;
4870
4871static int pmic8058_xoadc_vreg_config(int on)
4872{
4873 int rc;
4874
4875 if (on) {
4876 rc = regulator_enable(vreg_ldo18_adc);
4877 if (rc)
4878 pr_err("%s: Enable of regulator ldo18_adc "
4879 "failed\n", __func__);
4880 } else {
4881 rc = regulator_disable(vreg_ldo18_adc);
4882 if (rc)
4883 pr_err("%s: Disable of regulator ldo18_adc "
4884 "failed\n", __func__);
4885 }
4886
4887 return rc;
4888}
4889
4890static int pmic8058_xoadc_vreg_setup(void)
4891{
4892 int rc;
4893
4894 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4895 if (IS_ERR(vreg_ldo18_adc)) {
4896 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4897 __func__, PTR_ERR(vreg_ldo18_adc));
4898 rc = PTR_ERR(vreg_ldo18_adc);
4899 goto fail;
4900 }
4901
4902 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4903 if (rc) {
4904 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4905 goto fail;
4906 }
4907
4908 return rc;
4909fail:
4910 regulator_put(vreg_ldo18_adc);
4911 return rc;
4912}
4913
4914static void pmic8058_xoadc_vreg_shutdown(void)
4915{
4916 regulator_put(vreg_ldo18_adc);
4917}
4918
4919/* usec. For this ADC,
4920 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4921 * Each channel has different configuration, thus at the time of starting
4922 * the conversion, xoadc will return actual conversion time
4923 * */
4924static struct adc_properties pm8058_xoadc_data = {
4925 .adc_reference = 2200, /* milli-voltage for this adc */
4926 .bitresolution = 15,
4927 .bipolar = 0,
4928 .conversiontime = 54,
4929};
4930
Anirudh Ghayalc2019332011-11-12 06:29:10 +05304931static struct xoadc_platform_data pm8058_xoadc_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004932 .xoadc_prop = &pm8058_xoadc_data,
4933 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4934 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4935 .xoadc_num = XOADC_PMIC_0,
4936 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4937 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4938};
4939#endif
4940
4941#ifdef CONFIG_MSM_SDIO_AL
4942
4943static unsigned mdm2ap_status = 140;
4944
4945static int configure_mdm2ap_status(int on)
4946{
4947 int ret = 0;
4948 if (on)
4949 ret = msm_gpiomux_get(mdm2ap_status);
4950 else
4951 ret = msm_gpiomux_put(mdm2ap_status);
4952
4953 if (ret)
4954 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4955 on);
4956
4957 return ret;
4958}
4959
4960
4961static int get_mdm2ap_status(void)
4962{
4963 return gpio_get_value(mdm2ap_status);
4964}
4965
4966static struct sdio_al_platform_data sdio_al_pdata = {
4967 .config_mdm2ap_status = configure_mdm2ap_status,
4968 .get_mdm2ap_status = get_mdm2ap_status,
4969 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004970 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004971 .peer_sdioc_version_major = 0x0004,
4972 .peer_sdioc_boot_version_minor = 0x0001,
4973 .peer_sdioc_boot_version_major = 0x0003
4974};
4975
4976struct platform_device msm_device_sdio_al = {
4977 .name = "msm_sdio_al",
4978 .id = -1,
4979 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004980 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004981 .platform_data = &sdio_al_pdata,
4982 },
4983};
4984
4985#endif /* CONFIG_MSM_SDIO_AL */
4986
4987static struct platform_device *charm_devices[] __initdata = {
4988 &msm_charm_modem,
4989#ifdef CONFIG_MSM_SDIO_AL
4990 &msm_device_sdio_al,
4991#endif
4992};
4993
Lei Zhou338cab82011-08-19 13:38:17 -04004994#ifdef CONFIG_SND_SOC_MSM8660_APQ
4995static struct platform_device *dragon_alsa_devices[] __initdata = {
4996 &msm_pcm,
4997 &msm_pcm_routing,
4998 &msm_cpudai0,
4999 &msm_cpudai1,
5000 &msm_cpudai_hdmi_rx,
5001 &msm_cpudai_bt_rx,
5002 &msm_cpudai_bt_tx,
5003 &msm_cpudai_fm_rx,
5004 &msm_cpudai_fm_tx,
5005 &msm_cpu_fe,
5006 &msm_stub_codec,
5007 &msm_lpa_pcm,
5008};
5009#endif
5010
5011static struct platform_device *asoc_devices[] __initdata = {
5012 &asoc_msm_pcm,
5013 &asoc_msm_dai0,
5014 &asoc_msm_dai1,
5015};
5016
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005017static struct platform_device *surf_devices[] __initdata = {
5018 &msm_device_smd,
5019 &msm_device_uart_dm12,
5020#ifdef CONFIG_I2C_QUP
5021 &msm_gsbi3_qup_i2c_device,
5022 &msm_gsbi4_qup_i2c_device,
5023 &msm_gsbi7_qup_i2c_device,
5024 &msm_gsbi8_qup_i2c_device,
5025 &msm_gsbi9_qup_i2c_device,
5026 &msm_gsbi12_qup_i2c_device,
5027#endif
5028#ifdef CONFIG_SERIAL_MSM_HS
5029 &msm_device_uart_dm1,
5030#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05305031#ifdef CONFIG_MSM_SSBI
5032 &msm_device_ssbi_pmic1,
5033#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005034#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005035 &msm_device_ssbi2,
5036 &msm_device_ssbi3,
5037#endif
5038#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
5039 &isp1763_device,
5040#endif
5041
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005042#if defined (CONFIG_MSM_8x60_VOIP)
5043 &asoc_msm_mvs,
5044 &asoc_mvs_dai0,
5045 &asoc_mvs_dai1,
5046#endif
Lei Zhou338cab82011-08-19 13:38:17 -04005047
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005048#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
5049 &msm_device_otg,
5050#endif
5051#ifdef CONFIG_USB_GADGET_MSM_72K
5052 &msm_device_gadget_peripheral,
5053#endif
5054#ifdef CONFIG_USB_G_ANDROID
5055 &android_usb_device,
5056#endif
5057#ifdef CONFIG_BATTERY_MSM
5058 &msm_batt_device,
5059#endif
5060#ifdef CONFIG_ANDROID_PMEM
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005061#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005062 &android_pmem_device,
5063 &android_pmem_adsp_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005064 &android_pmem_smipool_device,
5065#endif
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005066 &android_pmem_audio_device,
5067#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005068#ifdef CONFIG_MSM_ROTATOR
5069 &msm_rotator_device,
5070#endif
5071 &msm_fb_device,
5072 &msm_kgsl_3d0,
5073 &msm_kgsl_2d0,
5074 &msm_kgsl_2d1,
5075 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005076#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5077 &lcdc_nt35582_panel_device,
5078#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005079#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
5080 &lcdc_samsung_oled_panel_device,
5081#endif
5082#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
5083 &lcdc_auo_wvga_panel_device,
5084#endif
5085#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
5086 &hdmi_msm_device,
5087#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
5088#ifdef CONFIG_FB_MSM_MIPI_DSI
5089 &mipi_dsi_toshiba_panel_device,
5090 &mipi_dsi_novatek_panel_device,
5091#endif
5092#ifdef CONFIG_MSM_CAMERA
5093#ifdef CONFIG_MT9E013
5094 &msm_camera_sensor_mt9e013,
5095#endif
5096#ifdef CONFIG_IMX074
5097 &msm_camera_sensor_imx074,
5098#endif
5099#ifdef CONFIG_WEBCAM_OV7692
5100 &msm_camera_sensor_webcam_ov7692,
5101#endif
5102#ifdef CONFIG_WEBCAM_OV9726
5103 &msm_camera_sensor_webcam_ov9726,
5104#endif
5105#ifdef CONFIG_QS_S5K4E1
5106 &msm_camera_sensor_qs_s5k4e1,
5107#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04005108#ifdef CONFIG_VX6953
5109 &msm_camera_sensor_vx6953,
5110#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005111#endif
5112#ifdef CONFIG_MSM_GEMINI
5113 &msm_gemini_device,
5114#endif
5115#ifdef CONFIG_MSM_VPE
5116 &msm_vpe_device,
5117#endif
5118
5119#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5120 &msm_rpm_log_device,
5121#endif
5122#if defined(CONFIG_MSM_RPM_STATS_LOG)
5123 &msm_rpm_stat_device,
5124#endif
5125 &msm_device_vidc,
5126#if (defined(CONFIG_MARIMBA_CORE)) && \
5127 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5128 &msm_bt_power_device,
5129#endif
5130#ifdef CONFIG_SENSORS_MSM_ADC
5131 &msm_adc_device,
5132#endif
David Collins6f032ba2011-08-31 14:08:15 -07005133 &rpm_regulator_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005134
5135#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5136 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5137 &qcrypto_device,
5138#endif
5139
5140#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5141 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5142 &qcedev_device,
5143#endif
5144
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005145
5146#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5147#ifdef CONFIG_MSM_USE_TSIF1
5148 &msm_device_tsif[1],
5149#else
5150 &msm_device_tsif[0],
5151#endif /* CONFIG_MSM_USE_TSIF1 */
5152#endif /* CONFIG_TSIF */
5153
5154#ifdef CONFIG_HW_RANDOM_MSM
5155 &msm_device_rng,
5156#endif
5157
5158 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005159 &msm_rpm_device,
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005160#ifdef CONFIG_ION_MSM
5161 &ion_dev,
5162#endif
Jeff Ohlstein7e668552011-10-06 16:17:25 -07005163 &msm8660_device_watchdog,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005164};
5165
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005166#ifdef CONFIG_ION_MSM
5167struct ion_platform_data ion_pdata = {
5168 .nr = MSM_ION_HEAP_NUM,
5169 .heaps = {
5170 {
5171 .id = ION_HEAP_SYSTEM_ID,
5172 .type = ION_HEAP_TYPE_SYSTEM,
5173 .name = ION_VMALLOC_HEAP_NAME,
5174 },
5175 {
5176 .id = ION_HEAP_SYSTEM_CONTIG_ID,
5177 .type = ION_HEAP_TYPE_SYSTEM_CONTIG,
5178 .name = ION_KMALLOC_HEAP_NAME,
5179 },
5180#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
5181 {
5182 .id = ION_HEAP_EBI_ID,
5183 .type = ION_HEAP_TYPE_CARVEOUT,
5184 .name = ION_EBI1_HEAP_NAME,
5185 .size = MSM_ION_EBI_SIZE,
5186 .memory_type = ION_EBI_TYPE,
5187 },
5188 {
5189 .id = ION_HEAP_ADSP_ID,
5190 .type = ION_HEAP_TYPE_CARVEOUT,
5191 .name = ION_ADSP_HEAP_NAME,
5192 .size = MSM_ION_ADSP_SIZE,
5193 .memory_type = ION_EBI_TYPE,
5194 },
5195 {
5196 .id = ION_HEAP_SMI_ID,
5197 .type = ION_HEAP_TYPE_CARVEOUT,
5198 .name = ION_SMI_HEAP_NAME,
5199 .size = MSM_ION_SMI_SIZE,
5200 .memory_type = ION_SMI_TYPE,
5201 },
5202#endif
5203 }
5204};
5205
5206struct platform_device ion_dev = {
5207 .name = "ion-msm",
5208 .id = 1,
5209 .dev = { .platform_data = &ion_pdata },
5210};
5211#endif
5212
5213
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005214static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5215 /* Kernel SMI memory pool for video core, used for firmware */
5216 /* and encoder, decoder scratch buffers */
5217 /* Kernel SMI memory pool should always precede the user space */
5218 /* SMI memory pool, as the video core will use offset address */
5219 /* from the Firmware base */
5220 [MEMTYPE_SMI_KERNEL] = {
5221 .start = KERNEL_SMI_BASE,
5222 .limit = KERNEL_SMI_SIZE,
5223 .size = KERNEL_SMI_SIZE,
5224 .flags = MEMTYPE_FLAGS_FIXED,
5225 },
5226 /* User space SMI memory pool for video core */
5227 /* used for encoder, decoder input & output buffers */
5228 [MEMTYPE_SMI] = {
5229 .start = USER_SMI_BASE,
5230 .limit = USER_SMI_SIZE,
5231 .flags = MEMTYPE_FLAGS_FIXED,
5232 },
5233 [MEMTYPE_EBI0] = {
5234 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5235 },
5236 [MEMTYPE_EBI1] = {
5237 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5238 },
5239};
5240
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005241static void reserve_ion_memory(void)
5242{
5243#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
5244 msm8x60_reserve_table[MEMTYPE_EBI1].size += MSM_ION_EBI_SIZE;
5245 msm8x60_reserve_table[MEMTYPE_EBI1].size += MSM_ION_ADSP_SIZE;
5246 msm8x60_reserve_table[MEMTYPE_SMI].size += MSM_ION_SMI_SIZE;
5247#endif
5248}
5249
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005250static void __init size_pmem_devices(void)
5251{
5252#ifdef CONFIG_ANDROID_PMEM
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005253#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005254 android_pmem_adsp_pdata.size = pmem_adsp_size;
5255 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005256 android_pmem_pdata.size = pmem_sf_size;
5257#endif
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005258 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5259#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005260}
5261
5262static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5263{
5264 msm8x60_reserve_table[p->memory_type].size += p->size;
5265}
5266
5267static void __init reserve_pmem_memory(void)
5268{
5269#ifdef CONFIG_ANDROID_PMEM
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005270#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005271 reserve_memory_for(&android_pmem_adsp_pdata);
5272 reserve_memory_for(&android_pmem_smipool_pdata);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005273 reserve_memory_for(&android_pmem_pdata);
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005274#endif
5275 reserve_memory_for(&android_pmem_audio_pdata);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005276 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5277#endif
5278}
5279
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005280
5281
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005282static void __init msm8x60_calculate_reserve_sizes(void)
5283{
5284 size_pmem_devices();
5285 reserve_pmem_memory();
Laura Abbott63cfd7e2011-10-10 18:21:01 -07005286 reserve_ion_memory();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005287}
5288
5289static int msm8x60_paddr_to_memtype(unsigned int paddr)
5290{
5291 if (paddr >= 0x40000000 && paddr < 0x60000000)
5292 return MEMTYPE_EBI1;
5293 if (paddr >= 0x38000000 && paddr < 0x40000000)
5294 return MEMTYPE_SMI;
5295 return MEMTYPE_NONE;
5296}
5297
5298static struct reserve_info msm8x60_reserve_info __initdata = {
5299 .memtype_reserve_table = msm8x60_reserve_table,
5300 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5301 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5302};
5303
5304static void __init msm8x60_reserve(void)
5305{
5306 reserve_info = &msm8x60_reserve_info;
5307 msm_reserve();
5308}
5309
5310#define EXT_CHG_VALID_MPP 10
5311#define EXT_CHG_VALID_MPP_2 11
5312
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305313static struct pm8xxx_mpp_init_info isl_mpp[] = {
5314 PM8XXX_MPP_INIT(EXT_CHG_VALID_MPP, D_INPUT,
5315 PM8058_MPP_DIG_LEVEL_S3, DIN_TO_INT),
5316 PM8XXX_MPP_INIT(EXT_CHG_VALID_MPP_2, D_BI_DIR,
5317 PM8058_MPP_DIG_LEVEL_S3, BI_PULLUP_10KOHM),
5318};
5319
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005320#ifdef CONFIG_ISL9519_CHARGER
5321static int isl_detection_setup(void)
5322{
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305323 int ret = 0, i;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005324
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305325 for (i = 0; i < ARRAY_SIZE(isl_mpp); i++) {
5326 ret = pm8xxx_mpp_config(isl_mpp[i].mpp,
5327 &isl_mpp[i].config);
5328 if (ret) {
5329 pr_err("%s: Config MPP %d of PM8058 failed\n",
5330 __func__, isl_mpp[i].mpp);
5331 return ret;
5332 }
5333 }
5334
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005335 return ret;
5336}
5337
5338static struct isl_platform_data isl_data __initdata = {
5339 .chgcurrent = 700,
5340 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5341 .chg_detection_config = isl_detection_setup,
5342 .max_system_voltage = 4200,
5343 .min_system_voltage = 3200,
5344 .term_current = 120,
5345 .input_current = 2048,
5346};
5347
5348static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5349 {
5350 I2C_BOARD_INFO("isl9519q", 0x9),
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305351 .irq = PM8058_IRQ_BASE + PM8058_CBLPWR_IRQ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005352 .platform_data = &isl_data,
5353 },
5354};
5355#endif
5356
5357#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5358static int smb137b_detection_setup(void)
5359{
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305360 int ret = 0, i;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005361
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305362 for (i = 0; i < ARRAY_SIZE(isl_mpp); i++) {
5363 ret = pm8xxx_mpp_config(isl_mpp[i].mpp,
5364 &isl_mpp[i].config);
5365 if (ret) {
5366 pr_err("%s: Config MPP %d of PM8058 failed\n",
5367 __func__, isl_mpp[i].mpp);
5368 return ret;
5369 }
5370 }
5371
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005372 return ret;
5373}
5374
5375static struct smb137b_platform_data smb137b_data __initdata = {
5376 .chg_detection_config = smb137b_detection_setup,
5377 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5378 .batt_mah_rating = 950,
5379};
5380
5381static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5382 {
5383 I2C_BOARD_INFO("smb137b", 0x08),
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305384 .irq = PM8058_IRQ_BASE + PM8058_CBLPWR_IRQ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005385 .platform_data = &smb137b_data,
5386 },
5387};
5388#endif
5389
5390#ifdef CONFIG_PMIC8058
5391#define PMIC_GPIO_SDC3_DET 22
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305392#define PMIC_GPIO_TOUCH_DISC_INTR 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005393
5394static int pm8058_gpios_init(void)
5395{
5396 int i;
5397 int rc;
5398 struct pm8058_gpio_cfg {
5399 int gpio;
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305400 struct pm_gpio cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005401 };
5402
5403 struct pm8058_gpio_cfg gpio_cfgs[] = {
5404 { /* FFA ethernet */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305405 PM8058_GPIO_PM_TO_SYS(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005406 {
5407 .direction = PM_GPIO_DIR_IN,
5408 .pull = PM_GPIO_PULL_DN,
5409 .vin_sel = 2,
5410 .function = PM_GPIO_FUNC_NORMAL,
5411 .inv_int_pol = 0,
5412 },
5413 },
5414#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5415 {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305416 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005417 {
5418 .direction = PM_GPIO_DIR_IN,
5419 .pull = PM_GPIO_PULL_UP_30,
5420 .vin_sel = 2,
5421 .function = PM_GPIO_FUNC_NORMAL,
5422 .inv_int_pol = 0,
5423 },
5424 },
5425#endif
5426 { /* core&surf gpio expander */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305427 PM8058_GPIO_PM_TO_SYS(UI_INT1_N),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005428 {
5429 .direction = PM_GPIO_DIR_IN,
5430 .pull = PM_GPIO_PULL_NO,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305431 .vin_sel = PM8058_GPIO_VIN_S3,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005432 .function = PM_GPIO_FUNC_NORMAL,
5433 .inv_int_pol = 0,
5434 },
5435 },
5436 { /* docking gpio expander */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305437 PM8058_GPIO_PM_TO_SYS(UI_INT2_N),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005438 {
5439 .direction = PM_GPIO_DIR_IN,
5440 .pull = PM_GPIO_PULL_NO,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305441 .vin_sel = PM8058_GPIO_VIN_S3,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005442 .function = PM_GPIO_FUNC_NORMAL,
5443 .inv_int_pol = 0,
5444 },
5445 },
5446 { /* FHA/keypad gpio expanders */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305447 PM8058_GPIO_PM_TO_SYS(UI_INT3_N),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005448 {
5449 .direction = PM_GPIO_DIR_IN,
5450 .pull = PM_GPIO_PULL_NO,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305451 .vin_sel = PM8058_GPIO_VIN_S3,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005452 .function = PM_GPIO_FUNC_NORMAL,
5453 .inv_int_pol = 0,
5454 },
5455 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005456 { /* Timpani Reset */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305457 PM8058_GPIO_PM_TO_SYS(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005458 {
5459 .direction = PM_GPIO_DIR_OUT,
5460 .output_value = 1,
5461 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5462 .pull = PM_GPIO_PULL_DN,
5463 .out_strength = PM_GPIO_STRENGTH_HIGH,
5464 .function = PM_GPIO_FUNC_NORMAL,
5465 .vin_sel = 2,
5466 .inv_int_pol = 0,
5467 }
5468 },
5469 { /* PMIC ID interrupt */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305470 PM8058_GPIO_PM_TO_SYS(36),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005471 {
5472 .direction = PM_GPIO_DIR_IN,
Anji jonnalaae745e92011-11-14 18:34:31 +05305473 .pull = PM_GPIO_PULL_NO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005474 .function = PM_GPIO_FUNC_NORMAL,
5475 .vin_sel = 2,
5476 .inv_int_pol = 0,
5477 }
5478 },
5479 };
5480
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305481#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
5482 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305483 struct pm_gpio touchdisc_intr_gpio_cfg = {
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305484 .direction = PM_GPIO_DIR_IN,
5485 .pull = PM_GPIO_PULL_UP_1P5,
5486 .vin_sel = 2,
5487 .function = PM_GPIO_FUNC_NORMAL,
5488 };
5489#endif
5490
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005491#if defined(CONFIG_HAPTIC_ISA1200) || \
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305492 defined(CONFIG_HAPTIC_ISA1200_MODULE)
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305493 struct pm_gpio en_hap_gpio_cfg = {
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305494 .direction = PM_GPIO_DIR_OUT,
5495 .pull = PM_GPIO_PULL_NO,
5496 .out_strength = PM_GPIO_STRENGTH_HIGH,
5497 .function = PM_GPIO_FUNC_NORMAL,
5498 .inv_int_pol = 0,
5499 .vin_sel = 2,
5500 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5501 .output_value = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005502 };
5503#endif
5504
5505#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5506 struct pm8058_gpio_cfg line_in_gpio_cfg = {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305507 PM8058_GPIO_PM_TO_SYS(18),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005508 {
5509 .direction = PM_GPIO_DIR_IN,
5510 .pull = PM_GPIO_PULL_UP_1P5,
5511 .vin_sel = 2,
5512 .function = PM_GPIO_FUNC_NORMAL,
5513 .inv_int_pol = 0,
5514 }
5515 };
5516#endif
5517
5518#if defined(CONFIG_QS_S5K4E1)
5519 {
5520 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305521 PM8058_GPIO_PM_TO_SYS(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005522 {
5523 .direction = PM_GPIO_DIR_OUT,
5524 .output_value = 0,
5525 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5526 .pull = PM_GPIO_PULL_DN,
5527 .out_strength = PM_GPIO_STRENGTH_HIGH,
5528 .function = PM_GPIO_FUNC_NORMAL,
5529 .vin_sel = 2,
5530 .inv_int_pol = 0,
5531 }
5532 };
5533#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005534#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5535 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305536 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1),
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005537 {
5538 .direction = PM_GPIO_DIR_OUT,
5539 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5540 .output_value = 1,
5541 .pull = PM_GPIO_PULL_UP_30,
5542 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305543 .vin_sel = PM8058_GPIO_VIN_L5,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005544 .out_strength = PM_GPIO_STRENGTH_HIGH,
5545 .function = PM_GPIO_FUNC_NORMAL,
5546 .inv_int_pol = 0,
5547 }
5548 };
5549#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005550#if defined(CONFIG_HAPTIC_ISA1200) || \
5551 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5552 if (machine_is_msm8x60_fluid()) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305553 rc = pm8xxx_gpio_config(
5554 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
5555 &en_hap_gpio_cfg);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005556 if (rc < 0) {
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305557 pr_err("%s: pmic haptics gpio config failed\n",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005558 __func__);
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305559 }
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305560 rc = pm8xxx_gpio_config(
5561 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_LDO_ENABLE),
5562 &en_hap_gpio_cfg);
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305563 if (rc < 0) {
5564 pr_err("%s: pmic haptics ldo gpio config failed\n",
5565 __func__);
5566 }
5567
5568 }
5569#endif
5570
5571#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
5572 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
5573 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
5574 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305575 rc = pm8xxx_gpio_config(
5576 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_TOUCH_DISC_INTR),
5577 &touchdisc_intr_gpio_cfg);
Mohan Pallaka4a1160d2011-09-09 15:17:45 +05305578 if (rc < 0) {
5579 pr_err("%s: Touchdisc interrupt gpio config failed\n",
5580 __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005581 }
5582 }
5583#endif
5584
5585#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5586 /* Line_in only for 8660 ffa & surf */
5587 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005588 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005589 machine_is_msm8x60_fusn_ffa()) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305590 rc = pm8xxx_gpio_config(line_in_gpio_cfg.gpio,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005591 &line_in_gpio_cfg.cfg);
5592 if (rc < 0) {
5593 pr_err("%s pmic line_in gpio config failed\n",
5594 __func__);
5595 return rc;
5596 }
5597 }
5598#endif
5599
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005600#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5601 if (machine_is_msm8x60_dragon()) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305602 rc = pm8xxx_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005603 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5604 if (rc < 0) {
5605 pr_err("%s pmic gpio config failed\n", __func__);
5606 return rc;
5607 }
5608 }
5609#endif
5610
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005611#if defined(CONFIG_QS_S5K4E1)
5612 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5613 if (machine_is_msm8x60_fluid()) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305614 rc = pm8xxx_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005615 &qs_hc37_cam_pd_gpio_cfg.cfg);
5616 if (rc < 0) {
5617 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5618 __func__);
5619 return rc;
5620 }
5621 }
5622 }
5623#endif
5624
5625 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305626 rc = pm8xxx_gpio_config(gpio_cfgs[i].gpio,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005627 &gpio_cfgs[i].cfg);
5628 if (rc < 0) {
5629 pr_err("%s pmic gpio config failed\n",
5630 __func__);
5631 return rc;
5632 }
5633 }
5634
5635 return 0;
5636}
5637
5638static const unsigned int ffa_keymap[] = {
5639 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5640 KEY(0, 1, KEY_UP), /* NAV - UP */
5641 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5642 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5643
5644 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5645 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5646 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5647 KEY(1, 3, KEY_VOLUMEDOWN),
5648
5649 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5650
5651 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5652 KEY(4, 1, KEY_UP), /* USER_UP */
5653 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5654 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5655 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5656
5657 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5658 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5659 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5660 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5661 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5662};
5663
Zhang Chang Ken683be172011-08-10 17:45:34 -04005664static const unsigned int dragon_keymap[] = {
5665 KEY(0, 0, KEY_MENU),
5666 KEY(0, 2, KEY_1),
5667 KEY(0, 3, KEY_4),
5668 KEY(0, 4, KEY_7),
5669
5670 KEY(1, 0, KEY_UP),
5671 KEY(1, 1, KEY_LEFT),
5672 KEY(1, 2, KEY_DOWN),
5673 KEY(1, 3, KEY_5),
5674 KEY(1, 4, KEY_8),
5675
5676 KEY(2, 0, KEY_HOME),
5677 KEY(2, 1, KEY_REPLY),
5678 KEY(2, 2, KEY_2),
5679 KEY(2, 3, KEY_6),
5680 KEY(2, 4, KEY_0),
5681
5682 KEY(3, 0, KEY_VOLUMEUP),
5683 KEY(3, 1, KEY_RIGHT),
5684 KEY(3, 2, KEY_3),
5685 KEY(3, 3, KEY_9),
5686 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5687
5688 KEY(4, 0, KEY_VOLUMEDOWN),
5689 KEY(4, 1, KEY_BACK),
5690 KEY(4, 2, KEY_CAMERA),
5691 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5692};
5693
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005694static struct matrix_keymap_data ffa_keymap_data = {
5695 .keymap_size = ARRAY_SIZE(ffa_keymap),
5696 .keymap = ffa_keymap,
5697};
5698
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305699static struct pm8xxx_keypad_platform_data ffa_keypad_data = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005700 .input_name = "ffa-keypad",
5701 .input_phys_device = "ffa-keypad/input0",
5702 .num_rows = 6,
5703 .num_cols = 5,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305704 .rows_gpio_start = PM8058_GPIO_PM_TO_SYS(8),
5705 .cols_gpio_start = PM8058_GPIO_PM_TO_SYS(0),
5706 .debounce_ms = 15,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005707 .scan_delay_ms = 32,
5708 .row_hold_ns = 91500,
5709 .wakeup = 1,
5710 .keymap_data = &ffa_keymap_data,
5711};
5712
Zhang Chang Ken683be172011-08-10 17:45:34 -04005713static struct matrix_keymap_data dragon_keymap_data = {
5714 .keymap_size = ARRAY_SIZE(dragon_keymap),
5715 .keymap = dragon_keymap,
5716};
5717
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305718static struct pm8xxx_keypad_platform_data dragon_keypad_data = {
Zhang Chang Ken683be172011-08-10 17:45:34 -04005719 .input_name = "dragon-keypad",
5720 .input_phys_device = "dragon-keypad/input0",
5721 .num_rows = 6,
5722 .num_cols = 5,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305723 .rows_gpio_start = PM8058_GPIO_PM_TO_SYS(8),
5724 .cols_gpio_start = PM8058_GPIO_PM_TO_SYS(0),
5725 .debounce_ms = 15,
Zhang Chang Ken683be172011-08-10 17:45:34 -04005726 .scan_delay_ms = 32,
5727 .row_hold_ns = 91500,
5728 .wakeup = 1,
5729 .keymap_data = &dragon_keymap_data,
5730};
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305731
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005732static const unsigned int fluid_keymap[] = {
5733 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5734 KEY(0, 1, KEY_UP), /* NAV - UP */
5735 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5736 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5737
5738 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5739 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5740 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5741 KEY(1, 3, KEY_VOLUMEUP),
5742
5743 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5744
5745 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5746 KEY(4, 1, KEY_UP), /* USER_UP */
5747 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5748 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5749 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5750
Jilai Wang9a895102011-07-12 14:00:35 -04005751 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005752 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5753 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5754 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5755 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5756};
5757
5758static struct matrix_keymap_data fluid_keymap_data = {
5759 .keymap_size = ARRAY_SIZE(fluid_keymap),
5760 .keymap = fluid_keymap,
5761};
5762
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305763static struct pm8xxx_keypad_platform_data fluid_keypad_data = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005764 .input_name = "fluid-keypad",
5765 .input_phys_device = "fluid-keypad/input0",
5766 .num_rows = 6,
5767 .num_cols = 5,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305768 .rows_gpio_start = PM8058_GPIO_PM_TO_SYS(8),
5769 .cols_gpio_start = PM8058_GPIO_PM_TO_SYS(0),
5770 .debounce_ms = 15,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005771 .scan_delay_ms = 32,
5772 .row_hold_ns = 91500,
5773 .wakeup = 1,
5774 .keymap_data = &fluid_keymap_data,
5775};
5776
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305777static struct pm8xxx_vibrator_platform_data pm8058_vib_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005778 .initial_vibrate_ms = 500,
5779 .level_mV = 3000,
5780 .max_timeout_ms = 15000,
5781};
5782
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305783static struct pm8xxx_rtc_platform_data pm8058_rtc_pdata = {
5784 .rtc_write_enable = false,
5785 .rtc_alarm_powerup = false,
5786};
5787
5788static struct pm8xxx_pwrkey_platform_data pm8058_pwrkey_pdata = {
5789 .pull_up = 1,
5790 .kpd_trigger_delay_us = 970,
5791 .wakeup = 1,
5792};
5793
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005794#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5795
5796static struct othc_accessory_info othc_accessories[] = {
5797 {
5798 .accessory = OTHC_SVIDEO_OUT,
5799 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5800 | OTHC_ADC_DETECT,
5801 .key_code = SW_VIDEOOUT_INSERT,
5802 .enabled = false,
5803 .adc_thres = {
5804 .min_threshold = 20,
5805 .max_threshold = 40,
5806 },
5807 },
5808 {
5809 .accessory = OTHC_ANC_HEADPHONE,
5810 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5811 OTHC_SWITCH_DETECT,
5812 .gpio = PM8058_LINE_IN_DET_GPIO,
5813 .active_low = 1,
5814 .key_code = SW_HEADPHONE_INSERT,
5815 .enabled = true,
5816 },
5817 {
5818 .accessory = OTHC_ANC_HEADSET,
5819 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5820 .gpio = PM8058_LINE_IN_DET_GPIO,
5821 .active_low = 1,
5822 .key_code = SW_HEADPHONE_INSERT,
5823 .enabled = true,
5824 },
5825 {
5826 .accessory = OTHC_HEADPHONE,
5827 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5828 .key_code = SW_HEADPHONE_INSERT,
5829 .enabled = true,
5830 },
5831 {
5832 .accessory = OTHC_MICROPHONE,
5833 .detect_flags = OTHC_GPIO_DETECT,
5834 .gpio = PM8058_LINE_IN_DET_GPIO,
5835 .active_low = 1,
5836 .key_code = SW_MICROPHONE_INSERT,
5837 .enabled = true,
5838 },
5839 {
5840 .accessory = OTHC_HEADSET,
5841 .detect_flags = OTHC_MICBIAS_DETECT,
5842 .key_code = SW_HEADPHONE_INSERT,
5843 .enabled = true,
5844 },
5845};
5846
5847static struct othc_switch_info switch_info[] = {
5848 {
5849 .min_adc_threshold = 0,
5850 .max_adc_threshold = 100,
5851 .key_code = KEY_PLAYPAUSE,
5852 },
5853 {
5854 .min_adc_threshold = 100,
5855 .max_adc_threshold = 200,
5856 .key_code = KEY_REWIND,
5857 },
5858 {
5859 .min_adc_threshold = 200,
5860 .max_adc_threshold = 500,
5861 .key_code = KEY_FASTFORWARD,
5862 },
5863};
5864
5865static struct othc_n_switch_config switch_config = {
5866 .voltage_settling_time_ms = 0,
5867 .num_adc_samples = 3,
5868 .adc_channel = CHANNEL_ADC_HDSET,
5869 .switch_info = switch_info,
5870 .num_keys = ARRAY_SIZE(switch_info),
5871 .default_sw_en = true,
5872 .default_sw_idx = 0,
5873};
5874
5875static struct hsed_bias_config hsed_bias_config = {
5876 /* HSED mic bias config info */
5877 .othc_headset = OTHC_HEADSET_NO,
5878 .othc_lowcurr_thresh_uA = 100,
5879 .othc_highcurr_thresh_uA = 600,
5880 .othc_hyst_prediv_us = 7800,
5881 .othc_period_clkdiv_us = 62500,
5882 .othc_hyst_clk_us = 121000,
5883 .othc_period_clk_us = 312500,
5884 .othc_wakeup = 1,
5885};
5886
5887static struct othc_hsed_config hsed_config_1 = {
5888 .hsed_bias_config = &hsed_bias_config,
5889 /*
5890 * The detection delay and switch reporting delay are
5891 * required to encounter a hardware bug (spurious switch
5892 * interrupts on slow insertion/removal of the headset).
5893 * This will introduce a delay in reporting the accessory
5894 * insertion and removal to the userspace.
5895 */
5896 .detection_delay_ms = 1500,
5897 /* Switch info */
5898 .switch_debounce_ms = 1500,
5899 .othc_support_n_switch = false,
5900 .switch_config = &switch_config,
5901 .ir_gpio = -1,
5902 /* Accessory info */
5903 .accessories_support = true,
5904 .accessories = othc_accessories,
5905 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5906};
5907
5908static struct othc_regulator_config othc_reg = {
5909 .regulator = "8058_l5",
5910 .max_uV = 2850000,
5911 .min_uV = 2850000,
5912};
5913
5914/* MIC_BIAS0 is configured as normal MIC BIAS */
5915static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5916 .micbias_select = OTHC_MICBIAS_0,
5917 .micbias_capability = OTHC_MICBIAS,
5918 .micbias_enable = OTHC_SIGNAL_OFF,
5919 .micbias_regulator = &othc_reg,
5920};
5921
5922/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5923static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5924 .micbias_select = OTHC_MICBIAS_1,
5925 .micbias_capability = OTHC_MICBIAS_HSED,
5926 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5927 .micbias_regulator = &othc_reg,
5928 .hsed_config = &hsed_config_1,
5929 .hsed_name = "8660_handset",
5930};
5931
5932/* MIC_BIAS2 is configured as normal MIC BIAS */
5933static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5934 .micbias_select = OTHC_MICBIAS_2,
5935 .micbias_capability = OTHC_MICBIAS,
5936 .micbias_enable = OTHC_SIGNAL_OFF,
5937 .micbias_regulator = &othc_reg,
5938};
5939
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005940
5941static void __init msm8x60_init_pm8058_othc(void)
5942{
5943 int i;
5944
5945 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5946 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5947 machine_is_msm8x60_fusn_ffa()) {
5948 /* 3-switch headset supported only by V2 FFA and FLUID */
5949 hsed_config_1.accessories_adc_support = true,
5950 /* ADC based accessory detection works only on V2 and FLUID */
5951 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5952 hsed_config_1.othc_support_n_switch = true;
5953 }
5954
5955 /* IR GPIO is absent on FLUID */
5956 if (machine_is_msm8x60_fluid())
5957 hsed_config_1.ir_gpio = -1;
5958
5959 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5960 if (machine_is_msm8x60_fluid()) {
5961 switch (othc_accessories[i].accessory) {
5962 case OTHC_ANC_HEADPHONE:
5963 case OTHC_ANC_HEADSET:
5964 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5965 break;
5966 case OTHC_MICROPHONE:
5967 othc_accessories[i].enabled = false;
5968 break;
5969 case OTHC_SVIDEO_OUT:
5970 othc_accessories[i].enabled = true;
5971 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5972 break;
5973 }
5974 }
5975 }
5976}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005977
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005978
5979static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
5980{
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305981 struct pm_gpio pwm_gpio_config = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005982 .direction = PM_GPIO_DIR_OUT,
5983 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5984 .output_value = 0,
5985 .pull = PM_GPIO_PULL_NO,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05305986 .vin_sel = PM8058_GPIO_VIN_VPH,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005987 .out_strength = PM_GPIO_STRENGTH_HIGH,
5988 .function = PM_GPIO_FUNC_2,
5989 };
5990
5991 int rc = -EINVAL;
5992 int id, mode, max_mA;
5993
5994 id = mode = max_mA = 0;
5995 switch (ch) {
5996 case 0:
5997 case 1:
5998 case 2:
5999 if (on) {
6000 id = 24 + ch;
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306001 rc = pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(id - 1),
6002 &pwm_gpio_config);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006003 if (rc)
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306004 pr_err("%s: pm8xxx_gpio_config(%d): rc=%d\n",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006005 __func__, id, rc);
6006 }
6007 break;
6008
6009 case 6:
6010 id = PM_PWM_LED_FLASH;
6011 mode = PM_PWM_CONF_PWM1;
6012 max_mA = 300;
6013 break;
6014
6015 case 7:
6016 id = PM_PWM_LED_FLASH1;
6017 mode = PM_PWM_CONF_PWM1;
6018 max_mA = 300;
6019 break;
6020
6021 default:
6022 break;
6023 }
6024
6025 if (ch >= 6 && ch <= 7) {
6026 if (!on) {
6027 mode = PM_PWM_CONF_NONE;
6028 max_mA = 0;
6029 }
6030 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6031 if (rc)
6032 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6033 __func__, ch, rc);
6034 }
6035 return rc;
6036
6037}
6038
6039static struct pm8058_pwm_pdata pm8058_pwm_data = {
6040 .config = pm8058_pwm_config,
6041};
6042
6043#define PM8058_GPIO_INT 88
6044
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006045static struct pmic8058_led pmic8058_flash_leds[] = {
6046 [0] = {
6047 .name = "camera:flash0",
6048 .max_brightness = 15,
6049 .id = PMIC8058_ID_FLASH_LED_0,
6050 },
6051 [1] = {
6052 .name = "camera:flash1",
6053 .max_brightness = 15,
6054 .id = PMIC8058_ID_FLASH_LED_1,
6055 },
6056};
6057
6058static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6059 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6060 .leds = pmic8058_flash_leds,
6061};
6062
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006063static struct pmic8058_led pmic8058_dragon_leds[] = {
6064 [0] = {
6065 /* RED */
6066 .name = "led_drv0",
6067 .max_brightness = 15,
6068 .id = PMIC8058_ID_LED_0,
6069 },/* 300 mA flash led0 drv sink */
6070 [1] = {
6071 /* Yellow */
6072 .name = "led_drv1",
6073 .max_brightness = 15,
6074 .id = PMIC8058_ID_LED_1,
6075 },/* 300 mA flash led0 drv sink */
6076 [2] = {
6077 /* Green */
6078 .name = "led_drv2",
6079 .max_brightness = 15,
6080 .id = PMIC8058_ID_LED_2,
6081 },/* 300 mA flash led0 drv sink */
6082 [3] = {
6083 .name = "led_psensor",
6084 .max_brightness = 15,
6085 .id = PMIC8058_ID_LED_KB_LIGHT,
6086 },/* 300 mA flash led0 drv sink */
6087};
6088
6089static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6090 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6091 .leds = pmic8058_dragon_leds,
6092};
6093
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006094static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6095 [0] = {
6096 .name = "led:drv0",
6097 .max_brightness = 15,
6098 .id = PMIC8058_ID_FLASH_LED_0,
6099 },/* 300 mA flash led0 drv sink */
6100 [1] = {
6101 .name = "led:drv1",
6102 .max_brightness = 15,
6103 .id = PMIC8058_ID_FLASH_LED_1,
6104 },/* 300 mA flash led1 sink */
6105 [2] = {
6106 .name = "led:drv2",
6107 .max_brightness = 20,
6108 .id = PMIC8058_ID_LED_0,
6109 },/* 40 mA led0 sink */
6110 [3] = {
6111 .name = "keypad:drv",
6112 .max_brightness = 15,
6113 .id = PMIC8058_ID_LED_KB_LIGHT,
6114 },/* 300 mA keypad drv sink */
6115};
6116
6117static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6118 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6119 .leds = pmic8058_fluid_flash_leds,
6120};
6121
Terence Hampson90508a92011-08-09 10:40:08 -04006122static struct pmic8058_charger_data pmic8058_charger_dragon = {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306123 .charger_data_valid = true,
Terence Hampson90508a92011-08-09 10:40:08 -04006124 .max_source_current = 1800,
6125 .charger_type = CHG_TYPE_AC,
6126};
6127
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306128static struct pmic8058_charger_data pmic8058_charger_ffa_surf = {
6129 .charger_data_valid = false,
6130};
6131
6132static struct pm8xxx_misc_platform_data pm8058_misc_pdata = {
6133 .priority = 0,
6134};
6135
6136static struct pm8xxx_irq_platform_data pm8058_irq_pdata = {
6137 .irq_base = PM8058_IRQ_BASE,
6138 .devirq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
6139 .irq_trigger_flag = IRQF_TRIGGER_LOW,
6140};
6141
6142static struct pm8xxx_gpio_platform_data pm8058_gpio_pdata = {
6143 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6144};
6145
6146static struct pm8xxx_mpp_platform_data pm8058_mpp_pdata = {
6147 .mpp_base = PM8058_MPP_PM_TO_SYS(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006148};
6149
6150static struct pm8058_platform_data pm8058_platform_data = {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306151 .irq_pdata = &pm8058_irq_pdata,
6152 .gpio_pdata = &pm8058_gpio_pdata,
6153 .mpp_pdata = &pm8058_mpp_pdata,
6154 .rtc_pdata = &pm8058_rtc_pdata,
6155 .pwrkey_pdata = &pm8058_pwrkey_pdata,
6156 .othc0_pdata = &othc_config_pdata_0,
6157 .othc1_pdata = &othc_config_pdata_1,
6158 .othc2_pdata = &othc_config_pdata_2,
6159 .pwm_pdata = &pm8058_pwm_data,
6160 .misc_pdata = &pm8058_misc_pdata,
6161#ifdef CONFIG_SENSORS_MSM_ADC
6162 .xoadc_pdata = &pm8058_xoadc_pdata,
6163#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006164};
6165
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306166#ifdef CONFIG_MSM_SSBI
6167static struct msm_ssbi_platform_data msm8x60_ssbi_pm8058_pdata __devinitdata = {
6168 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
6169 .slave = {
6170 .name = "pm8058-core",
6171 .platform_data = &pm8058_platform_data,
6172 },
6173};
6174#endif
6175#endif /* CONFIG_PMIC8058 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006176
6177#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6178 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6179#define TDISC_I2C_SLAVE_ADDR 0x67
6180#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6181#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6182
6183static const char *vregs_tdisc_name[] = {
6184 "8058_l5",
6185 "8058_s3",
6186};
6187
6188static const int vregs_tdisc_val[] = {
6189 2850000,/* uV */
6190 1800000,
6191};
6192static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6193
6194static int tdisc_shinetsu_setup(void)
6195{
6196 int rc, i;
6197
6198 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6199 if (rc) {
6200 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6201 __func__);
6202 return rc;
6203 }
6204
6205 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6206 if (rc) {
6207 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6208 __func__);
6209 goto fail_gpio_oe;
6210 }
6211
6212 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6213 if (rc) {
6214 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6215 __func__);
6216 gpio_free(GPIO_JOYSTICK_EN);
6217 goto fail_gpio_oe;
6218 }
6219
6220 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6221 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6222 if (IS_ERR(vregs_tdisc[i])) {
6223 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6224 __func__, vregs_tdisc_name[i],
6225 PTR_ERR(vregs_tdisc[i]));
6226 rc = PTR_ERR(vregs_tdisc[i]);
6227 goto vreg_get_fail;
6228 }
6229
6230 rc = regulator_set_voltage(vregs_tdisc[i],
6231 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6232 if (rc) {
6233 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6234 __func__, rc);
6235 goto vreg_set_voltage_fail;
6236 }
6237 }
6238
6239 return rc;
6240vreg_set_voltage_fail:
6241 i++;
6242vreg_get_fail:
6243 while (i)
6244 regulator_put(vregs_tdisc[--i]);
6245fail_gpio_oe:
6246 gpio_free(PMIC_GPIO_TDISC);
6247 return rc;
6248}
6249
6250static void tdisc_shinetsu_release(void)
6251{
6252 int i;
6253
6254 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6255 regulator_put(vregs_tdisc[i]);
6256
6257 gpio_free(PMIC_GPIO_TDISC);
6258 gpio_free(GPIO_JOYSTICK_EN);
6259}
6260
6261static int tdisc_shinetsu_enable(void)
6262{
6263 int i, rc = -EINVAL;
6264
6265 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6266 rc = regulator_enable(vregs_tdisc[i]);
6267 if (rc < 0) {
6268 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6269 __func__, vregs_tdisc_name[i], rc);
6270 goto vreg_fail;
6271 }
6272 }
6273
6274 /* Enable the OE (output enable) gpio */
6275 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6276 /* voltage and gpio stabilization delay */
6277 msleep(50);
6278
6279 return 0;
6280vreg_fail:
6281 while (i)
6282 regulator_disable(vregs_tdisc[--i]);
6283 return rc;
6284}
6285
6286static int tdisc_shinetsu_disable(void)
6287{
6288 int i, rc;
6289
6290 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6291 rc = regulator_disable(vregs_tdisc[i]);
6292 if (rc < 0) {
6293 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6294 __func__, vregs_tdisc_name[i], rc);
6295 goto tdisc_reg_fail;
6296 }
6297 }
6298
6299 /* Disable the OE (output enable) gpio */
6300 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6301
6302 return 0;
6303
6304tdisc_reg_fail:
6305 while (i)
6306 regulator_enable(vregs_tdisc[--i]);
6307 return rc;
6308}
6309
6310static struct tdisc_abs_values tdisc_abs = {
6311 .x_max = 32,
6312 .y_max = 32,
6313 .x_min = -32,
6314 .y_min = -32,
6315 .pressure_max = 32,
6316 .pressure_min = 0,
6317};
6318
6319static struct tdisc_platform_data tdisc_data = {
6320 .tdisc_setup = tdisc_shinetsu_setup,
6321 .tdisc_release = tdisc_shinetsu_release,
6322 .tdisc_enable = tdisc_shinetsu_enable,
6323 .tdisc_disable = tdisc_shinetsu_disable,
6324 .tdisc_wakeup = 0,
6325 .tdisc_gpio = PMIC_GPIO_TDISC,
6326 .tdisc_report_keys = true,
6327 .tdisc_report_relative = true,
6328 .tdisc_report_absolute = false,
6329 .tdisc_report_wheel = false,
6330 .tdisc_reverse_x = false,
6331 .tdisc_reverse_y = true,
6332 .tdisc_abs = &tdisc_abs,
6333};
6334
6335static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6336 {
6337 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6338 .irq = TDISC_INT,
6339 .platform_data = &tdisc_data,
6340 },
6341};
6342#endif
6343
6344#define PM_GPIO_CDC_RST_N 20
6345#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6346
6347static struct regulator *vreg_timpani_1;
6348static struct regulator *vreg_timpani_2;
6349
6350static unsigned int msm_timpani_setup_power(void)
6351{
6352 int rc;
6353
6354 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6355 if (IS_ERR(vreg_timpani_1)) {
6356 pr_err("%s: Unable to get 8058_l0\n", __func__);
6357 return -ENODEV;
6358 }
6359
6360 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6361 if (IS_ERR(vreg_timpani_2)) {
6362 pr_err("%s: Unable to get 8058_s3\n", __func__);
6363 regulator_put(vreg_timpani_1);
6364 return -ENODEV;
6365 }
6366
6367 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6368 if (rc) {
6369 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6370 goto fail;
6371 }
6372
6373 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6374 if (rc) {
6375 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6376 goto fail;
6377 }
6378
6379 rc = regulator_enable(vreg_timpani_1);
6380 if (rc) {
6381 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6382 goto fail;
6383 }
6384
6385 /* The settings for LDO0 should be set such that
6386 * it doesn't require to reset the timpani. */
6387 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6388 if (rc < 0) {
6389 pr_err("Timpani regulator optimum mode setting failed\n");
6390 goto fail;
6391 }
6392
6393 rc = regulator_enable(vreg_timpani_2);
6394 if (rc) {
6395 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6396 regulator_disable(vreg_timpani_1);
6397 goto fail;
6398 }
6399
6400 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6401 if (rc) {
6402 pr_err("%s: GPIO Request %d failed\n", __func__,
6403 GPIO_CDC_RST_N);
6404 regulator_disable(vreg_timpani_1);
6405 regulator_disable(vreg_timpani_2);
6406 goto fail;
6407 } else {
6408 gpio_direction_output(GPIO_CDC_RST_N, 1);
6409 usleep_range(1000, 1050);
6410 gpio_direction_output(GPIO_CDC_RST_N, 0);
6411 usleep_range(1000, 1050);
6412 gpio_direction_output(GPIO_CDC_RST_N, 1);
6413 gpio_free(GPIO_CDC_RST_N);
6414 }
6415 return rc;
6416
6417fail:
6418 regulator_put(vreg_timpani_1);
6419 regulator_put(vreg_timpani_2);
6420 return rc;
6421}
6422
6423static void msm_timpani_shutdown_power(void)
6424{
6425 int rc;
6426
6427 rc = regulator_disable(vreg_timpani_1);
6428 if (rc)
6429 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6430
6431 regulator_put(vreg_timpani_1);
6432
6433 rc = regulator_disable(vreg_timpani_2);
6434 if (rc)
6435 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6436
6437 regulator_put(vreg_timpani_2);
6438}
6439
6440/* Power analog function of codec */
6441static struct regulator *vreg_timpani_cdc_apwr;
6442static int msm_timpani_codec_power(int vreg_on)
6443{
6444 int rc = 0;
6445
6446 if (!vreg_timpani_cdc_apwr) {
6447
6448 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6449
6450 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6451 pr_err("%s: vreg_get failed (%ld)\n",
6452 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6453 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6454 return rc;
6455 }
6456 }
6457
6458 if (vreg_on) {
6459
6460 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6461 2200000, 2200000);
6462 if (rc) {
6463 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6464 __func__);
6465 goto vreg_fail;
6466 }
6467
6468 rc = regulator_enable(vreg_timpani_cdc_apwr);
6469 if (rc) {
6470 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6471 goto vreg_fail;
6472 }
6473 } else {
6474 rc = regulator_disable(vreg_timpani_cdc_apwr);
6475 if (rc) {
6476 pr_err("%s: vreg_disable failed %d\n",
6477 __func__, rc);
6478 goto vreg_fail;
6479 }
6480 }
6481
6482 return 0;
6483
6484vreg_fail:
6485 regulator_put(vreg_timpani_cdc_apwr);
6486 vreg_timpani_cdc_apwr = NULL;
6487 return rc;
6488}
6489
6490static struct marimba_codec_platform_data timpani_codec_pdata = {
6491 .marimba_codec_power = msm_timpani_codec_power,
6492};
6493
6494#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6495#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6496
6497static struct marimba_platform_data timpani_pdata = {
6498 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6499 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6500 .marimba_setup = msm_timpani_setup_power,
6501 .marimba_shutdown = msm_timpani_shutdown_power,
6502 .codec = &timpani_codec_pdata,
6503 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6504};
6505
6506#define TIMPANI_I2C_SLAVE_ADDR 0xD
6507
6508static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6509 {
6510 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6511 .platform_data = &timpani_pdata,
6512 },
6513};
6514
Lei Zhou338cab82011-08-19 13:38:17 -04006515#ifdef CONFIG_SND_SOC_WM8903
6516static struct wm8903_platform_data wm8903_pdata = {
6517 .gpio_cfg[2] = 0x3A8,
6518};
6519
6520#define WM8903_I2C_SLAVE_ADDR 0x34
6521static struct i2c_board_info wm8903_codec_i2c_info[] = {
6522 {
6523 I2C_BOARD_INFO("wm8903", WM8903_I2C_SLAVE_ADDR >> 1),
6524 .platform_data = &wm8903_pdata,
6525 },
6526};
6527#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006528#ifdef CONFIG_PMIC8901
6529
6530#define PM8901_GPIO_INT 91
6531
6532static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6533 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6534 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6535};
6536
6537static struct resource pm8901_temp_alarm[] = {
6538 {
6539 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6540 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6541 .flags = IORESOURCE_IRQ,
6542 },
6543 {
6544 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6545 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6546 .flags = IORESOURCE_IRQ,
6547 },
6548};
6549
6550/*
6551 * Consumer specific regulator names:
6552 * regulator name consumer dev_name
6553 */
6554static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6555 REGULATOR_SUPPLY("8901_mpp0", NULL),
6556};
6557static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6558 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6559};
6560static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6561 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6562};
6563
6564#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6565 _always_on, _active_high) \
6566 [PM8901_VREG_ID_##_id] = { \
6567 .init_data = { \
6568 .constraints = { \
6569 .valid_modes_mask = _modes, \
6570 .valid_ops_mask = _ops, \
6571 .min_uV = _min_uV, \
6572 .max_uV = _max_uV, \
6573 .input_uV = _min_uV, \
6574 .apply_uV = _apply_uV, \
6575 .always_on = _always_on, \
6576 }, \
6577 .consumer_supplies = vreg_consumers_8901_##_id, \
6578 .num_consumer_supplies = \
6579 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6580 }, \
6581 .active_high = _active_high, \
6582 }
6583
6584#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6585 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6586 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6587
6588#define PM8901_VREG_INIT_VS(_id) \
6589 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6590 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6591
6592static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6593 PM8901_VREG_INIT_MPP(MPP0, 1),
6594
6595 PM8901_VREG_INIT_VS(USB_OTG),
6596 PM8901_VREG_INIT_VS(HDMI_MVS),
6597};
6598
6599#define PM8901_VREG(_id) { \
6600 .name = "pm8901-regulator", \
6601 .id = _id, \
6602 .platform_data = &pm8901_vreg_init_pdata[_id], \
6603 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6604}
6605
6606static struct mfd_cell pm8901_subdevs[] = {
6607 { .name = "pm8901-mpp",
6608 .id = -1,
6609 .platform_data = &pm8901_mpp_data,
6610 .pdata_size = sizeof(pm8901_mpp_data),
6611 },
6612 { .name = "pm8901-tm",
6613 .id = -1,
6614 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6615 .resources = pm8901_temp_alarm,
6616 },
6617 PM8901_VREG(PM8901_VREG_ID_MPP0),
6618 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6619 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6620};
6621
6622static struct pm8901_platform_data pm8901_platform_data = {
6623 .irq_base = PM8901_IRQ_BASE,
6624 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6625 .sub_devices = pm8901_subdevs,
6626 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6627};
6628
6629static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6630 {
6631 I2C_BOARD_INFO("pm8901-core", 0x55),
6632 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6633 .platform_data = &pm8901_platform_data,
6634 },
6635};
6636
6637#endif /* CONFIG_PMIC8901 */
6638
6639#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6640 || defined(CONFIG_GPIO_SX150X_MODULE))
6641
6642static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006643static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006644
6645struct bahama_config_register{
6646 u8 reg;
6647 u8 value;
6648 u8 mask;
6649};
6650
6651enum version{
6652 VER_1_0,
6653 VER_2_0,
6654 VER_UNSUPPORTED = 0xFF
6655};
6656
6657static u8 read_bahama_ver(void)
6658{
6659 int rc;
6660 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6661 u8 bahama_version;
6662
6663 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6664 if (rc < 0) {
6665 printk(KERN_ERR
6666 "%s: version read failed: %d\n",
6667 __func__, rc);
6668 return VER_UNSUPPORTED;
6669 } else {
6670 printk(KERN_INFO
6671 "%s: version read got: 0x%x\n",
6672 __func__, bahama_version);
6673 }
6674
6675 switch (bahama_version) {
6676 case 0x08: /* varient of bahama v1 */
6677 case 0x10:
6678 case 0x00:
6679 return VER_1_0;
6680 case 0x09: /* variant of bahama v2 */
6681 return VER_2_0;
6682 default:
6683 return VER_UNSUPPORTED;
6684 }
6685}
6686
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006687static int msm_bahama_setup_power_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006688static unsigned int msm_bahama_setup_power(void)
6689{
6690 int rc = 0;
6691 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006692
6693 if (machine_is_msm8x60_dragon())
6694 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6695
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006696 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6697
6698 if (IS_ERR(vreg_bahama)) {
6699 rc = PTR_ERR(vreg_bahama);
6700 pr_err("%s: regulator_get %s = %d\n", __func__,
6701 msm_bahama_regulator, rc);
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006702 return rc;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006703 }
6704
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006705 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6706 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006707 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6708 msm_bahama_regulator, rc);
6709 goto unget;
6710 }
6711
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006712 rc = regulator_enable(vreg_bahama);
6713 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006714 pr_err("%s: regulator_enable %s = %d\n", __func__,
6715 msm_bahama_regulator, rc);
6716 goto unget;
6717 }
6718
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006719 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6720 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006721 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006722 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006723 goto unenable;
6724 }
6725
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006726 gpio_direction_output(msm_bahama_sys_rst, 0);
6727 usleep_range(1000, 1050);
6728 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
6729 usleep_range(1000, 1050);
6730 msm_bahama_setup_power_enable = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006731 return rc;
6732
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006733unenable:
6734 regulator_disable(vreg_bahama);
6735unget:
6736 regulator_put(vreg_bahama);
6737 return rc;
6738};
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006739
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006740static unsigned int msm_bahama_shutdown_power(int value)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006741{
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006742 if (msm_bahama_setup_power_enable) {
6743 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
6744 gpio_free(msm_bahama_sys_rst);
6745 regulator_disable(vreg_bahama);
6746 regulator_put(vreg_bahama);
6747 msm_bahama_setup_power_enable = 0;
6748 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006749
6750 return 0;
6751};
6752
6753static unsigned int msm_bahama_core_config(int type)
6754{
6755 int rc = 0;
6756
6757 if (type == BAHAMA_ID) {
6758
6759 int i;
6760 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6761
6762 const struct bahama_config_register v20_init[] = {
6763 /* reg, value, mask */
6764 { 0xF4, 0x84, 0xFF }, /* AREG */
6765 { 0xF0, 0x04, 0xFF } /* DREG */
6766 };
6767
6768 if (read_bahama_ver() == VER_2_0) {
6769 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6770 u8 value = v20_init[i].value;
6771 rc = marimba_write_bit_mask(&config,
6772 v20_init[i].reg,
6773 &value,
6774 sizeof(v20_init[i].value),
6775 v20_init[i].mask);
6776 if (rc < 0) {
6777 printk(KERN_ERR
6778 "%s: reg %d write failed: %d\n",
6779 __func__, v20_init[i].reg, rc);
6780 return rc;
6781 }
6782 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6783 " mask 0x%02x\n",
6784 __func__, v20_init[i].reg,
6785 v20_init[i].value, v20_init[i].mask);
6786 }
6787 }
6788 }
6789 printk(KERN_INFO "core type: %d\n", type);
6790
6791 return rc;
6792}
6793
6794static struct regulator *fm_regulator_s3;
6795static struct msm_xo_voter *fm_clock;
6796
6797static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6798{
6799 int rc = 0;
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306800 struct pm_gpio cfg = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006801 .direction = PM_GPIO_DIR_IN,
6802 .pull = PM_GPIO_PULL_NO,
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306803 .vin_sel = PM8058_GPIO_VIN_S3,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006804 .function = PM_GPIO_FUNC_NORMAL,
6805 .inv_int_pol = 0,
6806 };
6807
6808 if (!fm_regulator_s3) {
6809 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
6810 if (IS_ERR(fm_regulator_s3)) {
6811 rc = PTR_ERR(fm_regulator_s3);
6812 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
6813 __func__, rc);
6814 goto out;
6815 }
6816 }
6817
6818
6819 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
6820 if (rc < 0) {
6821 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
6822 __func__, rc);
6823 goto fm_fail_put;
6824 }
6825
6826 rc = regulator_enable(fm_regulator_s3);
6827 if (rc < 0) {
6828 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
6829 __func__, rc);
6830 goto fm_fail_put;
6831 }
6832
6833 /*Vote for XO clock*/
6834 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
6835
6836 if (IS_ERR(fm_clock)) {
6837 rc = PTR_ERR(fm_clock);
6838 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
6839 __func__, rc);
6840 goto fm_fail_switch;
6841 }
6842
6843 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
6844 if (rc < 0) {
6845 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
6846 __func__, rc);
6847 goto fm_fail_vote;
6848 }
6849
6850 /*GPIO 18 on PMIC is FM_IRQ*/
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306851 rc = pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(FM_GPIO), &cfg);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006852 if (rc) {
Anirudh Ghayalc2019332011-11-12 06:29:10 +05306853 printk(KERN_ERR "%s: return val of pm8xxx_gpio_config: %d\n",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006854 __func__, rc);
6855 goto fm_fail_clock;
6856 }
6857 goto out;
6858
6859fm_fail_clock:
6860 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
6861fm_fail_vote:
6862 msm_xo_put(fm_clock);
6863fm_fail_switch:
6864 regulator_disable(fm_regulator_s3);
6865fm_fail_put:
6866 regulator_put(fm_regulator_s3);
6867out:
6868 return rc;
6869};
6870
6871static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
6872{
6873 int rc = 0;
6874 if (fm_regulator_s3 != NULL) {
6875 rc = regulator_disable(fm_regulator_s3);
6876 if (rc < 0) {
6877 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
6878 __func__, rc);
6879 }
6880 regulator_put(fm_regulator_s3);
6881 fm_regulator_s3 = NULL;
6882 }
6883 printk(KERN_ERR "%s: Voting off for XO", __func__);
6884
6885 if (fm_clock != NULL) {
6886 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
6887 if (rc < 0) {
6888 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
6889 __func__, rc);
6890 }
6891 msm_xo_put(fm_clock);
6892 }
6893 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
6894}
6895
6896/* Slave id address for FM/CDC/QMEMBIST
6897 * Values can be programmed using Marimba slave id 0
6898 * should there be a conflict with other I2C devices
6899 * */
6900#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
6901#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
6902
6903static struct marimba_fm_platform_data marimba_fm_pdata = {
6904 .fm_setup = fm_radio_setup,
6905 .fm_shutdown = fm_radio_shutdown,
6906 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
6907 .is_fm_soc_i2s_master = false,
6908 .config_i2s_gpio = NULL,
6909};
6910
6911/*
6912Just initializing the BAHAMA related slave
6913*/
6914static struct marimba_platform_data marimba_pdata = {
6915 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
6916 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
6917 .bahama_setup = msm_bahama_setup_power,
6918 .bahama_shutdown = msm_bahama_shutdown_power,
6919 .bahama_core_config = msm_bahama_core_config,
6920 .fm = &marimba_fm_pdata,
6921 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6922};
6923
6924
6925static struct i2c_board_info msm_marimba_board_info[] = {
6926 {
6927 I2C_BOARD_INFO("marimba", 0xc),
6928 .platform_data = &marimba_pdata,
6929 }
6930};
6931#endif /* CONFIG_MAIMBA_CORE */
6932
6933#ifdef CONFIG_I2C
6934#define I2C_SURF 1
6935#define I2C_FFA (1 << 1)
6936#define I2C_RUMI (1 << 2)
6937#define I2C_SIM (1 << 3)
6938#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006939#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006940
6941struct i2c_registry {
6942 u8 machs;
6943 int bus;
6944 struct i2c_board_info *info;
6945 int len;
6946};
6947
6948static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006949#ifdef CONFIG_PMIC8901
6950 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006951 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006952 MSM_SSBI2_I2C_BUS_ID,
6953 pm8901_boardinfo,
6954 ARRAY_SIZE(pm8901_boardinfo),
6955 },
6956#endif
6957#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
6958 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006959 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006960 MSM_GSBI8_QUP_I2C_BUS_ID,
6961 core_expander_i2c_info,
6962 ARRAY_SIZE(core_expander_i2c_info),
6963 },
6964 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006965 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006966 MSM_GSBI8_QUP_I2C_BUS_ID,
6967 docking_expander_i2c_info,
6968 ARRAY_SIZE(docking_expander_i2c_info),
6969 },
6970 {
6971 I2C_SURF,
6972 MSM_GSBI8_QUP_I2C_BUS_ID,
6973 surf_expanders_i2c_info,
6974 ARRAY_SIZE(surf_expanders_i2c_info),
6975 },
6976 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006977 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006978 MSM_GSBI3_QUP_I2C_BUS_ID,
6979 fha_expanders_i2c_info,
6980 ARRAY_SIZE(fha_expanders_i2c_info),
6981 },
6982 {
6983 I2C_FLUID,
6984 MSM_GSBI3_QUP_I2C_BUS_ID,
6985 fluid_expanders_i2c_info,
6986 ARRAY_SIZE(fluid_expanders_i2c_info),
6987 },
6988 {
6989 I2C_FLUID,
6990 MSM_GSBI8_QUP_I2C_BUS_ID,
6991 fluid_core_expander_i2c_info,
6992 ARRAY_SIZE(fluid_core_expander_i2c_info),
6993 },
6994#endif
6995#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6996 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6997 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04006998 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006999 MSM_GSBI3_QUP_I2C_BUS_ID,
7000 msm_i2c_gsbi3_tdisc_info,
7001 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7002 },
7003#endif
7004 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007005 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007006 MSM_GSBI3_QUP_I2C_BUS_ID,
7007 cy8ctmg200_board_info,
7008 ARRAY_SIZE(cy8ctmg200_board_info),
7009 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007010 {
7011 I2C_DRAGON,
7012 MSM_GSBI3_QUP_I2C_BUS_ID,
7013 cy8ctma340_dragon_board_info,
7014 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7015 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007016#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7017 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7018 {
7019 I2C_FLUID,
7020 MSM_GSBI3_QUP_I2C_BUS_ID,
7021 cyttsp_fluid_info,
7022 ARRAY_SIZE(cyttsp_fluid_info),
7023 },
7024 {
7025 I2C_FFA | I2C_SURF,
7026 MSM_GSBI3_QUP_I2C_BUS_ID,
7027 cyttsp_ffa_info,
7028 ARRAY_SIZE(cyttsp_ffa_info),
7029 },
7030#endif
7031#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007032 {
7033 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007034 MSM_GSBI4_QUP_I2C_BUS_ID,
7035 msm_camera_boardinfo,
7036 ARRAY_SIZE(msm_camera_boardinfo),
7037 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007038 {
7039 I2C_DRAGON,
7040 MSM_GSBI4_QUP_I2C_BUS_ID,
7041 msm_camera_dragon_boardinfo,
7042 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7043 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007044#endif
7045 {
7046 I2C_SURF | I2C_FFA | I2C_FLUID,
7047 MSM_GSBI7_QUP_I2C_BUS_ID,
7048 msm_i2c_gsbi7_timpani_info,
7049 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7050 },
7051#if defined(CONFIG_MARIMBA_CORE)
7052 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007053 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007054 MSM_GSBI7_QUP_I2C_BUS_ID,
7055 msm_marimba_board_info,
7056 ARRAY_SIZE(msm_marimba_board_info),
7057 },
7058#endif /* CONFIG_MARIMBA_CORE */
7059#ifdef CONFIG_ISL9519_CHARGER
7060 {
7061 I2C_SURF | I2C_FFA,
7062 MSM_GSBI8_QUP_I2C_BUS_ID,
7063 isl_charger_i2c_info,
7064 ARRAY_SIZE(isl_charger_i2c_info),
7065 },
7066#endif
7067#if defined(CONFIG_HAPTIC_ISA1200) || \
7068 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7069 {
7070 I2C_FLUID,
7071 MSM_GSBI8_QUP_I2C_BUS_ID,
7072 msm_isa1200_board_info,
7073 ARRAY_SIZE(msm_isa1200_board_info),
7074 },
7075#endif
7076#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7077 {
7078 I2C_FLUID,
7079 MSM_GSBI8_QUP_I2C_BUS_ID,
7080 smb137b_charger_i2c_info,
7081 ARRAY_SIZE(smb137b_charger_i2c_info),
7082 },
7083#endif
7084#if defined(CONFIG_BATTERY_BQ27520) || \
7085 defined(CONFIG_BATTERY_BQ27520_MODULE)
7086 {
7087 I2C_FLUID,
7088 MSM_GSBI8_QUP_I2C_BUS_ID,
7089 msm_bq27520_board_info,
7090 ARRAY_SIZE(msm_bq27520_board_info),
7091 },
7092#endif
Lei Zhou338cab82011-08-19 13:38:17 -04007093#if defined(CONFIG_SND_SOC_WM8903) || defined(CONFIG_SND_SOC_WM8903_MODULE)
7094 {
7095 I2C_DRAGON,
7096 MSM_GSBI8_QUP_I2C_BUS_ID,
7097 wm8903_codec_i2c_info,
7098 ARRAY_SIZE(wm8903_codec_i2c_info),
7099 },
7100#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007101};
7102#endif /* CONFIG_I2C */
7103
7104static void fixup_i2c_configs(void)
7105{
7106#ifdef CONFIG_I2C
7107#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7108 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7109 sx150x_data[SX150X_CORE].irq_summary =
7110 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007111 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7112 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007113 sx150x_data[SX150X_CORE].irq_summary =
7114 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7115 else if (machine_is_msm8x60_fluid())
7116 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7117 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7118#endif
7119 /*
7120 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7121 * implies that the regulator connected to MPP0 is enabled when
7122 * MPP0 is low.
7123 */
7124 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7125 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7126 else
7127 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7128#endif
7129}
7130
7131static void register_i2c_devices(void)
7132{
7133#ifdef CONFIG_I2C
7134 u8 mach_mask = 0;
7135 int i;
7136
7137 /* Build the matching 'supported_machs' bitmask */
7138 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7139 mach_mask = I2C_SURF;
7140 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7141 mach_mask = I2C_FFA;
7142 else if (machine_is_msm8x60_rumi3())
7143 mach_mask = I2C_RUMI;
7144 else if (machine_is_msm8x60_sim())
7145 mach_mask = I2C_SIM;
7146 else if (machine_is_msm8x60_fluid())
7147 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007148 else if (machine_is_msm8x60_dragon())
7149 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007150 else
7151 pr_err("unmatched machine ID in register_i2c_devices\n");
7152
7153 /* Run the array and install devices as appropriate */
7154 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7155 if (msm8x60_i2c_devices[i].machs & mach_mask)
7156 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7157 msm8x60_i2c_devices[i].info,
7158 msm8x60_i2c_devices[i].len);
7159 }
7160#endif
7161}
7162
7163static void __init msm8x60_init_uart12dm(void)
7164{
7165#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7166 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7167 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7168
7169 if (!fpga_mem)
7170 pr_err("%s(): Error getting memory\n", __func__);
7171
7172 /* Advanced mode */
7173 writew(0xFFFF, fpga_mem + 0x15C);
7174 /* FPGA_UART_SEL */
7175 writew(0, fpga_mem + 0x172);
7176 /* FPGA_GPIO_CONFIG_117 */
7177 writew(1, fpga_mem + 0xEA);
7178 /* FPGA_GPIO_CONFIG_118 */
7179 writew(1, fpga_mem + 0xEC);
7180 mb();
7181 iounmap(fpga_mem);
7182#endif
7183}
7184
7185#define MSM_GSBI9_PHYS 0x19900000
7186#define GSBI_DUAL_MODE_CODE 0x60
7187
7188static void __init msm8x60_init_buses(void)
7189{
7190#ifdef CONFIG_I2C_QUP
7191 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7192 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7193 writel_relaxed(0x6 << 4, gsbi_mem);
7194 /* Ensure protocol code is written before proceeding further */
7195 mb();
7196 iounmap(gsbi_mem);
7197
7198 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7199 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7200 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7201 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7202
7203#ifdef CONFIG_MSM_GSBI9_UART
7204 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7205 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7206 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7207 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7208 iounmap(gsbi_mem);
7209 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7210 }
7211#endif
7212 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7213 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7214#endif
7215#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7216 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7217#endif
7218#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007219 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7220 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7221#endif
7222
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05307223#ifdef CONFIG_MSM_SSBI
7224 msm_device_ssbi_pmic1.dev.platform_data =
7225 &msm8x60_ssbi_pm8058_pdata;
7226#endif
7227
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007228 if (machine_is_msm8x60_fluid()) {
7229#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7230 (defined(CONFIG_SMB137B_CHARGER) || \
7231 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7232 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7233#endif
7234#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7235 msm_gsbi10_qup_spi_device.dev.platform_data =
7236 &msm_gsbi10_qup_spi_pdata;
7237#endif
7238 }
7239
7240#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7241 /*
7242 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7243 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7244 * and ID notifications are available only on V2 surf and FFA
7245 * with a hardware workaround.
7246 */
7247 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7248 (machine_is_msm8x60_surf() ||
7249 (machine_is_msm8x60_ffa() &&
7250 pmic_id_notif_supported)))
7251 msm_otg_pdata.phy_can_powercollapse = 1;
7252 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7253#endif
7254
7255#ifdef CONFIG_USB_GADGET_MSM_72K
7256 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7257#endif
7258
7259#ifdef CONFIG_SERIAL_MSM_HS
7260 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7261 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7262#endif
7263#ifdef CONFIG_MSM_GSBI9_UART
7264 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7265 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7266 if (IS_ERR(msm_device_uart_gsbi9))
7267 pr_err("%s(): Failed to create uart gsbi9 device\n",
7268 __func__);
7269 }
7270#endif
7271
7272#ifdef CONFIG_MSM_BUS_SCALING
7273
7274 /* RPM calls are only enabled on V2 */
7275 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7276 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7277 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7278 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7279 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7280 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7281 }
7282
7283 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7284 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7285 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7286 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7287 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7288#endif
7289}
7290
7291static void __init msm8x60_map_io(void)
7292{
7293 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7294 msm_map_msm8x60_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007295
7296 if (socinfo_init() < 0)
7297 pr_err("socinfo_init() failed!\n");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007298}
7299
7300/*
7301 * Most segments of the EBI2 bus are disabled by default.
7302 */
7303static void __init msm8x60_init_ebi2(void)
7304{
7305 uint32_t ebi2_cfg;
7306 void *ebi2_cfg_ptr;
Terence Hampsonb36a38c2011-09-19 19:10:40 -04007307 struct clk *mem_clk = clk_get_sys("msm_ebi2", "mem_clk");
7308
7309 if (IS_ERR(mem_clk)) {
7310 pr_err("%s: clk_get_sys(%s,%s), failed", __func__,
7311 "msm_ebi2", "mem_clk");
7312 return;
7313 }
7314 clk_enable(mem_clk);
7315 clk_put(mem_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007316
7317 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7318 if (ebi2_cfg_ptr != 0) {
7319 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7320
7321 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007322 machine_is_msm8x60_fluid() ||
7323 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007324 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7325 else if (machine_is_msm8x60_sim())
7326 ebi2_cfg |= (1 << 4); /* CS2 */
7327 else if (machine_is_msm8x60_rumi3())
7328 ebi2_cfg |= (1 << 5); /* CS3 */
7329
7330 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7331 iounmap(ebi2_cfg_ptr);
7332 }
7333
7334 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007335 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007336 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7337 if (ebi2_cfg_ptr != 0) {
7338 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7339 writel_relaxed(0UL, ebi2_cfg_ptr);
7340
7341 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7342 * LAN9221 Ethernet controller reads and writes.
7343 * The lowest 4 bits are the read delay, the next
7344 * 4 are the write delay. */
7345 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7346#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7347 /*
7348 * RECOVERY=5, HOLD_WR=1
7349 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7350 * WAIT_WR=1, WAIT_RD=2
7351 */
7352 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7353 /*
7354 * HOLD_RD=1
7355 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7356 */
7357 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7358#else
7359 /* EBI2 CS3 muxed address/data,
7360 * two cyc addr enable */
7361 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7362
7363#endif
7364 iounmap(ebi2_cfg_ptr);
7365 }
7366 }
7367}
7368
7369static void __init msm8x60_configure_smc91x(void)
7370{
7371 if (machine_is_msm8x60_sim()) {
7372
7373 smc91x_resources[0].start = 0x1b800300;
7374 smc91x_resources[0].end = 0x1b8003ff;
7375
7376 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7377 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7378
7379 } else if (machine_is_msm8x60_rumi3()) {
7380
7381 smc91x_resources[0].start = 0x1d000300;
7382 smc91x_resources[0].end = 0x1d0003ff;
7383
7384 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7385 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7386 }
7387}
7388
7389static void __init msm8x60_init_tlmm(void)
7390{
7391 if (machine_is_msm8x60_rumi3())
7392 msm_gpio_install_direct_irq(0, 0, 1);
7393}
7394
7395#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7396 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7397 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7398 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7399 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7400
Stepan Moskovchenko73b943b2011-10-31 22:43:00 -07007401/* 8x60 has 5 SDCC controllers */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007402#define MAX_SDCC_CONTROLLER 5
7403
7404struct msm_sdcc_gpio {
7405 /* maximum 10 GPIOs per SDCC controller */
7406 s16 no;
7407 /* name of this GPIO */
7408 const char *name;
7409 bool always_on;
7410 bool is_enabled;
7411};
7412
7413#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7414static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7415 {159, "sdc1_dat_0"},
7416 {160, "sdc1_dat_1"},
7417 {161, "sdc1_dat_2"},
7418 {162, "sdc1_dat_3"},
7419#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7420 {163, "sdc1_dat_4"},
7421 {164, "sdc1_dat_5"},
7422 {165, "sdc1_dat_6"},
7423 {166, "sdc1_dat_7"},
7424#endif
7425 {167, "sdc1_clk"},
7426 {168, "sdc1_cmd"}
7427};
7428#endif
7429
7430#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7431static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7432 {143, "sdc2_dat_0"},
7433 {144, "sdc2_dat_1", 1},
7434 {145, "sdc2_dat_2"},
7435 {146, "sdc2_dat_3"},
7436#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7437 {147, "sdc2_dat_4"},
7438 {148, "sdc2_dat_5"},
7439 {149, "sdc2_dat_6"},
7440 {150, "sdc2_dat_7"},
7441#endif
7442 {151, "sdc2_cmd"},
7443 {152, "sdc2_clk", 1}
7444};
7445#endif
7446
7447#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7448static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7449 {95, "sdc5_cmd"},
7450 {96, "sdc5_dat_3"},
7451 {97, "sdc5_clk", 1},
7452 {98, "sdc5_dat_2"},
7453 {99, "sdc5_dat_1", 1},
7454 {100, "sdc5_dat_0"}
7455};
7456#endif
7457
7458struct msm_sdcc_pad_pull_cfg {
7459 enum msm_tlmm_pull_tgt pull;
7460 u32 pull_val;
7461};
7462
7463struct msm_sdcc_pad_drv_cfg {
7464 enum msm_tlmm_hdrive_tgt drv;
7465 u32 drv_val;
7466};
7467
7468#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7469static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7470 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7471 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7472 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7473};
7474
7475static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7476 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7477 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7478};
7479
7480static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7481 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7482 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7483 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7484};
7485
7486static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7487 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7488 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7489};
7490#endif
7491
7492#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7493static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7494 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7495 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7496 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7497};
7498
7499static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7500 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7501 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7502};
7503
7504static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7505 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7506 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7507 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7508};
7509
7510static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7511 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7512 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7513};
7514#endif
7515
7516struct msm_sdcc_pin_cfg {
7517 /*
7518 * = 1 if controller pins are using gpios
7519 * = 0 if controller has dedicated MSM pins
7520 */
7521 u8 is_gpio;
7522 u8 cfg_sts;
7523 u8 gpio_data_size;
7524 struct msm_sdcc_gpio *gpio_data;
7525 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7526 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7527 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7528 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7529 u8 pad_drv_data_size;
7530 u8 pad_pull_data_size;
7531 u8 sdio_lpm_gpio_cfg;
7532};
7533
7534
7535static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7536#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7537 [0] = {
7538 .is_gpio = 1,
7539 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7540 .gpio_data = sdc1_gpio_cfg
7541 },
7542#endif
7543#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7544 [1] = {
7545 .is_gpio = 1,
7546 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7547 .gpio_data = sdc2_gpio_cfg
7548 },
7549#endif
7550#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7551 [2] = {
7552 .is_gpio = 0,
7553 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7554 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7555 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7556 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7557 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7558 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7559 },
7560#endif
7561#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7562 [3] = {
7563 .is_gpio = 0,
7564 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7565 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7566 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7567 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7568 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7569 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7570 },
7571#endif
7572#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7573 [4] = {
7574 .is_gpio = 1,
7575 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7576 .gpio_data = sdc5_gpio_cfg
7577 }
7578#endif
7579};
7580
7581static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7582{
7583 int rc = 0;
7584 struct msm_sdcc_pin_cfg *curr;
7585 int n;
7586
7587 curr = &sdcc_pin_cfg_data[dev_id - 1];
7588 if (!curr->gpio_data)
7589 goto out;
7590
7591 for (n = 0; n < curr->gpio_data_size; n++) {
7592 if (enable) {
7593
7594 if (curr->gpio_data[n].always_on &&
7595 curr->gpio_data[n].is_enabled)
7596 continue;
7597 pr_debug("%s: enable: %s\n", __func__,
7598 curr->gpio_data[n].name);
7599 rc = gpio_request(curr->gpio_data[n].no,
7600 curr->gpio_data[n].name);
7601 if (rc) {
7602 pr_err("%s: gpio_request(%d, %s)"
7603 "failed", __func__,
7604 curr->gpio_data[n].no,
7605 curr->gpio_data[n].name);
7606 goto free_gpios;
7607 }
7608 /* set direction as output for all GPIOs */
7609 rc = gpio_direction_output(
7610 curr->gpio_data[n].no, 1);
7611 if (rc) {
7612 pr_err("%s: gpio_direction_output"
7613 "(%d, 1) failed\n", __func__,
7614 curr->gpio_data[n].no);
7615 goto free_gpios;
7616 }
7617 curr->gpio_data[n].is_enabled = 1;
7618 } else {
7619 /*
7620 * now free this GPIO which will put GPIO
7621 * in low power mode and will also put GPIO
7622 * in input mode
7623 */
7624 if (curr->gpio_data[n].always_on)
7625 continue;
7626 pr_debug("%s: disable: %s\n", __func__,
7627 curr->gpio_data[n].name);
7628 gpio_free(curr->gpio_data[n].no);
7629 curr->gpio_data[n].is_enabled = 0;
7630 }
7631 }
7632 curr->cfg_sts = enable;
7633 goto out;
7634
7635free_gpios:
7636 for (; n >= 0; n--)
7637 gpio_free(curr->gpio_data[n].no);
7638out:
7639 return rc;
7640}
7641
7642static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7643{
7644 int rc = 0;
7645 struct msm_sdcc_pin_cfg *curr;
7646 int n;
7647
7648 curr = &sdcc_pin_cfg_data[dev_id - 1];
7649 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7650 goto out;
7651
7652 if (enable) {
7653 /*
7654 * set up the normal driver strength and
7655 * pull config for pads
7656 */
7657 for (n = 0; n < curr->pad_drv_data_size; n++) {
7658 if (curr->sdio_lpm_gpio_cfg) {
7659 if (curr->pad_drv_on_data[n].drv ==
7660 TLMM_HDRV_SDC4_DATA)
7661 continue;
7662 }
7663 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7664 curr->pad_drv_on_data[n].drv_val);
7665 }
7666 for (n = 0; n < curr->pad_pull_data_size; n++) {
7667 if (curr->sdio_lpm_gpio_cfg) {
7668 if (curr->pad_pull_on_data[n].pull ==
7669 TLMM_PULL_SDC4_DATA)
7670 continue;
7671 }
7672 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7673 curr->pad_pull_on_data[n].pull_val);
7674 }
7675 } else {
7676 /* set the low power config for pads */
7677 for (n = 0; n < curr->pad_drv_data_size; n++) {
7678 if (curr->sdio_lpm_gpio_cfg) {
7679 if (curr->pad_drv_off_data[n].drv ==
7680 TLMM_HDRV_SDC4_DATA)
7681 continue;
7682 }
7683 msm_tlmm_set_hdrive(
7684 curr->pad_drv_off_data[n].drv,
7685 curr->pad_drv_off_data[n].drv_val);
7686 }
7687 for (n = 0; n < curr->pad_pull_data_size; n++) {
7688 if (curr->sdio_lpm_gpio_cfg) {
7689 if (curr->pad_pull_off_data[n].pull ==
7690 TLMM_PULL_SDC4_DATA)
7691 continue;
7692 }
7693 msm_tlmm_set_pull(
7694 curr->pad_pull_off_data[n].pull,
7695 curr->pad_pull_off_data[n].pull_val);
7696 }
7697 }
7698 curr->cfg_sts = enable;
7699out:
7700 return rc;
7701}
7702
7703struct sdcc_reg {
7704 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7705 const char *reg_name;
7706 /*
7707 * is set voltage supported for this regulator?
7708 * 0 = not supported, 1 = supported
7709 */
7710 unsigned char set_voltage_sup;
7711 /* voltage level to be set */
7712 unsigned int level;
7713 /* VDD/VCC/VCCQ voltage regulator handle */
7714 struct regulator *reg;
7715 /* is this regulator enabled? */
7716 bool enabled;
7717 /* is this regulator needs to be always on? */
7718 bool always_on;
7719 /* is operating power mode setting required for this regulator? */
7720 bool op_pwr_mode_sup;
7721 /* Load values for low power and high power mode */
7722 unsigned int lpm_uA;
7723 unsigned int hpm_uA;
7724};
Stepan Moskovchenko73b943b2011-10-31 22:43:00 -07007725/* all SDCC controllers require VDD/VCC voltage */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007726static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7727/* only SDCC1 requires VCCQ voltage */
7728static struct sdcc_reg sdcc_vccq_reg_data[1];
7729/* all SDCC controllers may require voting for VDD PAD voltage */
7730static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7731
7732struct sdcc_reg_data {
7733 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7734 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7735 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7736 unsigned char sts; /* regulator enable/disable status */
7737};
Stepan Moskovchenko73b943b2011-10-31 22:43:00 -07007738/* msm8x60 has 5 SDCC controllers */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007739static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7740
7741static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7742{
7743 int rc = 0;
7744
7745 /* Get the regulator handle */
7746 vreg->reg = regulator_get(NULL, vreg->reg_name);
7747 if (IS_ERR(vreg->reg)) {
7748 rc = PTR_ERR(vreg->reg);
7749 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7750 __func__, vreg->reg_name, rc);
7751 goto out;
7752 }
7753
7754 /* Set the voltage level if required */
7755 if (vreg->set_voltage_sup) {
7756 rc = regulator_set_voltage(vreg->reg, vreg->level,
7757 vreg->level);
7758 if (rc) {
7759 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7760 __func__, vreg->reg_name, rc);
7761 goto vreg_put;
7762 }
7763 }
7764 goto out;
7765
7766vreg_put:
7767 regulator_put(vreg->reg);
7768out:
7769 return rc;
7770}
7771
7772static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7773{
7774 regulator_put(vreg->reg);
7775}
7776
7777/* this init function should be called only once for each SDCC */
7778static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7779{
7780 int rc = 0;
7781 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7782 struct sdcc_reg_data *curr;
7783
7784 curr = &sdcc_vreg_data[dev_id - 1];
7785 curr_vdd_reg = curr->vdd_data;
7786 curr_vccq_reg = curr->vccq_data;
7787 curr_vddp_reg = curr->vddp_data;
7788
7789 if (init) {
7790 /*
7791 * get the regulator handle from voltage regulator framework
7792 * and then try to set the voltage level for the regulator
7793 */
7794 if (curr_vdd_reg) {
7795 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7796 if (rc)
7797 goto out;
7798 }
7799 if (curr_vccq_reg) {
7800 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
7801 if (rc)
7802 goto vdd_reg_deinit;
7803 }
7804 if (curr_vddp_reg) {
7805 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
7806 if (rc)
7807 goto vccq_reg_deinit;
7808 }
7809 goto out;
7810 } else
7811 /* deregister with all regulators from regulator framework */
7812 goto vddp_reg_deinit;
7813
7814vddp_reg_deinit:
7815 if (curr_vddp_reg)
7816 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
7817vccq_reg_deinit:
7818 if (curr_vccq_reg)
7819 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
7820vdd_reg_deinit:
7821 if (curr_vdd_reg)
7822 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
7823out:
7824 return rc;
7825}
7826
7827static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
7828{
7829 int rc;
7830
7831 if (!vreg->enabled) {
7832 rc = regulator_enable(vreg->reg);
7833 if (rc) {
7834 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
7835 __func__, vreg->reg_name, rc);
7836 goto out;
7837 }
7838 vreg->enabled = 1;
7839 }
7840
7841 /* Put always_on regulator in HPM (high power mode) */
7842 if (vreg->always_on && vreg->op_pwr_mode_sup) {
7843 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
7844 if (rc < 0) {
7845 pr_err("%s: reg=%s: HPM setting failed"
7846 " hpm_uA=%d, rc=%d\n",
7847 __func__, vreg->reg_name,
7848 vreg->hpm_uA, rc);
7849 goto vreg_disable;
7850 }
7851 rc = 0;
7852 }
7853 goto out;
7854
7855vreg_disable:
7856 regulator_disable(vreg->reg);
7857 vreg->enabled = 0;
7858out:
7859 return rc;
7860}
7861
7862static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
7863{
7864 int rc;
7865
7866 /* Never disable always_on regulator */
7867 if (!vreg->always_on) {
7868 rc = regulator_disable(vreg->reg);
7869 if (rc) {
7870 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
7871 __func__, vreg->reg_name, rc);
7872 goto out;
7873 }
7874 vreg->enabled = 0;
7875 }
7876
7877 /* Put always_on regulator in LPM (low power mode) */
7878 if (vreg->always_on && vreg->op_pwr_mode_sup) {
7879 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
7880 if (rc < 0) {
7881 pr_err("%s: reg=%s: LPM setting failed"
7882 " lpm_uA=%d, rc=%d\n",
7883 __func__,
7884 vreg->reg_name,
7885 vreg->lpm_uA, rc);
7886 goto out;
7887 }
7888 rc = 0;
7889 }
7890
7891out:
7892 return rc;
7893}
7894
7895static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
7896{
7897 int rc = 0;
7898 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7899 struct sdcc_reg_data *curr;
7900
7901 curr = &sdcc_vreg_data[dev_id - 1];
7902 curr_vdd_reg = curr->vdd_data;
7903 curr_vccq_reg = curr->vccq_data;
7904 curr_vddp_reg = curr->vddp_data;
7905
7906 /* check if regulators are initialized or not? */
7907 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
7908 (curr_vccq_reg && !curr_vccq_reg->reg) ||
7909 (curr_vddp_reg && !curr_vddp_reg->reg)) {
7910 /* initialize voltage regulators required for this SDCC */
7911 rc = msm_sdcc_vreg_init(dev_id, 1);
7912 if (rc) {
7913 pr_err("%s: regulator init failed = %d\n",
7914 __func__, rc);
7915 goto out;
7916 }
7917 }
7918
7919 if (curr->sts == enable)
7920 goto out;
7921
7922 if (curr_vdd_reg) {
7923 if (enable)
7924 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
7925 else
7926 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
7927 if (rc)
7928 goto out;
7929 }
7930
7931 if (curr_vccq_reg) {
7932 if (enable)
7933 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
7934 else
7935 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
7936 if (rc)
7937 goto out;
7938 }
7939
7940 if (curr_vddp_reg) {
7941 if (enable)
7942 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
7943 else
7944 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
7945 if (rc)
7946 goto out;
7947 }
7948 curr->sts = enable;
7949
7950out:
7951 return rc;
7952}
7953
7954static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
7955{
7956 u32 rc_pin_cfg = 0;
7957 u32 rc_vreg_cfg = 0;
7958 u32 rc = 0;
7959 struct platform_device *pdev;
7960 struct msm_sdcc_pin_cfg *curr_pin_cfg;
7961
7962 pdev = container_of(dv, struct platform_device, dev);
7963
7964 /* setup gpio/pad */
7965 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
7966 if (curr_pin_cfg->cfg_sts == !!vdd)
7967 goto setup_vreg;
7968
7969 if (curr_pin_cfg->is_gpio)
7970 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
7971 else
7972 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
7973
7974setup_vreg:
7975 /* setup voltage regulators */
7976 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
7977
7978 if (rc_pin_cfg || rc_vreg_cfg)
7979 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
7980
7981 return rc;
7982}
7983
7984static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
7985{
7986 struct msm_sdcc_pin_cfg *curr_pin_cfg;
7987 struct platform_device *pdev;
7988
7989 pdev = container_of(dv, struct platform_device, dev);
7990 /* setup gpio/pad */
7991 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
7992
7993 if (curr_pin_cfg->cfg_sts == active)
7994 return;
7995
7996 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
7997 if (curr_pin_cfg->is_gpio)
7998 msm_sdcc_setup_gpio(pdev->id, active);
7999 else
8000 msm_sdcc_setup_pad(pdev->id, active);
8001 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8002}
8003
8004static int msm_sdc3_get_wpswitch(struct device *dev)
8005{
8006 struct platform_device *pdev;
8007 int status;
8008 pdev = container_of(dev, struct platform_device, dev);
8009
8010 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8011 if (status) {
8012 pr_err("%s:Failed to request GPIO %d\n",
8013 __func__, GPIO_SDC_WP);
8014 } else {
8015 status = gpio_direction_input(GPIO_SDC_WP);
8016 if (!status) {
8017 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8018 pr_info("%s: WP Status for Slot %d = %d\n",
8019 __func__, pdev->id, status);
8020 }
8021 gpio_free(GPIO_SDC_WP);
8022 }
8023 return status;
8024}
8025
8026#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8027int sdc5_register_status_notify(void (*callback)(int, void *),
8028 void *dev_id)
8029{
8030 sdc5_status_notify_cb = callback;
8031 sdc5_status_notify_cb_devid = dev_id;
8032 return 0;
8033}
8034#endif
8035
8036#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8037int sdc2_register_status_notify(void (*callback)(int, void *),
8038 void *dev_id)
8039{
8040 sdc2_status_notify_cb = callback;
8041 sdc2_status_notify_cb_devid = dev_id;
8042 return 0;
8043}
8044#endif
8045
8046/* Interrupt handler for SDC2 and SDC5 detection
8047 * This function uses dual-edge interrputs settings in order
8048 * to get SDIO detection when the GPIO is rising and SDIO removal
8049 * when the GPIO is falling */
8050static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8051{
8052 int status;
8053
8054 if (!machine_is_msm8x60_fusion() &&
8055 !machine_is_msm8x60_fusn_ffa())
8056 return IRQ_NONE;
8057
8058 status = gpio_get_value(MDM2AP_SYNC);
8059 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8060 __func__, status);
8061
8062#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8063 if (sdc2_status_notify_cb) {
8064 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8065 sdc2_status_notify_cb(status,
8066 sdc2_status_notify_cb_devid);
8067 }
8068#endif
8069
8070#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8071 if (sdc5_status_notify_cb) {
8072 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8073 sdc5_status_notify_cb(status,
8074 sdc5_status_notify_cb_devid);
8075 }
8076#endif
8077 return IRQ_HANDLED;
8078}
8079
8080static int msm8x60_multi_sdio_init(void)
8081{
8082 int ret, irq_num;
8083
8084 if (!machine_is_msm8x60_fusion() &&
8085 !machine_is_msm8x60_fusn_ffa())
8086 return 0;
8087
8088 ret = msm_gpiomux_get(MDM2AP_SYNC);
8089 if (ret) {
8090 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8091 __func__, MDM2AP_SYNC, ret);
8092 return ret;
8093 }
8094
8095 irq_num = gpio_to_irq(MDM2AP_SYNC);
8096
8097 ret = request_irq(irq_num,
8098 msm8x60_multi_sdio_slot_status_irq,
8099 IRQ_TYPE_EDGE_BOTH,
8100 "sdio_multidetection", NULL);
8101
8102 if (ret) {
8103 pr_err("%s:Failed to request irq, ret=%d\n",
8104 __func__, ret);
8105 return ret;
8106 }
8107
8108 return ret;
8109}
8110
8111#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8112#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8113static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8114{
8115 int status;
8116
8117 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8118 , "SD_HW_Detect");
8119 if (status) {
8120 pr_err("%s:Failed to request GPIO %d\n", __func__,
8121 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8122 } else {
8123 status = gpio_direction_input(
8124 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8125 if (!status)
8126 status = !(gpio_get_value_cansleep(
8127 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8128 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8129 }
8130 return (unsigned int) status;
8131}
8132#endif
8133#endif
8134
8135#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8136static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8137{
8138 struct platform_device *pdev;
8139 enum msm_mpm_pin pin;
8140 int ret = 0;
8141
8142 pdev = container_of(dev, struct platform_device, dev);
8143
8144 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8145 if (pdev->id == 4)
8146 pin = MSM_MPM_PIN_SDC4_DAT1;
8147 else
8148 return -EINVAL;
8149
8150 switch (mode) {
8151 case SDC_DAT1_DISABLE:
8152 ret = msm_mpm_enable_pin(pin, 0);
8153 break;
8154 case SDC_DAT1_ENABLE:
8155 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8156 ret = msm_mpm_enable_pin(pin, 1);
8157 break;
8158 case SDC_DAT1_ENWAKE:
8159 ret = msm_mpm_set_pin_wake(pin, 1);
8160 break;
8161 case SDC_DAT1_DISWAKE:
8162 ret = msm_mpm_set_pin_wake(pin, 0);
8163 break;
8164 default:
8165 ret = -EINVAL;
8166 break;
8167 }
8168 return ret;
8169}
8170#endif
8171#endif
8172
8173#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8174static struct mmc_platform_data msm8x60_sdc1_data = {
8175 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8176 .translate_vdd = msm_sdcc_setup_power,
8177#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8178 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8179#else
8180 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8181#endif
8182 .msmsdcc_fmin = 400000,
8183 .msmsdcc_fmid = 24000000,
8184 .msmsdcc_fmax = 48000000,
8185 .nonremovable = 1,
8186 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008187};
8188#endif
8189
8190#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8191static struct mmc_platform_data msm8x60_sdc2_data = {
8192 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8193 .translate_vdd = msm_sdcc_setup_power,
8194 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8195 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8196 .msmsdcc_fmin = 400000,
8197 .msmsdcc_fmid = 24000000,
8198 .msmsdcc_fmax = 48000000,
8199 .nonremovable = 0,
8200 .pclk_src_dfab = 1,
8201 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008202#ifdef CONFIG_MSM_SDIO_AL
8203 .is_sdio_al_client = 1,
8204#endif
8205};
8206#endif
8207
8208#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8209static struct mmc_platform_data msm8x60_sdc3_data = {
8210 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8211 .translate_vdd = msm_sdcc_setup_power,
8212 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8213 .wpswitch = msm_sdc3_get_wpswitch,
8214#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8215 .status = msm8x60_sdcc_slot_status,
8216 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8217 PMIC_GPIO_SDC3_DET - 1),
8218 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8219#endif
8220 .msmsdcc_fmin = 400000,
8221 .msmsdcc_fmid = 24000000,
8222 .msmsdcc_fmax = 48000000,
8223 .nonremovable = 0,
8224 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008225};
8226#endif
8227
8228#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8229static struct mmc_platform_data msm8x60_sdc4_data = {
8230 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8231 .translate_vdd = msm_sdcc_setup_power,
8232 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8233 .msmsdcc_fmin = 400000,
8234 .msmsdcc_fmid = 24000000,
8235 .msmsdcc_fmax = 48000000,
8236 .nonremovable = 0,
8237 .pclk_src_dfab = 1,
8238 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008239};
8240#endif
8241
8242#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8243static struct mmc_platform_data msm8x60_sdc5_data = {
8244 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8245 .translate_vdd = msm_sdcc_setup_power,
8246 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8247 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8248 .msmsdcc_fmin = 400000,
8249 .msmsdcc_fmid = 24000000,
8250 .msmsdcc_fmax = 48000000,
8251 .nonremovable = 0,
8252 .pclk_src_dfab = 1,
8253 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008254#ifdef CONFIG_MSM_SDIO_AL
8255 .is_sdio_al_client = 1,
8256#endif
8257};
8258#endif
8259
8260static void __init msm8x60_init_mmc(void)
8261{
8262#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8263 /* SDCC1 : eMMC card connected */
8264 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8265 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8266 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8267 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308268 sdcc_vreg_data[0].vdd_data->always_on = 1;
8269 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8270 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8271 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008272
8273 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8274 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8275 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8276 sdcc_vreg_data[0].vccq_data->always_on = 1;
8277
8278 msm_add_sdcc(1, &msm8x60_sdc1_data);
8279#endif
8280#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8281 /*
8282 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8283 * and no card is connected on 8660 SURF/FFA/FLUID.
8284 */
8285 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8286 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8287 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8288 sdcc_vreg_data[1].vdd_data->level = 1800000;
8289
8290 sdcc_vreg_data[1].vccq_data = NULL;
8291
8292 if (machine_is_msm8x60_fusion())
8293 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8294 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8295#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8296 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8297 msm_sdcc_setup_gpio(2, 1);
8298#endif
8299 msm_add_sdcc(2, &msm8x60_sdc2_data);
8300 }
8301#endif
8302#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8303 /* SDCC3 : External card slot connected */
8304 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8305 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8306 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8307 sdcc_vreg_data[2].vdd_data->level = 2850000;
8308 sdcc_vreg_data[2].vdd_data->always_on = 1;
8309 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8310 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8311 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8312
8313 sdcc_vreg_data[2].vccq_data = NULL;
8314
8315 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8316 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8317 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8318 sdcc_vreg_data[2].vddp_data->level = 2850000;
8319 sdcc_vreg_data[2].vddp_data->always_on = 1;
8320 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8321 /* Sleep current required is ~300 uA. But min. RPM
8322 * vote can be in terms of mA (min. 1 mA).
8323 * So let's vote for 2 mA during sleep.
8324 */
8325 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8326 /* Max. Active current required is 16 mA */
8327 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8328
8329 if (machine_is_msm8x60_fluid())
8330 msm8x60_sdc3_data.wpswitch = NULL;
8331 msm_add_sdcc(3, &msm8x60_sdc3_data);
8332#endif
8333#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8334 /* SDCC4 : WLAN WCN1314 chip is connected */
8335 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8336 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8337 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8338 sdcc_vreg_data[3].vdd_data->level = 1800000;
8339
8340 sdcc_vreg_data[3].vccq_data = NULL;
8341
8342 msm_add_sdcc(4, &msm8x60_sdc4_data);
8343#endif
8344#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8345 /*
8346 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8347 * and no card is connected on 8660 SURF/FFA/FLUID.
8348 */
8349 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8350 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8351 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8352 sdcc_vreg_data[4].vdd_data->level = 1800000;
8353
8354 sdcc_vreg_data[4].vccq_data = NULL;
8355
8356 if (machine_is_msm8x60_fusion())
8357 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8358 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8359#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8360 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8361 msm_sdcc_setup_gpio(5, 1);
8362#endif
8363 msm_add_sdcc(5, &msm8x60_sdc5_data);
8364 }
8365#endif
8366}
8367
8368#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8369static inline void display_common_power(int on) {}
8370#else
8371
8372#define _GET_REGULATOR(var, name) do { \
8373 if (var == NULL) { \
8374 var = regulator_get(NULL, name); \
8375 if (IS_ERR(var)) { \
8376 pr_err("'%s' regulator not found, rc=%ld\n", \
8377 name, PTR_ERR(var)); \
8378 var = NULL; \
8379 } \
8380 } \
8381} while (0)
8382
8383static int dsub_regulator(int on)
8384{
8385 static struct regulator *dsub_reg;
8386 static struct regulator *mpp0_reg;
8387 static int dsub_reg_enabled;
8388 int rc = 0;
8389
8390 _GET_REGULATOR(dsub_reg, "8901_l3");
8391 if (IS_ERR(dsub_reg)) {
8392 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8393 __func__, PTR_ERR(dsub_reg));
8394 return PTR_ERR(dsub_reg);
8395 }
8396
8397 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8398 if (IS_ERR(mpp0_reg)) {
8399 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8400 __func__, PTR_ERR(mpp0_reg));
8401 return PTR_ERR(mpp0_reg);
8402 }
8403
8404 if (on && !dsub_reg_enabled) {
8405 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8406 if (rc) {
8407 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8408 " err=%d", __func__, rc);
8409 goto dsub_regulator_err;
8410 }
8411 rc = regulator_enable(dsub_reg);
8412 if (rc) {
8413 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8414 " err=%d", __func__, rc);
8415 goto dsub_regulator_err;
8416 }
8417 rc = regulator_enable(mpp0_reg);
8418 if (rc) {
8419 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8420 " err=%d", __func__, rc);
8421 goto dsub_regulator_err;
8422 }
8423 dsub_reg_enabled = 1;
8424 } else if (!on && dsub_reg_enabled) {
8425 rc = regulator_disable(dsub_reg);
8426 if (rc)
8427 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8428 " err=%d", __func__, rc);
8429 rc = regulator_disable(mpp0_reg);
8430 if (rc)
8431 printk(KERN_WARNING "%s: failed to disable reg "
8432 "8901_mpp0 err=%d", __func__, rc);
8433 dsub_reg_enabled = 0;
8434 }
8435
8436 return rc;
8437
8438dsub_regulator_err:
8439 regulator_put(mpp0_reg);
8440 regulator_put(dsub_reg);
8441 return rc;
8442}
8443
8444static int display_power_on;
8445static void setup_display_power(void)
8446{
8447 if (display_power_on)
8448 if (lcdc_vga_enabled) {
8449 dsub_regulator(1);
8450 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8451 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8452 if (machine_is_msm8x60_ffa() ||
8453 machine_is_msm8x60_fusn_ffa())
8454 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8455 } else {
8456 dsub_regulator(0);
8457 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8458 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8459 if (machine_is_msm8x60_ffa() ||
8460 machine_is_msm8x60_fusn_ffa())
8461 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8462 }
8463 else {
8464 dsub_regulator(0);
8465 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8466 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8467 /* BACKLIGHT */
8468 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8469 /* LVDS */
8470 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8471 }
8472}
8473
8474#define _GET_REGULATOR(var, name) do { \
8475 if (var == NULL) { \
8476 var = regulator_get(NULL, name); \
8477 if (IS_ERR(var)) { \
8478 pr_err("'%s' regulator not found, rc=%ld\n", \
8479 name, PTR_ERR(var)); \
8480 var = NULL; \
8481 } \
8482 } \
8483} while (0)
8484
8485#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8486
8487static void display_common_power(int on)
8488{
8489 int rc;
8490 static struct regulator *display_reg;
8491
8492 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8493 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8494 if (on) {
8495 /* LVDS */
8496 _GET_REGULATOR(display_reg, "8901_l2");
8497 if (!display_reg)
8498 return;
8499 rc = regulator_set_voltage(display_reg,
8500 3300000, 3300000);
8501 if (rc)
8502 goto out;
8503 rc = regulator_enable(display_reg);
8504 if (rc)
8505 goto out;
8506 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8507 "LVDS_STDN_OUT_N");
8508 if (rc) {
8509 printk(KERN_ERR "%s: LVDS gpio %d request"
8510 "failed\n", __func__,
8511 GPIO_LVDS_SHUTDOWN_N);
8512 goto out2;
8513 }
8514
8515 /* BACKLIGHT */
8516 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8517 if (rc) {
8518 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8519 "failed\n", __func__,
8520 GPIO_BACKLIGHT_EN);
8521 goto out3;
8522 }
8523
8524 if (machine_is_msm8x60_ffa() ||
8525 machine_is_msm8x60_fusn_ffa()) {
8526 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8527 "DONGLE_PWR_EN");
8528 if (rc) {
8529 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8530 " %d request failed\n", __func__,
8531 GPIO_DONGLE_PWR_EN);
8532 goto out4;
8533 }
8534 }
8535
8536 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8537 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8538 if (machine_is_msm8x60_ffa() ||
8539 machine_is_msm8x60_fusn_ffa())
8540 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8541 mdelay(20);
8542 display_power_on = 1;
8543 setup_display_power();
8544 } else {
8545 if (display_power_on) {
8546 display_power_on = 0;
8547 setup_display_power();
8548 mdelay(20);
8549 if (machine_is_msm8x60_ffa() ||
8550 machine_is_msm8x60_fusn_ffa())
8551 gpio_free(GPIO_DONGLE_PWR_EN);
8552 goto out4;
8553 }
8554 }
8555 }
8556#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8557 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8558 else if (machine_is_msm8x60_fluid()) {
8559 static struct regulator *fluid_reg;
8560 static struct regulator *fluid_reg2;
8561
8562 if (on) {
8563 _GET_REGULATOR(fluid_reg, "8901_l2");
8564 if (!fluid_reg)
8565 return;
8566 _GET_REGULATOR(fluid_reg2, "8058_s3");
8567 if (!fluid_reg2) {
8568 regulator_put(fluid_reg);
8569 return;
8570 }
8571 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8572 if (rc) {
8573 regulator_put(fluid_reg2);
8574 regulator_put(fluid_reg);
8575 return;
8576 }
8577 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8578 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8579 regulator_enable(fluid_reg);
8580 regulator_enable(fluid_reg2);
8581 msleep(20);
8582 gpio_direction_output(GPIO_RESX_N, 0);
8583 udelay(10);
8584 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8585 display_power_on = 1;
8586 setup_display_power();
8587 } else {
8588 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8589 gpio_free(GPIO_RESX_N);
8590 msleep(20);
8591 regulator_disable(fluid_reg2);
8592 regulator_disable(fluid_reg);
8593 regulator_put(fluid_reg2);
8594 regulator_put(fluid_reg);
8595 display_power_on = 0;
8596 setup_display_power();
8597 fluid_reg = NULL;
8598 fluid_reg2 = NULL;
8599 }
8600 }
8601#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008602#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8603 else if (machine_is_msm8x60_dragon()) {
8604 static struct regulator *dragon_reg;
8605 static struct regulator *dragon_reg2;
8606
8607 if (on) {
8608 _GET_REGULATOR(dragon_reg, "8901_l2");
8609 if (!dragon_reg)
8610 return;
8611 _GET_REGULATOR(dragon_reg2, "8058_l16");
8612 if (!dragon_reg2) {
8613 regulator_put(dragon_reg);
8614 dragon_reg = NULL;
8615 return;
8616 }
8617
8618 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8619 if (rc) {
8620 pr_err("%s: gpio %d request failed with rc=%d\n",
8621 __func__, GPIO_NT35582_BL_EN, rc);
8622 regulator_put(dragon_reg);
8623 regulator_put(dragon_reg2);
8624 dragon_reg = NULL;
8625 dragon_reg2 = NULL;
8626 return;
8627 }
8628
8629 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8630 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8631 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8632 pr_err("%s: config gpio '%d' failed!\n",
8633 __func__, GPIO_NT35582_RESET);
8634 gpio_free(GPIO_NT35582_BL_EN);
8635 regulator_put(dragon_reg);
8636 regulator_put(dragon_reg2);
8637 dragon_reg = NULL;
8638 dragon_reg2 = NULL;
8639 return;
8640 }
8641
8642 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8643 if (rc) {
8644 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8645 __func__, GPIO_NT35582_RESET, rc);
8646 gpio_free(GPIO_NT35582_BL_EN);
8647 regulator_put(dragon_reg);
8648 regulator_put(dragon_reg2);
8649 dragon_reg = NULL;
8650 dragon_reg2 = NULL;
8651 return;
8652 }
8653
8654 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8655 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8656 regulator_enable(dragon_reg);
8657 regulator_enable(dragon_reg2);
8658 msleep(20);
8659
8660 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8661 msleep(20);
8662 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8663 msleep(20);
8664 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8665 msleep(50);
8666
8667 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8668
8669 display_power_on = 1;
8670 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8671 gpio_free(GPIO_NT35582_RESET);
8672 gpio_free(GPIO_NT35582_BL_EN);
8673 regulator_disable(dragon_reg2);
8674 regulator_disable(dragon_reg);
8675 regulator_put(dragon_reg2);
8676 regulator_put(dragon_reg);
8677 display_power_on = 0;
8678 dragon_reg = NULL;
8679 dragon_reg2 = NULL;
8680 }
8681 }
8682#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008683 return;
8684
8685out4:
8686 gpio_free(GPIO_BACKLIGHT_EN);
8687out3:
8688 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8689out2:
8690 regulator_disable(display_reg);
8691out:
8692 regulator_put(display_reg);
8693 display_reg = NULL;
8694}
8695#undef _GET_REGULATOR
8696#endif
8697
8698static int mipi_dsi_panel_power(int on);
8699
8700#define LCDC_NUM_GPIO 28
8701#define LCDC_GPIO_START 0
8702
8703static void lcdc_samsung_panel_power(int on)
8704{
8705 int n, ret = 0;
8706
8707 display_common_power(on);
8708
8709 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8710 if (on) {
8711 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8712 if (unlikely(ret)) {
8713 pr_err("%s not able to get gpio\n", __func__);
8714 break;
8715 }
8716 } else
8717 gpio_free(LCDC_GPIO_START + n);
8718 }
8719
8720 if (ret) {
8721 for (n--; n >= 0; n--)
8722 gpio_free(LCDC_GPIO_START + n);
8723 }
8724
8725 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8726}
8727
8728#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8729#define _GET_REGULATOR(var, name) do { \
8730 var = regulator_get(NULL, name); \
8731 if (IS_ERR(var)) { \
8732 pr_err("'%s' regulator not found, rc=%ld\n", \
8733 name, IS_ERR(var)); \
8734 var = NULL; \
8735 return -ENODEV; \
8736 } \
8737} while (0)
8738
8739static int hdmi_enable_5v(int on)
8740{
8741 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8742 static struct regulator *reg_8901_mpp0; /* External 5V */
8743 static int prev_on;
8744 int rc;
8745
8746 if (on == prev_on)
8747 return 0;
8748
8749 if (!reg_8901_hdmi_mvs)
8750 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8751 if (!reg_8901_mpp0)
8752 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8753
8754 if (on) {
8755 rc = regulator_enable(reg_8901_mpp0);
8756 if (rc) {
8757 pr_err("'%s' regulator enable failed, rc=%d\n",
8758 "reg_8901_mpp0", rc);
8759 return rc;
8760 }
8761 rc = regulator_enable(reg_8901_hdmi_mvs);
8762 if (rc) {
8763 pr_err("'%s' regulator enable failed, rc=%d\n",
8764 "8901_hdmi_mvs", rc);
8765 return rc;
8766 }
8767 pr_info("%s(on): success\n", __func__);
8768 } else {
8769 rc = regulator_disable(reg_8901_hdmi_mvs);
8770 if (rc)
8771 pr_warning("'%s' regulator disable failed, rc=%d\n",
8772 "8901_hdmi_mvs", rc);
8773 rc = regulator_disable(reg_8901_mpp0);
8774 if (rc)
8775 pr_warning("'%s' regulator disable failed, rc=%d\n",
8776 "reg_8901_mpp0", rc);
8777 pr_info("%s(off): success\n", __func__);
8778 }
8779
8780 prev_on = on;
8781
8782 return 0;
8783}
8784
8785static int hdmi_core_power(int on, int show)
8786{
8787 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8788 static int prev_on;
8789 int rc;
8790
8791 if (on == prev_on)
8792 return 0;
8793
8794 if (!reg_8058_l16)
8795 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8796
8797 if (on) {
8798 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8799 if (!rc)
8800 rc = regulator_enable(reg_8058_l16);
8801 if (rc) {
8802 pr_err("'%s' regulator enable failed, rc=%d\n",
8803 "8058_l16", rc);
8804 return rc;
8805 }
8806 rc = gpio_request(170, "HDMI_DDC_CLK");
8807 if (rc) {
8808 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8809 "HDMI_DDC_CLK", 170, rc);
8810 goto error1;
8811 }
8812 rc = gpio_request(171, "HDMI_DDC_DATA");
8813 if (rc) {
8814 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8815 "HDMI_DDC_DATA", 171, rc);
8816 goto error2;
8817 }
8818 rc = gpio_request(172, "HDMI_HPD");
8819 if (rc) {
8820 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8821 "HDMI_HPD", 172, rc);
8822 goto error3;
8823 }
8824 pr_info("%s(on): success\n", __func__);
8825 } else {
8826 gpio_free(170);
8827 gpio_free(171);
8828 gpio_free(172);
8829 rc = regulator_disable(reg_8058_l16);
8830 if (rc)
8831 pr_warning("'%s' regulator disable failed, rc=%d\n",
8832 "8058_l16", rc);
8833 pr_info("%s(off): success\n", __func__);
8834 }
8835
8836 prev_on = on;
8837
8838 return 0;
8839
8840error3:
8841 gpio_free(171);
8842error2:
8843 gpio_free(170);
8844error1:
8845 regulator_disable(reg_8058_l16);
8846 return rc;
8847}
8848
8849static int hdmi_cec_power(int on)
8850{
8851 static struct regulator *reg_8901_l3; /* HDMI_CEC */
8852 static int prev_on;
8853 int rc;
8854
8855 if (on == prev_on)
8856 return 0;
8857
8858 if (!reg_8901_l3)
8859 _GET_REGULATOR(reg_8901_l3, "8901_l3");
8860
8861 if (on) {
8862 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
8863 if (!rc)
8864 rc = regulator_enable(reg_8901_l3);
8865 if (rc) {
8866 pr_err("'%s' regulator enable failed, rc=%d\n",
8867 "8901_l3", rc);
8868 return rc;
8869 }
8870 rc = gpio_request(169, "HDMI_CEC_VAR");
8871 if (rc) {
8872 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8873 "HDMI_CEC_VAR", 169, rc);
8874 goto error;
8875 }
8876 pr_info("%s(on): success\n", __func__);
8877 } else {
8878 gpio_free(169);
8879 rc = regulator_disable(reg_8901_l3);
8880 if (rc)
8881 pr_warning("'%s' regulator disable failed, rc=%d\n",
8882 "8901_l3", rc);
8883 pr_info("%s(off): success\n", __func__);
8884 }
8885
8886 prev_on = on;
8887
8888 return 0;
8889error:
8890 regulator_disable(reg_8901_l3);
8891 return rc;
8892}
8893
8894#undef _GET_REGULATOR
8895
8896#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
8897
8898static int lcdc_panel_power(int on)
8899{
8900 int flag_on = !!on;
8901 static int lcdc_power_save_on;
8902
8903 if (lcdc_power_save_on == flag_on)
8904 return 0;
8905
8906 lcdc_power_save_on = flag_on;
8907
8908 lcdc_samsung_panel_power(on);
8909
8910 return 0;
8911}
8912
8913#ifdef CONFIG_MSM_BUS_SCALING
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008914static struct msm_bus_vectors mdp_init_vectors[] = {
8915 /* For now, 0th array entry is reserved.
8916 * Please leave 0 as is and don't use it
8917 */
8918 {
8919 .src = MSM_BUS_MASTER_MDP_PORT0,
8920 .dst = MSM_BUS_SLAVE_SMI,
8921 .ab = 0,
8922 .ib = 0,
8923 },
8924 /* Master and slaves can be from different fabrics */
8925 {
8926 .src = MSM_BUS_MASTER_MDP_PORT0,
8927 .dst = MSM_BUS_SLAVE_EBI_CH0,
8928 .ab = 0,
8929 .ib = 0,
8930 },
8931};
8932
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07008933#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
8934static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
8935 /* If HDMI is used as primary */
8936 {
8937 .src = MSM_BUS_MASTER_MDP_PORT0,
8938 .dst = MSM_BUS_SLAVE_SMI,
8939 .ab = 2000000000,
8940 .ib = 2000000000,
8941 },
8942 /* Master and slaves can be from different fabrics */
8943 {
8944 .src = MSM_BUS_MASTER_MDP_PORT0,
8945 .dst = MSM_BUS_SLAVE_EBI_CH0,
8946 .ab = 2000000000,
8947 .ib = 2000000000,
8948 },
8949};
8950
8951static struct msm_bus_paths mdp_bus_scale_usecases[] = {
8952 {
8953 ARRAY_SIZE(mdp_init_vectors),
8954 mdp_init_vectors,
8955 },
8956 {
8957 ARRAY_SIZE(hdmi_as_primary_vectors),
8958 hdmi_as_primary_vectors,
8959 },
8960 {
8961 ARRAY_SIZE(hdmi_as_primary_vectors),
8962 hdmi_as_primary_vectors,
8963 },
8964 {
8965 ARRAY_SIZE(hdmi_as_primary_vectors),
8966 hdmi_as_primary_vectors,
8967 },
8968 {
8969 ARRAY_SIZE(hdmi_as_primary_vectors),
8970 hdmi_as_primary_vectors,
8971 },
8972 {
8973 ARRAY_SIZE(hdmi_as_primary_vectors),
8974 hdmi_as_primary_vectors,
8975 },
8976};
8977#else
8978#ifdef CONFIG_FB_MSM_LCDC_DSUB
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008979static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
8980 /* Default case static display/UI/2d/3d if FB SMI */
8981 {
8982 .src = MSM_BUS_MASTER_MDP_PORT0,
8983 .dst = MSM_BUS_SLAVE_SMI,
8984 .ab = 388800000,
8985 .ib = 486000000,
8986 },
8987 /* Master and slaves can be from different fabrics */
8988 {
8989 .src = MSM_BUS_MASTER_MDP_PORT0,
8990 .dst = MSM_BUS_SLAVE_EBI_CH0,
8991 .ab = 0,
8992 .ib = 0,
8993 },
8994};
8995
8996static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
8997 /* Default case static display/UI/2d/3d if FB SMI */
8998 {
8999 .src = MSM_BUS_MASTER_MDP_PORT0,
9000 .dst = MSM_BUS_SLAVE_SMI,
9001 .ab = 0,
9002 .ib = 0,
9003 },
9004 /* Master and slaves can be from different fabrics */
9005 {
9006 .src = MSM_BUS_MASTER_MDP_PORT0,
9007 .dst = MSM_BUS_SLAVE_EBI_CH0,
9008 .ab = 388800000,
9009 .ib = 486000000 * 2,
9010 },
9011};
9012static struct msm_bus_vectors mdp_vga_vectors[] = {
9013 /* VGA and less video */
9014 {
9015 .src = MSM_BUS_MASTER_MDP_PORT0,
9016 .dst = MSM_BUS_SLAVE_SMI,
9017 .ab = 458092800,
9018 .ib = 572616000,
9019 },
9020 {
9021 .src = MSM_BUS_MASTER_MDP_PORT0,
9022 .dst = MSM_BUS_SLAVE_EBI_CH0,
9023 .ab = 458092800,
9024 .ib = 572616000 * 2,
9025 },
9026};
9027static struct msm_bus_vectors mdp_720p_vectors[] = {
9028 /* 720p and less video */
9029 {
9030 .src = MSM_BUS_MASTER_MDP_PORT0,
9031 .dst = MSM_BUS_SLAVE_SMI,
9032 .ab = 471744000,
9033 .ib = 589680000,
9034 },
9035 /* Master and slaves can be from different fabrics */
9036 {
9037 .src = MSM_BUS_MASTER_MDP_PORT0,
9038 .dst = MSM_BUS_SLAVE_EBI_CH0,
9039 .ab = 471744000,
9040 .ib = 589680000 * 2,
9041 },
9042};
9043
9044static struct msm_bus_vectors mdp_1080p_vectors[] = {
9045 /* 1080p and less video */
9046 {
9047 .src = MSM_BUS_MASTER_MDP_PORT0,
9048 .dst = MSM_BUS_SLAVE_SMI,
9049 .ab = 575424000,
9050 .ib = 719280000,
9051 },
9052 /* Master and slaves can be from different fabrics */
9053 {
9054 .src = MSM_BUS_MASTER_MDP_PORT0,
9055 .dst = MSM_BUS_SLAVE_EBI_CH0,
9056 .ab = 575424000,
9057 .ib = 719280000 * 2,
9058 },
9059};
9060
9061#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009062static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9063 /* Default case static display/UI/2d/3d if FB SMI */
9064 {
9065 .src = MSM_BUS_MASTER_MDP_PORT0,
9066 .dst = MSM_BUS_SLAVE_SMI,
9067 .ab = 175110000,
9068 .ib = 218887500,
9069 },
9070 /* Master and slaves can be from different fabrics */
9071 {
9072 .src = MSM_BUS_MASTER_MDP_PORT0,
9073 .dst = MSM_BUS_SLAVE_EBI_CH0,
9074 .ab = 0,
9075 .ib = 0,
9076 },
9077};
9078
9079static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9080 /* Default case static display/UI/2d/3d if FB SMI */
9081 {
9082 .src = MSM_BUS_MASTER_MDP_PORT0,
9083 .dst = MSM_BUS_SLAVE_SMI,
9084 .ab = 0,
9085 .ib = 0,
9086 },
9087 /* Master and slaves can be from different fabrics */
9088 {
9089 .src = MSM_BUS_MASTER_MDP_PORT0,
9090 .dst = MSM_BUS_SLAVE_EBI_CH0,
9091 .ab = 216000000,
9092 .ib = 270000000 * 2,
9093 },
9094};
9095static struct msm_bus_vectors mdp_vga_vectors[] = {
9096 /* VGA and less video */
9097 {
9098 .src = MSM_BUS_MASTER_MDP_PORT0,
9099 .dst = MSM_BUS_SLAVE_SMI,
9100 .ab = 216000000,
9101 .ib = 270000000,
9102 },
9103 {
9104 .src = MSM_BUS_MASTER_MDP_PORT0,
9105 .dst = MSM_BUS_SLAVE_EBI_CH0,
9106 .ab = 216000000,
9107 .ib = 270000000 * 2,
9108 },
9109};
9110
9111static struct msm_bus_vectors mdp_720p_vectors[] = {
9112 /* 720p and less video */
9113 {
9114 .src = MSM_BUS_MASTER_MDP_PORT0,
9115 .dst = MSM_BUS_SLAVE_SMI,
9116 .ab = 230400000,
9117 .ib = 288000000,
9118 },
9119 /* Master and slaves can be from different fabrics */
9120 {
9121 .src = MSM_BUS_MASTER_MDP_PORT0,
9122 .dst = MSM_BUS_SLAVE_EBI_CH0,
9123 .ab = 230400000,
9124 .ib = 288000000 * 2,
9125 },
9126};
9127
9128static struct msm_bus_vectors mdp_1080p_vectors[] = {
9129 /* 1080p and less video */
9130 {
9131 .src = MSM_BUS_MASTER_MDP_PORT0,
9132 .dst = MSM_BUS_SLAVE_SMI,
9133 .ab = 334080000,
9134 .ib = 417600000,
9135 },
9136 /* Master and slaves can be from different fabrics */
9137 {
9138 .src = MSM_BUS_MASTER_MDP_PORT0,
9139 .dst = MSM_BUS_SLAVE_EBI_CH0,
9140 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009141 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009142 },
9143};
9144
9145#endif
9146static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9147 {
9148 ARRAY_SIZE(mdp_init_vectors),
9149 mdp_init_vectors,
9150 },
9151 {
9152 ARRAY_SIZE(mdp_sd_smi_vectors),
9153 mdp_sd_smi_vectors,
9154 },
9155 {
9156 ARRAY_SIZE(mdp_sd_ebi_vectors),
9157 mdp_sd_ebi_vectors,
9158 },
9159 {
9160 ARRAY_SIZE(mdp_vga_vectors),
9161 mdp_vga_vectors,
9162 },
9163 {
9164 ARRAY_SIZE(mdp_720p_vectors),
9165 mdp_720p_vectors,
9166 },
9167 {
9168 ARRAY_SIZE(mdp_1080p_vectors),
9169 mdp_1080p_vectors,
9170 },
9171};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009172#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009173static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9174 mdp_bus_scale_usecases,
9175 ARRAY_SIZE(mdp_bus_scale_usecases),
9176 .name = "mdp",
9177};
9178
9179#endif
9180#ifdef CONFIG_MSM_BUS_SCALING
9181static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9182 /* For now, 0th array entry is reserved.
9183 * Please leave 0 as is and don't use it
9184 */
9185 {
9186 .src = MSM_BUS_MASTER_MDP_PORT0,
9187 .dst = MSM_BUS_SLAVE_SMI,
9188 .ab = 0,
9189 .ib = 0,
9190 },
9191 /* Master and slaves can be from different fabrics */
9192 {
9193 .src = MSM_BUS_MASTER_MDP_PORT0,
9194 .dst = MSM_BUS_SLAVE_EBI_CH0,
9195 .ab = 0,
9196 .ib = 0,
9197 },
9198};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009199#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9200static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9201 /* For now, 0th array entry is reserved.
9202 * Please leave 0 as is and don't use it
9203 */
9204 {
9205 .src = MSM_BUS_MASTER_MDP_PORT0,
9206 .dst = MSM_BUS_SLAVE_SMI,
9207 .ab = 2000000000,
9208 .ib = 2000000000,
9209 },
9210 /* Master and slaves can be from different fabrics */
9211 {
9212 .src = MSM_BUS_MASTER_MDP_PORT0,
9213 .dst = MSM_BUS_SLAVE_EBI_CH0,
9214 .ab = 2000000000,
9215 .ib = 2000000000,
9216 },
9217};
9218#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009219static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9220 /* For now, 0th array entry is reserved.
9221 * Please leave 0 as is and don't use it
9222 */
9223 {
9224 .src = MSM_BUS_MASTER_MDP_PORT0,
9225 .dst = MSM_BUS_SLAVE_SMI,
9226 .ab = 566092800,
9227 .ib = 707616000,
9228 },
9229 /* Master and slaves can be from different fabrics */
9230 {
9231 .src = MSM_BUS_MASTER_MDP_PORT0,
9232 .dst = MSM_BUS_SLAVE_EBI_CH0,
9233 .ab = 566092800,
9234 .ib = 707616000,
9235 },
9236};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009237#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009238static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9239 {
9240 ARRAY_SIZE(dtv_bus_init_vectors),
9241 dtv_bus_init_vectors,
9242 },
9243 {
9244 ARRAY_SIZE(dtv_bus_def_vectors),
9245 dtv_bus_def_vectors,
9246 },
9247};
9248static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9249 dtv_bus_scale_usecases,
9250 ARRAY_SIZE(dtv_bus_scale_usecases),
9251 .name = "dtv",
9252};
9253
9254static struct lcdc_platform_data dtv_pdata = {
9255 .bus_scale_table = &dtv_bus_scale_pdata,
9256};
9257#endif
9258
9259
9260static struct lcdc_platform_data lcdc_pdata = {
9261 .lcdc_power_save = lcdc_panel_power,
9262};
9263
9264
9265#define MDP_VSYNC_GPIO 28
9266
9267/*
9268 * MIPI_DSI only use 8058_LDO0 which need always on
9269 * therefore it need to be put at low power mode if
9270 * it was not used instead of turn it off.
9271 */
9272static int mipi_dsi_panel_power(int on)
9273{
9274 int flag_on = !!on;
9275 static int mipi_dsi_power_save_on;
9276 static struct regulator *ldo0;
9277 int rc = 0;
9278
9279 if (mipi_dsi_power_save_on == flag_on)
9280 return 0;
9281
9282 mipi_dsi_power_save_on = flag_on;
9283
9284 if (ldo0 == NULL) { /* init */
9285 ldo0 = regulator_get(NULL, "8058_l0");
9286 if (IS_ERR(ldo0)) {
9287 pr_debug("%s: LDO0 failed\n", __func__);
9288 rc = PTR_ERR(ldo0);
9289 return rc;
9290 }
9291
9292 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9293 if (rc)
9294 goto out;
9295
9296 rc = regulator_enable(ldo0);
9297 if (rc)
9298 goto out;
9299 }
9300
9301 if (on) {
9302 /* set ldo0 to HPM */
9303 rc = regulator_set_optimum_mode(ldo0, 100000);
9304 if (rc < 0)
9305 goto out;
9306 } else {
9307 /* set ldo0 to LPM */
9308 rc = regulator_set_optimum_mode(ldo0, 9000);
9309 if (rc < 0)
9310 goto out;
9311 }
9312
9313 return 0;
9314out:
9315 regulator_disable(ldo0);
9316 regulator_put(ldo0);
9317 ldo0 = NULL;
9318 return rc;
9319}
9320
9321static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9322 .vsync_gpio = MDP_VSYNC_GPIO,
9323 .dsi_power_save = mipi_dsi_panel_power,
9324};
9325
9326#ifdef CONFIG_FB_MSM_TVOUT
9327static struct regulator *reg_8058_l13;
9328
9329static int atv_dac_power(int on)
9330{
9331 int rc = 0;
9332 #define _GET_REGULATOR(var, name) do { \
9333 var = regulator_get(NULL, name); \
9334 if (IS_ERR(var)) { \
9335 pr_info("'%s' regulator not found, rc=%ld\n", \
9336 name, IS_ERR(var)); \
9337 var = NULL; \
9338 return -ENODEV; \
9339 } \
9340 } while (0)
9341
9342 if (!reg_8058_l13)
9343 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9344 #undef _GET_REGULATOR
9345
9346 if (on) {
9347 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9348 if (rc) {
9349 pr_info("%s: '%s' regulator set voltage failed,\
9350 rc=%d\n", __func__, "8058_l13", rc);
9351 return rc;
9352 }
9353
9354 rc = regulator_enable(reg_8058_l13);
9355 if (rc) {
9356 pr_err("%s: '%s' regulator enable failed,\
9357 rc=%d\n", __func__, "8058_l13", rc);
9358 return rc;
9359 }
9360 } else {
9361 rc = regulator_force_disable(reg_8058_l13);
9362 if (rc)
9363 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9364 __func__, "8058_l13", rc);
9365 }
9366 return rc;
9367
9368}
9369#endif
9370
9371#ifdef CONFIG_FB_MSM_MIPI_DSI
9372int mdp_core_clk_rate_table[] = {
9373 85330000,
9374 85330000,
9375 160000000,
9376 200000000,
9377};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009378#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
9379int mdp_core_clk_rate_table[] = {
9380 200000000,
9381 200000000,
9382 200000000,
9383 200000000,
9384};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009385#else
9386int mdp_core_clk_rate_table[] = {
9387 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009388 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009389 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009390 200000000,
9391};
9392#endif
9393
9394static struct msm_panel_common_pdata mdp_pdata = {
9395 .gpio = MDP_VSYNC_GPIO,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009396#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9397 .mdp_core_clk_rate = 200000000,
9398#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009399 .mdp_core_clk_rate = 59080000,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009400#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009401 .mdp_core_clk_table = mdp_core_clk_rate_table,
9402 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9403#ifdef CONFIG_MSM_BUS_SCALING
9404 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9405#endif
9406 .mdp_rev = MDP_REV_41,
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07009407 .writeback_offset = writeback_offset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009408};
9409
9410#ifdef CONFIG_FB_MSM_TVOUT
9411
9412#ifdef CONFIG_MSM_BUS_SCALING
9413static struct msm_bus_vectors atv_bus_init_vectors[] = {
9414 /* For now, 0th array entry is reserved.
9415 * Please leave 0 as is and don't use it
9416 */
9417 {
9418 .src = MSM_BUS_MASTER_MDP_PORT0,
9419 .dst = MSM_BUS_SLAVE_SMI,
9420 .ab = 0,
9421 .ib = 0,
9422 },
9423 /* Master and slaves can be from different fabrics */
9424 {
9425 .src = MSM_BUS_MASTER_MDP_PORT0,
9426 .dst = MSM_BUS_SLAVE_EBI_CH0,
9427 .ab = 0,
9428 .ib = 0,
9429 },
9430};
9431static struct msm_bus_vectors atv_bus_def_vectors[] = {
9432 /* For now, 0th array entry is reserved.
9433 * Please leave 0 as is and don't use it
9434 */
9435 {
9436 .src = MSM_BUS_MASTER_MDP_PORT0,
9437 .dst = MSM_BUS_SLAVE_SMI,
9438 .ab = 236390400,
9439 .ib = 265939200,
9440 },
9441 /* Master and slaves can be from different fabrics */
9442 {
9443 .src = MSM_BUS_MASTER_MDP_PORT0,
9444 .dst = MSM_BUS_SLAVE_EBI_CH0,
9445 .ab = 236390400,
9446 .ib = 265939200,
9447 },
9448};
9449static struct msm_bus_paths atv_bus_scale_usecases[] = {
9450 {
9451 ARRAY_SIZE(atv_bus_init_vectors),
9452 atv_bus_init_vectors,
9453 },
9454 {
9455 ARRAY_SIZE(atv_bus_def_vectors),
9456 atv_bus_def_vectors,
9457 },
9458};
9459static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9460 atv_bus_scale_usecases,
9461 ARRAY_SIZE(atv_bus_scale_usecases),
9462 .name = "atv",
9463};
9464#endif
9465
9466static struct tvenc_platform_data atv_pdata = {
9467 .poll = 0,
9468 .pm_vid_en = atv_dac_power,
9469#ifdef CONFIG_MSM_BUS_SCALING
9470 .bus_scale_table = &atv_bus_scale_pdata,
9471#endif
9472};
9473#endif
9474
9475static void __init msm_fb_add_devices(void)
9476{
9477#ifdef CONFIG_FB_MSM_LCDC_DSUB
9478 mdp_pdata.mdp_core_clk_table = NULL;
9479 mdp_pdata.num_mdp_clk = 0;
9480 mdp_pdata.mdp_core_clk_rate = 200000000;
9481#endif
9482 if (machine_is_msm8x60_rumi3())
9483 msm_fb_register_device("mdp", NULL);
9484 else
9485 msm_fb_register_device("mdp", &mdp_pdata);
9486
9487 msm_fb_register_device("lcdc", &lcdc_pdata);
9488 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9489#ifdef CONFIG_MSM_BUS_SCALING
9490 msm_fb_register_device("dtv", &dtv_pdata);
9491#endif
9492#ifdef CONFIG_FB_MSM_TVOUT
9493 msm_fb_register_device("tvenc", &atv_pdata);
9494 msm_fb_register_device("tvout_device", NULL);
9495#endif
9496}
9497
9498#if (defined(CONFIG_MARIMBA_CORE)) && \
9499 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9500
9501static const struct {
9502 char *name;
9503 int vmin;
9504 int vmax;
9505} bt_regs_info[] = {
9506 { "8058_s3", 1800000, 1800000 },
9507 { "8058_s2", 1300000, 1300000 },
9508 { "8058_l8", 2900000, 3050000 },
9509};
9510
9511static struct {
9512 bool enabled;
9513} bt_regs_status[] = {
9514 { false },
9515 { false },
9516 { false },
9517};
9518static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9519
9520static int bahama_bt(int on)
9521{
9522 int rc;
9523 int i;
9524 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9525
9526 struct bahama_variant_register {
9527 const size_t size;
9528 const struct bahama_config_register *set;
9529 };
9530
9531 const struct bahama_config_register *p;
9532
9533 u8 version;
9534
9535 const struct bahama_config_register v10_bt_on[] = {
9536 { 0xE9, 0x00, 0xFF },
9537 { 0xF4, 0x80, 0xFF },
9538 { 0xE4, 0x00, 0xFF },
9539 { 0xE5, 0x00, 0x0F },
9540#ifdef CONFIG_WLAN
9541 { 0xE6, 0x38, 0x7F },
9542 { 0xE7, 0x06, 0xFF },
9543#endif
9544 { 0xE9, 0x21, 0xFF },
9545 { 0x01, 0x0C, 0x1F },
9546 { 0x01, 0x08, 0x1F },
9547 };
9548
9549 const struct bahama_config_register v20_bt_on_fm_off[] = {
9550 { 0x11, 0x0C, 0xFF },
9551 { 0x13, 0x01, 0xFF },
9552 { 0xF4, 0x80, 0xFF },
9553 { 0xF0, 0x00, 0xFF },
9554 { 0xE9, 0x00, 0xFF },
9555#ifdef CONFIG_WLAN
9556 { 0x81, 0x00, 0x7F },
9557 { 0x82, 0x00, 0xFF },
9558 { 0xE6, 0x38, 0x7F },
9559 { 0xE7, 0x06, 0xFF },
9560#endif
9561 { 0xE9, 0x21, 0xFF },
9562 };
9563
9564 const struct bahama_config_register v20_bt_on_fm_on[] = {
9565 { 0x11, 0x0C, 0xFF },
9566 { 0x13, 0x01, 0xFF },
9567 { 0xF4, 0x86, 0xFF },
9568 { 0xF0, 0x06, 0xFF },
9569 { 0xE9, 0x00, 0xFF },
9570#ifdef CONFIG_WLAN
9571 { 0x81, 0x00, 0x7F },
9572 { 0x82, 0x00, 0xFF },
9573 { 0xE6, 0x38, 0x7F },
9574 { 0xE7, 0x06, 0xFF },
9575#endif
9576 { 0xE9, 0x21, 0xFF },
9577 };
9578
9579 const struct bahama_config_register v10_bt_off[] = {
9580 { 0xE9, 0x00, 0xFF },
9581 };
9582
9583 const struct bahama_config_register v20_bt_off_fm_off[] = {
9584 { 0xF4, 0x84, 0xFF },
9585 { 0xF0, 0x04, 0xFF },
9586 { 0xE9, 0x00, 0xFF }
9587 };
9588
9589 const struct bahama_config_register v20_bt_off_fm_on[] = {
9590 { 0xF4, 0x86, 0xFF },
9591 { 0xF0, 0x06, 0xFF },
9592 { 0xE9, 0x00, 0xFF }
9593 };
9594 const struct bahama_variant_register bt_bahama[2][3] = {
9595 {
9596 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9597 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9598 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9599 },
9600 {
9601 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9602 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9603 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9604 }
9605 };
9606
9607 u8 offset = 0; /* index into bahama configs */
9608
9609 on = on ? 1 : 0;
9610 version = read_bahama_ver();
9611
9612 if (version == VER_UNSUPPORTED) {
9613 dev_err(&msm_bt_power_device.dev,
9614 "%s: unsupported version\n",
9615 __func__);
9616 return -EIO;
9617 }
9618
9619 if (version == VER_2_0) {
9620 if (marimba_get_fm_status(&config))
9621 offset = 0x01;
9622 }
9623
9624 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9625 if (on && (version == VER_2_0)) {
9626 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9627 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9628 && (bt_regs_status[i].enabled == true)) {
9629 if (regulator_disable(bt_regs[i])) {
9630 dev_err(&msm_bt_power_device.dev,
9631 "%s: regulator disable failed",
9632 __func__);
9633 }
9634 bt_regs_status[i].enabled = false;
9635 break;
9636 }
9637 }
9638 }
9639
9640 p = bt_bahama[on][version + offset].set;
9641
9642 dev_info(&msm_bt_power_device.dev,
9643 "%s: found version %d\n", __func__, version);
9644
9645 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9646 u8 value = (p+i)->value;
9647 rc = marimba_write_bit_mask(&config,
9648 (p+i)->reg,
9649 &value,
9650 sizeof((p+i)->value),
9651 (p+i)->mask);
9652 if (rc < 0) {
9653 dev_err(&msm_bt_power_device.dev,
9654 "%s: reg %d write failed: %d\n",
9655 __func__, (p+i)->reg, rc);
9656 return rc;
9657 }
9658 dev_dbg(&msm_bt_power_device.dev,
9659 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9660 __func__, (p+i)->reg,
9661 value, (p+i)->mask);
9662 }
9663 /* Update BT Status */
9664 if (on)
9665 marimba_set_bt_status(&config, true);
9666 else
9667 marimba_set_bt_status(&config, false);
9668
9669 return 0;
9670}
9671
9672static int bluetooth_use_regulators(int on)
9673{
9674 int i, recover = -1, rc = 0;
9675
9676 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9677 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9678 bt_regs_info[i].name) :
9679 (regulator_put(bt_regs[i]), NULL);
9680 if (IS_ERR(bt_regs[i])) {
9681 rc = PTR_ERR(bt_regs[i]);
9682 dev_err(&msm_bt_power_device.dev,
9683 "regulator %s get failed (%d)\n",
9684 bt_regs_info[i].name, rc);
9685 recover = i - 1;
9686 bt_regs[i] = NULL;
9687 break;
9688 }
9689
9690 if (!on)
9691 continue;
9692
9693 rc = regulator_set_voltage(bt_regs[i],
9694 bt_regs_info[i].vmin,
9695 bt_regs_info[i].vmax);
9696 if (rc < 0) {
9697 dev_err(&msm_bt_power_device.dev,
9698 "regulator %s voltage set (%d)\n",
9699 bt_regs_info[i].name, rc);
9700 recover = i;
9701 break;
9702 }
9703 }
9704
9705 if (on && (recover > -1))
9706 for (i = recover; i >= 0; i--) {
9707 regulator_put(bt_regs[i]);
9708 bt_regs[i] = NULL;
9709 }
9710
9711 return rc;
9712}
9713
9714static int bluetooth_switch_regulators(int on)
9715{
9716 int i, rc = 0;
9717
9718 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9719 if (on && (bt_regs_status[i].enabled == false)) {
9720 rc = regulator_enable(bt_regs[i]);
9721 if (rc < 0) {
9722 dev_err(&msm_bt_power_device.dev,
9723 "regulator %s %s failed (%d)\n",
9724 bt_regs_info[i].name,
9725 "enable", rc);
9726 if (i > 0) {
9727 while (--i) {
9728 regulator_disable(bt_regs[i]);
9729 bt_regs_status[i].enabled
9730 = false;
9731 }
9732 break;
9733 }
9734 }
9735 bt_regs_status[i].enabled = true;
9736 } else if (!on && (bt_regs_status[i].enabled == true)) {
9737 rc = regulator_disable(bt_regs[i]);
9738 if (rc < 0) {
9739 dev_err(&msm_bt_power_device.dev,
9740 "regulator %s %s failed (%d)\n",
9741 bt_regs_info[i].name,
9742 "disable", rc);
9743 break;
9744 }
9745 bt_regs_status[i].enabled = false;
9746 }
9747 }
9748 return rc;
9749}
9750
9751static struct msm_xo_voter *bt_clock;
9752
9753static int bluetooth_power(int on)
9754{
9755 int rc = 0;
9756 int id;
9757
9758 /* In case probe function fails, cur_connv_type would be -1 */
9759 id = adie_get_detected_connectivity_type();
9760 if (id != BAHAMA_ID) {
9761 pr_err("%s: unexpected adie connectivity type: %d\n",
9762 __func__, id);
9763 return -ENODEV;
9764 }
9765
9766 if (on) {
9767
9768 rc = bluetooth_use_regulators(1);
9769 if (rc < 0)
9770 goto out;
9771
9772 rc = bluetooth_switch_regulators(1);
9773
9774 if (rc < 0)
9775 goto fail_put;
9776
9777 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9778
9779 if (IS_ERR(bt_clock)) {
9780 pr_err("Couldn't get TCXO_D0 voter\n");
9781 goto fail_switch;
9782 }
9783
9784 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9785
9786 if (rc < 0) {
9787 pr_err("Failed to vote for TCXO_DO ON\n");
9788 goto fail_vote;
9789 }
9790
9791 rc = bahama_bt(1);
9792
9793 if (rc < 0)
9794 goto fail_clock;
9795
9796 msleep(10);
9797
9798 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9799
9800 if (rc < 0) {
9801 pr_err("Failed to vote for TCXO_DO pin control\n");
9802 goto fail_vote;
9803 }
9804 } else {
9805 /* check for initial RFKILL block (power off) */
9806 /* some RFKILL versions/configurations rfkill_register */
9807 /* calls here for an initial set_block */
9808 /* avoid calling i2c and regulator before unblock (on) */
9809 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
9810 dev_info(&msm_bt_power_device.dev,
9811 "%s: initialized OFF/blocked\n", __func__);
9812 goto out;
9813 }
9814
9815 bahama_bt(0);
9816
9817fail_clock:
9818 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
9819fail_vote:
9820 msm_xo_put(bt_clock);
9821fail_switch:
9822 bluetooth_switch_regulators(0);
9823fail_put:
9824 bluetooth_use_regulators(0);
9825 }
9826
9827out:
9828 if (rc < 0)
9829 on = 0;
9830 dev_info(&msm_bt_power_device.dev,
9831 "Bluetooth power switch: state %d result %d\n", on, rc);
9832
9833 return rc;
9834}
9835
9836#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
9837
9838static void __init msm8x60_cfg_smsc911x(void)
9839{
9840 smsc911x_resources[1].start =
9841 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
9842 smsc911x_resources[1].end =
9843 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
9844}
9845
9846#ifdef CONFIG_MSM_RPM
9847static struct msm_rpm_platform_data msm_rpm_data = {
9848 .reg_base_addrs = {
9849 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
9850 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
9851 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
9852 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
9853 },
9854
9855 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
9856 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
9857 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
9858 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
9859 .msm_apps_ipc_rpm_val = 4,
9860};
9861#endif
9862
Laura Abbott5d2d1e62011-08-10 16:27:35 -07009863void msm_fusion_setup_pinctrl(void)
9864{
9865 struct msm_xo_voter *a1;
9866
9867 if (socinfo_get_platform_subtype() == 0x3) {
9868 /*
9869 * Vote for the A1 clock to be in pin control mode before
9870 * the external images are loaded.
9871 */
9872 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
9873 BUG_ON(!a1);
9874 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
9875 }
9876}
9877
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009878struct msm_board_data {
9879 struct msm_gpiomux_configs *gpiomux_cfgs;
9880};
9881
9882static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
9883 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9884};
9885
9886static struct msm_board_data msm8x60_sim_board_data __initdata = {
9887 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9888};
9889
9890static struct msm_board_data msm8x60_surf_board_data __initdata = {
9891 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9892};
9893
9894static struct msm_board_data msm8x60_ffa_board_data __initdata = {
9895 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
9896};
9897
9898static struct msm_board_data msm8x60_fluid_board_data __initdata = {
9899 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
9900};
9901
9902static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
9903 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
9904};
9905
9906static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
9907 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
9908};
9909
Zhang Chang Kenef05b172011-07-27 15:28:13 -04009910static struct msm_board_data msm8x60_dragon_board_data __initdata = {
9911 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
9912};
9913
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009914static void __init msm8x60_init(struct msm_board_data *board_data)
9915{
9916 uint32_t soc_platform_version;
9917
Anirudh Ghayalc2019332011-11-12 06:29:10 +05309918 pmic_reset_irq = PM8058_IRQ_BASE + PM8058_RESOUT_IRQ;
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -07009919
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009920 /*
9921 * Initialize RPM first as other drivers and devices may need
9922 * it for their initialization.
9923 */
9924#ifdef CONFIG_MSM_RPM
9925 BUG_ON(msm_rpm_init(&msm_rpm_data));
9926#endif
9927 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
9928 ARRAY_SIZE(msm_rpmrs_levels)));
9929 if (msm_xo_init())
9930 pr_err("Failed to initialize XO votes\n");
9931
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009932 msm8x60_check_2d_hardware();
9933
9934 /* Change SPM handling of core 1 if PMM 8160 is present. */
9935 soc_platform_version = socinfo_get_platform_version();
9936 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
9937 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
9938 struct msm_spm_platform_data *spm_data;
9939
9940 spm_data = &msm_spm_data_v1[1];
9941 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
9942 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
9943
9944 spm_data = &msm_spm_data[1];
9945 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
9946 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
9947 }
9948
9949 /*
9950 * Initialize SPM before acpuclock as the latter calls into SPM
9951 * driver to set ACPU voltages.
9952 */
9953 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
9954 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
9955 else
9956 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
9957
9958 /*
9959 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
9960 * devices so that the RPM doesn't drop into a low power mode that an
9961 * un-reworked SURF cannot resume from.
9962 */
9963 if (machine_is_msm8x60_surf()) {
David Collins6f032ba2011-08-31 14:08:15 -07009964 int i;
9965
9966 for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
9967 if (rpm_regulator_init_data[i].id
9968 == RPM_VREG_ID_PM8901_L4
9969 || rpm_regulator_init_data[i].id
9970 == RPM_VREG_ID_PM8901_L6)
9971 rpm_regulator_init_data[i]
9972 .init_data.constraints.always_on = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009973 }
9974
9975 /*
9976 * Disable regulator info printing so that regulator registration
9977 * messages do not enter the kmsg log.
9978 */
9979 regulator_suppress_info_printing();
9980
9981 /* Initialize regulators needed for clock_init. */
9982 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
9983
Stephen Boydbb600ae2011-08-02 20:11:40 -07009984 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009985
9986 /* Buses need to be initialized before early-device registration
9987 * to get the platform data for fabrics.
9988 */
9989 msm8x60_init_buses();
9990 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
9991 /* CPU frequency control is not supported on simulated targets. */
9992 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
Matt Wagantallec57f062011-08-16 23:54:46 -07009993 acpuclk_init(&acpuclk_8x60_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009994
Terence Hampsonb36a38c2011-09-19 19:10:40 -04009995 /*
9996 * Enable EBI2 only for boards which make use of it. Leave
9997 * it disabled for all others for additional power savings.
9998 */
9999 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10000 machine_is_msm8x60_rumi3() ||
10001 machine_is_msm8x60_sim() ||
10002 machine_is_msm8x60_fluid() ||
10003 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010004 msm8x60_init_ebi2();
10005 msm8x60_init_tlmm();
10006 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10007 msm8x60_init_uart12dm();
10008 msm8x60_init_mmc();
10009
10010#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10011 msm8x60_init_pm8058_othc();
10012#endif
10013
Anirudh Ghayalc2019332011-11-12 06:29:10 +053010014 if (machine_is_msm8x60_fluid())
10015 pm8058_platform_data.keypad_pdata = &fluid_keypad_data;
10016 else if (machine_is_msm8x60_dragon())
10017 pm8058_platform_data.keypad_pdata = &dragon_keypad_data;
10018 else
10019 pm8058_platform_data.keypad_pdata = &ffa_keypad_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010020
Jilai Wang53d27a82011-07-13 14:32:58 -040010021 /* Specify reset pin for OV9726 */
10022 if (machine_is_msm8x60_dragon()) {
10023 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10024 ov9726_sensor_8660_info.mount_angle = 270;
10025 }
10026
Anirudh Ghayalc2019332011-11-12 06:29:10 +053010027#ifdef CONFIG_BATTERY_MSM8X60
10028 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10029 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
10030 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10031 platform_device_register(&msm_charger_device);
10032#endif
10033
10034 if (machine_is_msm8x60_dragon())
10035 pm8058_platform_data.charger_pdata = &pmic8058_charger_dragon;
10036 if (!machine_is_msm8x60_fluid())
10037 pm8058_platform_data.charger_pdata = &pmic8058_charger_ffa_surf;
10038
10039 /* configure pmic leds */
10040 if (machine_is_msm8x60_fluid())
10041 pm8058_platform_data.leds_pdata = &pm8058_fluid_flash_leds_data;
10042 else if (machine_is_msm8x60_dragon())
10043 pm8058_platform_data.leds_pdata = &pm8058_dragon_leds_data;
10044 else
10045 pm8058_platform_data.leds_pdata = &pm8058_flash_leds_data;
10046
10047 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10048 machine_is_msm8x60_dragon()) {
10049 pm8058_platform_data.vibrator_pdata = &pm8058_vib_pdata;
10050 }
10051
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010052 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10053 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010054 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010055 msm8x60_cfg_smsc911x();
10056 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10057 platform_add_devices(msm_footswitch_devices,
10058 msm_num_footswitch_devices);
10059 platform_add_devices(surf_devices,
10060 ARRAY_SIZE(surf_devices));
10061
10062#ifdef CONFIG_MSM_DSPS
10063 if (machine_is_msm8x60_fluid()) {
10064 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10065 msm8x60_init_dsps();
10066 }
10067#endif
10068
10069#ifdef CONFIG_USB_EHCI_MSM_72K
10070 /*
10071 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10072 * fluid
10073 */
10074 if (machine_is_msm8x60_fluid()) {
10075 pm8901_mpp_config_digital_out(1,
10076 PM8901_MPP_DIG_LEVEL_L5, 1);
10077 }
10078 msm_add_host(0, &msm_usb_host_pdata);
10079#endif
Lei Zhou338cab82011-08-19 13:38:17 -040010080
10081#ifdef CONFIG_SND_SOC_MSM8660_APQ
10082 if (machine_is_msm8x60_dragon())
10083 platform_add_devices(dragon_alsa_devices,
10084 ARRAY_SIZE(dragon_alsa_devices));
10085 else
10086#endif
10087 platform_add_devices(asoc_devices,
10088 ARRAY_SIZE(asoc_devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010089 } else {
10090 msm8x60_configure_smc91x();
10091 platform_add_devices(rumi_sim_devices,
10092 ARRAY_SIZE(rumi_sim_devices));
10093 }
10094#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010095 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10096 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010097 msm8x60_cfg_isp1763();
10098#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010099
10100 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10101 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10102
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010103
10104#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10105 if (machine_is_msm8x60_fluid())
10106 platform_device_register(&msm_gsbi10_qup_spi_device);
10107 else
10108 platform_device_register(&msm_gsbi1_qup_spi_device);
10109#endif
10110
10111#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10112 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10113 if (machine_is_msm8x60_fluid())
10114 cyttsp_set_params();
10115#endif
10116 if (!machine_is_msm8x60_sim())
10117 msm_fb_add_devices();
10118 fixup_i2c_configs();
10119 register_i2c_devices();
10120
Terence Hampson1c73fef2011-07-19 17:10:49 -040010121 if (machine_is_msm8x60_dragon())
10122 smsc911x_config.reset_gpio
10123 = GPIO_ETHERNET_RESET_N_DRAGON;
10124
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010125 platform_device_register(&smsc911x_device);
10126
10127#if (defined(CONFIG_SPI_QUP)) && \
10128 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010129 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10130 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010131
10132 if (machine_is_msm8x60_fluid()) {
10133#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10134 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10135 spi_register_board_info(lcdc_samsung_spi_board_info,
10136 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10137 } else
10138#endif
10139 {
10140#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10141 spi_register_board_info(lcdc_auo_spi_board_info,
10142 ARRAY_SIZE(lcdc_auo_spi_board_info));
10143#endif
10144 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010145#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10146 } else if (machine_is_msm8x60_dragon()) {
10147 spi_register_board_info(lcdc_nt35582_spi_board_info,
10148 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10149#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010150 }
10151#endif
10152
10153 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10154 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10155 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10156 msm_pm_data);
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -060010157 BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010158
Anirudh Ghayalc2019332011-11-12 06:29:10 +053010159 pm8058_gpios_init();
10160
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010161#ifdef CONFIG_SENSORS_MSM_ADC
10162 if (machine_is_msm8x60_fluid()) {
10163 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10164 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10165 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10166 msm_adc_pdata.gpio_config = APROC_CONFIG;
10167 else
10168 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10169 }
10170 msm_adc_pdata.target_hw = MSM_8x60;
10171#endif
10172#ifdef CONFIG_MSM8X60_AUDIO
10173 msm_snddev_init();
10174#endif
10175#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10176 if (machine_is_msm8x60_fluid())
10177 platform_device_register(&fluid_leds_gpio);
10178 else
10179 platform_device_register(&gpio_leds);
10180#endif
10181
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010182 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010183
10184 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10185 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010186}
10187
10188static void __init msm8x60_rumi3_init(void)
10189{
10190 msm8x60_init(&msm8x60_rumi3_board_data);
10191}
10192
10193static void __init msm8x60_sim_init(void)
10194{
10195 msm8x60_init(&msm8x60_sim_board_data);
10196}
10197
10198static void __init msm8x60_surf_init(void)
10199{
10200 msm8x60_init(&msm8x60_surf_board_data);
10201}
10202
10203static void __init msm8x60_ffa_init(void)
10204{
10205 msm8x60_init(&msm8x60_ffa_board_data);
10206}
10207
10208static void __init msm8x60_fluid_init(void)
10209{
10210 msm8x60_init(&msm8x60_fluid_board_data);
10211}
10212
10213static void __init msm8x60_charm_surf_init(void)
10214{
10215 msm8x60_init(&msm8x60_charm_surf_board_data);
10216}
10217
10218static void __init msm8x60_charm_ffa_init(void)
10219{
10220 msm8x60_init(&msm8x60_charm_ffa_board_data);
10221}
10222
10223static void __init msm8x60_charm_init_early(void)
10224{
10225 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010226}
10227
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010228static void __init msm8x60_dragon_init(void)
10229{
10230 msm8x60_init(&msm8x60_dragon_board_data);
10231}
10232
Steve Mucklea55df6e2010-01-07 12:43:24 -080010233MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10234 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010235 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010236 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010237 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010238 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010239 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010240MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010241
10242MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10243 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010244 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010245 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010246 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010247 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010248 .init_early = msm8x60_charm_init_early,
10249MACHINE_END
10250
10251MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10252 .map_io = msm8x60_map_io,
10253 .reserve = msm8x60_reserve,
10254 .init_irq = msm8x60_init_irq,
10255 .init_machine = msm8x60_surf_init,
10256 .timer = &msm_timer,
10257 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010258MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010259
10260MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10261 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010262 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010263 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010264 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010265 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010266 .init_early = msm8x60_charm_init_early,
10267MACHINE_END
10268
10269MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10270 .map_io = msm8x60_map_io,
10271 .reserve = msm8x60_reserve,
10272 .init_irq = msm8x60_init_irq,
10273 .init_machine = msm8x60_fluid_init,
10274 .timer = &msm_timer,
10275 .init_early = msm8x60_charm_init_early,
10276MACHINE_END
10277
10278MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10279 .map_io = msm8x60_map_io,
10280 .reserve = msm8x60_reserve,
10281 .init_irq = msm8x60_init_irq,
10282 .init_machine = msm8x60_charm_surf_init,
10283 .timer = &msm_timer,
10284 .init_early = msm8x60_charm_init_early,
10285MACHINE_END
10286
10287MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10288 .map_io = msm8x60_map_io,
10289 .reserve = msm8x60_reserve,
10290 .init_irq = msm8x60_init_irq,
10291 .init_machine = msm8x60_charm_ffa_init,
10292 .timer = &msm_timer,
10293 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010294MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010295
10296MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10297 .map_io = msm8x60_map_io,
10298 .reserve = msm8x60_reserve,
10299 .init_irq = msm8x60_init_irq,
10300 .init_machine = msm8x60_dragon_init,
10301 .timer = &msm_timer,
10302 .init_early = msm8x60_charm_init_early,
10303MACHINE_END