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review.evervolv.com / android_kernel_htc_msm8960 / c259ae52e204d42f8b2d484c85517a4c367030e1 / . / arch / s390 / kernel / reipl64.S
blob: c41930499a5f1d0ca921e69e820c3810dcf4a216 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * arch/s390/kernel/reipl.S
3 *
4 * S390 version
5 * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]7 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8 */
9
10#include <asm/lowcore.h>
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]11
12#
13# do_reipl_asm
14# Parameter: r2 = schid of reipl device
15#
16
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]17 .globl do_reipl_asm
18do_reipl_asm: basr %r13,0
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]19.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
20.Lpg1: # do store status of all registers
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]21
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]22 stg %r1,.Lregsave-.Lpg0(%r13)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]23 lghi %r1,0x1000
24 stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
25 lg %r0,.Lregsave-.Lpg0(%r13)
26 stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
27 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
28 stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]29 lg %r10,.Ldump_pfx-.Lpg0(%r13)
30 mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]31 stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1)
32 stckc .Lclkcmp-.Lpg0(%r13)
33 mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(8,%r1),.Lclkcmp-.Lpg0(%r13)
34 stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
35 stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
36
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]37 lctlg %c6,%c6,.Lall-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]38 lgr %r1,%r2
39 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
40 stsch .Lschib-.Lpg0(%r13)
41 oi .Lschib+5-.Lpg0(%r13),0x84
42.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
43 msch .Lschib-.Lpg0(%r13)
44 lghi %r0,5
45.Lssch: ssch .Liplorb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]46 jz .L001
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]47 brct %r0,.Lssch
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]48 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]49.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
50.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]51.Lcont: c %r1,__LC_SUBCHANNEL_ID
52 jnz .Ltpi
53 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
54 jnz .Ltpi
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]55 tsch .Liplirb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]56 tm .Liplirb+9-.Lpg0(%r13),0xbf
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]57 jz .L002
58 bas %r14,.Ldisab-.Lpg0(%r13)
59.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
60 jz .L003
61 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]62.L003: st %r1,__LC_SUBCHANNEL_ID
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]63 lhi %r1,0 # mode 0 = esa
64 slr %r0,%r0 # set cpuid to zero
65 sigp %r1,%r0,0x12 # switch to esa mode
66 lpsw 0
67.Ldisab: sll %r14,1
68 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
69 st %r14,.Ldispsw+12-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]70 lpswe .Ldispsw-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]71 .align 8
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]72.Lclkcmp: .quad 0x0000000000000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]73.Lall: .quad 0x00000000ff000000
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]74.Ldump_pfx: .quad dump_prefix_page
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]75.Lregsave: .quad 0x0000000000000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]76 .align 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]77/*
78 * These addresses have to be 31 bit otherwise
79 * the sigp will throw a specifcation exception
80 * when switching to ESA mode as bit 31 be set
81 * in the ESA psw.
82 * Bit 31 of the addresses has to be 0 for the
83 * 31bit lpswe instruction a fact they appear to have
84 * ommited from the pop.
85 */
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]86.Lnewpsw: .quad 0x0000000080000000
87 .quad .Lpg1
88.Lpcnew: .quad 0x0000000080000000
89 .quad .Lecs
90.Lionew: .quad 0x0000000080000000
91 .quad .Lcont
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]92.Lwaitpsw: .quad 0x0202000080000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]93 .quad .Ltpi
94.Ldispsw: .quad 0x0002000080000000
95 .quad 0x0000000000000000
96.Liplccws: .long 0x02000000,0x60000018
97 .long 0x08000008,0x20000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]98.Liplorb: .long 0x0049504c,0x0040ff80
99 .long 0x00000000+.Liplccws
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]100.Lschib: .long 0x00000000,0x00000000
101 .long 0x00000000,0x00000000
102 .long 0x00000000,0x00000000
103 .long 0x00000000,0x00000000
104 .long 0x00000000,0x00000000
105 .long 0x00000000,0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]106.Liplirb: .long 0x00000000,0x00000000
107 .long 0x00000000,0x00000000
108 .long 0x00000000,0x00000000
109 .long 0x00000000,0x00000000
110 .long 0x00000000,0x00000000
111 .long 0x00000000,0x00000000
112 .long 0x00000000,0x00000000
113 .long 0x00000000,0x00000000