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review.evervolv.com / android_kernel_htc_msm8960 / c436fd2bc1d4255f888dfd68a9f73098cebf30a7 / . / drivers / gpu / drm / radeon / evergreend.h
blob: 2eaaea061d6ca119e5b7a93380b6516367689311 [file] [log] [blame]
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]40/* Registers */
41
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]42#define RCU_IND_INDEX 0x100
43#define RCU_IND_DATA 0x104
44
45#define GRBM_GFX_INDEX 0x802C
46#define INSTANCE_INDEX(x) ((x) << 0)
47#define SE_INDEX(x) ((x) << 16)
48#define INSTANCE_BROADCAST_WRITES (1 << 30)
49#define SE_BROADCAST_WRITES (1 << 31)
50#define RLC_GFX_INDEX 0x3fC4
51#define CC_GC_SHADER_PIPE_CONFIG 0x8950
52#define WRITE_DIS (1 << 0)
53#define CC_RB_BACKEND_DISABLE 0x98F4
54#define BACKEND_DISABLE(x) ((x) << 16)
55#define GB_ADDR_CONFIG 0x98F8
56#define NUM_PIPES(x) ((x) << 0)
57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59#define NUM_SHADER_ENGINES(x) ((x) << 12)
60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61#define NUM_GPUS(x) ((x) << 20)
62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63#define ROW_SIZE(x) ((x) << 28)
64#define GB_BACKEND_MAP 0x98FC
65#define DMIF_ADDR_CONFIG 0xBD4
66#define HDP_ADDR_CONFIG 0x2F48
Alex Deucherf25a5c62011-05-19 11:07:57 -0400[diff] [blame]67#define HDP_MISC_CNTL 0x2F4C
68#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]69
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]70#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]71#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]72
73#define CGTS_SYS_TCC_DISABLE 0x3F90
74#define CGTS_TCC_DISABLE 0x9148
75#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
76#define CGTS_USER_TCC_DISABLE 0x914C
77
78#define CONFIG_MEMSIZE 0x5428
79
Alex Deucherc436fd22012-11-08 10:08:04 -0500[diff] [blame^]80#define CP_STRMOUT_CNTL 0x84FC
81
82#define CP_COHER_CNTL 0x85F0
83#define CP_COHER_SIZE 0x85F4
Marek Olšákdd220a02012-01-27 12:17:59 -0500[diff] [blame]84#define CP_COHER_BASE 0x85F8
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]85#define CP_ME_CNTL 0x86D8
86#define CP_ME_HALT (1 << 28)
87#define CP_PFP_HALT (1 << 26)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]88#define CP_ME_RAM_DATA 0xC160
89#define CP_ME_RAM_RADDR 0xC158
90#define CP_ME_RAM_WADDR 0xC15C
91#define CP_MEQ_THRESHOLDS 0x8764
92#define STQ_SPLIT(x) ((x) << 0)
93#define CP_PERFMON_CNTL 0x87FC
94#define CP_PFP_UCODE_ADDR 0xC150
95#define CP_PFP_UCODE_DATA 0xC154
96#define CP_QUEUE_THRESHOLDS 0x8760
97#define ROQ_IB1_START(x) ((x) << 0)
98#define ROQ_IB2_START(x) ((x) << 8)
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]99#define CP_RB_BASE 0xC100
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]100#define CP_RB_CNTL 0xC104
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]101#define RB_BUFSZ(x) ((x) << 0)
102#define RB_BLKSZ(x) ((x) << 8)
103#define RB_NO_UPDATE (1 << 27)
104#define RB_RPTR_WR_ENA (1 << 31)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]105#define BUF_SWAP_32BIT (2 << 16)
106#define CP_RB_RPTR 0x8700
107#define CP_RB_RPTR_ADDR 0xC10C
Alex Deucher0f234f52011-02-13 19:06:33 -0500[diff] [blame]108#define RB_RPTR_SWAP(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]109#define CP_RB_RPTR_ADDR_HI 0xC110
110#define CP_RB_RPTR_WR 0xC108
111#define CP_RB_WPTR 0xC114
112#define CP_RB_WPTR_ADDR 0xC118
113#define CP_RB_WPTR_ADDR_HI 0xC11C
114#define CP_RB_WPTR_DELAY 0x8704
115#define CP_SEM_WAIT_TIMER 0x85BC
Alex Deucher11ef3f12012-01-20 14:47:43 -0500[diff] [blame]116#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
Alex Deucherfe251e22010-03-24 13:36:43 -0400[diff] [blame]117#define CP_DEBUG 0xC1FC
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]118
119
120#define GC_USER_SHADER_PIPE_CONFIG 0x8954
121#define INACTIVE_QD_PIPES(x) ((x) << 8)
122#define INACTIVE_QD_PIPES_MASK 0x0000FF00
123#define INACTIVE_SIMDS(x) ((x) << 16)
124#define INACTIVE_SIMDS_MASK 0x00FF0000
125
126#define GRBM_CNTL 0x8000
127#define GRBM_READ_TIMEOUT(x) ((x) << 0)
128#define GRBM_SOFT_RESET 0x8020
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]129#define SOFT_RESET_CP (1 << 0)
130#define SOFT_RESET_CB (1 << 1)
131#define SOFT_RESET_DB (1 << 3)
132#define SOFT_RESET_PA (1 << 5)
133#define SOFT_RESET_SC (1 << 6)
134#define SOFT_RESET_SPI (1 << 8)
135#define SOFT_RESET_SH (1 << 9)
136#define SOFT_RESET_SX (1 << 10)
137#define SOFT_RESET_TC (1 << 11)
138#define SOFT_RESET_TA (1 << 12)
139#define SOFT_RESET_VC (1 << 13)
140#define SOFT_RESET_VGT (1 << 14)
141
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]142#define GRBM_STATUS 0x8010
143#define CMDFIFO_AVAIL_MASK 0x0000000F
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]144#define SRBM_RQ_PENDING (1 << 5)
145#define CF_RQ_PENDING (1 << 7)
146#define PF_RQ_PENDING (1 << 8)
147#define GRBM_EE_BUSY (1 << 10)
148#define SX_CLEAN (1 << 11)
149#define DB_CLEAN (1 << 12)
150#define CB_CLEAN (1 << 13)
151#define TA_BUSY (1 << 14)
152#define VGT_BUSY_NO_DMA (1 << 16)
153#define VGT_BUSY (1 << 17)
154#define SX_BUSY (1 << 20)
155#define SH_BUSY (1 << 21)
156#define SPI_BUSY (1 << 22)
157#define SC_BUSY (1 << 24)
158#define PA_BUSY (1 << 25)
159#define DB_BUSY (1 << 26)
160#define CP_COHERENCY_BUSY (1 << 28)
161#define CP_BUSY (1 << 29)
162#define CB_BUSY (1 << 30)
163#define GUI_ACTIVE (1 << 31)
164#define GRBM_STATUS_SE0 0x8014
165#define GRBM_STATUS_SE1 0x8018
166#define SE_SX_CLEAN (1 << 0)
167#define SE_DB_CLEAN (1 << 1)
168#define SE_CB_CLEAN (1 << 2)
169#define SE_TA_BUSY (1 << 25)
170#define SE_SX_BUSY (1 << 26)
171#define SE_SPI_BUSY (1 << 27)
172#define SE_SH_BUSY (1 << 28)
173#define SE_SC_BUSY (1 << 29)
174#define SE_DB_BUSY (1 << 30)
175#define SE_CB_BUSY (1 << 31)
Alex Deuchere33df252010-11-22 17:56:32 -0500[diff] [blame]176/* evergreen */
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]177#define CG_THERMAL_CTRL 0x72c
178#define TOFFSET_MASK 0x00003FE0
179#define TOFFSET_SHIFT 5
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]180#define CG_MULT_THERMAL_STATUS 0x740
181#define ASIC_T(x) ((x) << 16)
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]182#define ASIC_T_MASK 0x07FF0000
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]183#define ASIC_T_SHIFT 16
Alex Deucher67b3f822011-05-25 18:45:37 -0400[diff] [blame]184#define CG_TS0_STATUS 0x760
185#define TS0_ADC_DOUT_MASK 0x000003FF
186#define TS0_ADC_DOUT_SHIFT 0
Alex Deuchere33df252010-11-22 17:56:32 -0500[diff] [blame]187/* APU */
188#define CG_THERMAL_STATUS 0x678
Alex Deucher21a81222010-07-02 12:58:16 -0400[diff] [blame]189
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]190#define HDP_HOST_PATH_CNTL 0x2C00
191#define HDP_NONSURFACE_BASE 0x2C04
192#define HDP_NONSURFACE_INFO 0x2C08
193#define HDP_NONSURFACE_SIZE 0x2C0C
Alex Deucher6f2f48a2010-12-15 11:01:56 -0500[diff] [blame]194#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]195#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
196#define HDP_TILING_CONFIG 0x2F3C
197
198#define MC_SHARED_CHMAP 0x2004
199#define NOOFCHAN_SHIFT 12
200#define NOOFCHAN_MASK 0x00003000
Alex Deucher9535ab72010-11-22 17:56:18 -0500[diff] [blame]201#define MC_SHARED_CHREMAP 0x2008
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]202
203#define MC_ARB_RAMCFG 0x2760
204#define NOOFBANK_SHIFT 0
205#define NOOFBANK_MASK 0x00000003
206#define NOOFRANK_SHIFT 2
207#define NOOFRANK_MASK 0x00000004
208#define NOOFROWS_SHIFT 3
209#define NOOFROWS_MASK 0x00000038
210#define NOOFCOLS_SHIFT 6
211#define NOOFCOLS_MASK 0x000000C0
212#define CHANSIZE_SHIFT 8
213#define CHANSIZE_MASK 0x00000100
214#define BURSTLENGTH_SHIFT 9
215#define BURSTLENGTH_MASK 0x00000200
216#define CHANSIZE_OVERRIDE (1 << 11)
Alex Deucherd9282fc2011-05-11 03:15:24 -0400[diff] [blame]217#define FUS_MC_ARB_RAMCFG 0x2768
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]218#define MC_VM_AGP_TOP 0x2028
219#define MC_VM_AGP_BOT 0x202C
220#define MC_VM_AGP_BASE 0x2030
221#define MC_VM_FB_LOCATION 0x2024
Alex Deucherb4183e32010-12-15 11:04:10 -0500[diff] [blame]222#define MC_FUS_VM_FB_OFFSET 0x2898
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]223#define MC_VM_MB_L1_TLB0_CNTL 0x2234
224#define MC_VM_MB_L1_TLB1_CNTL 0x2238
225#define MC_VM_MB_L1_TLB2_CNTL 0x223C
226#define MC_VM_MB_L1_TLB3_CNTL 0x2240
227#define ENABLE_L1_TLB (1 << 0)
228#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
229#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
230#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
231#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
232#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
233#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
234#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
235#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
236#define MC_VM_MD_L1_TLB0_CNTL 0x2654
237#define MC_VM_MD_L1_TLB1_CNTL 0x2658
238#define MC_VM_MD_L1_TLB2_CNTL 0x265C
Alex Deucherfe3777a2012-05-31 18:54:43 -0400[diff] [blame]239#define MC_VM_MD_L1_TLB3_CNTL 0x2698
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400[diff] [blame]240
241#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
242#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
243#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
244
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]245#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
246#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
247#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
248
249#define PA_CL_ENHANCE 0x8A14
250#define CLIP_VTX_REORDER_ENA (1 << 0)
251#define NUM_CLIP_SEQ(x) ((x) << 1)
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]252#define PA_SC_ENHANCE 0x8BF0
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]253#define PA_SC_AA_CONFIG 0x28C04
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]254#define MSAA_NUM_SAMPLES_SHIFT 0
255#define MSAA_NUM_SAMPLES_MASK 0x3
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]256#define PA_SC_CLIPRECT_RULE 0x2820C
257#define PA_SC_EDGERULE 0x28230
258#define PA_SC_FIFO_SIZE 0x8BCC
259#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
260#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]261#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]262#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]263#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
264#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]265#define PA_SC_LINE_STIPPLE 0x28A0C
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]266#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]267#define PA_SC_LINE_STIPPLE_STATE 0x8B10
268
269#define SCRATCH_REG0 0x8500
270#define SCRATCH_REG1 0x8504
271#define SCRATCH_REG2 0x8508
272#define SCRATCH_REG3 0x850C
273#define SCRATCH_REG4 0x8510
274#define SCRATCH_REG5 0x8514
275#define SCRATCH_REG6 0x8518
276#define SCRATCH_REG7 0x851C
277#define SCRATCH_UMSK 0x8540
278#define SCRATCH_ADDR 0x8544
279
Alex Deucher789ed2a2012-06-14 22:06:36 +0200[diff] [blame]280#define SMX_SAR_CTL0 0xA008
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]281#define SMX_DC_CTL0 0xA020
282#define USE_HASH_FUNCTION (1 << 0)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]283#define NUMBER_OF_SETS(x) ((x) << 1)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]284#define FLUSH_ALL_ON_EVENT (1 << 10)
285#define STALL_ON_EVENT (1 << 11)
286#define SMX_EVENT_CTL 0xA02C
287#define ES_FLUSH_CTL(x) ((x) << 0)
288#define GS_FLUSH_CTL(x) ((x) << 3)
289#define ACK_FLUSH_CTL(x) ((x) << 6)
290#define SYNC_FLUSH_CTL (1 << 8)
291
292#define SPI_CONFIG_CNTL 0x9100
293#define GPR_WRITE_PRIORITY(x) ((x) << 0)
294#define SPI_CONFIG_CNTL_1 0x913C
295#define VTX_DONE_DELAY(x) ((x) << 0)
296#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
297#define SPI_INPUT_Z 0x286D8
298#define SPI_PS_IN_CONTROL_0 0x286CC
299#define NUM_INTERP(x) ((x)<<0)
300#define POSITION_ENA (1<<8)
301#define POSITION_CENTROID (1<<9)
302#define POSITION_ADDR(x) ((x)<<10)
303#define PARAM_GEN(x) ((x)<<15)
304#define PARAM_GEN_ADDR(x) ((x)<<19)
305#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
306#define PERSP_GRADIENT_ENA (1<<28)
307#define LINEAR_GRADIENT_ENA (1<<29)
308#define POSITION_SAMPLE (1<<30)
309#define BARYC_AT_SAMPLE_ENA (1<<31)
310
311#define SQ_CONFIG 0x8C00
312#define VC_ENABLE (1 << 0)
313#define EXPORT_SRC_C (1 << 1)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]314#define CS_PRIO(x) ((x) << 18)
315#define LS_PRIO(x) ((x) << 20)
316#define HS_PRIO(x) ((x) << 22)
317#define PS_PRIO(x) ((x) << 24)
318#define VS_PRIO(x) ((x) << 26)
319#define GS_PRIO(x) ((x) << 28)
320#define ES_PRIO(x) ((x) << 30)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]321#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
322#define NUM_PS_GPRS(x) ((x) << 0)
323#define NUM_VS_GPRS(x) ((x) << 16)
324#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
325#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
326#define NUM_GS_GPRS(x) ((x) << 0)
327#define NUM_ES_GPRS(x) ((x) << 16)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]328#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
329#define NUM_HS_GPRS(x) ((x) << 0)
330#define NUM_LS_GPRS(x) ((x) << 16)
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]331#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
332#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]333#define SQ_THREAD_RESOURCE_MGMT 0x8C18
334#define NUM_PS_THREADS(x) ((x) << 0)
335#define NUM_VS_THREADS(x) ((x) << 8)
336#define NUM_GS_THREADS(x) ((x) << 16)
337#define NUM_ES_THREADS(x) ((x) << 24)
338#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
339#define NUM_HS_THREADS(x) ((x) << 0)
340#define NUM_LS_THREADS(x) ((x) << 8)
341#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
342#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
343#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
344#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
345#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
346#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
347#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
348#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
349#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
350#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]351#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
352#define SQ_STATIC_THREAD_MGMT_1 0x8E20
353#define SQ_STATIC_THREAD_MGMT_2 0x8E24
354#define SQ_STATIC_THREAD_MGMT_3 0x8E28
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]355#define SQ_LDS_RESOURCE_MGMT 0x8E2C
356
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]357#define SQ_MS_FIFO_SIZES 0x8CF0
358#define CACHE_FIFO_SIZE(x) ((x) << 0)
359#define FETCH_FIFO_HIWATER(x) ((x) << 8)
360#define DONE_FIFO_HIWATER(x) ((x) << 16)
361#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
362
363#define SX_DEBUG_1 0x9058
364#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
365#define SX_EXPORT_BUFFER_SIZES 0x900C
366#define COLOR_BUFFER_SIZE(x) ((x) << 0)
367#define POSITION_BUFFER_SIZE(x) ((x) << 8)
368#define SMX_BUFFER_SIZE(x) ((x) << 16)
Alex Deucher033b5652011-06-08 15:26:45 -0400[diff] [blame]369#define SX_MEMORY_EXPORT_BASE 0x9010
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]370#define SX_MISC 0x28350
371
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]372#define CB_PERF_CTR0_SEL_0 0x9A20
373#define CB_PERF_CTR0_SEL_1 0x9A24
374#define CB_PERF_CTR1_SEL_0 0x9A28
375#define CB_PERF_CTR1_SEL_1 0x9A2C
376#define CB_PERF_CTR2_SEL_0 0x9A30
377#define CB_PERF_CTR2_SEL_1 0x9A34
378#define CB_PERF_CTR3_SEL_0 0x9A38
379#define CB_PERF_CTR3_SEL_1 0x9A3C
380
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]381#define TA_CNTL_AUX 0x9508
382#define DISABLE_CUBE_WRAP (1 << 0)
383#define DISABLE_CUBE_ANISO (1 << 1)
384#define SYNC_GRADIENT (1 << 24)
385#define SYNC_WALKER (1 << 25)
386#define SYNC_ALIGNER (1 << 26)
387
Alex Deucher9535ab72010-11-22 17:56:18 -0500[diff] [blame]388#define TCP_CHAN_STEER_LO 0x960c
389#define TCP_CHAN_STEER_HI 0x9610
390
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]391#define VGT_CACHE_INVALIDATION 0x88C4
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400[diff] [blame]392#define CACHE_INVALIDATION(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]393#define VC_ONLY 0
394#define TC_ONLY 1
395#define VC_AND_TC 2
396#define AUTO_INVLD_EN(x) ((x) << 6)
397#define NO_AUTO 0
398#define ES_AUTO 1
399#define GS_AUTO 2
400#define ES_AND_GS_AUTO 3
401#define VGT_GS_VERTEX_REUSE 0x88D4
402#define VGT_NUM_INSTANCES 0x8974
403#define VGT_OUT_DEALLOC_CNTL 0x28C5C
404#define DEALLOC_DIST_MASK 0x0000007F
405#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
406#define VTX_REUSE_DEPTH_MASK 0x000000FF
407
408#define VM_CONTEXT0_CNTL 0x1410
409#define ENABLE_CONTEXT (1 << 0)
410#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
411#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
412#define VM_CONTEXT1_CNTL 0x1414
413#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
414#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
415#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
416#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
417#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
418#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
419#define RESPONSE_TYPE_MASK 0x000000F0
420#define RESPONSE_TYPE_SHIFT 4
421#define VM_L2_CNTL 0x1400
422#define ENABLE_L2_CACHE (1 << 0)
423#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
424#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
425#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
426#define VM_L2_CNTL2 0x1404
427#define INVALIDATE_ALL_L1_TLBS (1 << 0)
428#define INVALIDATE_L2_CACHE (1 << 1)
429#define VM_L2_CNTL3 0x1408
430#define BANK_SELECT(x) ((x) << 0)
431#define CACHE_UPDATE_MODE(x) ((x) << 6)
432#define VM_L2_STATUS 0x140C
433#define L2_BUSY (1 << 0)
434
435#define WAIT_UNTIL 0x8040
436
437#define SRBM_STATUS 0x0E50
Alex Deucher747943e2010-03-24 13:26:36 -0400[diff] [blame]438#define SRBM_SOFT_RESET 0x0E60
439#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
440#define SOFT_RESET_BIF (1 << 1)
441#define SOFT_RESET_CG (1 << 2)
442#define SOFT_RESET_DC (1 << 5)
443#define SOFT_RESET_GRBM (1 << 8)
444#define SOFT_RESET_HDP (1 << 9)
445#define SOFT_RESET_IH (1 << 10)
446#define SOFT_RESET_MC (1 << 11)
447#define SOFT_RESET_RLC (1 << 13)
448#define SOFT_RESET_ROM (1 << 14)
449#define SOFT_RESET_SEM (1 << 15)
450#define SOFT_RESET_VMC (1 << 17)
451#define SOFT_RESET_TST (1 << 21)
452#define SOFT_RESET_REGBB (1 << 22)
453#define SOFT_RESET_ORB (1 << 23)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]454
Alex Deucherf9d9c362010-10-22 02:51:05 -0400[diff] [blame]455/* display watermarks */
456#define DC_LB_MEMORY_SPLIT 0x6b0c
457#define PRIORITY_A_CNT 0x6b18
458#define PRIORITY_MARK_MASK 0x7fff
459#define PRIORITY_OFF (1 << 16)
460#define PRIORITY_ALWAYS_ON (1 << 20)
461#define PRIORITY_B_CNT 0x6b1c
462#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
463# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
464#define PIPE0_LATENCY_CONTROL 0x0bf4
465# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
466# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
467
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]468#define IH_RB_CNTL 0x3e00
469# define IH_RB_ENABLE (1 << 0)
470# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
471# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
472# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
473# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
474# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
475# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
476#define IH_RB_BASE 0x3e04
477#define IH_RB_RPTR 0x3e08
478#define IH_RB_WPTR 0x3e0c
479# define RB_OVERFLOW (1 << 0)
480# define WPTR_OFFSET_MASK 0x3fffc
481#define IH_RB_WPTR_ADDR_HI 0x3e10
482#define IH_RB_WPTR_ADDR_LO 0x3e14
483#define IH_CNTL 0x3e18
484# define ENABLE_INTR (1 << 0)
Alex Deucherfcb857a2011-07-06 19:52:27 +0000[diff] [blame]485# define IH_MC_SWAP(x) ((x) << 1)
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]486# define IH_MC_SWAP_NONE 0
487# define IH_MC_SWAP_16BIT 1
488# define IH_MC_SWAP_32BIT 2
489# define IH_MC_SWAP_64BIT 3
490# define RPTR_REARM (1 << 4)
491# define MC_WRREQ_CREDIT(x) ((x) << 15)
492# define MC_WR_CLEAN_CNT(x) ((x) << 20)
493
494#define CP_INT_CNTL 0xc124
495# define CNTX_BUSY_INT_ENABLE (1 << 19)
496# define CNTX_EMPTY_INT_ENABLE (1 << 20)
497# define SCRATCH_INT_ENABLE (1 << 25)
498# define TIME_STAMP_INT_ENABLE (1 << 26)
499# define IB2_INT_ENABLE (1 << 29)
500# define IB1_INT_ENABLE (1 << 30)
501# define RB_INT_ENABLE (1 << 31)
502#define CP_INT_STATUS 0xc128
503# define SCRATCH_INT_STAT (1 << 25)
504# define TIME_STAMP_INT_STAT (1 << 26)
505# define IB2_INT_STAT (1 << 29)
506# define IB1_INT_STAT (1 << 30)
507# define RB_INT_STAT (1 << 31)
508
509#define GRBM_INT_CNTL 0x8060
510# define RDERR_INT_ENABLE (1 << 0)
511# define GUI_IDLE_INT_ENABLE (1 << 19)
512
513/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
514#define CRTC_STATUS_FRAME_COUNT 0x6e98
515
516/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
517#define VLINE_STATUS 0x6bb8
518# define VLINE_OCCURRED (1 << 0)
519# define VLINE_ACK (1 << 4)
520# define VLINE_STAT (1 << 12)
521# define VLINE_INTERRUPT (1 << 16)
522# define VLINE_INTERRUPT_TYPE (1 << 17)
523/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
524#define VBLANK_STATUS 0x6bbc
525# define VBLANK_OCCURRED (1 << 0)
526# define VBLANK_ACK (1 << 4)
527# define VBLANK_STAT (1 << 12)
528# define VBLANK_INTERRUPT (1 << 16)
529# define VBLANK_INTERRUPT_TYPE (1 << 17)
530
531/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
532#define INT_MASK 0x6b40
533# define VBLANK_INT_MASK (1 << 0)
534# define VLINE_INT_MASK (1 << 4)
535
536#define DISP_INTERRUPT_STATUS 0x60f4
537# define LB_D1_VLINE_INTERRUPT (1 << 2)
538# define LB_D1_VBLANK_INTERRUPT (1 << 3)
539# define DC_HPD1_INTERRUPT (1 << 17)
540# define DC_HPD1_RX_INTERRUPT (1 << 18)
541# define DACA_AUTODETECT_INTERRUPT (1 << 22)
542# define DACB_AUTODETECT_INTERRUPT (1 << 23)
543# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
544# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
545#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
546# define LB_D2_VLINE_INTERRUPT (1 << 2)
547# define LB_D2_VBLANK_INTERRUPT (1 << 3)
548# define DC_HPD2_INTERRUPT (1 << 17)
549# define DC_HPD2_RX_INTERRUPT (1 << 18)
550# define DISP_TIMER_INTERRUPT (1 << 24)
551#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
552# define LB_D3_VLINE_INTERRUPT (1 << 2)
553# define LB_D3_VBLANK_INTERRUPT (1 << 3)
554# define DC_HPD3_INTERRUPT (1 << 17)
555# define DC_HPD3_RX_INTERRUPT (1 << 18)
556#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
557# define LB_D4_VLINE_INTERRUPT (1 << 2)
558# define LB_D4_VBLANK_INTERRUPT (1 << 3)
559# define DC_HPD4_INTERRUPT (1 << 17)
560# define DC_HPD4_RX_INTERRUPT (1 << 18)
561#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
562# define LB_D5_VLINE_INTERRUPT (1 << 2)
563# define LB_D5_VBLANK_INTERRUPT (1 << 3)
564# define DC_HPD5_INTERRUPT (1 << 17)
565# define DC_HPD5_RX_INTERRUPT (1 << 18)
Alex Deucher37cba6c2011-07-06 19:37:47 +0000[diff] [blame]566#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]567# define LB_D6_VLINE_INTERRUPT (1 << 2)
568# define LB_D6_VBLANK_INTERRUPT (1 << 3)
569# define DC_HPD6_INTERRUPT (1 << 17)
570# define DC_HPD6_RX_INTERRUPT (1 << 18)
571
572/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
573#define GRPH_INT_STATUS 0x6858
574# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
575# define GRPH_PFLIP_INT_CLEAR (1 << 8)
576/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
577#define GRPH_INT_CONTROL 0x685c
578# define GRPH_PFLIP_INT_MASK (1 << 0)
579# define GRPH_PFLIP_INT_TYPE (1 << 8)
580
581#define DACA_AUTODETECT_INT_CONTROL 0x66c8
582#define DACB_AUTODETECT_INT_CONTROL 0x67c8
583
584#define DC_HPD1_INT_STATUS 0x601c
585#define DC_HPD2_INT_STATUS 0x6028
586#define DC_HPD3_INT_STATUS 0x6034
587#define DC_HPD4_INT_STATUS 0x6040
588#define DC_HPD5_INT_STATUS 0x604c
589#define DC_HPD6_INT_STATUS 0x6058
590# define DC_HPDx_INT_STATUS (1 << 0)
591# define DC_HPDx_SENSE (1 << 1)
592# define DC_HPDx_RX_INT_STATUS (1 << 8)
593
594#define DC_HPD1_INT_CONTROL 0x6020
595#define DC_HPD2_INT_CONTROL 0x602c
596#define DC_HPD3_INT_CONTROL 0x6038
597#define DC_HPD4_INT_CONTROL 0x6044
598#define DC_HPD5_INT_CONTROL 0x6050
599#define DC_HPD6_INT_CONTROL 0x605c
600# define DC_HPDx_INT_ACK (1 << 0)
601# define DC_HPDx_INT_POLARITY (1 << 8)
602# define DC_HPDx_INT_EN (1 << 16)
603# define DC_HPDx_RX_INT_ACK (1 << 20)
604# define DC_HPDx_RX_INT_EN (1 << 24)
605
606#define DC_HPD1_CONTROL 0x6024
607#define DC_HPD2_CONTROL 0x6030
608#define DC_HPD3_CONTROL 0x603c
609#define DC_HPD4_CONTROL 0x6048
610#define DC_HPD5_CONTROL 0x6054
611#define DC_HPD6_CONTROL 0x6060
612# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
613# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
614# define DC_HPDx_EN (1 << 28)
615
Alex Deucher9e46a482011-01-06 18:49:35 -0500[diff] [blame]616/* PCIE link stuff */
617#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
618#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
619# define LC_LINK_WIDTH_SHIFT 0
620# define LC_LINK_WIDTH_MASK 0x7
621# define LC_LINK_WIDTH_X0 0
622# define LC_LINK_WIDTH_X1 1
623# define LC_LINK_WIDTH_X2 2
624# define LC_LINK_WIDTH_X4 3
625# define LC_LINK_WIDTH_X8 4
626# define LC_LINK_WIDTH_X16 6
627# define LC_LINK_WIDTH_RD_SHIFT 4
628# define LC_LINK_WIDTH_RD_MASK 0x70
629# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
630# define LC_RECONFIG_NOW (1 << 8)
631# define LC_RENEGOTIATION_SUPPORT (1 << 9)
632# define LC_RENEGOTIATE_EN (1 << 10)
633# define LC_SHORT_RECONFIG_EN (1 << 11)
634# define LC_UPCONFIGURE_SUPPORT (1 << 12)
635# define LC_UPCONFIGURE_DIS (1 << 13)
636#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
637# define LC_GEN2_EN_STRAP (1 << 0)
638# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
639# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
640# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
641# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
642# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
643# define LC_CURRENT_DATA_RATE (1 << 11)
644# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
645# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
646# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
647# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
648#define MM_CFGREGS_CNTL 0x544c
649# define MM_WR_TO_CFG_EN (1 << 3)
650#define LINK_CNTL2 0x88 /* F0 */
651# define TARGET_LINK_SPEED_MASK (0xf << 0)
652# define SELECTABLE_DEEMPHASIS (1 << 6)
653
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]654/*
655 * PM4
656 */
657#define PACKET_TYPE0 0
658#define PACKET_TYPE1 1
659#define PACKET_TYPE2 2
660#define PACKET_TYPE3 3
661
662#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
663#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
664#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
665#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
666#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
667 (((reg) >> 2) & 0xFFFF) | \
668 ((n) & 0x3FFF) << 16)
669#define CP_PACKET2 0x80000000
670#define PACKET2_PAD_SHIFT 0
671#define PACKET2_PAD_MASK (0x3fffffff << 0)
672
673#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
674
675#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
676 (((op) & 0xFF) << 8) | \
677 ((n) & 0x3FFF) << 16)
678
679/* Packet 3 types */
680#define PACKET3_NOP 0x10
681#define PACKET3_SET_BASE 0x11
682#define PACKET3_CLEAR_STATE 0x12
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]683#define PACKET3_INDEX_BUFFER_SIZE 0x13
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]684#define PACKET3_DISPATCH_DIRECT 0x15
685#define PACKET3_DISPATCH_INDIRECT 0x16
686#define PACKET3_INDIRECT_BUFFER_END 0x17
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]687#define PACKET3_MODE_CONTROL 0x18
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]688#define PACKET3_SET_PREDICATION 0x20
689#define PACKET3_REG_RMW 0x21
690#define PACKET3_COND_EXEC 0x22
691#define PACKET3_PRED_EXEC 0x23
692#define PACKET3_DRAW_INDIRECT 0x24
693#define PACKET3_DRAW_INDEX_INDIRECT 0x25
694#define PACKET3_INDEX_BASE 0x26
695#define PACKET3_DRAW_INDEX_2 0x27
696#define PACKET3_CONTEXT_CONTROL 0x28
697#define PACKET3_DRAW_INDEX_OFFSET 0x29
698#define PACKET3_INDEX_TYPE 0x2A
699#define PACKET3_DRAW_INDEX 0x2B
700#define PACKET3_DRAW_INDEX_AUTO 0x2D
701#define PACKET3_DRAW_INDEX_IMMD 0x2E
702#define PACKET3_NUM_INSTANCES 0x2F
703#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
704#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
705#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
706#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
707#define PACKET3_MEM_SEMAPHORE 0x39
708#define PACKET3_MPEG_INDEX 0x3A
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]709#define PACKET3_COPY_DW 0x3B
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]710#define PACKET3_WAIT_REG_MEM 0x3C
711#define PACKET3_MEM_WRITE 0x3D
712#define PACKET3_INDIRECT_BUFFER 0x32
713#define PACKET3_SURFACE_SYNC 0x43
714# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
715# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
716# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
717# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
718# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
719# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
720# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
721# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
722# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
723# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
724# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
725# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]726# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]727# define PACKET3_FULL_CACHE_ENA (1 << 20)
728# define PACKET3_TC_ACTION_ENA (1 << 23)
729# define PACKET3_VC_ACTION_ENA (1 << 24)
730# define PACKET3_CB_ACTION_ENA (1 << 25)
731# define PACKET3_DB_ACTION_ENA (1 << 26)
732# define PACKET3_SH_ACTION_ENA (1 << 27)
Alex Deucher32171d22011-01-06 19:13:32 -0500[diff] [blame]733# define PACKET3_SX_ACTION_ENA (1 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]734#define PACKET3_ME_INITIALIZE 0x44
735#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
736#define PACKET3_COND_WRITE 0x45
737#define PACKET3_EVENT_WRITE 0x46
738#define PACKET3_EVENT_WRITE_EOP 0x47
739#define PACKET3_EVENT_WRITE_EOS 0x48
740#define PACKET3_PREAMBLE_CNTL 0x4A
Alex Deucher2281a372010-10-21 13:31:38 -0400[diff] [blame]741# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
742# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]743#define PACKET3_RB_OFFSET 0x4B
744#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
745#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
746#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
747#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
748#define PACKET3_ONE_REG_WRITE 0x57
749#define PACKET3_SET_CONFIG_REG 0x68
750#define PACKET3_SET_CONFIG_REG_START 0x00008000
751#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
752#define PACKET3_SET_CONTEXT_REG 0x69
753#define PACKET3_SET_CONTEXT_REG_START 0x00028000
754#define PACKET3_SET_CONTEXT_REG_END 0x00029000
755#define PACKET3_SET_ALU_CONST 0x6A
756/* alu const buffers only; no reg file */
757#define PACKET3_SET_BOOL_CONST 0x6B
758#define PACKET3_SET_BOOL_CONST_START 0x0003a500
759#define PACKET3_SET_BOOL_CONST_END 0x0003a518
760#define PACKET3_SET_LOOP_CONST 0x6C
761#define PACKET3_SET_LOOP_CONST_START 0x0003a200
762#define PACKET3_SET_LOOP_CONST_END 0x0003a500
763#define PACKET3_SET_RESOURCE 0x6D
764#define PACKET3_SET_RESOURCE_START 0x00030000
765#define PACKET3_SET_RESOURCE_END 0x00038000
766#define PACKET3_SET_SAMPLER 0x6E
767#define PACKET3_SET_SAMPLER_START 0x0003c000
768#define PACKET3_SET_SAMPLER_END 0x0003c600
769#define PACKET3_SET_CTL_CONST 0x6F
770#define PACKET3_SET_CTL_CONST_START 0x0003cff0
771#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
772#define PACKET3_SET_RESOURCE_OFFSET 0x70
773#define PACKET3_SET_ALU_CONST_VS 0x71
774#define PACKET3_SET_ALU_CONST_DI 0x72
775#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
776#define PACKET3_SET_RESOURCE_INDIRECT 0x74
777#define PACKET3_SET_APPEND_CNT 0x75
778
779#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
780#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
781#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
782#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
783#define SQ_TEX_VTX_INVALID_BUFFER 0x1
784#define SQ_TEX_VTX_VALID_TEXTURE 0x2
785#define SQ_TEX_VTX_VALID_BUFFER 0x3
786
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]787#define VGT_VTX_VECT_EJECT_REG 0x88b0
788
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]789#define SQ_CONST_MEM_BASE 0x8df8
790
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]791#define SQ_ESGS_RING_BASE 0x8c40
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]792#define SQ_ESGS_RING_SIZE 0x8c44
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]793#define SQ_GSVS_RING_BASE 0x8c48
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]794#define SQ_GSVS_RING_SIZE 0x8c4c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]795#define SQ_ESTMP_RING_BASE 0x8c50
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]796#define SQ_ESTMP_RING_SIZE 0x8c54
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]797#define SQ_GSTMP_RING_BASE 0x8c58
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]798#define SQ_GSTMP_RING_SIZE 0x8c5c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]799#define SQ_VSTMP_RING_BASE 0x8c60
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]800#define SQ_VSTMP_RING_SIZE 0x8c64
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]801#define SQ_PSTMP_RING_BASE 0x8c68
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]802#define SQ_PSTMP_RING_SIZE 0x8c6c
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]803#define SQ_LSTMP_RING_BASE 0x8e10
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]804#define SQ_LSTMP_RING_SIZE 0x8e14
Alex Deucher8aa75002011-03-02 20:07:40 -0500[diff] [blame]805#define SQ_HSTMP_RING_BASE 0x8e18
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]806#define SQ_HSTMP_RING_SIZE 0x8e1c
807#define VGT_TF_RING_SIZE 0x8988
808
809#define SQ_ESGS_RING_ITEMSIZE 0x28900
810#define SQ_GSVS_RING_ITEMSIZE 0x28904
811#define SQ_ESTMP_RING_ITEMSIZE 0x28908
812#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
813#define SQ_VSTMP_RING_ITEMSIZE 0x28910
814#define SQ_PSTMP_RING_ITEMSIZE 0x28914
815#define SQ_LSTMP_RING_ITEMSIZE 0x28830
816#define SQ_HSTMP_RING_ITEMSIZE 0x28834
817
818#define SQ_GS_VERT_ITEMSIZE 0x2891c
819#define SQ_GS_VERT_ITEMSIZE_1 0x28920
820#define SQ_GS_VERT_ITEMSIZE_2 0x28924
821#define SQ_GS_VERT_ITEMSIZE_3 0x28928
822#define SQ_GSVS_RING_OFFSET_1 0x2892c
823#define SQ_GSVS_RING_OFFSET_2 0x28930
824#define SQ_GSVS_RING_OFFSET_3 0x28934
825
Alex Deucher60a4a3e2010-06-29 17:03:35 -0400[diff] [blame]826#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
827#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
828
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]829#define SQ_ALU_CONST_CACHE_PS_0 0x28940
830#define SQ_ALU_CONST_CACHE_PS_1 0x28944
831#define SQ_ALU_CONST_CACHE_PS_2 0x28948
832#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
833#define SQ_ALU_CONST_CACHE_PS_4 0x28950
834#define SQ_ALU_CONST_CACHE_PS_5 0x28954
835#define SQ_ALU_CONST_CACHE_PS_6 0x28958
836#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
837#define SQ_ALU_CONST_CACHE_PS_8 0x28960
838#define SQ_ALU_CONST_CACHE_PS_9 0x28964
839#define SQ_ALU_CONST_CACHE_PS_10 0x28968
840#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
841#define SQ_ALU_CONST_CACHE_PS_12 0x28970
842#define SQ_ALU_CONST_CACHE_PS_13 0x28974
843#define SQ_ALU_CONST_CACHE_PS_14 0x28978
844#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
845#define SQ_ALU_CONST_CACHE_VS_0 0x28980
846#define SQ_ALU_CONST_CACHE_VS_1 0x28984
847#define SQ_ALU_CONST_CACHE_VS_2 0x28988
848#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
849#define SQ_ALU_CONST_CACHE_VS_4 0x28990
850#define SQ_ALU_CONST_CACHE_VS_5 0x28994
851#define SQ_ALU_CONST_CACHE_VS_6 0x28998
852#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
853#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
854#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
855#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
856#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
857#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
858#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
859#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
860#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
861#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
862#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
863#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
864#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
865#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
866#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
867#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
868#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
869#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
870#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
871#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
872#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
873#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
874#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
875#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
876#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
877#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
878#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
879#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
880#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
881#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
882#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
883#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
884#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
885#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
886#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
887#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
888#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
889#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
890#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
891#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
892#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
893#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
894#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
895#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
896#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
897#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
898#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
899#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
900#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
901#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
902#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
903#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
904#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
905#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
906#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
907#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
908#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
909
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400[diff] [blame]910#define PA_SC_SCREEN_SCISSOR_TL 0x28030
911#define PA_SC_GENERIC_SCISSOR_TL 0x28240
912#define PA_SC_WINDOW_SCISSOR_TL 0x28204
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400[diff] [blame]913
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]914#define VGT_PRIMITIVE_TYPE 0x8958
915#define VGT_INDEX_TYPE 0x895C
916
917#define VGT_NUM_INDICES 0x8970
918
919#define VGT_COMPUTE_DIM_X 0x8990
920#define VGT_COMPUTE_DIM_Y 0x8994
921#define VGT_COMPUTE_DIM_Z 0x8998
922#define VGT_COMPUTE_START_X 0x899C
923#define VGT_COMPUTE_START_Y 0x89A0
924#define VGT_COMPUTE_START_Z 0x89A4
925#define VGT_COMPUTE_INDEX 0x89A8
926#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
927#define VGT_HS_OFFCHIP_PARAM 0x89B0
928
929#define DB_DEBUG 0x9830
930#define DB_DEBUG2 0x9834
931#define DB_DEBUG3 0x9838
932#define DB_DEBUG4 0x983C
933#define DB_WATERMARKS 0x9854
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]934#define DB_DEPTH_CONTROL 0x28800
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]935#define R_028800_DB_DEPTH_CONTROL 0x028800
936#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
937#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
938#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
939#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
940#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
941#define C_028800_Z_ENABLE 0xFFFFFFFD
942#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
943#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
944#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
945#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
946#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
947#define C_028800_ZFUNC 0xFFFFFF8F
948#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
949#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
950#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
951#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
952#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
953#define C_028800_STENCILFUNC 0xFFFFF8FF
954#define V_028800_STENCILFUNC_NEVER 0x00000000
955#define V_028800_STENCILFUNC_LESS 0x00000001
956#define V_028800_STENCILFUNC_EQUAL 0x00000002
957#define V_028800_STENCILFUNC_LEQUAL 0x00000003
958#define V_028800_STENCILFUNC_GREATER 0x00000004
959#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
960#define V_028800_STENCILFUNC_GEQUAL 0x00000006
961#define V_028800_STENCILFUNC_ALWAYS 0x00000007
962#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
963#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
964#define C_028800_STENCILFAIL 0xFFFFC7FF
965#define V_028800_STENCIL_KEEP 0x00000000
966#define V_028800_STENCIL_ZERO 0x00000001
967#define V_028800_STENCIL_REPLACE 0x00000002
968#define V_028800_STENCIL_INCR 0x00000003
969#define V_028800_STENCIL_DECR 0x00000004
970#define V_028800_STENCIL_INVERT 0x00000005
971#define V_028800_STENCIL_INCR_WRAP 0x00000006
972#define V_028800_STENCIL_DECR_WRAP 0x00000007
973#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
974#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
975#define C_028800_STENCILZPASS 0xFFFE3FFF
976#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
977#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
978#define C_028800_STENCILZFAIL 0xFFF1FFFF
979#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
980#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
981#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
982#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
983#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
984#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
985#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
986#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
987#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
988#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
989#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
990#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]991#define DB_DEPTH_VIEW 0x28008
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]992#define R_028008_DB_DEPTH_VIEW 0x00028008
993#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
994#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
995#define C_028008_SLICE_START 0xFFFFF800
996#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
997#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
998#define C_028008_SLICE_MAX 0xFF001FFF
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]999#define DB_HTILE_DATA_BASE 0x28014
Jerome Glisse88f50c82012-03-21 19:18:21 -0400[diff] [blame]1000#define DB_HTILE_SURFACE 0x28abc
1001#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1002#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1003#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1004#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1005#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1006#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1007#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1008#define DB_Z_INFO 0x28040
1009# define Z_ARRAY_MODE(x) ((x) << 4)
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1010# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1011# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1012# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1013# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1014# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1015#define R_028040_DB_Z_INFO 0x028040
1016#define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1017#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1018#define C_028040_FORMAT 0xFFFFFFFC
1019#define V_028040_Z_INVALID 0x00000000
1020#define V_028040_Z_16 0x00000001
1021#define V_028040_Z_24 0x00000002
1022#define V_028040_Z_32_FLOAT 0x00000003
1023#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1024#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1025#define C_028040_ARRAY_MODE 0xFFFFFF0F
1026#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1027#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1028#define C_028040_READ_SIZE 0xEFFFFFFF
1029#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1030#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1031#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1032#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1033#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1034#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1035#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1036#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1037#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1038#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1039#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1040#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1041#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1042#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1043#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1044#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1045#define DB_STENCIL_INFO 0x28044
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1046#define R_028044_DB_STENCIL_INFO 0x028044
1047#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1048#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1049#define C_028044_FORMAT 0xFFFFFFFE
1050#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1051#define DB_Z_READ_BASE 0x28048
1052#define DB_STENCIL_READ_BASE 0x2804c
1053#define DB_Z_WRITE_BASE 0x28050
1054#define DB_STENCIL_WRITE_BASE 0x28054
1055#define DB_DEPTH_SIZE 0x28058
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1056#define R_028058_DB_DEPTH_SIZE 0x028058
1057#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1058#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1059#define C_028058_PITCH_TILE_MAX 0xFFFFF800
1060#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1061#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1062#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1063#define R_02805C_DB_DEPTH_SLICE 0x02805C
1064#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1065#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1066#define C_02805C_SLICE_TILE_MAX 0xFFC00000
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1067
1068#define SQ_PGM_START_PS 0x28840
1069#define SQ_PGM_START_VS 0x2885c
1070#define SQ_PGM_START_GS 0x28874
1071#define SQ_PGM_START_ES 0x2888c
1072#define SQ_PGM_START_FS 0x288a4
1073#define SQ_PGM_START_HS 0x288b8
1074#define SQ_PGM_START_LS 0x288d0
1075
Marek Olšákdd220a02012-01-27 12:17:59 -0500[diff] [blame]1076#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1077#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1078#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1079#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1080#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1081#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1082#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1083#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1084#define VGT_STRMOUT_CONFIG 0x28b94
1085#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
1086
1087#define CB_TARGET_MASK 0x28238
1088#define CB_SHADER_MASK 0x2823c
1089
1090#define GDS_ADDR_BASE 0x28720
1091
1092#define CB_IMMED0_BASE 0x28b9c
1093#define CB_IMMED1_BASE 0x28ba0
1094#define CB_IMMED2_BASE 0x28ba4
1095#define CB_IMMED3_BASE 0x28ba8
1096#define CB_IMMED4_BASE 0x28bac
1097#define CB_IMMED5_BASE 0x28bb0
1098#define CB_IMMED6_BASE 0x28bb4
1099#define CB_IMMED7_BASE 0x28bb8
1100#define CB_IMMED8_BASE 0x28bbc
1101#define CB_IMMED9_BASE 0x28bc0
1102#define CB_IMMED10_BASE 0x28bc4
1103#define CB_IMMED11_BASE 0x28bc8
1104
1105/* all 12 CB blocks have these regs */
1106#define CB_COLOR0_BASE 0x28c60
1107#define CB_COLOR0_PITCH 0x28c64
1108#define CB_COLOR0_SLICE 0x28c68
1109#define CB_COLOR0_VIEW 0x28c6c
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1110#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
1111#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
1112#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
1113#define C_028C6C_SLICE_START 0xFFFFF800
1114#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1115#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1116#define C_028C6C_SLICE_MAX 0xFF001FFF
1117#define R_028C70_CB_COLOR0_INFO 0x028C70
1118#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
1119#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
1120#define C_028C70_ENDIAN 0xFFFFFFFC
1121#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
1122#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
1123#define C_028C70_FORMAT 0xFFFFFF03
1124#define V_028C70_COLOR_INVALID 0x00000000
1125#define V_028C70_COLOR_8 0x00000001
1126#define V_028C70_COLOR_4_4 0x00000002
1127#define V_028C70_COLOR_3_3_2 0x00000003
1128#define V_028C70_COLOR_16 0x00000005
1129#define V_028C70_COLOR_16_FLOAT 0x00000006
1130#define V_028C70_COLOR_8_8 0x00000007
1131#define V_028C70_COLOR_5_6_5 0x00000008
1132#define V_028C70_COLOR_6_5_5 0x00000009
1133#define V_028C70_COLOR_1_5_5_5 0x0000000A
1134#define V_028C70_COLOR_4_4_4_4 0x0000000B
1135#define V_028C70_COLOR_5_5_5_1 0x0000000C
1136#define V_028C70_COLOR_32 0x0000000D
1137#define V_028C70_COLOR_32_FLOAT 0x0000000E
1138#define V_028C70_COLOR_16_16 0x0000000F
1139#define V_028C70_COLOR_16_16_FLOAT 0x00000010
1140#define V_028C70_COLOR_8_24 0x00000011
1141#define V_028C70_COLOR_8_24_FLOAT 0x00000012
1142#define V_028C70_COLOR_24_8 0x00000013
1143#define V_028C70_COLOR_24_8_FLOAT 0x00000014
1144#define V_028C70_COLOR_10_11_11 0x00000015
1145#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
1146#define V_028C70_COLOR_11_11_10 0x00000017
1147#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
1148#define V_028C70_COLOR_2_10_10_10 0x00000019
1149#define V_028C70_COLOR_8_8_8_8 0x0000001A
1150#define V_028C70_COLOR_10_10_10_2 0x0000001B
1151#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
1152#define V_028C70_COLOR_32_32 0x0000001D
1153#define V_028C70_COLOR_32_32_FLOAT 0x0000001E
1154#define V_028C70_COLOR_16_16_16_16 0x0000001F
1155#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
1156#define V_028C70_COLOR_32_32_32_32 0x00000022
1157#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
1158#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
1159#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
1160#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1161#define C_028C70_ARRAY_MODE 0xFFFFF0FF
1162#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
1163#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
1164#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
1165#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
1166#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1167#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1168#define C_028C70_NUMBER_TYPE 0xFFFF8FFF
1169#define V_028C70_NUMBER_UNORM 0x00000000
1170#define V_028C70_NUMBER_SNORM 0x00000001
1171#define V_028C70_NUMBER_USCALED 0x00000002
1172#define V_028C70_NUMBER_SSCALED 0x00000003
1173#define V_028C70_NUMBER_UINT 0x00000004
1174#define V_028C70_NUMBER_SINT 0x00000005
1175#define V_028C70_NUMBER_SRGB 0x00000006
1176#define V_028C70_NUMBER_FLOAT 0x00000007
1177#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
1178#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
1179#define C_028C70_COMP_SWAP 0xFFFE7FFF
1180#define V_028C70_SWAP_STD 0x00000000
1181#define V_028C70_SWAP_ALT 0x00000001
1182#define V_028C70_SWAP_STD_REV 0x00000002
1183#define V_028C70_SWAP_ALT_REV 0x00000003
1184#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
1185#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
1186#define C_028C70_FAST_CLEAR 0xFFFDFFFF
1187#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
1188#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
1189#define C_028C70_COMPRESSION 0xFFF3FFFF
1190#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
1191#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
1192#define C_028C70_BLEND_CLAMP 0xFFF7FFFF
1193#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
1194#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
1195#define C_028C70_BLEND_BYPASS 0xFFEFFFFF
1196#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
1197#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
1198#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
1199#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
1200#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
1201#define C_028C70_ROUND_MODE 0xFFBFFFFF
1202#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
1203#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
1204#define C_028C70_TILE_COMPACT 0xFF7FFFFF
1205#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
1206#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
1207#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
1208#define V_028C70_EXPORT_4C_32BPC 0x0
1209#define V_028C70_EXPORT_4C_16BPC 0x1
1210#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
1211#define S_028C70_RAT(x) (((x) & 0x1) << 26)
1212#define G_028C70_RAT(x) (((x) >> 26) & 0x1)
1213#define C_028C70_RAT 0xFBFFFFFF
1214#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
1215#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
1216#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
1217
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1218#define CB_COLOR0_INFO 0x28c70
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1219# define CB_FORMAT(x) ((x) << 2)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1220# define CB_ARRAY_MODE(x) ((x) << 8)
1221# define ARRAY_LINEAR_GENERAL 0
1222# define ARRAY_LINEAR_ALIGNED 1
1223# define ARRAY_1D_TILED_THIN1 2
1224# define ARRAY_2D_TILED_THIN1 4
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1225# define CB_SOURCE_FORMAT(x) ((x) << 24)
1226# define CB_SF_EXPORT_FULL 0
1227# define CB_SF_EXPORT_NORM 1
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1228#define R_028C74_CB_COLOR0_ATTRIB 0x028C74
1229#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
1230#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
1231#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
1232#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
1233#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
1234#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
1235#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
1236#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
1237#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
1238#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1239#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
1240#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1241#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1242#define CB_COLOR0_ATTRIB 0x28c74
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1243# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
1244# define ADDR_SURF_TILE_SPLIT_64B 0
1245# define ADDR_SURF_TILE_SPLIT_128B 1
1246# define ADDR_SURF_TILE_SPLIT_256B 2
1247# define ADDR_SURF_TILE_SPLIT_512B 3
1248# define ADDR_SURF_TILE_SPLIT_1KB 4
1249# define ADDR_SURF_TILE_SPLIT_2KB 5
1250# define ADDR_SURF_TILE_SPLIT_4KB 6
1251# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
1252# define ADDR_SURF_2_BANK 0
1253# define ADDR_SURF_4_BANK 1
1254# define ADDR_SURF_8_BANK 2
1255# define ADDR_SURF_16_BANK 3
1256# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
1257# define ADDR_SURF_BANK_WIDTH_1 0
1258# define ADDR_SURF_BANK_WIDTH_2 1
1259# define ADDR_SURF_BANK_WIDTH_4 2
1260# define ADDR_SURF_BANK_WIDTH_8 3
1261# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1262# define ADDR_SURF_BANK_HEIGHT_1 0
1263# define ADDR_SURF_BANK_HEIGHT_2 1
1264# define ADDR_SURF_BANK_HEIGHT_4 2
1265# define ADDR_SURF_BANK_HEIGHT_8 3
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1266# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1267#define CB_COLOR0_DIM 0x28c78
1268/* only CB0-7 blocks have these regs */
1269#define CB_COLOR0_CMASK 0x28c7c
1270#define CB_COLOR0_CMASK_SLICE 0x28c80
1271#define CB_COLOR0_FMASK 0x28c84
1272#define CB_COLOR0_FMASK_SLICE 0x28c88
1273#define CB_COLOR0_CLEAR_WORD0 0x28c8c
1274#define CB_COLOR0_CLEAR_WORD1 0x28c90
1275#define CB_COLOR0_CLEAR_WORD2 0x28c94
1276#define CB_COLOR0_CLEAR_WORD3 0x28c98
1277
1278#define CB_COLOR1_BASE 0x28c9c
1279#define CB_COLOR2_BASE 0x28cd8
1280#define CB_COLOR3_BASE 0x28d14
1281#define CB_COLOR4_BASE 0x28d50
1282#define CB_COLOR5_BASE 0x28d8c
1283#define CB_COLOR6_BASE 0x28dc8
1284#define CB_COLOR7_BASE 0x28e04
1285#define CB_COLOR8_BASE 0x28e40
1286#define CB_COLOR9_BASE 0x28e5c
1287#define CB_COLOR10_BASE 0x28e78
1288#define CB_COLOR11_BASE 0x28e94
1289
1290#define CB_COLOR1_PITCH 0x28ca0
1291#define CB_COLOR2_PITCH 0x28cdc
1292#define CB_COLOR3_PITCH 0x28d18
1293#define CB_COLOR4_PITCH 0x28d54
1294#define CB_COLOR5_PITCH 0x28d90
1295#define CB_COLOR6_PITCH 0x28dcc
1296#define CB_COLOR7_PITCH 0x28e08
1297#define CB_COLOR8_PITCH 0x28e44
1298#define CB_COLOR9_PITCH 0x28e60
1299#define CB_COLOR10_PITCH 0x28e7c
1300#define CB_COLOR11_PITCH 0x28e98
1301
1302#define CB_COLOR1_SLICE 0x28ca4
1303#define CB_COLOR2_SLICE 0x28ce0
1304#define CB_COLOR3_SLICE 0x28d1c
1305#define CB_COLOR4_SLICE 0x28d58
1306#define CB_COLOR5_SLICE 0x28d94
1307#define CB_COLOR6_SLICE 0x28dd0
1308#define CB_COLOR7_SLICE 0x28e0c
1309#define CB_COLOR8_SLICE 0x28e48
1310#define CB_COLOR9_SLICE 0x28e64
1311#define CB_COLOR10_SLICE 0x28e80
1312#define CB_COLOR11_SLICE 0x28e9c
1313
1314#define CB_COLOR1_VIEW 0x28ca8
1315#define CB_COLOR2_VIEW 0x28ce4
1316#define CB_COLOR3_VIEW 0x28d20
1317#define CB_COLOR4_VIEW 0x28d5c
1318#define CB_COLOR5_VIEW 0x28d98
1319#define CB_COLOR6_VIEW 0x28dd4
1320#define CB_COLOR7_VIEW 0x28e10
1321#define CB_COLOR8_VIEW 0x28e4c
1322#define CB_COLOR9_VIEW 0x28e68
1323#define CB_COLOR10_VIEW 0x28e84
1324#define CB_COLOR11_VIEW 0x28ea0
1325
1326#define CB_COLOR1_INFO 0x28cac
1327#define CB_COLOR2_INFO 0x28ce8
1328#define CB_COLOR3_INFO 0x28d24
1329#define CB_COLOR4_INFO 0x28d60
1330#define CB_COLOR5_INFO 0x28d9c
1331#define CB_COLOR6_INFO 0x28dd8
1332#define CB_COLOR7_INFO 0x28e14
1333#define CB_COLOR8_INFO 0x28e50
1334#define CB_COLOR9_INFO 0x28e6c
1335#define CB_COLOR10_INFO 0x28e88
1336#define CB_COLOR11_INFO 0x28ea4
1337
1338#define CB_COLOR1_ATTRIB 0x28cb0
1339#define CB_COLOR2_ATTRIB 0x28cec
1340#define CB_COLOR3_ATTRIB 0x28d28
1341#define CB_COLOR4_ATTRIB 0x28d64
1342#define CB_COLOR5_ATTRIB 0x28da0
1343#define CB_COLOR6_ATTRIB 0x28ddc
1344#define CB_COLOR7_ATTRIB 0x28e18
1345#define CB_COLOR8_ATTRIB 0x28e54
1346#define CB_COLOR9_ATTRIB 0x28e70
1347#define CB_COLOR10_ATTRIB 0x28e8c
1348#define CB_COLOR11_ATTRIB 0x28ea8
1349
1350#define CB_COLOR1_DIM 0x28cb4
1351#define CB_COLOR2_DIM 0x28cf0
1352#define CB_COLOR3_DIM 0x28d2c
1353#define CB_COLOR4_DIM 0x28d68
1354#define CB_COLOR5_DIM 0x28da4
1355#define CB_COLOR6_DIM 0x28de0
1356#define CB_COLOR7_DIM 0x28e1c
1357#define CB_COLOR8_DIM 0x28e58
1358#define CB_COLOR9_DIM 0x28e74
1359#define CB_COLOR10_DIM 0x28e90
1360#define CB_COLOR11_DIM 0x28eac
1361
1362#define CB_COLOR1_CMASK 0x28cb8
1363#define CB_COLOR2_CMASK 0x28cf4
1364#define CB_COLOR3_CMASK 0x28d30
1365#define CB_COLOR4_CMASK 0x28d6c
1366#define CB_COLOR5_CMASK 0x28da8
1367#define CB_COLOR6_CMASK 0x28de4
1368#define CB_COLOR7_CMASK 0x28e20
1369
1370#define CB_COLOR1_CMASK_SLICE 0x28cbc
1371#define CB_COLOR2_CMASK_SLICE 0x28cf8
1372#define CB_COLOR3_CMASK_SLICE 0x28d34
1373#define CB_COLOR4_CMASK_SLICE 0x28d70
1374#define CB_COLOR5_CMASK_SLICE 0x28dac
1375#define CB_COLOR6_CMASK_SLICE 0x28de8
1376#define CB_COLOR7_CMASK_SLICE 0x28e24
1377
1378#define CB_COLOR1_FMASK 0x28cc0
1379#define CB_COLOR2_FMASK 0x28cfc
1380#define CB_COLOR3_FMASK 0x28d38
1381#define CB_COLOR4_FMASK 0x28d74
1382#define CB_COLOR5_FMASK 0x28db0
1383#define CB_COLOR6_FMASK 0x28dec
1384#define CB_COLOR7_FMASK 0x28e28
1385
1386#define CB_COLOR1_FMASK_SLICE 0x28cc4
1387#define CB_COLOR2_FMASK_SLICE 0x28d00
1388#define CB_COLOR3_FMASK_SLICE 0x28d3c
1389#define CB_COLOR4_FMASK_SLICE 0x28d78
1390#define CB_COLOR5_FMASK_SLICE 0x28db4
1391#define CB_COLOR6_FMASK_SLICE 0x28df0
1392#define CB_COLOR7_FMASK_SLICE 0x28e2c
1393
1394#define CB_COLOR1_CLEAR_WORD0 0x28cc8
1395#define CB_COLOR2_CLEAR_WORD0 0x28d04
1396#define CB_COLOR3_CLEAR_WORD0 0x28d40
1397#define CB_COLOR4_CLEAR_WORD0 0x28d7c
1398#define CB_COLOR5_CLEAR_WORD0 0x28db8
1399#define CB_COLOR6_CLEAR_WORD0 0x28df4
1400#define CB_COLOR7_CLEAR_WORD0 0x28e30
1401
1402#define CB_COLOR1_CLEAR_WORD1 0x28ccc
1403#define CB_COLOR2_CLEAR_WORD1 0x28d08
1404#define CB_COLOR3_CLEAR_WORD1 0x28d44
1405#define CB_COLOR4_CLEAR_WORD1 0x28d80
1406#define CB_COLOR5_CLEAR_WORD1 0x28dbc
1407#define CB_COLOR6_CLEAR_WORD1 0x28df8
1408#define CB_COLOR7_CLEAR_WORD1 0x28e34
1409
1410#define CB_COLOR1_CLEAR_WORD2 0x28cd0
1411#define CB_COLOR2_CLEAR_WORD2 0x28d0c
1412#define CB_COLOR3_CLEAR_WORD2 0x28d48
1413#define CB_COLOR4_CLEAR_WORD2 0x28d84
1414#define CB_COLOR5_CLEAR_WORD2 0x28dc0
1415#define CB_COLOR6_CLEAR_WORD2 0x28dfc
1416#define CB_COLOR7_CLEAR_WORD2 0x28e38
1417
1418#define CB_COLOR1_CLEAR_WORD3 0x28cd4
1419#define CB_COLOR2_CLEAR_WORD3 0x28d10
1420#define CB_COLOR3_CLEAR_WORD3 0x28d4c
1421#define CB_COLOR4_CLEAR_WORD3 0x28d88
1422#define CB_COLOR5_CLEAR_WORD3 0x28dc4
1423#define CB_COLOR6_CLEAR_WORD3 0x28e00
1424#define CB_COLOR7_CLEAR_WORD3 0x28e3c
1425
1426#define SQ_TEX_RESOURCE_WORD0_0 0x30000
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1427# define TEX_DIM(x) ((x) << 0)
1428# define SQ_TEX_DIM_1D 0
1429# define SQ_TEX_DIM_2D 1
1430# define SQ_TEX_DIM_3D 2
1431# define SQ_TEX_DIM_CUBEMAP 3
1432# define SQ_TEX_DIM_1D_ARRAY 4
1433# define SQ_TEX_DIM_2D_ARRAY 5
1434# define SQ_TEX_DIM_2D_MSAA 6
1435# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1436#define SQ_TEX_RESOURCE_WORD1_0 0x30004
1437# define TEX_ARRAY_MODE(x) ((x) << 28)
1438#define SQ_TEX_RESOURCE_WORD2_0 0x30008
1439#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1440#define SQ_TEX_RESOURCE_WORD4_0 0x30010
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1441# define TEX_DST_SEL_X(x) ((x) << 16)
1442# define TEX_DST_SEL_Y(x) ((x) << 19)
1443# define TEX_DST_SEL_Z(x) ((x) << 22)
1444# define TEX_DST_SEL_W(x) ((x) << 25)
1445# define SQ_SEL_X 0
1446# define SQ_SEL_Y 1
1447# define SQ_SEL_Z 2
1448# define SQ_SEL_W 3
1449# define SQ_SEL_0 4
1450# define SQ_SEL_1 5
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1451#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1452#define SQ_TEX_RESOURCE_WORD6_0 0x30018
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1453# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1454#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1455# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
Alex Deucherf3a71df2011-11-28 14:49:28 -0500[diff] [blame]1456# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1457# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1458# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
Jerome Glisse285484e2011-12-16 17:03:42 -0500[diff] [blame]1459#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
1460#define S_030000_DIM(x) (((x) & 0x7) << 0)
1461#define G_030000_DIM(x) (((x) >> 0) & 0x7)
1462#define C_030000_DIM 0xFFFFFFF8
1463#define V_030000_SQ_TEX_DIM_1D 0x00000000
1464#define V_030000_SQ_TEX_DIM_2D 0x00000001
1465#define V_030000_SQ_TEX_DIM_3D 0x00000002
1466#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
1467#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1468#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1469#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
1470#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1471#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
1472#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
1473#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
1474#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
1475#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
1476#define C_030000_PITCH 0xFFFC003F
1477#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
1478#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
1479#define C_030000_TEX_WIDTH 0x0003FFFF
1480#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
1481#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
1482#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
1483#define C_030004_TEX_HEIGHT 0xFFFFC000
1484#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
1485#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
1486#define C_030004_TEX_DEPTH 0xF8003FFF
1487#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
1488#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
1489#define C_030004_ARRAY_MODE 0x0FFFFFFF
1490#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
1491#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1492#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1493#define C_030008_BASE_ADDRESS 0x00000000
1494#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
1495#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1496#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1497#define C_03000C_MIP_ADDRESS 0x00000000
1498#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
1499#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1500#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1501#define C_030010_FORMAT_COMP_X 0xFFFFFFFC
1502#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
1503#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
1504#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
1505#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1506#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1507#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
1508#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1509#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1510#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
1511#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1512#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1513#define C_030010_FORMAT_COMP_W 0xFFFFFF3F
1514#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1515#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1516#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
1517#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
1518#define V_030010_SQ_NUM_FORMAT_INT 0x00000001
1519#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
1520#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1521#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1522#define C_030010_SRF_MODE_ALL 0xFFFFFBFF
1523#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
1524#define V_030010_SRF_MODE_NO_ZERO 0x00000001
1525#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1526#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1527#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
1528#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1529#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1530#define C_030010_ENDIAN_SWAP 0xFFFFCFFF
1531#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
1532#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1533#define C_030010_DST_SEL_X 0xFFF8FFFF
1534#define V_030010_SQ_SEL_X 0x00000000
1535#define V_030010_SQ_SEL_Y 0x00000001
1536#define V_030010_SQ_SEL_Z 0x00000002
1537#define V_030010_SQ_SEL_W 0x00000003
1538#define V_030010_SQ_SEL_0 0x00000004
1539#define V_030010_SQ_SEL_1 0x00000005
1540#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1541#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1542#define C_030010_DST_SEL_Y 0xFFC7FFFF
1543#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1544#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1545#define C_030010_DST_SEL_Z 0xFE3FFFFF
1546#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
1547#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1548#define C_030010_DST_SEL_W 0xF1FFFFFF
1549#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1550#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1551#define C_030010_BASE_LEVEL 0x0FFFFFFF
1552#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
1553#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1554#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1555#define C_030014_LAST_LEVEL 0xFFFFFFF0
1556#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1557#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1558#define C_030014_BASE_ARRAY 0xFFFE000F
1559#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1560#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1561#define C_030014_LAST_ARRAY 0xC001FFFF
1562#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
1563#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
1564#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
1565#define C_030018_MAX_ANISO 0xFFFFFFF8
1566#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
1567#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
1568#define C_030018_PERF_MODULATION 0xFFFFFFC7
1569#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
1570#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
1571#define C_030018_INTERLACED 0xFFFFFFBF
1572#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
1573#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
1574#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
1575#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
1576#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
1577#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
1578#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
1579#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1580#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
1581#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
1582#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
1583#define S_03001C_TYPE(x) (((x) & 0x3) << 30)
1584#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
1585#define C_03001C_TYPE 0x3FFFFFFF
1586#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
1587#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
1588#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
1589#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
1590#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
1591#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
1592#define C_03001C_DATA_FORMAT 0xFFFFFFC0
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1593
Ilija Hadzic6018faf2011-10-12 23:29:36 -0400[diff] [blame]1594#define SQ_VTX_CONSTANT_WORD0_0 0x30000
1595#define SQ_VTX_CONSTANT_WORD1_0 0x30004
1596#define SQ_VTX_CONSTANT_WORD2_0 0x30008
1597# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
1598# define SQ_VTXC_STRIDE(x) ((x) << 8)
1599# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
1600# define SQ_ENDIAN_NONE 0
1601# define SQ_ENDIAN_8IN16 1
1602# define SQ_ENDIAN_8IN32 2
1603#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
1604# define SQ_VTCX_SEL_X(x) ((x) << 3)
1605# define SQ_VTCX_SEL_Y(x) ((x) << 6)
1606# define SQ_VTCX_SEL_Z(x) ((x) << 9)
1607# define SQ_VTCX_SEL_W(x) ((x) << 12)
1608#define SQ_VTX_CONSTANT_WORD4_0 0x30010
1609#define SQ_VTX_CONSTANT_WORD5_0 0x30014
1610#define SQ_VTX_CONSTANT_WORD6_0 0x30018
1611#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
1612
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]1613#define TD_PS_BORDER_COLOR_INDEX 0xA400
1614#define TD_PS_BORDER_COLOR_RED 0xA404
1615#define TD_PS_BORDER_COLOR_GREEN 0xA408
1616#define TD_PS_BORDER_COLOR_BLUE 0xA40C
1617#define TD_PS_BORDER_COLOR_ALPHA 0xA410
1618#define TD_VS_BORDER_COLOR_INDEX 0xA414
1619#define TD_VS_BORDER_COLOR_RED 0xA418
1620#define TD_VS_BORDER_COLOR_GREEN 0xA41C
1621#define TD_VS_BORDER_COLOR_BLUE 0xA420
1622#define TD_VS_BORDER_COLOR_ALPHA 0xA424
1623#define TD_GS_BORDER_COLOR_INDEX 0xA428
1624#define TD_GS_BORDER_COLOR_RED 0xA42C
1625#define TD_GS_BORDER_COLOR_GREEN 0xA430
1626#define TD_GS_BORDER_COLOR_BLUE 0xA434
1627#define TD_GS_BORDER_COLOR_ALPHA 0xA438
1628#define TD_HS_BORDER_COLOR_INDEX 0xA43C
1629#define TD_HS_BORDER_COLOR_RED 0xA440
1630#define TD_HS_BORDER_COLOR_GREEN 0xA444
1631#define TD_HS_BORDER_COLOR_BLUE 0xA448
1632#define TD_HS_BORDER_COLOR_ALPHA 0xA44C
1633#define TD_LS_BORDER_COLOR_INDEX 0xA450
1634#define TD_LS_BORDER_COLOR_RED 0xA454
1635#define TD_LS_BORDER_COLOR_GREEN 0xA458
1636#define TD_LS_BORDER_COLOR_BLUE 0xA45C
1637#define TD_LS_BORDER_COLOR_ALPHA 0xA460
1638#define TD_CS_BORDER_COLOR_INDEX 0xA464
1639#define TD_CS_BORDER_COLOR_RED 0xA468
1640#define TD_CS_BORDER_COLOR_GREEN 0xA46C
1641#define TD_CS_BORDER_COLOR_BLUE 0xA470
1642#define TD_CS_BORDER_COLOR_ALPHA 0xA474
1643
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1644/* cayman 3D regs */
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]1645#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
1646#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1647#define CAYMAN_DB_EQAA 0x28804
1648#define CAYMAN_DB_DEPTH_INFO 0x2803C
1649#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1650#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1651#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
Alex Deucher033b5652011-06-08 15:26:45 -0400[diff] [blame]1652#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
Alex Deucherc175ca92011-03-02 20:07:37 -0500[diff] [blame]1653/* cayman packet3 addition */
1654#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]1655
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]1656#endif