| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/include/asm/arch-s3c2410/regs-adc.h |
| 2 | * |
| 3 | * Copyright (c) 2004 Shannon Holland <holland@loser.net> |
| 4 | * |
| 5 | * This program is free software; yosu can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * S3C2410 ADC registers |
| 10 | * |
| 11 | * Changelog: |
| 12 | * 27-09-2004 SAH Created file |
| 13 | */ |
| 14 | |
| 15 | #ifndef __ASM_ARCH_REGS_ADC_H |
| 16 | #define __ASM_ARCH_REGS_ADC_H "regs-adc.h" |
| 17 | |
| 18 | #define S3C2410_ADCREG(x) (x) |
| 19 | |
| 20 | #define S3C2410_ADCCON S3C2410_ADCREG(0x00) |
| 21 | #define S3C2410_ADCTSC S3C2410_ADCREG(0x04) |
| 22 | #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) |
| 23 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) |
| 24 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) |
| 25 | |
| 26 | |
| 27 | /* ADCCON Register Bits */ |
| 28 | #define S3C2410_ADCCON_ECFLG (1<<15) |
| 29 | #define S3C2410_ADCCON_PRSCEN (1<<14) |
| 30 | #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) |
| 31 | #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) |
| 32 | #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) |
| 33 | #define S3C2410_ADCCON_MUXMASK (0x7<<3) |
| 34 | #define S3C2410_ADCCON_STDBM (1<<2) |
| 35 | #define S3C2410_ADCCON_READ_START (1<<1) |
| 36 | #define S3C2410_ADCCON_ENABLE_START (1<<0) |
| 37 | #define S3C2410_ADCCON_STARTMASK (0x3<<0) |
| 38 | |
| 39 | |
| 40 | /* ADCTSC Register Bits */ |
| 41 | #define S3C2410_ADCTSC_YM_SEN (1<<7) |
| 42 | #define S3C2410_ADCTSC_YP_SEN (1<<6) |
| 43 | #define S3C2410_ADCTSC_XM_SEN (1<<5) |
| 44 | #define S3C2410_ADCTSC_XP_SEN (1<<4) |
| 45 | #define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) |
| 46 | #define S3C2410_ADCTSC_AUTO_PST (1<<2) |
| 47 | #define S3C2410_ADCTSC_XY_PST (0x3<<0) |
| 48 | |
| 49 | /* ADCDAT0 Bits */ |
| 50 | #define S3C2410_ADCDAT0_UPDOWN (1<<15) |
| 51 | #define S3C2410_ADCDAT0_AUTO_PST (1<<14) |
| 52 | #define S3C2410_ADCDAT0_XY_PST (0x3<<12) |
| 53 | #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) |
| 54 | |
| 55 | /* ADCDAT1 Bits */ |
| 56 | #define S3C2410_ADCDAT1_UPDOWN (1<<15) |
| 57 | #define S3C2410_ADCDAT1_AUTO_PST (1<<14) |
| 58 | #define S3C2410_ADCDAT1_XY_PST (0x3<<12) |
| 59 | #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) |
| 60 | |
| 61 | #endif /* __ASM_ARCH_REGS_ADC_H */ |
| 62 | |
| 63 | |