| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * linux/include/asm-arm/arch-sa1100/irqs.h | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 1996 Russell King | 
|  | 5 | * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). | 
|  | 6 | * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) | 
|  | 7 | * | 
|  | 8 | * 2001/11/14	RMK	Cleaned up and standardised a lot of the IRQs. | 
|  | 9 | */ | 
|  | 10 | #include <linux/config.h> | 
|  | 11 |  | 
|  | 12 | #define	IRQ_GPIO0		0 | 
|  | 13 | #define	IRQ_GPIO1		1 | 
|  | 14 | #define	IRQ_GPIO2		2 | 
|  | 15 | #define	IRQ_GPIO3		3 | 
|  | 16 | #define	IRQ_GPIO4		4 | 
|  | 17 | #define	IRQ_GPIO5		5 | 
|  | 18 | #define	IRQ_GPIO6		6 | 
|  | 19 | #define	IRQ_GPIO7		7 | 
|  | 20 | #define	IRQ_GPIO8		8 | 
|  | 21 | #define	IRQ_GPIO9		9 | 
|  | 22 | #define	IRQ_GPIO10		10 | 
|  | 23 | #define	IRQ_GPIO11_27		11 | 
|  | 24 | #define	IRQ_LCD  		12	/* LCD controller           */ | 
|  | 25 | #define	IRQ_Ser0UDC		13	/* Ser. port 0 UDC          */ | 
|  | 26 | #define	IRQ_Ser1SDLC		14	/* Ser. port 1 SDLC         */ | 
|  | 27 | #define	IRQ_Ser1UART		15	/* Ser. port 1 UART         */ | 
|  | 28 | #define	IRQ_Ser2ICP		16	/* Ser. port 2 ICP          */ | 
|  | 29 | #define	IRQ_Ser3UART		17	/* Ser. port 3 UART         */ | 
|  | 30 | #define	IRQ_Ser4MCP		18	/* Ser. port 4 MCP          */ | 
|  | 31 | #define	IRQ_Ser4SSP		19	/* Ser. port 4 SSP          */ | 
|  | 32 | #define	IRQ_DMA0 		20	/* DMA controller channel 0 */ | 
|  | 33 | #define	IRQ_DMA1 		21	/* DMA controller channel 1 */ | 
|  | 34 | #define	IRQ_DMA2 		22	/* DMA controller channel 2 */ | 
|  | 35 | #define	IRQ_DMA3 		23	/* DMA controller channel 3 */ | 
|  | 36 | #define	IRQ_DMA4 		24	/* DMA controller channel 4 */ | 
|  | 37 | #define	IRQ_DMA5 		25	/* DMA controller channel 5 */ | 
|  | 38 | #define	IRQ_OST0 		26	/* OS Timer match 0         */ | 
|  | 39 | #define	IRQ_OST1 		27	/* OS Timer match 1         */ | 
|  | 40 | #define	IRQ_OST2 		28	/* OS Timer match 2         */ | 
|  | 41 | #define	IRQ_OST3 		29	/* OS Timer match 3         */ | 
|  | 42 | #define	IRQ_RTC1Hz		30	/* RTC 1 Hz clock           */ | 
|  | 43 | #define	IRQ_RTCAlrm		31	/* RTC Alarm                */ | 
|  | 44 |  | 
|  | 45 | #define	IRQ_GPIO11		32 | 
|  | 46 | #define	IRQ_GPIO12		33 | 
|  | 47 | #define	IRQ_GPIO13		34 | 
|  | 48 | #define	IRQ_GPIO14		35 | 
|  | 49 | #define	IRQ_GPIO15		36 | 
|  | 50 | #define	IRQ_GPIO16		37 | 
|  | 51 | #define	IRQ_GPIO17		38 | 
|  | 52 | #define	IRQ_GPIO18		39 | 
|  | 53 | #define	IRQ_GPIO19		40 | 
|  | 54 | #define	IRQ_GPIO20		41 | 
|  | 55 | #define	IRQ_GPIO21		42 | 
|  | 56 | #define	IRQ_GPIO22		43 | 
|  | 57 | #define	IRQ_GPIO23		44 | 
|  | 58 | #define	IRQ_GPIO24		45 | 
|  | 59 | #define	IRQ_GPIO25		46 | 
|  | 60 | #define	IRQ_GPIO26		47 | 
|  | 61 | #define	IRQ_GPIO27		48 | 
|  | 62 |  | 
|  | 63 | /* | 
|  | 64 | * The next 16 interrupts are for board specific purposes.  Since | 
|  | 65 | * the kernel can only run on one machine at a time, we can re-use | 
|  | 66 | * these.  If you need more, increase IRQ_BOARD_END, but keep it | 
|  | 67 | * within sensible limits.  IRQs 49 to 64 are available. | 
|  | 68 | */ | 
|  | 69 | #define IRQ_BOARD_START		49 | 
|  | 70 | #define IRQ_BOARD_END		65 | 
|  | 71 |  | 
|  | 72 | #define IRQ_SA1111_START	(IRQ_BOARD_END) | 
|  | 73 | #define IRQ_GPAIN0		(IRQ_BOARD_END + 0) | 
|  | 74 | #define IRQ_GPAIN1		(IRQ_BOARD_END + 1) | 
|  | 75 | #define IRQ_GPAIN2		(IRQ_BOARD_END + 2) | 
|  | 76 | #define IRQ_GPAIN3		(IRQ_BOARD_END + 3) | 
|  | 77 | #define IRQ_GPBIN0		(IRQ_BOARD_END + 4) | 
|  | 78 | #define IRQ_GPBIN1		(IRQ_BOARD_END + 5) | 
|  | 79 | #define IRQ_GPBIN2		(IRQ_BOARD_END + 6) | 
|  | 80 | #define IRQ_GPBIN3		(IRQ_BOARD_END + 7) | 
|  | 81 | #define IRQ_GPBIN4		(IRQ_BOARD_END + 8) | 
|  | 82 | #define IRQ_GPBIN5		(IRQ_BOARD_END + 9) | 
|  | 83 | #define IRQ_GPCIN0		(IRQ_BOARD_END + 10) | 
|  | 84 | #define IRQ_GPCIN1		(IRQ_BOARD_END + 11) | 
|  | 85 | #define IRQ_GPCIN2		(IRQ_BOARD_END + 12) | 
|  | 86 | #define IRQ_GPCIN3		(IRQ_BOARD_END + 13) | 
|  | 87 | #define IRQ_GPCIN4		(IRQ_BOARD_END + 14) | 
|  | 88 | #define IRQ_GPCIN5		(IRQ_BOARD_END + 15) | 
|  | 89 | #define IRQ_GPCIN6		(IRQ_BOARD_END + 16) | 
|  | 90 | #define IRQ_GPCIN7		(IRQ_BOARD_END + 17) | 
|  | 91 | #define IRQ_MSTXINT		(IRQ_BOARD_END + 18) | 
|  | 92 | #define IRQ_MSRXINT		(IRQ_BOARD_END + 19) | 
|  | 93 | #define IRQ_MSSTOPERRINT	(IRQ_BOARD_END + 20) | 
|  | 94 | #define IRQ_TPTXINT		(IRQ_BOARD_END + 21) | 
|  | 95 | #define IRQ_TPRXINT		(IRQ_BOARD_END + 22) | 
|  | 96 | #define IRQ_TPSTOPERRINT	(IRQ_BOARD_END + 23) | 
|  | 97 | #define SSPXMTINT		(IRQ_BOARD_END + 24) | 
|  | 98 | #define SSPRCVINT		(IRQ_BOARD_END + 25) | 
|  | 99 | #define SSPROR			(IRQ_BOARD_END + 26) | 
|  | 100 | #define AUDXMTDMADONEA		(IRQ_BOARD_END + 32) | 
|  | 101 | #define AUDRCVDMADONEA		(IRQ_BOARD_END + 33) | 
|  | 102 | #define AUDXMTDMADONEB		(IRQ_BOARD_END + 34) | 
|  | 103 | #define AUDRCVDMADONEB		(IRQ_BOARD_END + 35) | 
|  | 104 | #define AUDTFSR			(IRQ_BOARD_END + 36) | 
|  | 105 | #define AUDRFSR			(IRQ_BOARD_END + 37) | 
|  | 106 | #define AUDTUR			(IRQ_BOARD_END + 38) | 
|  | 107 | #define AUDROR			(IRQ_BOARD_END + 39) | 
|  | 108 | #define AUDDTS			(IRQ_BOARD_END + 40) | 
|  | 109 | #define AUDRDD			(IRQ_BOARD_END + 41) | 
|  | 110 | #define AUDSTO			(IRQ_BOARD_END + 42) | 
|  | 111 | #define IRQ_USBPWR		(IRQ_BOARD_END + 43) | 
|  | 112 | #define IRQ_HCIM		(IRQ_BOARD_END + 44) | 
|  | 113 | #define IRQ_HCIBUFFACC		(IRQ_BOARD_END + 45) | 
|  | 114 | #define IRQ_HCIRMTWKP		(IRQ_BOARD_END + 46) | 
|  | 115 | #define IRQ_NHCIMFCIR		(IRQ_BOARD_END + 47) | 
|  | 116 | #define IRQ_USB_PORT_RESUME	(IRQ_BOARD_END + 48) | 
|  | 117 | #define IRQ_S0_READY_NINT	(IRQ_BOARD_END + 49) | 
|  | 118 | #define IRQ_S1_READY_NINT	(IRQ_BOARD_END + 50) | 
|  | 119 | #define IRQ_S0_CD_VALID		(IRQ_BOARD_END + 51) | 
|  | 120 | #define IRQ_S1_CD_VALID		(IRQ_BOARD_END + 52) | 
|  | 121 | #define IRQ_S0_BVD1_STSCHG	(IRQ_BOARD_END + 53) | 
|  | 122 | #define IRQ_S1_BVD1_STSCHG	(IRQ_BOARD_END + 54) | 
|  | 123 |  | 
|  | 124 | #define IRQ_LOCOMO_START	(IRQ_BOARD_END) | 
|  | 125 | #define IRQ_LOCOMO_KEY		(IRQ_BOARD_END + 0) | 
|  | 126 | #define IRQ_LOCOMO_GPIO0	(IRQ_BOARD_END + 1) | 
|  | 127 | #define IRQ_LOCOMO_GPIO1	(IRQ_BOARD_END + 2) | 
|  | 128 | #define IRQ_LOCOMO_GPIO2	(IRQ_BOARD_END + 3) | 
|  | 129 | #define IRQ_LOCOMO_GPIO3	(IRQ_BOARD_END + 4) | 
|  | 130 | #define IRQ_LOCOMO_GPIO4	(IRQ_BOARD_END + 5) | 
|  | 131 | #define IRQ_LOCOMO_GPIO5	(IRQ_BOARD_END + 6) | 
|  | 132 | #define IRQ_LOCOMO_GPIO6	(IRQ_BOARD_END + 7) | 
|  | 133 | #define IRQ_LOCOMO_GPIO7	(IRQ_BOARD_END + 8) | 
|  | 134 | #define IRQ_LOCOMO_GPIO8	(IRQ_BOARD_END + 9) | 
|  | 135 | #define IRQ_LOCOMO_GPIO9	(IRQ_BOARD_END + 10) | 
|  | 136 | #define IRQ_LOCOMO_GPIO10	(IRQ_BOARD_END + 11) | 
|  | 137 | #define IRQ_LOCOMO_GPIO11	(IRQ_BOARD_END + 12) | 
|  | 138 | #define IRQ_LOCOMO_GPIO12	(IRQ_BOARD_END + 13) | 
|  | 139 | #define IRQ_LOCOMO_GPIO13	(IRQ_BOARD_END + 14) | 
|  | 140 | #define IRQ_LOCOMO_GPIO14	(IRQ_BOARD_END + 15) | 
|  | 141 | #define IRQ_LOCOMO_GPIO15	(IRQ_BOARD_END + 16) | 
|  | 142 | #define IRQ_LOCOMO_LT		(IRQ_BOARD_END + 17) | 
|  | 143 | #define IRQ_LOCOMO_SPI_RFR	(IRQ_BOARD_END + 18) | 
|  | 144 | #define IRQ_LOCOMO_SPI_RFW	(IRQ_BOARD_END + 19) | 
|  | 145 | #define IRQ_LOCOMO_SPI_OVRN	(IRQ_BOARD_END + 20) | 
|  | 146 | #define IRQ_LOCOMO_SPI_TEND	(IRQ_BOARD_END + 21) | 
|  | 147 |  | 
|  | 148 | /* | 
|  | 149 | * Figure out the MAX IRQ number. | 
|  | 150 | * | 
|  | 151 | * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. | 
|  | 152 | * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 | 
|  | 153 | * Otherwise, we have the standard IRQs only. | 
|  | 154 | */ | 
|  | 155 | #ifdef CONFIG_SA1111 | 
|  | 156 | #define NR_IRQS			(IRQ_S1_BVD1_STSCHG + 1) | 
|  | 157 | #elif defined(CONFIG_SA1100_H3800) | 
|  | 158 | #define NR_IRQS			(IRQ_BOARD_END) | 
|  | 159 | #elif defined(CONFIG_SHARP_LOCOMO) | 
|  | 160 | #define NR_IRQS			(IRQ_LOCOMO_SPI_TEND + 1) | 
|  | 161 | #else | 
|  | 162 | #define NR_IRQS			(IRQ_BOARD_START) | 
|  | 163 | #endif | 
|  | 164 |  | 
|  | 165 | /* | 
|  | 166 | * Board specific IRQs.  Define them here. | 
|  | 167 | * Do not surround them with ifdefs. | 
|  | 168 | */ | 
|  | 169 | #define IRQ_NEPONSET_SMC9196	(IRQ_BOARD_START + 0) | 
|  | 170 | #define IRQ_NEPONSET_USAR	(IRQ_BOARD_START + 1) | 
|  | 171 | #define IRQ_NEPONSET_SA1111	(IRQ_BOARD_START + 2) | 
|  | 172 |  | 
|  | 173 | /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ | 
|  | 174 | #define IRQ_LOCOMO_KEY_BASE	(IRQ_BOARD_START + 0) | 
|  | 175 | #define IRQ_LOCOMO_GPIO_BASE	(IRQ_BOARD_START + 1) | 
|  | 176 | #define IRQ_LOCOMO_LT_BASE	(IRQ_BOARD_START + 2) | 
|  | 177 | #define IRQ_LOCOMO_SPI_BASE	(IRQ_BOARD_START + 3) | 
|  | 178 |  | 
|  | 179 | /* H3800-specific IRQs (CONFIG_SA1100_H3800) */ | 
|  | 180 | #define H3800_KPIO_IRQ_START    (IRQ_BOARD_START) | 
|  | 181 | #define IRQ_H3800_KEY           (IRQ_BOARD_START + 0) | 
|  | 182 | #define IRQ_H3800_SPI           (IRQ_BOARD_START + 1) | 
|  | 183 | #define IRQ_H3800_OWM           (IRQ_BOARD_START + 2) | 
|  | 184 | #define IRQ_H3800_ADC           (IRQ_BOARD_START + 3) | 
|  | 185 | #define IRQ_H3800_UART_0        (IRQ_BOARD_START + 4) | 
|  | 186 | #define IRQ_H3800_UART_1        (IRQ_BOARD_START + 5) | 
|  | 187 | #define IRQ_H3800_TIMER_0       (IRQ_BOARD_START + 6) | 
|  | 188 | #define IRQ_H3800_TIMER_1       (IRQ_BOARD_START + 7) | 
|  | 189 | #define IRQ_H3800_TIMER_2       (IRQ_BOARD_START + 8) | 
|  | 190 | #define H3800_KPIO_IRQ_COUNT    9 | 
|  | 191 |  | 
|  | 192 | #define H3800_GPIO_IRQ_START    (IRQ_BOARD_START + 9) | 
|  | 193 | #define IRQ_H3800_PEN           (IRQ_BOARD_START + 9) | 
|  | 194 | #define IRQ_H3800_SD_DETECT     (IRQ_BOARD_START + 10) | 
|  | 195 | #define IRQ_H3800_EAR_IN        (IRQ_BOARD_START + 11) | 
|  | 196 | #define IRQ_H3800_USB_DETECT    (IRQ_BOARD_START + 12) | 
|  | 197 | #define IRQ_H3800_SD_CON_SLT    (IRQ_BOARD_START + 13) | 
|  | 198 | #define H3800_GPIO_IRQ_COUNT    5 |