Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * IRQ subsystem internal functions and variables: |
Thomas Gleixner | dbec07b | 2011-02-07 20:19:55 +0100 | [diff] [blame] | 3 | * |
| 4 | * Do not ever include this file from anything else than |
| 5 | * kernel/irq/. Do not even think about using any information outside |
| 6 | * of this file for your non core code. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | */ |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 8 | #include <linux/irqdesc.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | |
Thomas Gleixner | c1ee626 | 2011-02-17 17:45:15 +0100 | [diff] [blame] | 10 | #ifdef CONFIG_SPARSE_IRQ |
| 11 | # define IRQ_BITMAP_BITS (NR_IRQS + 8196) |
| 12 | #else |
| 13 | # define IRQ_BITMAP_BITS NR_IRQS |
| 14 | #endif |
| 15 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 16 | #include "compat.h" |
Thomas Gleixner | e6bea9c | 2011-02-09 13:16:52 +0100 | [diff] [blame] | 17 | #include "settings.h" |
| 18 | |
Thomas Gleixner | dbec07b | 2011-02-07 20:19:55 +0100 | [diff] [blame] | 19 | #define istate core_internal_state__do_not_mess_with_it |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | extern int noirqdebug; |
| 22 | |
Thomas Gleixner | 1535dfa | 2011-02-07 01:55:43 +0100 | [diff] [blame] | 23 | /* |
| 24 | * Bits used by threaded handlers: |
| 25 | * IRQTF_RUNTHREAD - signals that the interrupt handler thread should run |
| 26 | * IRQTF_DIED - handler thread died |
| 27 | * IRQTF_WARNED - warning "IRQ_WAKE_THREAD w/o thread_fn" has been printed |
| 28 | * IRQTF_AFFINITY - irq thread is requested to adjust affinity |
| 29 | */ |
| 30 | enum { |
| 31 | IRQTF_RUNTHREAD, |
| 32 | IRQTF_DIED, |
| 33 | IRQTF_WARNED, |
| 34 | IRQTF_AFFINITY, |
| 35 | }; |
| 36 | |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 37 | /* |
| 38 | * Bit masks for desc->state |
| 39 | * |
| 40 | * IRQS_AUTODETECT - autodetection in progress |
Thomas Gleixner | 7acdd53 | 2011-02-07 20:40:54 +0100 | [diff] [blame] | 41 | * IRQS_SPURIOUS_DISABLED - was disabled due to spurious interrupt |
| 42 | * detection |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 43 | * IRQS_POLL_INPROGRESS - polling in progress |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 44 | * IRQS_INPROGRESS - Interrupt in progress |
Thomas Gleixner | 3d67bae | 2011-02-07 21:02:10 +0100 | [diff] [blame] | 45 | * IRQS_ONESHOT - irq is not unmasked in primary handler |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 46 | * IRQS_REPLAY - irq is replayed |
| 47 | * IRQS_WAITING - irq is waiting |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 48 | * IRQS_DISABLED - irq is disabled |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 49 | * IRQS_PENDING - irq is pending and replayed later |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 50 | * IRQS_MASKED - irq is masked |
Thomas Gleixner | c531e83 | 2011-02-08 12:44:58 +0100 | [diff] [blame^] | 51 | * IRQS_SUSPENDED - irq is suspended |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 52 | */ |
| 53 | enum { |
| 54 | IRQS_AUTODETECT = 0x00000001, |
Thomas Gleixner | 7acdd53 | 2011-02-07 20:40:54 +0100 | [diff] [blame] | 55 | IRQS_SPURIOUS_DISABLED = 0x00000002, |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 56 | IRQS_POLL_INPROGRESS = 0x00000008, |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 57 | IRQS_INPROGRESS = 0x00000010, |
Thomas Gleixner | 3d67bae | 2011-02-07 21:02:10 +0100 | [diff] [blame] | 58 | IRQS_ONESHOT = 0x00000020, |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 59 | IRQS_REPLAY = 0x00000040, |
| 60 | IRQS_WAITING = 0x00000080, |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 61 | IRQS_DISABLED = 0x00000100, |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 62 | IRQS_PENDING = 0x00000200, |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 63 | IRQS_MASKED = 0x00000400, |
Thomas Gleixner | c531e83 | 2011-02-08 12:44:58 +0100 | [diff] [blame^] | 64 | IRQS_SUSPENDED = 0x00000800, |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 65 | }; |
| 66 | |
Thomas Gleixner | a77c463 | 2010-10-01 14:44:58 +0200 | [diff] [blame] | 67 | #define irq_data_to_desc(data) container_of(data, struct irq_desc, irq_data) |
| 68 | |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 69 | /* Set default functions for irq_chip structures: */ |
| 70 | extern void irq_chip_set_defaults(struct irq_chip *chip); |
| 71 | |
| 72 | /* Set default handler: */ |
| 73 | extern void compat_irq_chip_set_default_handler(struct irq_desc *desc); |
| 74 | |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 75 | extern int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, |
| 76 | unsigned long flags); |
Rafael J. Wysocki | 0a0c516 | 2009-03-16 22:33:49 +0100 | [diff] [blame] | 77 | extern void __disable_irq(struct irq_desc *desc, unsigned int irq, bool susp); |
| 78 | extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume); |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 79 | |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 80 | extern int irq_startup(struct irq_desc *desc); |
| 81 | extern void irq_shutdown(struct irq_desc *desc); |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 82 | extern void irq_enable(struct irq_desc *desc); |
| 83 | extern void irq_disable(struct irq_desc *desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 84 | |
Yinghai Lu | 85ac16d | 2009-04-27 18:00:38 -0700 | [diff] [blame] | 85 | extern void init_kstat_irqs(struct irq_desc *desc, int node, int nr); |
Mike Travis | 0fa0ebb | 2009-01-10 22:24:06 -0800 | [diff] [blame] | 86 | |
Thomas Gleixner | 4912609 | 2011-02-07 01:08:49 +0100 | [diff] [blame] | 87 | irqreturn_t handle_irq_event_percpu(struct irq_desc *desc, struct irqaction *action); |
| 88 | irqreturn_t handle_irq_event(struct irq_desc *desc); |
| 89 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 90 | /* Resending of interrupts :*/ |
| 91 | void check_irq_resend(struct irq_desc *desc, unsigned int irq); |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 92 | bool irq_wait_for_poll(struct irq_desc *desc); |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 93 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | #ifdef CONFIG_PROC_FS |
Yinghai Lu | 2c6927a | 2008-08-19 20:50:11 -0700 | [diff] [blame] | 95 | extern void register_irq_proc(unsigned int irq, struct irq_desc *desc); |
Thomas Gleixner | 13bfe99 | 2010-09-30 02:46:07 +0200 | [diff] [blame] | 96 | extern void unregister_irq_proc(unsigned int irq, struct irq_desc *desc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | extern void register_handler_proc(unsigned int irq, struct irqaction *action); |
| 98 | extern void unregister_handler_proc(unsigned int irq, struct irqaction *action); |
| 99 | #else |
Yinghai Lu | 2c6927a | 2008-08-19 20:50:11 -0700 | [diff] [blame] | 100 | static inline void register_irq_proc(unsigned int irq, struct irq_desc *desc) { } |
Thomas Gleixner | 13bfe99 | 2010-09-30 02:46:07 +0200 | [diff] [blame] | 101 | static inline void unregister_irq_proc(unsigned int irq, struct irq_desc *desc) { } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | static inline void register_handler_proc(unsigned int irq, |
| 103 | struct irqaction *action) { } |
| 104 | static inline void unregister_handler_proc(unsigned int irq, |
| 105 | struct irqaction *action) { } |
| 106 | #endif |
| 107 | |
Thomas Gleixner | 3b8249e | 2011-02-07 16:02:20 +0100 | [diff] [blame] | 108 | extern int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask); |
Thomas Gleixner | f6d87f4 | 2008-11-07 13:18:30 +0100 | [diff] [blame] | 109 | |
Thomas Gleixner | 591d2fb | 2009-07-21 11:09:39 +0200 | [diff] [blame] | 110 | extern void irq_set_thread_affinity(struct irq_desc *desc); |
Yinghai Lu | 57b150c | 2009-04-27 17:59:53 -0700 | [diff] [blame] | 111 | |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 112 | /* Inline functions for support of irq chips on slow busses */ |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 113 | static inline void chip_bus_lock(struct irq_desc *desc) |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 114 | { |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 115 | if (unlikely(desc->irq_data.chip->irq_bus_lock)) |
| 116 | desc->irq_data.chip->irq_bus_lock(&desc->irq_data); |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 117 | } |
| 118 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 119 | static inline void chip_bus_sync_unlock(struct irq_desc *desc) |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 120 | { |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 121 | if (unlikely(desc->irq_data.chip->irq_bus_sync_unlock)) |
| 122 | desc->irq_data.chip->irq_bus_sync_unlock(&desc->irq_data); |
Thomas Gleixner | 70aedd2 | 2009-08-13 12:17:48 +0200 | [diff] [blame] | 123 | } |
| 124 | |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 125 | /* |
| 126 | * Debugging printout: |
| 127 | */ |
| 128 | |
| 129 | #include <linux/kallsyms.h> |
| 130 | |
| 131 | #define P(f) if (desc->status & f) printk("%14s set\n", #f) |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 132 | #define PS(f) if (desc->istate & f) printk("%14s set\n", #f) |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 133 | |
| 134 | static inline void print_irq_desc(unsigned int irq, struct irq_desc *desc) |
| 135 | { |
| 136 | printk("irq %d, desc: %p, depth: %d, count: %d, unhandled: %d\n", |
| 137 | irq, desc, desc->depth, desc->irq_count, desc->irqs_unhandled); |
| 138 | printk("->handle_irq(): %p, ", desc->handle_irq); |
| 139 | print_symbol("%s\n", (unsigned long)desc->handle_irq); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 140 | printk("->irq_data.chip(): %p, ", desc->irq_data.chip); |
| 141 | print_symbol("%s\n", (unsigned long)desc->irq_data.chip); |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 142 | printk("->action(): %p\n", desc->action); |
| 143 | if (desc->action) { |
| 144 | printk("->action->handler(): %p, ", desc->action->handler); |
| 145 | print_symbol("%s\n", (unsigned long)desc->action->handler); |
| 146 | } |
| 147 | |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 148 | P(IRQ_LEVEL); |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 149 | #ifdef CONFIG_IRQ_PER_CPU |
| 150 | P(IRQ_PER_CPU); |
| 151 | #endif |
| 152 | P(IRQ_NOPROBE); |
| 153 | P(IRQ_NOREQUEST); |
| 154 | P(IRQ_NOAUTOEN); |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 155 | |
| 156 | PS(IRQS_AUTODETECT); |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 157 | PS(IRQS_INPROGRESS); |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 158 | PS(IRQS_REPLAY); |
| 159 | PS(IRQS_WAITING); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 160 | PS(IRQS_DISABLED); |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 161 | PS(IRQS_PENDING); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 162 | PS(IRQS_MASKED); |
Ingo Molnar | 43f7775 | 2006-06-29 02:24:58 -0700 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | #undef P |
Thomas Gleixner | bd062e7 | 2011-02-07 20:25:25 +0100 | [diff] [blame] | 166 | #undef PS |