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review.evervolv.com / android_kernel_htc_msm8960 / c710a5e5d6a3578f539596702f7c991928b74d33 / . / drivers / spi / spi_qsd.h
blob: bda9e17f00df33dce661aa209fae4613d42744b6 [file] [log] [blame]
Harini Jayaramanc710a5e2011-11-22 12:02:43 -0700[diff] [blame^]1/* Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef _SPI_QSD_H
15#define _SPI_QSD_H
16
17#define SPI_DRV_NAME "spi_qsd"
18
19#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
20
21#define QSD_REG(x) (x)
22#define QUP_REG(x)
23
24#define SPI_FIFO_WORD_CNT 0x0048
25
26#else
27
28#define QSD_REG(x)
29#define QUP_REG(x) (x)
30
31#define QUP_CONFIG 0x0000 /* N & NO_INPUT/NO_OUPUT bits */
32#define QUP_ERROR_FLAGS_EN 0x030C
33#define QUP_ERR_MASK 0x3
34#define SPI_OUTPUT_FIFO_WORD_CNT 0x010C
35#define SPI_INPUT_FIFO_WORD_CNT 0x0214
36#define QUP_MX_WRITE_COUNT 0x0150
37#define QUP_MX_WRITE_CNT_CURRENT 0x0154
38
39#define QUP_CONFIG_SPI_MODE 0x0100
40#endif
41
42#define GSBI_CTRL_REG 0x0
43#define GSBI_SPI_CONFIG 0x30
44#define QUP_HARDWARE_VER 0x0030
45#define QUP_OPERATIONAL_MASK 0x0028
46#define QUP_ERROR_FLAGS 0x0308
47
48#define SPI_CONFIG QSD_REG(0x0000) QUP_REG(0x0300)
49#define SPI_IO_CONTROL QSD_REG(0x0004) QUP_REG(0x0304)
50#define SPI_IO_MODES QSD_REG(0x0008) QUP_REG(0x0008)
51#define SPI_SW_RESET QSD_REG(0x000C) QUP_REG(0x000C)
52#define SPI_TIME_OUT_CURRENT QSD_REG(0x0014) QUP_REG(0x0014)
53#define SPI_MX_OUTPUT_COUNT QSD_REG(0x0018) QUP_REG(0x0100)
54#define SPI_MX_OUTPUT_CNT_CURRENT QSD_REG(0x001C) QUP_REG(0x0104)
55#define SPI_MX_INPUT_COUNT QSD_REG(0x0020) QUP_REG(0x0200)
56#define SPI_MX_INPUT_CNT_CURRENT QSD_REG(0x0024) QUP_REG(0x0204)
57#define SPI_MX_READ_COUNT QSD_REG(0x0028) QUP_REG(0x0208)
58#define SPI_MX_READ_CNT_CURRENT QSD_REG(0x002C) QUP_REG(0x020C)
59#define SPI_OPERATIONAL QSD_REG(0x0030) QUP_REG(0x0018)
60#define SPI_ERROR_FLAGS QSD_REG(0x0034) QUP_REG(0x001C)
61#define SPI_ERROR_FLAGS_EN QSD_REG(0x0038) QUP_REG(0x0020)
62#define SPI_DEASSERT_WAIT QSD_REG(0x003C) QUP_REG(0x0310)
63#define SPI_OUTPUT_DEBUG QSD_REG(0x0040) QUP_REG(0x0108)
64#define SPI_INPUT_DEBUG QSD_REG(0x0044) QUP_REG(0x0210)
65#define SPI_TEST_CTRL QSD_REG(0x004C) QUP_REG(0x0024)
66#define SPI_OUTPUT_FIFO QSD_REG(0x0100) QUP_REG(0x0110)
67#define SPI_INPUT_FIFO QSD_REG(0x0200) QUP_REG(0x0218)
68#define SPI_STATE QSD_REG(SPI_OPERATIONAL) QUP_REG(0x0004)
69
70/* SPI_CONFIG fields */
71#define SPI_CFG_INPUT_FIRST 0x00000200
72#define SPI_NO_INPUT 0x00000080
73#define SPI_NO_OUTPUT 0x00000040
74#define SPI_CFG_LOOPBACK 0x00000100
75#define SPI_CFG_N 0x0000001F
76
77/* SPI_IO_CONTROL fields */
78#define SPI_IO_C_FORCE_CS 0x00000800
79#define SPI_IO_C_CLK_IDLE_HIGH 0x00000400
80#define SPI_IO_C_MX_CS_MODE 0x00000100
81#define SPI_IO_C_CS_N_POLARITY 0x000000F0
82#define SPI_IO_C_CS_N_POLARITY_0 0x00000010
83#define SPI_IO_C_CS_SELECT 0x0000000C
84#define SPI_IO_C_TRISTATE_CS 0x00000002
85#define SPI_IO_C_NO_TRI_STATE 0x00000001
86
87/* SPI_IO_MODES fields */
88#define SPI_IO_M_OUTPUT_BIT_SHIFT_EN QSD_REG(0x00004000) QUP_REG(0x00010000)
89#define SPI_IO_M_PACK_EN QSD_REG(0x00002000) QUP_REG(0x00008000)
90#define SPI_IO_M_UNPACK_EN QSD_REG(0x00001000) QUP_REG(0x00004000)
91#define SPI_IO_M_INPUT_MODE QSD_REG(0x00000C00) QUP_REG(0x00003000)
92#define SPI_IO_M_OUTPUT_MODE QSD_REG(0x00000300) QUP_REG(0x00000C00)
93#define SPI_IO_M_INPUT_FIFO_SIZE QSD_REG(0x000000C0) QUP_REG(0x00000380)
94#define SPI_IO_M_INPUT_BLOCK_SIZE QSD_REG(0x00000030) QUP_REG(0x00000060)
95#define SPI_IO_M_OUTPUT_FIFO_SIZE QSD_REG(0x0000000C) QUP_REG(0x0000001C)
96#define SPI_IO_M_OUTPUT_BLOCK_SIZE QSD_REG(0x00000003) QUP_REG(0x00000003)
97
98#define INPUT_BLOCK_SZ_SHIFT QSD_REG(4) QUP_REG(5)
99#define INPUT_FIFO_SZ_SHIFT QSD_REG(6) QUP_REG(7)
100#define OUTPUT_BLOCK_SZ_SHIFT QSD_REG(0) QUP_REG(0)
101#define OUTPUT_FIFO_SZ_SHIFT QSD_REG(2) QUP_REG(2)
102#define OUTPUT_MODE_SHIFT QSD_REG(8) QUP_REG(10)
103#define INPUT_MODE_SHIFT QSD_REG(10) QUP_REG(12)
104
105/* SPI_OPERATIONAL fields */
106#define SPI_OP_MAX_INPUT_DONE_FLAG 0x00000800
107#define SPI_OP_MAX_OUTPUT_DONE_FLAG 0x00000400
108#define SPI_OP_INPUT_SERVICE_FLAG 0x00000200
109#define SPI_OP_OUTPUT_SERVICE_FLAG 0x00000100
110#define SPI_OP_INPUT_FIFO_FULL 0x00000080
111#define SPI_OP_OUTPUT_FIFO_FULL 0x00000040
112#define SPI_OP_IP_FIFO_NOT_EMPTY 0x00000020
113#define SPI_OP_OP_FIFO_NOT_EMPTY 0x00000010
114#define SPI_OP_STATE_VALID 0x00000004
115#define SPI_OP_STATE 0x00000003
116
117#define SPI_OP_STATE_CLEAR_BITS 0x2
118enum msm_spi_state {
119 SPI_OP_STATE_RESET = 0x00000000,
120 SPI_OP_STATE_RUN = 0x00000001,
121 SPI_OP_STATE_PAUSE = 0x00000003,
122};
123
124/* SPI_ERROR_FLAGS fields */
125#define SPI_ERR_OUTPUT_OVER_RUN_ERR 0x00000020
126#define SPI_ERR_INPUT_UNDER_RUN_ERR 0x00000010
127#define SPI_ERR_OUTPUT_UNDER_RUN_ERR 0x00000008
128#define SPI_ERR_INPUT_OVER_RUN_ERR 0x00000004
129#define SPI_ERR_CLK_OVER_RUN_ERR 0x00000002
130#define SPI_ERR_CLK_UNDER_RUN_ERR 0x00000001
131
132/* We don't allow transactions larger than 4K-64 or 64K-64 due to
133 mx_input/output_cnt register size */
134#define SPI_MAX_TRANSFERS QSD_REG(0xFC0) QUP_REG(0xFC0)
135#define SPI_MAX_LEN (SPI_MAX_TRANSFERS * dd->bytes_per_word)
136
137#define SPI_NUM_CHIPSELECTS 4
138#define SPI_SUPPORTED_MODES (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP)
139
140#define SPI_DELAY_THRESHOLD 1
141/* Default timeout is 10 milliseconds */
142#define SPI_DEFAULT_TIMEOUT 10
143/* 250 microseconds */
144#define SPI_TRYLOCK_DELAY 250
145
146/* Data Mover burst size */
147#define DM_BURST_SIZE 16
148/* Data Mover commands should be aligned to 64 bit(8 bytes) */
149#define DM_BYTE_ALIGN 8
150
151#define SPI_QUP_VERSION_NONE 0x0
152#define SPI_QUP_VERSION_BFAM 0x2
153
154static char const * const spi_rsrcs[] = {
155 "spi_clk",
156 "spi_miso",
157 "spi_mosi"
158};
159
160static char const * const spi_cs_rsrcs[] = {
161 "spi_cs",
162 "spi_cs1",
163 "spi_cs2",
164 "spi_cs3",
165};
166
167enum msm_spi_mode {
168 SPI_FIFO_MODE = 0x0, /* 00 */
169 SPI_BLOCK_MODE = 0x1, /* 01 */
170 SPI_DMOV_MODE = 0x2, /* 10 */
171 SPI_BAM_MODE = 0x3, /* 11 */
172 SPI_MODE_NONE = 0xFF, /* invalid value */
173};
174
175/* Structure for SPI CS GPIOs */
176struct spi_cs_gpio {
177 int gpio_num;
178 bool valid;
179};
180
181/* Structures for Data Mover */
182struct spi_dmov_cmd {
183 dmov_box box; /* data aligned to max(dm_burst_size, block_size)
184 (<= fifo_size) */
185 dmov_s single_pad; /* data unaligned to max(dm_burst_size, block_size)
186 padded to fit */
187 dma_addr_t cmd_ptr;
188};
189
190static struct pm_qos_request_list qos_req_list;
191
192#ifdef CONFIG_DEBUG_FS
193/* Used to create debugfs entries */
194static const struct {
195 const char *name;
196 mode_t mode;
197 int offset;
198} debugfs_spi_regs[] = {
199 {"config", S_IRUGO | S_IWUSR, SPI_CONFIG},
200 {"io_control", S_IRUGO | S_IWUSR, SPI_IO_CONTROL},
201 {"io_modes", S_IRUGO | S_IWUSR, SPI_IO_MODES},
202 {"sw_reset", S_IWUSR, SPI_SW_RESET},
203 {"time_out_current", S_IRUGO, SPI_TIME_OUT_CURRENT},
204 {"mx_output_count", S_IRUGO | S_IWUSR, SPI_MX_OUTPUT_COUNT},
205 {"mx_output_cnt_current", S_IRUGO, SPI_MX_OUTPUT_CNT_CURRENT},
206 {"mx_input_count", S_IRUGO | S_IWUSR, SPI_MX_INPUT_COUNT},
207 {"mx_input_cnt_current", S_IRUGO, SPI_MX_INPUT_CNT_CURRENT},
208 {"mx_read_count", S_IRUGO | S_IWUSR, SPI_MX_READ_COUNT},
209 {"mx_read_cnt_current", S_IRUGO, SPI_MX_READ_CNT_CURRENT},
210 {"operational", S_IRUGO | S_IWUSR, SPI_OPERATIONAL},
211 {"error_flags", S_IRUGO | S_IWUSR, SPI_ERROR_FLAGS},
212 {"error_flags_en", S_IRUGO | S_IWUSR, SPI_ERROR_FLAGS_EN},
213 {"deassert_wait", S_IRUGO | S_IWUSR, SPI_DEASSERT_WAIT},
214 {"output_debug", S_IRUGO, SPI_OUTPUT_DEBUG},
215 {"input_debug", S_IRUGO, SPI_INPUT_DEBUG},
216 {"test_ctrl", S_IRUGO | S_IWUSR, SPI_TEST_CTRL},
217 {"output_fifo", S_IWUSR, SPI_OUTPUT_FIFO},
218 {"input_fifo" , S_IRUSR, SPI_INPUT_FIFO},
219 {"spi_state", S_IRUGO | S_IWUSR, SPI_STATE},
220#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
221 {"fifo_word_cnt", S_IRUGO, SPI_FIFO_WORD_CNT},
222#else
223 {"qup_config", S_IRUGO | S_IWUSR, QUP_CONFIG},
224 {"qup_error_flags", S_IRUGO | S_IWUSR, QUP_ERROR_FLAGS},
225 {"qup_error_flags_en", S_IRUGO | S_IWUSR, QUP_ERROR_FLAGS_EN},
226 {"mx_write_cnt", S_IRUGO | S_IWUSR, QUP_MX_WRITE_COUNT},
227 {"mx_write_cnt_current", S_IRUGO, QUP_MX_WRITE_CNT_CURRENT},
228 {"output_fifo_word_cnt", S_IRUGO, SPI_OUTPUT_FIFO_WORD_CNT},
229 {"input_fifo_word_cnt", S_IRUGO, SPI_INPUT_FIFO_WORD_CNT},
230#endif
231};
232#endif
233
234struct msm_spi {
235 u8 *read_buf;
236 const u8 *write_buf;
237 void __iomem *base;
238 struct device *dev;
239 spinlock_t queue_lock;
240 struct mutex core_lock;
241 struct list_head queue;
242 struct workqueue_struct *workqueue;
243 struct work_struct work_data;
244 struct spi_message *cur_msg;
245 struct spi_transfer *cur_transfer;
246 struct completion transfer_complete;
247 struct clk *clk;
248 struct clk *pclk;
249 unsigned long mem_phys_addr;
250 size_t mem_size;
251 int input_fifo_size;
252 int output_fifo_size;
253 u32 rx_bytes_remaining;
254 u32 tx_bytes_remaining;
255 u32 clock_speed;
256 int irq_in;
257 int read_xfr_cnt;
258 int write_xfr_cnt;
259 int write_len;
260 int read_len;
261#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
262 int irq_out;
263 int irq_err;
264#endif
265 int bytes_per_word;
266 bool suspended;
267 bool transfer_pending;
268 wait_queue_head_t continue_suspend;
269 /* DMA data */
270 enum msm_spi_mode mode;
271 bool use_dma;
272 int tx_dma_chan;
273 int tx_dma_crci;
274 int rx_dma_chan;
275 int rx_dma_crci;
276 /* Data Mover Commands */
277 struct spi_dmov_cmd *tx_dmov_cmd;
278 struct spi_dmov_cmd *rx_dmov_cmd;
279 /* Physical address of the tx dmov box command */
280 dma_addr_t tx_dmov_cmd_dma;
281 dma_addr_t rx_dmov_cmd_dma;
282 struct msm_dmov_cmd tx_hdr;
283 struct msm_dmov_cmd rx_hdr;
284 int input_block_size;
285 int output_block_size;
286 int burst_size;
287 atomic_t rx_irq_called;
288 /* Used to pad messages unaligned to block size */
289 u8 *tx_padding;
290 dma_addr_t tx_padding_dma;
291 u8 *rx_padding;
292 dma_addr_t rx_padding_dma;
293 u32 unaligned_len;
294 /* DMA statistics */
295 int stat_dmov_tx_err;
296 int stat_dmov_rx_err;
297 int stat_rx;
298 int stat_dmov_rx;
299 int stat_tx;
300 int stat_dmov_tx;
301#ifdef CONFIG_DEBUG_FS
302 struct dentry *dent_spi;
303 struct dentry *debugfs_spi_regs[ARRAY_SIZE(debugfs_spi_regs)];
304#endif
305 struct msm_spi_platform_data *pdata; /* Platform data */
306 /* Remote Spinlock Data */
307 bool use_rlock;
308 remote_mutex_t r_lock;
309 uint32_t pm_lat;
310 /* When set indicates multiple transfers in a single message */
311 bool multi_xfr;
312 bool done;
313 u32 cur_msg_len;
314 /* Used in FIFO mode to keep track of the transfer being processed */
315 struct spi_transfer *cur_tx_transfer;
316 struct spi_transfer *cur_rx_transfer;
317 /* Temporary buffer used for WR-WR or WR-RD transfers */
318 u8 *temp_buf;
319 /* GPIO pin numbers for SPI clk, miso and mosi */
320 int spi_gpios[ARRAY_SIZE(spi_rsrcs)];
321 /* SPI CS GPIOs for each slave */
322 struct spi_cs_gpio cs_gpios[ARRAY_SIZE(spi_cs_rsrcs)];
323 int qup_ver;
324};
325
326/* Forward declaration */
327static irqreturn_t msm_spi_input_irq(int irq, void *dev_id);
328static irqreturn_t msm_spi_output_irq(int irq, void *dev_id);
329static irqreturn_t msm_spi_error_irq(int irq, void *dev_id);
330static inline int msm_spi_set_state(struct msm_spi *dd,
331 enum msm_spi_state state);
332static void msm_spi_write_word_to_fifo(struct msm_spi *dd);
333static inline void msm_spi_write_rmn_to_fifo(struct msm_spi *dd);
334static irqreturn_t msm_spi_qup_irq(int irq, void *dev_id);
335
336#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
337static inline void msm_spi_disable_irqs(struct msm_spi *dd)
338{
339 disable_irq(dd->irq_in);
340 disable_irq(dd->irq_out);
341 disable_irq(dd->irq_err);
342}
343
344static inline void msm_spi_enable_irqs(struct msm_spi *dd)
345{
346 enable_irq(dd->irq_in);
347 enable_irq(dd->irq_out);
348 enable_irq(dd->irq_err);
349}
350
351static inline int msm_spi_request_irq(struct msm_spi *dd,
352 struct platform_device *pdev,
353 struct spi_master *master)
354{
355 int rc;
356
357 dd->irq_in = platform_get_irq(pdev, 0);
358 dd->irq_out = platform_get_irq(pdev, 1);
359 dd->irq_err = platform_get_irq(pdev, 2);
360 if ((dd->irq_in < 0) || (dd->irq_out < 0) || (dd->irq_err < 0))
361 return -EINVAL;
362
363 rc = devm_request_irq(dd->dev, dd->irq_in, msm_spi_input_irq,
364 IRQF_TRIGGER_RISING, pdev->name, dd);
365 if (rc)
366 goto error_irq;
367
368 rc = devm_request_irq(dd->dev, dd->irq_out, msm_spi_output_irq,
369 IRQF_TRIGGER_RISING, pdev->name, dd);
370 if (rc)
371 goto error_irq;
372
373 rc = devm_request_irq(dd->dev, dd->irq_err, msm_spi_error_irq,
374 IRQF_TRIGGER_RISING, pdev->name, master);
375 if (rc)
376 goto error_irq;
377
378error_irq:
379 return rc;
380}
381
382static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err) {}
383static inline void msm_spi_ack_clk_err(struct msm_spi *dd) {}
384static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw) {}
385
386static inline int msm_spi_prepare_for_write(struct msm_spi *dd) { return 0; }
387static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
388{
389 msm_spi_write_word_to_fifo(dd);
390}
391static inline void msm_spi_set_write_count(struct msm_spi *dd, int val) {}
392
393static inline void msm_spi_complete(struct msm_spi *dd)
394{
395 complete(&dd->transfer_complete);
396}
397
398static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
399{
400 writel_relaxed(0x0000007B, dd->base + SPI_ERROR_FLAGS_EN);
401}
402
403static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
404{
405 writel_relaxed(0x0000007F, dd->base + SPI_ERROR_FLAGS);
406}
407
408#else
409/* In QUP the same interrupt line is used for input, output and error*/
410static inline int msm_spi_request_irq(struct msm_spi *dd,
411 struct platform_device *pdev,
412 struct spi_master *master)
413{
414 dd->irq_in = platform_get_irq(pdev, 0);
415 if (dd->irq_in < 0)
416 return -EINVAL;
417
418 return devm_request_irq(dd->dev, dd->irq_in, msm_spi_qup_irq,
419 IRQF_TRIGGER_HIGH, pdev->name, dd);
420}
421
422static inline void msm_spi_disable_irqs(struct msm_spi *dd)
423{
424 disable_irq(dd->irq_in);
425}
426
427static inline void msm_spi_enable_irqs(struct msm_spi *dd)
428{
429 enable_irq(dd->irq_in);
430}
431
432static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err)
433{
434 *spi_err = readl_relaxed(dd->base + QUP_ERROR_FLAGS);
435}
436
437static inline void msm_spi_ack_clk_err(struct msm_spi *dd)
438{
439 writel_relaxed(QUP_ERR_MASK, dd->base + QUP_ERROR_FLAGS);
440}
441
442static inline void msm_spi_add_configs(struct msm_spi *dd, u32 *config, int n);
443
444/* QUP has no_input, no_output, and N bits at QUP_CONFIG */
445static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw)
446{
447 u32 qup_config = readl_relaxed(dd->base + QUP_CONFIG);
448
449 msm_spi_add_configs(dd, &qup_config, bpw-1);
450 writel_relaxed(qup_config | QUP_CONFIG_SPI_MODE,
451 dd->base + QUP_CONFIG);
452}
453
454static inline int msm_spi_prepare_for_write(struct msm_spi *dd)
455{
456 if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
457 return -EINVAL;
458 if (msm_spi_set_state(dd, SPI_OP_STATE_PAUSE))
459 return -EINVAL;
460 return 0;
461}
462
463static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
464{
465 if (read_count <= dd->input_fifo_size)
466 msm_spi_write_rmn_to_fifo(dd);
467 else
468 msm_spi_write_word_to_fifo(dd);
469}
470
471static inline void msm_spi_set_write_count(struct msm_spi *dd, int val)
472{
473 writel_relaxed(val, dd->base + QUP_MX_WRITE_COUNT);
474}
475
476static inline void msm_spi_complete(struct msm_spi *dd)
477{
478 dd->done = 1;
479}
480
481static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
482{
483 writel_relaxed(0x00000078, dd->base + SPI_ERROR_FLAGS_EN);
484}
485
486static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
487{
488 writel_relaxed(0x0000007C, dd->base + SPI_ERROR_FLAGS);
489}
490
491#endif
492#endif