Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / c87abd75b35e8f991ff8ff1510d6fb62612c61fa / . / include / asm-mips / tx4938 / rbtx4938.h
blob: b14acb575be2aaffcc2fc965e429c59c991a0878 [file] [log] [blame]
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]1/*
2 * linux/include/asm-mips/tx4938/rbtx4938.h
3 * Definitions for TX4937/TX4938
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#ifndef __ASM_TX_BOARDS_RBTX4938_H
13#define __ASM_TX_BOARDS_RBTX4938_H
14
15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h>
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame^]17#include <asm/txx9irq.h>
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]18
19/* CS */
20#define RBTX4938_CE0 0x1c000000 /* 64M */
21#define RBTX4938_CE2 0x17f00000 /* 1M */
22
23/* Address map */
24#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
25#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
26#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
27#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
28#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
29#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
30#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
31#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
32#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
33#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
34#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
35#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
36#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
37#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
38#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
39#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
40#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
41#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
42#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
43#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
44#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
45#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
46#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
47#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
48
49/* Ethernet port address (Jumperless Mode (W12:Open)) */
50#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
51
52/* bits for ISTAT/IMASK/IMSTAT */
53#define RBTX4938_INTB_PCID 0
54#define RBTX4938_INTB_PCIC 1
55#define RBTX4938_INTB_PCIB 2
56#define RBTX4938_INTB_PCIA 3
57#define RBTX4938_INTB_RTC 4
58#define RBTX4938_INTB_ATA 5
59#define RBTX4938_INTB_MODEM 6
60#define RBTX4938_INTB_SWINT 7
61#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
62#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
63#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
64#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
65#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
66#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
67#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
68#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
69
70#define rbtx4938_fpga_rev_ptr \
71 ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
72#define rbtx4938_led_ptr \
73 ((volatile unsigned char *)RBTX4938_LED_ADDR)
74#define rbtx4938_dipsw_ptr \
75 ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
76#define rbtx4938_bdipsw_ptr \
77 ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
78#define rbtx4938_imask_ptr \
79 ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
80#define rbtx4938_imask2_ptr \
81 ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
82#define rbtx4938_intpol_ptr \
83 ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
84#define rbtx4938_istat_ptr \
85 ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
86#define rbtx4938_istat2_ptr \
87 ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
88#define rbtx4938_imstat_ptr \
89 ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
90#define rbtx4938_imstat2_ptr \
91 ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
92#define rbtx4938_softint_ptr \
93 ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
94#define rbtx4938_piosel_ptr \
95 ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
96#define rbtx4938_spics_ptr \
97 ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
98#define rbtx4938_sfpwr_ptr \
99 ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
100#define rbtx4938_sfvol_ptr \
101 ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
102#define rbtx4938_softreset_ptr \
103 ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
104#define rbtx4938_softresetlock_ptr \
105 ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
106#define rbtx4938_pcireset_ptr \
107 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
108
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]109/*
110 * IRQ mappings
111 */
112
113#define RBTX4938_SOFT_INT0 0 /* not used */
114#define RBTX4938_SOFT_INT1 1 /* not used */
115#define RBTX4938_IRC_INT 2
116#define RBTX4938_TIMER_INT 7
117
118/* These are the virtual IRQ numbers, we divide all IRQ's into
119 * 'spaces', the 'space' determines where and how to enable/disable
120 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
121 * IRQ hardware is supported.
122 */
123#define RBTX4938_NR_IRQ_LOCAL 8
124#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
125#define RBTX4938_NR_IRQ_IOC 8
126
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame^]127#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
128#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]129
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame^]130#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
131#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]132#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
133#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
134#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
135#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
136#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
137
138#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
139#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
140
141#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
142#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
143#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
144#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
145#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
146#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
147
148#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
149#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
150#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
151#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
152#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
153#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
154#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
155#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
156#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
157#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
158#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
159#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
160#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
161#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
162#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
163#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
164#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
165#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
166#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
167#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
168#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
169#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
170#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
171#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
172#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
173#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
174#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
175#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
176
177
178/* IOC (PCI, etc) */
179#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
180/* Onboard 10M Ether */
181#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
182
183#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
184#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
185
Ralf Baechle23fbee92005-07-25 22:45:45 +0000[diff] [blame]186#endif /* __ASM_TX_BOARDS_RBTX4938_H */