| Doug Warzecha | 90563ec | 2005-09-06 15:17:15 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  *  dcdbas.h: Definitions for Dell Systems Management Base driver | 
 | 3 |  * | 
 | 4 |  *  Copyright (C) 1995-2005 Dell Inc. | 
 | 5 |  * | 
 | 6 |  *  This program is free software; you can redistribute it and/or modify | 
 | 7 |  *  it under the terms of the GNU General Public License v2.0 as published by | 
 | 8 |  *  the Free Software Foundation. | 
 | 9 |  * | 
 | 10 |  *  This program is distributed in the hope that it will be useful, | 
 | 11 |  *  but WITHOUT ANY WARRANTY; without even the implied warranty of | 
 | 12 |  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
 | 13 |  *  GNU General Public License for more details. | 
 | 14 |  */ | 
 | 15 |  | 
 | 16 | #ifndef _DCDBAS_H_ | 
 | 17 | #define _DCDBAS_H_ | 
 | 18 |  | 
 | 19 | #include <linux/device.h> | 
 | 20 | #include <linux/input.h> | 
 | 21 | #include <linux/sysfs.h> | 
 | 22 | #include <linux/types.h> | 
 | 23 |  | 
 | 24 | #define MAX_SMI_DATA_BUF_SIZE			(256 * 1024) | 
 | 25 |  | 
 | 26 | #define HC_ACTION_NONE				(0) | 
 | 27 | #define HC_ACTION_HOST_CONTROL_POWEROFF		BIT(1) | 
 | 28 | #define HC_ACTION_HOST_CONTROL_POWERCYCLE	BIT(2) | 
 | 29 |  | 
 | 30 | #define HC_SMITYPE_NONE				(0) | 
 | 31 | #define HC_SMITYPE_TYPE1			(1) | 
 | 32 | #define HC_SMITYPE_TYPE2			(2) | 
 | 33 | #define HC_SMITYPE_TYPE3			(3) | 
 | 34 |  | 
 | 35 | #define ESM_APM_CMD				(0x0A0) | 
 | 36 | #define ESM_APM_POWER_CYCLE			(0x10) | 
 | 37 | #define ESM_STATUS_CMD_UNSUCCESSFUL		(-1) | 
 | 38 |  | 
 | 39 | #define CMOS_BASE_PORT				(0x070) | 
 | 40 | #define CMOS_PAGE1_INDEX_PORT			(0) | 
 | 41 | #define CMOS_PAGE1_DATA_PORT			(1) | 
 | 42 | #define CMOS_PAGE2_INDEX_PORT_PIIX4		(2) | 
 | 43 | #define CMOS_PAGE2_DATA_PORT_PIIX4		(3) | 
 | 44 | #define PE1400_APM_CONTROL_PORT			(0x0B0) | 
 | 45 | #define PCAT_APM_CONTROL_PORT			(0x0B2) | 
 | 46 | #define PCAT_APM_STATUS_PORT			(0x0B3) | 
 | 47 | #define PE1300_CMOS_CMD_STRUCT_PTR		(0x38) | 
 | 48 | #define PE1400_CMOS_CMD_STRUCT_PTR		(0x70) | 
 | 49 |  | 
 | 50 | #define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN	(14) | 
 | 51 | #define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM		(16) | 
 | 52 |  | 
 | 53 | #define TIMEOUT_USEC_SHORT_SEMA_BLOCKING	(10000) | 
 | 54 | #define EXPIRED_TIMER				(0) | 
 | 55 |  | 
 | 56 | #define SMI_CMD_MAGIC				(0x534D4931) | 
 | 57 |  | 
 | 58 | #define DCDBAS_DEV_ATTR_RW(_name) \ | 
 | 59 | 	DEVICE_ATTR(_name,0600,_name##_show,_name##_store); | 
 | 60 |  | 
 | 61 | #define DCDBAS_DEV_ATTR_RO(_name) \ | 
 | 62 | 	DEVICE_ATTR(_name,0400,_name##_show,NULL); | 
 | 63 |  | 
 | 64 | #define DCDBAS_DEV_ATTR_WO(_name) \ | 
 | 65 | 	DEVICE_ATTR(_name,0200,NULL,_name##_store); | 
 | 66 |  | 
 | 67 | #define DCDBAS_BIN_ATTR_RW(_name) \ | 
 | 68 | struct bin_attribute bin_attr_##_name = { \ | 
 | 69 | 	.attr =  { .name = __stringify(_name), \ | 
 | 70 | 		   .mode = 0600, \ | 
 | 71 | 		   .owner = THIS_MODULE }, \ | 
 | 72 | 	.read =  _name##_read, \ | 
 | 73 | 	.write = _name##_write, \ | 
 | 74 | } | 
 | 75 |  | 
 | 76 | struct smi_cmd { | 
 | 77 | 	__u32 magic; | 
 | 78 | 	__u32 ebx; | 
 | 79 | 	__u32 ecx; | 
 | 80 | 	__u16 command_address; | 
 | 81 | 	__u8 command_code; | 
 | 82 | 	__u8 reserved; | 
 | 83 | 	__u8 command_buffer[1]; | 
 | 84 | } __attribute__ ((packed)); | 
 | 85 |  | 
 | 86 | struct apm_cmd { | 
 | 87 | 	__u8 command; | 
 | 88 | 	__s8 status; | 
 | 89 | 	__u16 reserved; | 
 | 90 | 	union { | 
 | 91 | 		struct { | 
 | 92 | 			__u8 parm[MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN]; | 
 | 93 | 		} __attribute__ ((packed)) shortreq; | 
 | 94 |  | 
 | 95 | 		struct { | 
 | 96 | 			__u16 num_sg_entries; | 
 | 97 | 			struct { | 
 | 98 | 				__u32 size; | 
 | 99 | 				__u64 addr; | 
 | 100 | 			} __attribute__ ((packed)) | 
 | 101 | 			    sglist[MAX_SYSMGMT_LONGCMD_SGENTRY_NUM]; | 
 | 102 | 		} __attribute__ ((packed)) longreq; | 
 | 103 | 	} __attribute__ ((packed)) parameters; | 
 | 104 | } __attribute__ ((packed)); | 
 | 105 |  | 
 | 106 | #endif /* _DCDBAS_H_ */ | 
 | 107 |  |