Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
| 4 | Copyright(c) 2007 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/if_ether.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/netdevice.h> |
| 32 | |
| 33 | #include "e1000_mac.h" |
| 34 | |
| 35 | #include "igb.h" |
| 36 | |
| 37 | static s32 igb_set_default_fc(struct e1000_hw *hw); |
| 38 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 39 | |
| 40 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 41 | * igb_remove_device - Free device specific structure |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 42 | * @hw: pointer to the HW structure |
| 43 | * |
| 44 | * If a device specific structure was allocated, this function will |
| 45 | * free it. |
| 46 | **/ |
| 47 | void igb_remove_device(struct e1000_hw *hw) |
| 48 | { |
| 49 | /* Freeing the dev_spec member of e1000_hw structure */ |
| 50 | kfree(hw->dev_spec); |
| 51 | } |
| 52 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 53 | static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
| 54 | { |
| 55 | struct igb_adapter *adapter = hw->back; |
| 56 | u16 cap_offset; |
| 57 | |
| 58 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); |
| 59 | if (!cap_offset) |
| 60 | return -E1000_ERR_CONFIG; |
| 61 | |
| 62 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); |
| 63 | |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 68 | * igb_get_bus_info_pcie - Get PCIe bus information |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 69 | * @hw: pointer to the HW structure |
| 70 | * |
| 71 | * Determines and stores the system bus information for a particular |
| 72 | * network interface. The following bus information is determined and stored: |
| 73 | * bus speed, bus width, type (PCIe), and PCIe function. |
| 74 | **/ |
| 75 | s32 igb_get_bus_info_pcie(struct e1000_hw *hw) |
| 76 | { |
| 77 | struct e1000_bus_info *bus = &hw->bus; |
| 78 | s32 ret_val; |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 79 | u32 reg; |
| 80 | u16 pcie_link_status; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 81 | |
| 82 | bus->type = e1000_bus_type_pci_express; |
| 83 | bus->speed = e1000_bus_speed_2500; |
| 84 | |
| 85 | ret_val = igb_read_pcie_cap_reg(hw, |
| 86 | PCIE_LINK_STATUS, |
| 87 | &pcie_link_status); |
| 88 | if (ret_val) |
| 89 | bus->width = e1000_bus_width_unknown; |
| 90 | else |
| 91 | bus->width = (enum e1000_bus_width)((pcie_link_status & |
| 92 | PCIE_LINK_WIDTH_MASK) >> |
| 93 | PCIE_LINK_WIDTH_SHIFT); |
| 94 | |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 95 | reg = rd32(E1000_STATUS); |
| 96 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 102 | * igb_clear_vfta - Clear VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 103 | * @hw: pointer to the HW structure |
| 104 | * |
| 105 | * Clears the register array which contains the VLAN filter table by |
| 106 | * setting all the values to 0. |
| 107 | **/ |
| 108 | void igb_clear_vfta(struct e1000_hw *hw) |
| 109 | { |
| 110 | u32 offset; |
| 111 | |
| 112 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 113 | array_wr32(E1000_VFTA, offset, 0); |
| 114 | wrfl(); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 119 | * igb_write_vfta - Write value to VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 120 | * @hw: pointer to the HW structure |
| 121 | * @offset: register offset in VLAN filter table |
| 122 | * @value: register value written to VLAN filter table |
| 123 | * |
| 124 | * Writes value at the given offset in the register array which stores |
| 125 | * the VLAN filter table. |
| 126 | **/ |
| 127 | void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
| 128 | { |
| 129 | array_wr32(E1000_VFTA, offset, value); |
| 130 | wrfl(); |
| 131 | } |
| 132 | |
| 133 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 134 | * igb_check_alt_mac_addr - Check for alternate MAC addr |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 135 | * @hw: pointer to the HW structure |
| 136 | * |
| 137 | * Checks the nvm for an alternate MAC address. An alternate MAC address |
| 138 | * can be setup by pre-boot software and must be treated like a permanent |
| 139 | * address and must override the actual permanent MAC address. If an |
| 140 | * alternate MAC address is fopund it is saved in the hw struct and |
| 141 | * prgrammed into RAR0 and the cuntion returns success, otherwise the |
| 142 | * fucntion returns an error. |
| 143 | **/ |
| 144 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw) |
| 145 | { |
| 146 | u32 i; |
| 147 | s32 ret_val = 0; |
| 148 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; |
| 149 | u8 alt_mac_addr[ETH_ALEN]; |
| 150 | |
| 151 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
| 152 | &nvm_alt_mac_addr_offset); |
| 153 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 154 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 155 | goto out; |
| 156 | } |
| 157 | |
| 158 | if (nvm_alt_mac_addr_offset == 0xFFFF) { |
| 159 | ret_val = -(E1000_NOT_IMPLEMENTED); |
| 160 | goto out; |
| 161 | } |
| 162 | |
| 163 | if (hw->bus.func == E1000_FUNC_1) |
| 164 | nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16); |
| 165 | |
| 166 | for (i = 0; i < ETH_ALEN; i += 2) { |
| 167 | offset = nvm_alt_mac_addr_offset + (i >> 1); |
| 168 | ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); |
| 169 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 170 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 171 | goto out; |
| 172 | } |
| 173 | |
| 174 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
| 175 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); |
| 176 | } |
| 177 | |
| 178 | /* if multicast bit is set, the alternate address will not be used */ |
| 179 | if (alt_mac_addr[0] & 0x01) { |
| 180 | ret_val = -(E1000_NOT_IMPLEMENTED); |
| 181 | goto out; |
| 182 | } |
| 183 | |
| 184 | for (i = 0; i < ETH_ALEN; i++) |
| 185 | hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; |
| 186 | |
| 187 | hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); |
| 188 | |
| 189 | out: |
| 190 | return ret_val; |
| 191 | } |
| 192 | |
| 193 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 194 | * igb_rar_set - Set receive address register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 195 | * @hw: pointer to the HW structure |
| 196 | * @addr: pointer to the receive address |
| 197 | * @index: receive address array register |
| 198 | * |
| 199 | * Sets the receive address array register at index to the address passed |
| 200 | * in by addr. |
| 201 | **/ |
| 202 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
| 203 | { |
| 204 | u32 rar_low, rar_high; |
| 205 | |
| 206 | /* |
| 207 | * HW expects these in little endian so we reverse the byte order |
| 208 | * from network order (big endian) to little endian |
| 209 | */ |
| 210 | rar_low = ((u32) addr[0] | |
| 211 | ((u32) addr[1] << 8) | |
| 212 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
| 213 | |
| 214 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
| 215 | |
| 216 | if (!hw->mac.disable_av) |
| 217 | rar_high |= E1000_RAH_AV; |
| 218 | |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 219 | wr32(E1000_RAL(index), rar_low); |
| 220 | wr32(E1000_RAH(index), rar_high); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 224 | * igb_mta_set - Set multicast filter table address |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 225 | * @hw: pointer to the HW structure |
| 226 | * @hash_value: determines the MTA register and bit to set |
| 227 | * |
| 228 | * The multicast table address is a register array of 32-bit registers. |
| 229 | * The hash_value is used to determine what register the bit is in, the |
| 230 | * current value is read, the new bit is OR'd in and the new value is |
| 231 | * written back into the register. |
| 232 | **/ |
Alexander Duyck | 549bdd8 | 2008-08-04 15:00:06 -0700 | [diff] [blame] | 233 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 234 | { |
| 235 | u32 hash_bit, hash_reg, mta; |
| 236 | |
| 237 | /* |
| 238 | * The MTA is a register array of 32-bit registers. It is |
| 239 | * treated like an array of (32*mta_reg_count) bits. We want to |
| 240 | * set bit BitArray[hash_value]. So we figure out what register |
| 241 | * the bit is in, read it, OR in the new bit, then write |
| 242 | * back the new value. The (hw->mac.mta_reg_count - 1) serves as a |
| 243 | * mask to bits 31:5 of the hash value which gives us the |
| 244 | * register we're modifying. The hash bit within that register |
| 245 | * is determined by the lower 5 bits of the hash value. |
| 246 | */ |
| 247 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 248 | hash_bit = hash_value & 0x1F; |
| 249 | |
| 250 | mta = array_rd32(E1000_MTA, hash_reg); |
| 251 | |
| 252 | mta |= (1 << hash_bit); |
| 253 | |
| 254 | array_wr32(E1000_MTA, hash_reg, mta); |
| 255 | wrfl(); |
| 256 | } |
| 257 | |
| 258 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 259 | * igb_hash_mc_addr - Generate a multicast hash value |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 260 | * @hw: pointer to the HW structure |
| 261 | * @mc_addr: pointer to a multicast address |
| 262 | * |
| 263 | * Generates a multicast address hash value which is used to determine |
| 264 | * the multicast filter table array address and new table value. See |
| 265 | * igb_mta_set() |
| 266 | **/ |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 267 | u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 268 | { |
| 269 | u32 hash_value, hash_mask; |
| 270 | u8 bit_shift = 0; |
| 271 | |
| 272 | /* Register count multiplied by bits per register */ |
| 273 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
| 274 | |
| 275 | /* |
| 276 | * For a mc_filter_type of 0, bit_shift is the number of left-shifts |
| 277 | * where 0xFF would still fall within the hash mask. |
| 278 | */ |
| 279 | while (hash_mask >> bit_shift != 0xFF) |
| 280 | bit_shift++; |
| 281 | |
| 282 | /* |
| 283 | * The portion of the address that is used for the hash table |
| 284 | * is determined by the mc_filter_type setting. |
| 285 | * The algorithm is such that there is a total of 8 bits of shifting. |
| 286 | * The bit_shift for a mc_filter_type of 0 represents the number of |
| 287 | * left-shifts where the MSB of mc_addr[5] would still fall within |
| 288 | * the hash_mask. Case 0 does this exactly. Since there are a total |
| 289 | * of 8 bits of shifting, then mc_addr[4] will shift right the |
| 290 | * remaining number of bits. Thus 8 - bit_shift. The rest of the |
| 291 | * cases are a variation of this algorithm...essentially raising the |
| 292 | * number of bits to shift mc_addr[5] left, while still keeping the |
| 293 | * 8-bit shifting total. |
| 294 | * |
| 295 | * For example, given the following Destination MAC Address and an |
| 296 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
| 297 | * we can see that the bit_shift for case 0 is 4. These are the hash |
| 298 | * values resulting from each mc_filter_type... |
| 299 | * [0] [1] [2] [3] [4] [5] |
| 300 | * 01 AA 00 12 34 56 |
| 301 | * LSB MSB |
| 302 | * |
| 303 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
| 304 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
| 305 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
| 306 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
| 307 | */ |
| 308 | switch (hw->mac.mc_filter_type) { |
| 309 | default: |
| 310 | case 0: |
| 311 | break; |
| 312 | case 1: |
| 313 | bit_shift += 1; |
| 314 | break; |
| 315 | case 2: |
| 316 | bit_shift += 2; |
| 317 | break; |
| 318 | case 3: |
| 319 | bit_shift += 4; |
| 320 | break; |
| 321 | } |
| 322 | |
| 323 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
| 324 | (((u16) mc_addr[5]) << bit_shift))); |
| 325 | |
| 326 | return hash_value; |
| 327 | } |
| 328 | |
| 329 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 330 | * igb_clear_hw_cntrs_base - Clear base hardware counters |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 331 | * @hw: pointer to the HW structure |
| 332 | * |
| 333 | * Clears the base hardware counters by reading the counter registers. |
| 334 | **/ |
| 335 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw) |
| 336 | { |
| 337 | u32 temp; |
| 338 | |
| 339 | temp = rd32(E1000_CRCERRS); |
| 340 | temp = rd32(E1000_SYMERRS); |
| 341 | temp = rd32(E1000_MPC); |
| 342 | temp = rd32(E1000_SCC); |
| 343 | temp = rd32(E1000_ECOL); |
| 344 | temp = rd32(E1000_MCC); |
| 345 | temp = rd32(E1000_LATECOL); |
| 346 | temp = rd32(E1000_COLC); |
| 347 | temp = rd32(E1000_DC); |
| 348 | temp = rd32(E1000_SEC); |
| 349 | temp = rd32(E1000_RLEC); |
| 350 | temp = rd32(E1000_XONRXC); |
| 351 | temp = rd32(E1000_XONTXC); |
| 352 | temp = rd32(E1000_XOFFRXC); |
| 353 | temp = rd32(E1000_XOFFTXC); |
| 354 | temp = rd32(E1000_FCRUC); |
| 355 | temp = rd32(E1000_GPRC); |
| 356 | temp = rd32(E1000_BPRC); |
| 357 | temp = rd32(E1000_MPRC); |
| 358 | temp = rd32(E1000_GPTC); |
| 359 | temp = rd32(E1000_GORCL); |
| 360 | temp = rd32(E1000_GORCH); |
| 361 | temp = rd32(E1000_GOTCL); |
| 362 | temp = rd32(E1000_GOTCH); |
| 363 | temp = rd32(E1000_RNBC); |
| 364 | temp = rd32(E1000_RUC); |
| 365 | temp = rd32(E1000_RFC); |
| 366 | temp = rd32(E1000_ROC); |
| 367 | temp = rd32(E1000_RJC); |
| 368 | temp = rd32(E1000_TORL); |
| 369 | temp = rd32(E1000_TORH); |
| 370 | temp = rd32(E1000_TOTL); |
| 371 | temp = rd32(E1000_TOTH); |
| 372 | temp = rd32(E1000_TPR); |
| 373 | temp = rd32(E1000_TPT); |
| 374 | temp = rd32(E1000_MPTC); |
| 375 | temp = rd32(E1000_BPTC); |
| 376 | } |
| 377 | |
| 378 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 379 | * igb_check_for_copper_link - Check for link (Copper) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 380 | * @hw: pointer to the HW structure |
| 381 | * |
| 382 | * Checks to see of the link status of the hardware has changed. If a |
| 383 | * change in link status has been detected, then we read the PHY registers |
| 384 | * to get the current speed/duplex if link exists. |
| 385 | **/ |
| 386 | s32 igb_check_for_copper_link(struct e1000_hw *hw) |
| 387 | { |
| 388 | struct e1000_mac_info *mac = &hw->mac; |
| 389 | s32 ret_val; |
| 390 | bool link; |
| 391 | |
| 392 | /* |
| 393 | * We only want to go out to the PHY registers to see if Auto-Neg |
| 394 | * has completed and/or if our link status has changed. The |
| 395 | * get_link_status flag is set upon receiving a Link Status |
| 396 | * Change or Rx Sequence Error interrupt. |
| 397 | */ |
| 398 | if (!mac->get_link_status) { |
| 399 | ret_val = 0; |
| 400 | goto out; |
| 401 | } |
| 402 | |
| 403 | /* |
| 404 | * First we want to see if the MII Status Register reports |
| 405 | * link. If so, then we want to get the current speed/duplex |
| 406 | * of the PHY. |
| 407 | */ |
| 408 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 409 | if (ret_val) |
| 410 | goto out; |
| 411 | |
| 412 | if (!link) |
| 413 | goto out; /* No link detected */ |
| 414 | |
| 415 | mac->get_link_status = false; |
| 416 | |
| 417 | /* |
| 418 | * Check if there was DownShift, must be checked |
| 419 | * immediately after link-up |
| 420 | */ |
| 421 | igb_check_downshift(hw); |
| 422 | |
| 423 | /* |
| 424 | * If we are forcing speed/duplex, then we simply return since |
| 425 | * we have already determined whether we have link or not. |
| 426 | */ |
| 427 | if (!mac->autoneg) { |
| 428 | ret_val = -E1000_ERR_CONFIG; |
| 429 | goto out; |
| 430 | } |
| 431 | |
| 432 | /* |
| 433 | * Auto-Neg is enabled. Auto Speed Detection takes care |
| 434 | * of MAC speed/duplex configuration. So we only need to |
| 435 | * configure Collision Distance in the MAC. |
| 436 | */ |
| 437 | igb_config_collision_dist(hw); |
| 438 | |
| 439 | /* |
| 440 | * Configure Flow Control now that Auto-Neg has completed. |
| 441 | * First, we need to restore the desired flow control |
| 442 | * settings because we may have had to re-autoneg with a |
| 443 | * different link partner. |
| 444 | */ |
| 445 | ret_val = igb_config_fc_after_link_up(hw); |
| 446 | if (ret_val) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 447 | hw_dbg("Error configuring flow control\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 448 | |
| 449 | out: |
| 450 | return ret_val; |
| 451 | } |
| 452 | |
| 453 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 454 | * igb_setup_link - Setup flow control and link settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 455 | * @hw: pointer to the HW structure |
| 456 | * |
| 457 | * Determines which flow control settings to use, then configures flow |
| 458 | * control. Calls the appropriate media-specific link configuration |
| 459 | * function. Assuming the adapter has a valid link partner, a valid link |
| 460 | * should be established. Assumes the hardware has previously been reset |
| 461 | * and the transmitter and receiver are not enabled. |
| 462 | **/ |
| 463 | s32 igb_setup_link(struct e1000_hw *hw) |
| 464 | { |
| 465 | s32 ret_val = 0; |
| 466 | |
| 467 | /* |
| 468 | * In the case of the phy reset being blocked, we already have a link. |
| 469 | * We do not need to set it up again. |
| 470 | */ |
| 471 | if (igb_check_reset_block(hw)) |
| 472 | goto out; |
| 473 | |
| 474 | ret_val = igb_set_default_fc(hw); |
| 475 | if (ret_val) |
| 476 | goto out; |
| 477 | |
| 478 | /* |
| 479 | * We want to save off the original Flow Control configuration just |
| 480 | * in case we get disconnected and then reconnected into a different |
| 481 | * hub or switch with different Flow Control capabilities. |
| 482 | */ |
| 483 | hw->fc.original_type = hw->fc.type; |
| 484 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 485 | hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 486 | |
| 487 | /* Call the necessary media_type subroutine to configure the link. */ |
| 488 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
| 489 | if (ret_val) |
| 490 | goto out; |
| 491 | |
| 492 | /* |
| 493 | * Initialize the flow control address, type, and PAUSE timer |
| 494 | * registers to their default values. This is done even if flow |
| 495 | * control is disabled, because it does not hurt anything to |
| 496 | * initialize these registers. |
| 497 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 498 | hw_dbg("Initializing the Flow Control address, type and timer regs\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 499 | wr32(E1000_FCT, FLOW_CONTROL_TYPE); |
| 500 | wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 501 | wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 502 | |
| 503 | wr32(E1000_FCTTV, hw->fc.pause_time); |
| 504 | |
| 505 | ret_val = igb_set_fc_watermarks(hw); |
| 506 | |
| 507 | out: |
| 508 | return ret_val; |
| 509 | } |
| 510 | |
| 511 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 512 | * igb_config_collision_dist - Configure collision distance |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 513 | * @hw: pointer to the HW structure |
| 514 | * |
| 515 | * Configures the collision distance to the default value and is used |
| 516 | * during link setup. Currently no func pointer exists and all |
| 517 | * implementations are handled in the generic version of this function. |
| 518 | **/ |
| 519 | void igb_config_collision_dist(struct e1000_hw *hw) |
| 520 | { |
| 521 | u32 tctl; |
| 522 | |
| 523 | tctl = rd32(E1000_TCTL); |
| 524 | |
| 525 | tctl &= ~E1000_TCTL_COLD; |
| 526 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
| 527 | |
| 528 | wr32(E1000_TCTL, tctl); |
| 529 | wrfl(); |
| 530 | } |
| 531 | |
| 532 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 533 | * igb_set_fc_watermarks - Set flow control high/low watermarks |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 534 | * @hw: pointer to the HW structure |
| 535 | * |
| 536 | * Sets the flow control high/low threshold (watermark) registers. If |
| 537 | * flow control XON frame transmission is enabled, then set XON frame |
| 538 | * tansmission as well. |
| 539 | **/ |
| 540 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw) |
| 541 | { |
| 542 | s32 ret_val = 0; |
| 543 | u32 fcrtl = 0, fcrth = 0; |
| 544 | |
| 545 | /* |
| 546 | * Set the flow control receive threshold registers. Normally, |
| 547 | * these registers will be set to a default threshold that may be |
| 548 | * adjusted later by the driver's runtime code. However, if the |
| 549 | * ability to transmit pause frames is not enabled, then these |
| 550 | * registers will be set to 0. |
| 551 | */ |
| 552 | if (hw->fc.type & e1000_fc_tx_pause) { |
| 553 | /* |
| 554 | * We need to set up the Receive Threshold high and low water |
| 555 | * marks as well as (optionally) enabling the transmission of |
| 556 | * XON frames. |
| 557 | */ |
| 558 | fcrtl = hw->fc.low_water; |
| 559 | if (hw->fc.send_xon) |
| 560 | fcrtl |= E1000_FCRTL_XONE; |
| 561 | |
| 562 | fcrth = hw->fc.high_water; |
| 563 | } |
| 564 | wr32(E1000_FCRTL, fcrtl); |
| 565 | wr32(E1000_FCRTH, fcrth); |
| 566 | |
| 567 | return ret_val; |
| 568 | } |
| 569 | |
| 570 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 571 | * igb_set_default_fc - Set flow control default values |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 572 | * @hw: pointer to the HW structure |
| 573 | * |
| 574 | * Read the EEPROM for the default values for flow control and store the |
| 575 | * values. |
| 576 | **/ |
| 577 | static s32 igb_set_default_fc(struct e1000_hw *hw) |
| 578 | { |
| 579 | s32 ret_val = 0; |
| 580 | u16 nvm_data; |
| 581 | |
| 582 | /* |
| 583 | * Read and store word 0x0F of the EEPROM. This word contains bits |
| 584 | * that determine the hardware's default PAUSE (flow control) mode, |
| 585 | * a bit that determines whether the HW defaults to enabling or |
| 586 | * disabling auto-negotiation, and the direction of the |
| 587 | * SW defined pins. If there is no SW over-ride of the flow |
| 588 | * control setting, then the variable hw->fc will |
| 589 | * be initialized based on a value in the EEPROM. |
| 590 | */ |
| 591 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, |
| 592 | &nvm_data); |
| 593 | |
| 594 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 595 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 596 | goto out; |
| 597 | } |
| 598 | |
| 599 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
| 600 | hw->fc.type = e1000_fc_none; |
| 601 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == |
| 602 | NVM_WORD0F_ASM_DIR) |
| 603 | hw->fc.type = e1000_fc_tx_pause; |
| 604 | else |
| 605 | hw->fc.type = e1000_fc_full; |
| 606 | |
| 607 | out: |
| 608 | return ret_val; |
| 609 | } |
| 610 | |
| 611 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 612 | * igb_force_mac_fc - Force the MAC's flow control settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 613 | * @hw: pointer to the HW structure |
| 614 | * |
| 615 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
| 616 | * device control register to reflect the adapter settings. TFCE and RFCE |
| 617 | * need to be explicitly set by software when a copper PHY is used because |
| 618 | * autonegotiation is managed by the PHY rather than the MAC. Software must |
| 619 | * also configure these bits when link is forced on a fiber connection. |
| 620 | **/ |
| 621 | s32 igb_force_mac_fc(struct e1000_hw *hw) |
| 622 | { |
| 623 | u32 ctrl; |
| 624 | s32 ret_val = 0; |
| 625 | |
| 626 | ctrl = rd32(E1000_CTRL); |
| 627 | |
| 628 | /* |
| 629 | * Because we didn't get link via the internal auto-negotiation |
| 630 | * mechanism (we either forced link or we got link via PHY |
| 631 | * auto-neg), we have to manually enable/disable transmit an |
| 632 | * receive flow control. |
| 633 | * |
| 634 | * The "Case" statement below enables/disable flow control |
| 635 | * according to the "hw->fc.type" parameter. |
| 636 | * |
| 637 | * The possible values of the "fc" parameter are: |
| 638 | * 0: Flow control is completely disabled |
| 639 | * 1: Rx flow control is enabled (we can receive pause |
| 640 | * frames but not send pause frames). |
| 641 | * 2: Tx flow control is enabled (we can send pause frames |
| 642 | * frames but we do not receive pause frames). |
| 643 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
| 644 | * other: No other values should be possible at this point. |
| 645 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 646 | hw_dbg("hw->fc.type = %u\n", hw->fc.type); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 647 | |
| 648 | switch (hw->fc.type) { |
| 649 | case e1000_fc_none: |
| 650 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 651 | break; |
| 652 | case e1000_fc_rx_pause: |
| 653 | ctrl &= (~E1000_CTRL_TFCE); |
| 654 | ctrl |= E1000_CTRL_RFCE; |
| 655 | break; |
| 656 | case e1000_fc_tx_pause: |
| 657 | ctrl &= (~E1000_CTRL_RFCE); |
| 658 | ctrl |= E1000_CTRL_TFCE; |
| 659 | break; |
| 660 | case e1000_fc_full: |
| 661 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 662 | break; |
| 663 | default: |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 664 | hw_dbg("Flow control param set incorrectly\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 665 | ret_val = -E1000_ERR_CONFIG; |
| 666 | goto out; |
| 667 | } |
| 668 | |
| 669 | wr32(E1000_CTRL, ctrl); |
| 670 | |
| 671 | out: |
| 672 | return ret_val; |
| 673 | } |
| 674 | |
| 675 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 676 | * igb_config_fc_after_link_up - Configures flow control after link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 677 | * @hw: pointer to the HW structure |
| 678 | * |
| 679 | * Checks the status of auto-negotiation after link up to ensure that the |
| 680 | * speed and duplex were not forced. If the link needed to be forced, then |
| 681 | * flow control needs to be forced also. If auto-negotiation is enabled |
| 682 | * and did not fail, then we configure flow control based on our link |
| 683 | * partner. |
| 684 | **/ |
| 685 | s32 igb_config_fc_after_link_up(struct e1000_hw *hw) |
| 686 | { |
| 687 | struct e1000_mac_info *mac = &hw->mac; |
| 688 | s32 ret_val = 0; |
| 689 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
| 690 | u16 speed, duplex; |
| 691 | |
| 692 | /* |
| 693 | * Check for the case where we have fiber media and auto-neg failed |
| 694 | * so we had to force link. In this case, we need to force the |
| 695 | * configuration of the MAC to match the "fc" parameter. |
| 696 | */ |
| 697 | if (mac->autoneg_failed) { |
| 698 | if (hw->phy.media_type == e1000_media_type_fiber || |
| 699 | hw->phy.media_type == e1000_media_type_internal_serdes) |
| 700 | ret_val = igb_force_mac_fc(hw); |
| 701 | } else { |
| 702 | if (hw->phy.media_type == e1000_media_type_copper) |
| 703 | ret_val = igb_force_mac_fc(hw); |
| 704 | } |
| 705 | |
| 706 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 707 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 708 | goto out; |
| 709 | } |
| 710 | |
| 711 | /* |
| 712 | * Check for the case where we have copper media and auto-neg is |
| 713 | * enabled. In this case, we need to check and see if Auto-Neg |
| 714 | * has completed, and if so, how the PHY and link partner has |
| 715 | * flow control configured. |
| 716 | */ |
| 717 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
| 718 | /* |
| 719 | * Read the MII Status Register and check to see if AutoNeg |
| 720 | * has completed. We read this twice because this reg has |
| 721 | * some "sticky" (latched) bits. |
| 722 | */ |
| 723 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, |
| 724 | &mii_status_reg); |
| 725 | if (ret_val) |
| 726 | goto out; |
| 727 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, |
| 728 | &mii_status_reg); |
| 729 | if (ret_val) |
| 730 | goto out; |
| 731 | |
| 732 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 733 | hw_dbg("Copper PHY and Auto Neg " |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 734 | "has not completed.\n"); |
| 735 | goto out; |
| 736 | } |
| 737 | |
| 738 | /* |
| 739 | * The AutoNeg process has completed, so we now need to |
| 740 | * read both the Auto Negotiation Advertisement |
| 741 | * Register (Address 4) and the Auto_Negotiation Base |
| 742 | * Page Ability Register (Address 5) to determine how |
| 743 | * flow control was negotiated. |
| 744 | */ |
| 745 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV, |
| 746 | &mii_nway_adv_reg); |
| 747 | if (ret_val) |
| 748 | goto out; |
| 749 | ret_val = hw->phy.ops.read_phy_reg(hw, PHY_LP_ABILITY, |
| 750 | &mii_nway_lp_ability_reg); |
| 751 | if (ret_val) |
| 752 | goto out; |
| 753 | |
| 754 | /* |
| 755 | * Two bits in the Auto Negotiation Advertisement Register |
| 756 | * (Address 4) and two bits in the Auto Negotiation Base |
| 757 | * Page Ability Register (Address 5) determine flow control |
| 758 | * for both the PHY and the link partner. The following |
| 759 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 760 | * 1999, describes these PAUSE resolution bits and how flow |
| 761 | * control is determined based upon these settings. |
| 762 | * NOTE: DC = Don't Care |
| 763 | * |
| 764 | * LOCAL DEVICE | LINK PARTNER |
| 765 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 766 | *-------|---------|-------|---------|-------------------- |
| 767 | * 0 | 0 | DC | DC | e1000_fc_none |
| 768 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 769 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 770 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 771 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 772 | * 1 | DC | 1 | DC | e1000_fc_full |
| 773 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 774 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 775 | * |
| 776 | * Are both PAUSE bits set to 1? If so, this implies |
| 777 | * Symmetric Flow Control is enabled at both ends. The |
| 778 | * ASM_DIR bits are irrelevant per the spec. |
| 779 | * |
| 780 | * For Symmetric Flow Control: |
| 781 | * |
| 782 | * LOCAL DEVICE | LINK PARTNER |
| 783 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 784 | *-------|---------|-------|---------|-------------------- |
| 785 | * 1 | DC | 1 | DC | E1000_fc_full |
| 786 | * |
| 787 | */ |
| 788 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 789 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
| 790 | /* |
| 791 | * Now we need to check if the user selected RX ONLY |
| 792 | * of pause frames. In this case, we had to advertise |
| 793 | * FULL flow control because we could not advertise RX |
| 794 | * ONLY. Hence, we must now check to see if we need to |
| 795 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 796 | */ |
| 797 | if (hw->fc.original_type == e1000_fc_full) { |
| 798 | hw->fc.type = e1000_fc_full; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 799 | hw_dbg("Flow Control = FULL.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 800 | } else { |
| 801 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 802 | hw_dbg("Flow Control = " |
| 803 | "RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 804 | } |
| 805 | } |
| 806 | /* |
| 807 | * For receiving PAUSE frames ONLY. |
| 808 | * |
| 809 | * LOCAL DEVICE | LINK PARTNER |
| 810 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 811 | *-------|---------|-------|---------|-------------------- |
| 812 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 813 | */ |
| 814 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 815 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 816 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 817 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 818 | hw->fc.type = e1000_fc_tx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 819 | hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 820 | } |
| 821 | /* |
| 822 | * For transmitting PAUSE frames ONLY. |
| 823 | * |
| 824 | * LOCAL DEVICE | LINK PARTNER |
| 825 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 826 | *-------|---------|-------|---------|-------------------- |
| 827 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 828 | */ |
| 829 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 830 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 831 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 832 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 833 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 834 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 835 | } |
| 836 | /* |
| 837 | * Per the IEEE spec, at this point flow control should be |
| 838 | * disabled. However, we want to consider that we could |
| 839 | * be connected to a legacy switch that doesn't advertise |
| 840 | * desired flow control, but can be forced on the link |
| 841 | * partner. So if we advertised no flow control, that is |
| 842 | * what we will resolve to. If we advertised some kind of |
| 843 | * receive capability (Rx Pause Only or Full Flow Control) |
| 844 | * and the link partner advertised none, we will configure |
| 845 | * ourselves to enable Rx Flow Control only. We can do |
| 846 | * this safely for two reasons: If the link partner really |
| 847 | * didn't want flow control enabled, and we enable Rx, no |
| 848 | * harm done since we won't be receiving any PAUSE frames |
| 849 | * anyway. If the intent on the link partner was to have |
| 850 | * flow control enabled, then by us enabling RX only, we |
| 851 | * can at least receive pause frames and process them. |
| 852 | * This is a good idea because in most cases, since we are |
| 853 | * predominantly a server NIC, more times than not we will |
| 854 | * be asked to delay transmission of packets than asking |
| 855 | * our link partner to pause transmission of frames. |
| 856 | */ |
| 857 | else if ((hw->fc.original_type == e1000_fc_none || |
| 858 | hw->fc.original_type == e1000_fc_tx_pause) || |
| 859 | hw->fc.strict_ieee) { |
| 860 | hw->fc.type = e1000_fc_none; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 861 | hw_dbg("Flow Control = NONE.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 862 | } else { |
| 863 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 864 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 865 | } |
| 866 | |
| 867 | /* |
| 868 | * Now we need to do one last check... If we auto- |
| 869 | * negotiated to HALF DUPLEX, flow control should not be |
| 870 | * enabled per IEEE 802.3 spec. |
| 871 | */ |
| 872 | ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); |
| 873 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 874 | hw_dbg("Error getting link speed and duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 875 | goto out; |
| 876 | } |
| 877 | |
| 878 | if (duplex == HALF_DUPLEX) |
| 879 | hw->fc.type = e1000_fc_none; |
| 880 | |
| 881 | /* |
| 882 | * Now we call a subroutine to actually force the MAC |
| 883 | * controller to use the correct flow control settings. |
| 884 | */ |
| 885 | ret_val = igb_force_mac_fc(hw); |
| 886 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 887 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 888 | goto out; |
| 889 | } |
| 890 | } |
| 891 | |
| 892 | out: |
| 893 | return ret_val; |
| 894 | } |
| 895 | |
| 896 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 897 | * igb_get_speed_and_duplex_copper - Retreive current speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 898 | * @hw: pointer to the HW structure |
| 899 | * @speed: stores the current speed |
| 900 | * @duplex: stores the current duplex |
| 901 | * |
| 902 | * Read the status register for the current speed/duplex and store the current |
| 903 | * speed and duplex for copper connections. |
| 904 | **/ |
| 905 | s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, |
| 906 | u16 *duplex) |
| 907 | { |
| 908 | u32 status; |
| 909 | |
| 910 | status = rd32(E1000_STATUS); |
| 911 | if (status & E1000_STATUS_SPEED_1000) { |
| 912 | *speed = SPEED_1000; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 913 | hw_dbg("1000 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 914 | } else if (status & E1000_STATUS_SPEED_100) { |
| 915 | *speed = SPEED_100; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 916 | hw_dbg("100 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 917 | } else { |
| 918 | *speed = SPEED_10; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 919 | hw_dbg("10 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 920 | } |
| 921 | |
| 922 | if (status & E1000_STATUS_FD) { |
| 923 | *duplex = FULL_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 924 | hw_dbg("Full Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 925 | } else { |
| 926 | *duplex = HALF_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 927 | hw_dbg("Half Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | return 0; |
| 931 | } |
| 932 | |
| 933 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 934 | * igb_get_hw_semaphore - Acquire hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 935 | * @hw: pointer to the HW structure |
| 936 | * |
| 937 | * Acquire the HW semaphore to access the PHY or NVM |
| 938 | **/ |
| 939 | s32 igb_get_hw_semaphore(struct e1000_hw *hw) |
| 940 | { |
| 941 | u32 swsm; |
| 942 | s32 ret_val = 0; |
| 943 | s32 timeout = hw->nvm.word_size + 1; |
| 944 | s32 i = 0; |
| 945 | |
| 946 | /* Get the SW semaphore */ |
| 947 | while (i < timeout) { |
| 948 | swsm = rd32(E1000_SWSM); |
| 949 | if (!(swsm & E1000_SWSM_SMBI)) |
| 950 | break; |
| 951 | |
| 952 | udelay(50); |
| 953 | i++; |
| 954 | } |
| 955 | |
| 956 | if (i == timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 957 | hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 958 | ret_val = -E1000_ERR_NVM; |
| 959 | goto out; |
| 960 | } |
| 961 | |
| 962 | /* Get the FW semaphore. */ |
| 963 | for (i = 0; i < timeout; i++) { |
| 964 | swsm = rd32(E1000_SWSM); |
| 965 | wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); |
| 966 | |
| 967 | /* Semaphore acquired if bit latched */ |
| 968 | if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) |
| 969 | break; |
| 970 | |
| 971 | udelay(50); |
| 972 | } |
| 973 | |
| 974 | if (i == timeout) { |
| 975 | /* Release semaphores */ |
| 976 | igb_put_hw_semaphore(hw); |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 977 | hw_dbg("Driver can't access the NVM\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 978 | ret_val = -E1000_ERR_NVM; |
| 979 | goto out; |
| 980 | } |
| 981 | |
| 982 | out: |
| 983 | return ret_val; |
| 984 | } |
| 985 | |
| 986 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 987 | * igb_put_hw_semaphore - Release hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 988 | * @hw: pointer to the HW structure |
| 989 | * |
| 990 | * Release hardware semaphore used to access the PHY or NVM |
| 991 | **/ |
| 992 | void igb_put_hw_semaphore(struct e1000_hw *hw) |
| 993 | { |
| 994 | u32 swsm; |
| 995 | |
| 996 | swsm = rd32(E1000_SWSM); |
| 997 | |
| 998 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 999 | |
| 1000 | wr32(E1000_SWSM, swsm); |
| 1001 | } |
| 1002 | |
| 1003 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1004 | * igb_get_auto_rd_done - Check for auto read completion |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1005 | * @hw: pointer to the HW structure |
| 1006 | * |
| 1007 | * Check EEPROM for Auto Read done bit. |
| 1008 | **/ |
| 1009 | s32 igb_get_auto_rd_done(struct e1000_hw *hw) |
| 1010 | { |
| 1011 | s32 i = 0; |
| 1012 | s32 ret_val = 0; |
| 1013 | |
| 1014 | |
| 1015 | while (i < AUTO_READ_DONE_TIMEOUT) { |
| 1016 | if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) |
| 1017 | break; |
| 1018 | msleep(1); |
| 1019 | i++; |
| 1020 | } |
| 1021 | |
| 1022 | if (i == AUTO_READ_DONE_TIMEOUT) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1023 | hw_dbg("Auto read by HW from NVM has not completed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1024 | ret_val = -E1000_ERR_RESET; |
| 1025 | goto out; |
| 1026 | } |
| 1027 | |
| 1028 | out: |
| 1029 | return ret_val; |
| 1030 | } |
| 1031 | |
| 1032 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1033 | * igb_valid_led_default - Verify a valid default LED config |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1034 | * @hw: pointer to the HW structure |
| 1035 | * @data: pointer to the NVM (EEPROM) |
| 1036 | * |
| 1037 | * Read the EEPROM for the current default LED configuration. If the |
| 1038 | * LED configuration is not valid, set to a valid LED configuration. |
| 1039 | **/ |
| 1040 | static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) |
| 1041 | { |
| 1042 | s32 ret_val; |
| 1043 | |
| 1044 | ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
| 1045 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1046 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1047 | goto out; |
| 1048 | } |
| 1049 | |
| 1050 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
| 1051 | *data = ID_LED_DEFAULT; |
| 1052 | |
| 1053 | out: |
| 1054 | return ret_val; |
| 1055 | } |
| 1056 | |
| 1057 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1058 | * igb_id_led_init - |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1059 | * @hw: pointer to the HW structure |
| 1060 | * |
| 1061 | **/ |
| 1062 | s32 igb_id_led_init(struct e1000_hw *hw) |
| 1063 | { |
| 1064 | struct e1000_mac_info *mac = &hw->mac; |
| 1065 | s32 ret_val; |
| 1066 | const u32 ledctl_mask = 0x000000FF; |
| 1067 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 1068 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 1069 | u16 data, i, temp; |
| 1070 | const u16 led_mask = 0x0F; |
| 1071 | |
| 1072 | ret_val = igb_valid_led_default(hw, &data); |
| 1073 | if (ret_val) |
| 1074 | goto out; |
| 1075 | |
| 1076 | mac->ledctl_default = rd32(E1000_LEDCTL); |
| 1077 | mac->ledctl_mode1 = mac->ledctl_default; |
| 1078 | mac->ledctl_mode2 = mac->ledctl_default; |
| 1079 | |
| 1080 | for (i = 0; i < 4; i++) { |
| 1081 | temp = (data >> (i << 2)) & led_mask; |
| 1082 | switch (temp) { |
| 1083 | case ID_LED_ON1_DEF2: |
| 1084 | case ID_LED_ON1_ON2: |
| 1085 | case ID_LED_ON1_OFF2: |
| 1086 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1087 | mac->ledctl_mode1 |= ledctl_on << (i << 3); |
| 1088 | break; |
| 1089 | case ID_LED_OFF1_DEF2: |
| 1090 | case ID_LED_OFF1_ON2: |
| 1091 | case ID_LED_OFF1_OFF2: |
| 1092 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1093 | mac->ledctl_mode1 |= ledctl_off << (i << 3); |
| 1094 | break; |
| 1095 | default: |
| 1096 | /* Do nothing */ |
| 1097 | break; |
| 1098 | } |
| 1099 | switch (temp) { |
| 1100 | case ID_LED_DEF1_ON2: |
| 1101 | case ID_LED_ON1_ON2: |
| 1102 | case ID_LED_OFF1_ON2: |
| 1103 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1104 | mac->ledctl_mode2 |= ledctl_on << (i << 3); |
| 1105 | break; |
| 1106 | case ID_LED_DEF1_OFF2: |
| 1107 | case ID_LED_ON1_OFF2: |
| 1108 | case ID_LED_OFF1_OFF2: |
| 1109 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1110 | mac->ledctl_mode2 |= ledctl_off << (i << 3); |
| 1111 | break; |
| 1112 | default: |
| 1113 | /* Do nothing */ |
| 1114 | break; |
| 1115 | } |
| 1116 | } |
| 1117 | |
| 1118 | out: |
| 1119 | return ret_val; |
| 1120 | } |
| 1121 | |
| 1122 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1123 | * igb_cleanup_led - Set LED config to default operation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1124 | * @hw: pointer to the HW structure |
| 1125 | * |
| 1126 | * Remove the current LED configuration and set the LED configuration |
| 1127 | * to the default value, saved from the EEPROM. |
| 1128 | **/ |
| 1129 | s32 igb_cleanup_led(struct e1000_hw *hw) |
| 1130 | { |
| 1131 | wr32(E1000_LEDCTL, hw->mac.ledctl_default); |
| 1132 | return 0; |
| 1133 | } |
| 1134 | |
| 1135 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1136 | * igb_blink_led - Blink LED |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1137 | * @hw: pointer to the HW structure |
| 1138 | * |
| 1139 | * Blink the led's which are set to be on. |
| 1140 | **/ |
| 1141 | s32 igb_blink_led(struct e1000_hw *hw) |
| 1142 | { |
| 1143 | u32 ledctl_blink = 0; |
| 1144 | u32 i; |
| 1145 | |
| 1146 | if (hw->phy.media_type == e1000_media_type_fiber) { |
| 1147 | /* always blink LED0 for PCI-E fiber */ |
| 1148 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
| 1149 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
| 1150 | } else { |
| 1151 | /* |
| 1152 | * set the blink bit for each LED that's "on" (0x0E) |
| 1153 | * in ledctl_mode2 |
| 1154 | */ |
| 1155 | ledctl_blink = hw->mac.ledctl_mode2; |
| 1156 | for (i = 0; i < 4; i++) |
| 1157 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 1158 | E1000_LEDCTL_MODE_LED_ON) |
| 1159 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
| 1160 | (i * 8)); |
| 1161 | } |
| 1162 | |
| 1163 | wr32(E1000_LEDCTL, ledctl_blink); |
| 1164 | |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
| 1168 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1169 | * igb_led_off - Turn LED off |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1170 | * @hw: pointer to the HW structure |
| 1171 | * |
| 1172 | * Turn LED off. |
| 1173 | **/ |
| 1174 | s32 igb_led_off(struct e1000_hw *hw) |
| 1175 | { |
| 1176 | u32 ctrl; |
| 1177 | |
| 1178 | switch (hw->phy.media_type) { |
| 1179 | case e1000_media_type_fiber: |
| 1180 | ctrl = rd32(E1000_CTRL); |
| 1181 | ctrl |= E1000_CTRL_SWDPIN0; |
| 1182 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1183 | wr32(E1000_CTRL, ctrl); |
| 1184 | break; |
| 1185 | case e1000_media_type_copper: |
| 1186 | wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); |
| 1187 | break; |
| 1188 | default: |
| 1189 | break; |
| 1190 | } |
| 1191 | |
| 1192 | return 0; |
| 1193 | } |
| 1194 | |
| 1195 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1196 | * igb_disable_pcie_master - Disables PCI-express master access |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1197 | * @hw: pointer to the HW structure |
| 1198 | * |
| 1199 | * Returns 0 (0) if successful, else returns -10 |
| 1200 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued |
| 1201 | * the master requests to be disabled. |
| 1202 | * |
| 1203 | * Disables PCI-Express master access and verifies there are no pending |
| 1204 | * requests. |
| 1205 | **/ |
| 1206 | s32 igb_disable_pcie_master(struct e1000_hw *hw) |
| 1207 | { |
| 1208 | u32 ctrl; |
| 1209 | s32 timeout = MASTER_DISABLE_TIMEOUT; |
| 1210 | s32 ret_val = 0; |
| 1211 | |
| 1212 | if (hw->bus.type != e1000_bus_type_pci_express) |
| 1213 | goto out; |
| 1214 | |
| 1215 | ctrl = rd32(E1000_CTRL); |
| 1216 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 1217 | wr32(E1000_CTRL, ctrl); |
| 1218 | |
| 1219 | while (timeout) { |
| 1220 | if (!(rd32(E1000_STATUS) & |
| 1221 | E1000_STATUS_GIO_MASTER_ENABLE)) |
| 1222 | break; |
| 1223 | udelay(100); |
| 1224 | timeout--; |
| 1225 | } |
| 1226 | |
| 1227 | if (!timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1228 | hw_dbg("Master requests are pending.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1229 | ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 1230 | goto out; |
| 1231 | } |
| 1232 | |
| 1233 | out: |
| 1234 | return ret_val; |
| 1235 | } |
| 1236 | |
| 1237 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1238 | * igb_reset_adaptive - Reset Adaptive Interframe Spacing |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1239 | * @hw: pointer to the HW structure |
| 1240 | * |
| 1241 | * Reset the Adaptive Interframe Spacing throttle to default values. |
| 1242 | **/ |
| 1243 | void igb_reset_adaptive(struct e1000_hw *hw) |
| 1244 | { |
| 1245 | struct e1000_mac_info *mac = &hw->mac; |
| 1246 | |
| 1247 | if (!mac->adaptive_ifs) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1248 | hw_dbg("Not in Adaptive IFS mode!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1249 | goto out; |
| 1250 | } |
| 1251 | |
| 1252 | if (!mac->ifs_params_forced) { |
| 1253 | mac->current_ifs_val = 0; |
| 1254 | mac->ifs_min_val = IFS_MIN; |
| 1255 | mac->ifs_max_val = IFS_MAX; |
| 1256 | mac->ifs_step_size = IFS_STEP; |
| 1257 | mac->ifs_ratio = IFS_RATIO; |
| 1258 | } |
| 1259 | |
| 1260 | mac->in_ifs_mode = false; |
| 1261 | wr32(E1000_AIT, 0); |
| 1262 | out: |
| 1263 | return; |
| 1264 | } |
| 1265 | |
| 1266 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1267 | * igb_update_adaptive - Update Adaptive Interframe Spacing |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1268 | * @hw: pointer to the HW structure |
| 1269 | * |
| 1270 | * Update the Adaptive Interframe Spacing Throttle value based on the |
| 1271 | * time between transmitted packets and time between collisions. |
| 1272 | **/ |
| 1273 | void igb_update_adaptive(struct e1000_hw *hw) |
| 1274 | { |
| 1275 | struct e1000_mac_info *mac = &hw->mac; |
| 1276 | |
| 1277 | if (!mac->adaptive_ifs) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1278 | hw_dbg("Not in Adaptive IFS mode!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1279 | goto out; |
| 1280 | } |
| 1281 | |
| 1282 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
| 1283 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
| 1284 | mac->in_ifs_mode = true; |
| 1285 | if (mac->current_ifs_val < mac->ifs_max_val) { |
| 1286 | if (!mac->current_ifs_val) |
| 1287 | mac->current_ifs_val = mac->ifs_min_val; |
| 1288 | else |
| 1289 | mac->current_ifs_val += |
| 1290 | mac->ifs_step_size; |
| 1291 | wr32(E1000_AIT, |
| 1292 | mac->current_ifs_val); |
| 1293 | } |
| 1294 | } |
| 1295 | } else { |
| 1296 | if (mac->in_ifs_mode && |
| 1297 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
| 1298 | mac->current_ifs_val = 0; |
| 1299 | mac->in_ifs_mode = false; |
| 1300 | wr32(E1000_AIT, 0); |
| 1301 | } |
| 1302 | } |
| 1303 | out: |
| 1304 | return; |
| 1305 | } |
| 1306 | |
| 1307 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1308 | * igb_validate_mdi_setting - Verify MDI/MDIx settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1309 | * @hw: pointer to the HW structure |
| 1310 | * |
| 1311 | * Verify that when not using auto-negotitation that MDI/MDIx is correctly |
| 1312 | * set, which is forced to MDI mode only. |
| 1313 | **/ |
| 1314 | s32 igb_validate_mdi_setting(struct e1000_hw *hw) |
| 1315 | { |
| 1316 | s32 ret_val = 0; |
| 1317 | |
| 1318 | if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1319 | hw_dbg("Invalid MDI setting detected\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1320 | hw->phy.mdix = 1; |
| 1321 | ret_val = -E1000_ERR_CONFIG; |
| 1322 | goto out; |
| 1323 | } |
| 1324 | |
| 1325 | out: |
| 1326 | return ret_val; |
| 1327 | } |
| 1328 | |
| 1329 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1330 | * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1331 | * @hw: pointer to the HW structure |
| 1332 | * @reg: 32bit register offset such as E1000_SCTL |
| 1333 | * @offset: register offset to write to |
| 1334 | * @data: data to write at register offset |
| 1335 | * |
| 1336 | * Writes an address/data control type register. There are several of these |
| 1337 | * and they all have the format address << 8 | data and bit 31 is polled for |
| 1338 | * completion. |
| 1339 | **/ |
| 1340 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, |
| 1341 | u32 offset, u8 data) |
| 1342 | { |
| 1343 | u32 i, regvalue = 0; |
| 1344 | s32 ret_val = 0; |
| 1345 | |
| 1346 | /* Set up the address and data */ |
| 1347 | regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); |
| 1348 | wr32(reg, regvalue); |
| 1349 | |
| 1350 | /* Poll the ready bit to see if the MDI read completed */ |
| 1351 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { |
| 1352 | udelay(5); |
| 1353 | regvalue = rd32(reg); |
| 1354 | if (regvalue & E1000_GEN_CTL_READY) |
| 1355 | break; |
| 1356 | } |
| 1357 | if (!(regvalue & E1000_GEN_CTL_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1358 | hw_dbg("Reg %08x did not indicate ready\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1359 | ret_val = -E1000_ERR_PHY; |
| 1360 | goto out; |
| 1361 | } |
| 1362 | |
| 1363 | out: |
| 1364 | return ret_val; |
| 1365 | } |
| 1366 | |
| 1367 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1368 | * igb_enable_mng_pass_thru - Enable processing of ARP's |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1369 | * @hw: pointer to the HW structure |
| 1370 | * |
| 1371 | * Verifies the hardware needs to allow ARPs to be processed by the host. |
| 1372 | **/ |
| 1373 | bool igb_enable_mng_pass_thru(struct e1000_hw *hw) |
| 1374 | { |
| 1375 | u32 manc; |
| 1376 | u32 fwsm, factps; |
| 1377 | bool ret_val = false; |
| 1378 | |
| 1379 | if (!hw->mac.asf_firmware_present) |
| 1380 | goto out; |
| 1381 | |
| 1382 | manc = rd32(E1000_MANC); |
| 1383 | |
| 1384 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
| 1385 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
| 1386 | goto out; |
| 1387 | |
| 1388 | if (hw->mac.arc_subsystem_valid) { |
| 1389 | fwsm = rd32(E1000_FWSM); |
| 1390 | factps = rd32(E1000_FACTPS); |
| 1391 | |
| 1392 | if (!(factps & E1000_FACTPS_MNGCG) && |
| 1393 | ((fwsm & E1000_FWSM_MODE_MASK) == |
| 1394 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { |
| 1395 | ret_val = true; |
| 1396 | goto out; |
| 1397 | } |
| 1398 | } else { |
| 1399 | if ((manc & E1000_MANC_SMBUS_EN) && |
| 1400 | !(manc & E1000_MANC_ASF_EN)) { |
| 1401 | ret_val = true; |
| 1402 | goto out; |
| 1403 | } |
| 1404 | } |
| 1405 | |
| 1406 | out: |
| 1407 | return ret_val; |
| 1408 | } |